same70q21.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70Q21_
36 #define _SAME70Q21_
37 
46 
47 #ifdef __cplusplus
48  extern "C" {
49 #endif
50 
51 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
52 #include <stdint.h>
53 #endif
54 
55 /* ************************************************************************** */
56 /* CMSIS DEFINITIONS FOR SAME70Q21 */
57 /* ************************************************************************** */
60 
62 typedef enum IRQn
63 {
64 /****** Cortex-M7 Processor Exceptions Numbers ******************************/
65  NonMaskableInt_IRQn = -14,
66  HardFault_IRQn = -13,
67  MemoryManagement_IRQn = -12,
68  BusFault_IRQn = -11,
69  UsageFault_IRQn = -10,
70  SVCall_IRQn = -5,
71  DebugMonitor_IRQn = -4,
72  PendSV_IRQn = -2,
73  SysTick_IRQn = -1,
74 /****** SAME70Q21 specific Interrupt Numbers *********************************/
75 
76  SUPC_IRQn = 0,
77  RSTC_IRQn = 1,
78  RTC_IRQn = 2,
79  RTT_IRQn = 3,
80  WDT_IRQn = 4,
81  PMC_IRQn = 5,
82  EFC_IRQn = 6,
83  UART0_IRQn = 7,
84  UART1_IRQn = 8,
85  PIOA_IRQn = 10,
86  PIOB_IRQn = 11,
87  PIOC_IRQn = 12,
88  USART0_IRQn = 13,
89  USART1_IRQn = 14,
90  USART2_IRQn = 15,
91  PIOD_IRQn = 16,
92  PIOE_IRQn = 17,
93  HSMCI_IRQn = 18,
94  TWIHS0_IRQn = 19,
95  TWIHS1_IRQn = 20,
96  SPI0_IRQn = 21,
97  SSC_IRQn = 22,
98  TC0_IRQn = 23,
99  TC1_IRQn = 24,
100  TC2_IRQn = 25,
101  TC3_IRQn = 26,
102  TC4_IRQn = 27,
103  TC5_IRQn = 28,
104  AFEC0_IRQn = 29,
105  DACC_IRQn = 30,
106  PWM0_IRQn = 31,
107  ICM_IRQn = 32,
108  ACC_IRQn = 33,
109  USBHS_IRQn = 34,
110  MCAN0_INT0_IRQn = 35,
111  MCAN0_INT1_IRQn = 36,
112  MCAN1_INT0_IRQn = 37,
113  MCAN1_INT1_IRQn = 38,
114  GMAC_IRQn = 39,
115  AFEC1_IRQn = 40,
116  TWIHS2_IRQn = 41,
117  SPI1_IRQn = 42,
118  QSPI_IRQn = 43,
119  UART2_IRQn = 44,
120  UART3_IRQn = 45,
121  UART4_IRQn = 46,
122  TC6_IRQn = 47,
123  TC7_IRQn = 48,
124  TC8_IRQn = 49,
125  TC9_IRQn = 50,
126  TC10_IRQn = 51,
127  TC11_IRQn = 52,
128  AES_IRQn = 56,
129  TRNG_IRQn = 57,
130  XDMAC_IRQn = 58,
131  ISI_IRQn = 59,
132  PWM1_IRQn = 60,
133  FPU_IRQn = 61,
134  SDRAMC_IRQn = 62,
135  RSWDT_IRQn = 63,
136  CCW_IRQn = 64,
137  CCF_IRQn = 65,
138  GMAC_Q1_IRQn = 66,
139  GMAC_Q2_IRQn = 67,
140  IXC_IRQn = 68,
142  PERIPH_COUNT_IRQn = 74
143 } IRQn_Type;
144 
145 typedef struct _DeviceVectors
146 {
147  /* Stack pointer */
148  void* pvStack;
149 
150  /* Cortex-M handlers */
151  void* pfnReset_Handler;
152  void* pfnNMI_Handler;
153  void* pfnHardFault_Handler;
154  void* pfnMemManage_Handler;
155  void* pfnBusFault_Handler;
156  void* pfnUsageFault_Handler;
157  void* pfnReserved1_Handler;
158  void* pfnReserved2_Handler;
159  void* pfnReserved3_Handler;
160  void* pfnReserved4_Handler;
161  void* pfnSVC_Handler;
162  void* pfnDebugMon_Handler;
163  void* pfnReserved5_Handler;
164  void* pfnPendSV_Handler;
165  void* pfnSysTick_Handler;
166 
167  /* Peripheral handlers */
168  void* pfnSUPC_Handler; /* 0 Supply Controller */
169  void* pfnRSTC_Handler; /* 1 Reset Controller */
170  void* pfnRTC_Handler; /* 2 Real Time Clock */
171  void* pfnRTT_Handler; /* 3 Real Time Timer */
172  void* pfnWDT_Handler; /* 4 Watchdog Timer */
173  void* pfnPMC_Handler; /* 5 Power Management Controller */
174  void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
175  void* pfnUART0_Handler; /* 7 UART 0 */
176  void* pfnUART1_Handler; /* 8 UART 1 */
177  void* pvReserved9;
178  void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
179  void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
180  void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
181  void* pfnUSART0_Handler; /* 13 USART 0 */
182  void* pfnUSART1_Handler; /* 14 USART 1 */
183  void* pfnUSART2_Handler; /* 15 USART 2 */
184  void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
185  void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
186  void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
187  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
188  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
189  void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
190  void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
191  void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
192  void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
193  void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
194  void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
195  void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
196  void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
197  void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
198  void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
199  void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
200  void* pfnICM_Handler; /* 32 Integrity Check Monitor */
201  void* pfnACC_Handler; /* 33 Analog Comparator */
202  void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
203  void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */
204  void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */
205  void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */
206  void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */
207  void* pfnGMAC_Handler; /* 39 Ethernet MAC */
208  void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
209  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
210  void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
211  void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
212  void* pfnUART2_Handler; /* 44 UART 2 */
213  void* pfnUART3_Handler; /* 45 UART 3 */
214  void* pfnUART4_Handler; /* 46 UART 4 */
215  void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
216  void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
217  void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
218  void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
219  void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
220  void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
221  void* pvReserved53;
222  void* pvReserved54;
223  void* pvReserved55;
224  void* pfnAES_Handler; /* 56 AES */
225  void* pfnTRNG_Handler; /* 57 True Random Generator */
226  void* pfnXDMAC_Handler; /* 58 DMA */
227  void* pfnISI_Handler; /* 59 Camera Interface */
228  void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
229  void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */
230  void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */
231  void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */
232  void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */
233  void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */
234  void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */
235  void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */
236  void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */
237  void* pvReserved69;
238  void* pvReserved70;
239  void* pvReserved71;
240  void* pvReserved72;
241  void* pvReserved73;
242 } DeviceVectors;
243 
244 /* Cortex-M7 core handlers */
245 void Reset_Handler ( void );
246 void NMI_Handler ( void );
247 void HardFault_Handler ( void );
248 void MemManage_Handler ( void );
249 void BusFault_Handler ( void );
250 void UsageFault_Handler ( void );
251 void SVC_Handler ( void );
252 void DebugMon_Handler ( void );
253 void PendSV_Handler ( void );
254 void SysTick_Handler ( void );
255 
256 /* Peripherals handlers */
257 void ACC_Handler ( void );
258 void AES_Handler ( void );
259 void AFEC0_Handler ( void );
260 void AFEC1_Handler ( void );
261 void CCF_Handler ( void );
262 void CCW_Handler ( void );
263 void DACC_Handler ( void );
264 void EFC_Handler ( void );
265 void FPU_Handler ( void );
266 void GMAC_Handler ( void );
267 void HSMCI_Handler ( void );
268 void ICM_Handler ( void );
269 void ISI_Handler ( void );
270 void IXC_Handler ( void );
271 void MCAN0_INT0_Handler ( void );
272 void MCAN0_INT1_Handler ( void );
273 void MCAN1_INT0_Handler ( void );
274 void MCAN1_INT1_Handler ( void );
275 void PIOA_Handler ( void );
276 void PIOB_Handler ( void );
277 void PIOC_Handler ( void );
278 void PIOD_Handler ( void );
279 void PIOE_Handler ( void );
280 void PMC_Handler ( void );
281 void PWM0_Handler ( void );
282 void PWM1_Handler ( void );
283 void GMAC_Q1_Handler ( void );
284 void GMAC_Q2_Handler ( void );
285 void QSPI_Handler ( void );
286 void RSTC_Handler ( void );
287 void RSWDT_Handler ( void );
288 void RTC_Handler ( void );
289 void RTT_Handler ( void );
290 void SDRAMC_Handler ( void );
291 void SPI0_Handler ( void );
292 void SPI1_Handler ( void );
293 void SSC_Handler ( void );
294 void SUPC_Handler ( void );
295 void TC0_Handler ( void );
296 void TC1_Handler ( void );
297 void TC2_Handler ( void );
298 void TC3_Handler ( void );
299 void TC4_Handler ( void );
300 void TC5_Handler ( void );
301 void TC6_Handler ( void );
302 void TC7_Handler ( void );
303 void TC8_Handler ( void );
304 void TC9_Handler ( void );
305 void TC10_Handler ( void );
306 void TC11_Handler ( void );
307 void TRNG_Handler ( void );
308 void TWIHS0_Handler ( void );
309 void TWIHS1_Handler ( void );
310 void TWIHS2_Handler ( void );
311 void UART0_Handler ( void );
312 void UART1_Handler ( void );
313 void UART2_Handler ( void );
314 void UART3_Handler ( void );
315 void UART4_Handler ( void );
316 void USART0_Handler ( void );
317 void USART1_Handler ( void );
318 void USART2_Handler ( void );
319 void USBHS_Handler ( void );
320 void WDT_Handler ( void );
321 void XDMAC_Handler ( void );
322 
327 #define __CM7_REV 0x0000
328 #define __MPU_PRESENT 1
329 #define __NVIC_PRIO_BITS 3
330 #define __FPU_PRESENT 1
331 #define __FPU_DP 1
332 #define __ICACHE_PRESENT 1
333 #define __DCACHE_PRESENT 1
334 #define __DTCM_PRESENT 1
335 #define __ITCM_PRESENT 1
336 #define __Vendor_SysTickConfig 0
337 #define __SAM_M7_REVB 0
339 /*
340  * \brief CMSIS includes
341  */
342 
343 #include <core_cm7.h>
344 #if !defined DONT_USE_CMSIS_INIT
345 #include "system_same70.h"
346 #endif /* DONT_USE_CMSIS_INIT */
347 
350 /* ************************************************************************** */
352 /* ************************************************************************** */
355 
356 #include "component/acc.h"
357 #include "component/aes.h"
358 #include "component/afec.h"
359 #include "component/chipid.h"
360 #include "component/dacc.h"
361 #include "component/efc.h"
362 #include "component/gmac.h"
363 #include "component/gpbr.h"
364 #include "component/hsmci.h"
365 #include "component/icm.h"
366 #include "component/isi.h"
367 #include "component/matrix.h"
368 #include "component/mcan.h"
369 #include "component/pio.h"
370 #include "component/pmc.h"
371 #include "component/pwm.h"
372 #include "component/qspi.h"
373 #include "component/rstc.h"
374 #include "component/rswdt.h"
375 #include "component/rtc.h"
376 #include "component/rtt.h"
377 #include "component/sdramc.h"
378 #include "component/smc.h"
379 #include "component/spi.h"
380 #include "component/ssc.h"
381 #include "component/supc.h"
382 #include "component/tc.h"
383 #include "component/trng.h"
384 #include "component/twihs.h"
385 #include "component/uart.h"
386 #include "component/usart.h"
387 #include "component/usbhs.h"
388 #include "component/utmi.h"
389 #include "component/wdt.h"
390 #include "component/xdmac.h"
393 /* ************************************************************************** */
394 /* REGISTER ACCESS DEFINITIONS FOR SAME70Q21 */
395 /* ************************************************************************** */
398 
399 #include "instance/hsmci.h"
400 #include "instance/ssc.h"
401 #include "instance/spi0.h"
402 #include "instance/tc0.h"
403 #include "instance/tc1.h"
404 #include "instance/tc2.h"
405 #include "instance/twihs0.h"
406 #include "instance/twihs1.h"
407 #include "instance/pwm0.h"
408 #include "instance/usart0.h"
409 #include "instance/usart1.h"
410 #include "instance/usart2.h"
411 #include "instance/mcan0.h"
412 #include "instance/mcan1.h"
413 #include "instance/usbhs.h"
414 #include "instance/afec0.h"
415 #include "instance/dacc.h"
416 #include "instance/acc.h"
417 #include "instance/icm.h"
418 #include "instance/isi.h"
419 #include "instance/gmac.h"
420 #include "instance/tc3.h"
421 #include "instance/spi1.h"
422 #include "instance/pwm1.h"
423 #include "instance/twihs2.h"
424 #include "instance/afec1.h"
425 #include "instance/aes.h"
426 #include "instance/trng.h"
427 #include "instance/xdmac.h"
428 #include "instance/qspi.h"
429 #include "instance/smc.h"
430 #include "instance/sdramc.h"
431 #include "instance/matrix.h"
432 #include "instance/utmi.h"
433 #include "instance/pmc.h"
434 #include "instance/uart0.h"
435 #include "instance/chipid.h"
436 #include "instance/uart1.h"
437 #include "instance/efc.h"
438 #include "instance/pioa.h"
439 #include "instance/piob.h"
440 #include "instance/pioc.h"
441 #include "instance/piod.h"
442 #include "instance/pioe.h"
443 #include "instance/rstc.h"
444 #include "instance/supc.h"
445 #include "instance/rtt.h"
446 #include "instance/wdt.h"
447 #include "instance/rtc.h"
448 #include "instance/gpbr.h"
449 #include "instance/rswdt.h"
450 #include "instance/uart2.h"
451 #include "instance/uart3.h"
452 #include "instance/uart4.h"
455 /* ************************************************************************** */
456 /* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */
457 /* ************************************************************************** */
460 
461 #define ID_SUPC ( 0)
462 #define ID_RSTC ( 1)
463 #define ID_RTC ( 2)
464 #define ID_RTT ( 3)
465 #define ID_WDT ( 4)
466 #define ID_PMC ( 5)
467 #define ID_EFC ( 6)
468 #define ID_UART0 ( 7)
469 #define ID_UART1 ( 8)
470 #define ID_SMC ( 9)
471 #define ID_PIOA (10)
472 #define ID_PIOB (11)
473 #define ID_PIOC (12)
474 #define ID_USART0 (13)
475 #define ID_USART1 (14)
476 #define ID_USART2 (15)
477 #define ID_PIOD (16)
478 #define ID_PIOE (17)
479 #define ID_HSMCI (18)
480 #define ID_TWIHS0 (19)
481 #define ID_TWIHS1 (20)
482 #define ID_SPI0 (21)
483 #define ID_SSC (22)
484 #define ID_TC0 (23)
485 #define ID_TC1 (24)
486 #define ID_TC2 (25)
487 #define ID_TC3 (26)
488 #define ID_TC4 (27)
489 #define ID_TC5 (28)
490 #define ID_AFEC0 (29)
491 #define ID_DACC (30)
492 #define ID_PWM0 (31)
493 #define ID_ICM (32)
494 #define ID_ACC (33)
495 #define ID_USBHS (34)
496 #define ID_MCAN0 (35)
497 #define ID_MCAN1 (37)
498 #define ID_GMAC (39)
499 #define ID_AFEC1 (40)
500 #define ID_TWIHS2 (41)
501 #define ID_SPI1 (42)
502 #define ID_QSPI (43)
503 #define ID_UART2 (44)
504 #define ID_UART3 (45)
505 #define ID_UART4 (46)
506 #define ID_TC6 (47)
507 #define ID_TC7 (48)
508 #define ID_TC8 (49)
509 #define ID_TC9 (50)
510 #define ID_TC10 (51)
511 #define ID_TC11 (52)
512 #define ID_AES (56)
513 #define ID_TRNG (57)
514 #define ID_XDMAC (58)
515 #define ID_ISI (59)
516 #define ID_PWM1 (60)
517 #define ID_SDRAMC (62)
518 #define ID_RSWDT (63)
519 #define ID_IXC (68)
521 #define ID_PERIPH_COUNT (74)
523 
524 /* ************************************************************************** */
525 /* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */
526 /* ************************************************************************** */
529 
530 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
531 #define HSMCI (0x40000000U)
532 #define SSC (0x40004000U)
533 #define SPI0 (0x40008000U)
534 #define TC0 (0x4000C000U)
535 #define TC1 (0x40010000U)
536 #define TC2 (0x40014000U)
537 #define TWIHS0 (0x40018000U)
538 #define TWIHS1 (0x4001C000U)
539 #define PWM0 (0x40020000U)
540 #define USART0 (0x40024000U)
541 #define USART1 (0x40028000U)
542 #define USART2 (0x4002C000U)
543 #define MCAN0 (0x40030000U)
544 #define MCAN1 (0x40034000U)
545 #define USBHS (0x40038000U)
546 #define AFEC0 (0x4003C000U)
547 #define DACC (0x40040000U)
548 #define ACC (0x40044000U)
549 #define ICM (0x40048000U)
550 #define ISI (0x4004C000U)
551 #define GMAC (0x40050000U)
552 #define TC3 (0x40054000U)
553 #define SPI1 (0x40058000U)
554 #define PWM1 (0x4005C000U)
555 #define TWIHS2 (0x40060000U)
556 #define AFEC1 (0x40064000U)
557 #define AES (0x4006C000U)
558 #define TRNG (0x40070000U)
559 #define XDMAC (0x40078000U)
560 #define QSPI (0x4007C000U)
561 #define SMC (0x40080000U)
562 #define SDRAMC (0x40084000U)
563 #define MATRIX (0x40088000U)
564 #define UTMI (0x400E0400U)
565 #define PMC (0x400E0600U)
566 #define UART0 (0x400E0800U)
567 #define CHIPID (0x400E0940U)
568 #define UART1 (0x400E0A00U)
569 #define EFC (0x400E0C00U)
570 #define PIOA (0x400E0E00U)
571 #define PIOB (0x400E1000U)
572 #define PIOC (0x400E1200U)
573 #define PIOD (0x400E1400U)
574 #define PIOE (0x400E1600U)
575 #define RSTC (0x400E1800U)
576 #define SUPC (0x400E1810U)
577 #define RTT (0x400E1830U)
578 #define WDT (0x400E1850U)
579 #define RTC (0x400E1860U)
580 #define GPBR (0x400E1890U)
581 #define RSWDT (0x400E1900U)
582 #define UART2 (0x400E1A00U)
583 #define UART3 (0x400E1C00U)
584 #define UART4 (0x400E1E00U)
585 #else
586 #define HSMCI ((Hsmci *)0x40000000U)
587 #define SSC ((Ssc *)0x40004000U)
588 #define SPI0 ((Spi *)0x40008000U)
589 #define TC0 ((Tc *)0x4000C000U)
590 #define TC1 ((Tc *)0x40010000U)
591 #define TC2 ((Tc *)0x40014000U)
592 #define TWIHS0 ((Twihs *)0x40018000U)
593 #define TWIHS1 ((Twihs *)0x4001C000U)
594 #define PWM0 ((Pwm *)0x40020000U)
595 #define USART0 ((Usart *)0x40024000U)
596 #define USART1 ((Usart *)0x40028000U)
597 #define USART2 ((Usart *)0x4002C000U)
598 #define MCAN0 ((Mcan *)0x40030000U)
599 #define MCAN1 ((Mcan *)0x40034000U)
600 #define USBHS ((Usbhs *)0x40038000U)
601 #define AFEC0 ((Afec *)0x4003C000U)
602 #define DACC ((Dacc *)0x40040000U)
603 #define ACC ((Acc *)0x40044000U)
604 #define ICM ((Icm *)0x40048000U)
605 #define ISI ((Isi *)0x4004C000U)
606 #define GMAC ((Gmac *)0x40050000U)
607 #define TC3 ((Tc *)0x40054000U)
608 #define SPI1 ((Spi *)0x40058000U)
609 #define PWM1 ((Pwm *)0x4005C000U)
610 #define TWIHS2 ((Twihs *)0x40060000U)
611 #define AFEC1 ((Afec *)0x40064000U)
612 #define AES ((Aes *)0x4006C000U)
613 #define TRNG ((Trng *)0x40070000U)
614 #define XDMAC ((Xdmac *)0x40078000U)
615 #define QSPI ((Qspi *)0x4007C000U)
616 #define SMC ((Smc *)0x40080000U)
617 #define SDRAMC ((Sdramc *)0x40084000U)
618 #define MATRIX ((Matrix *)0x40088000U)
619 #define UTMI ((Utmi *)0x400E0400U)
620 #define PMC ((Pmc *)0x400E0600U)
621 #define UART0 ((Uart *)0x400E0800U)
622 #define CHIPID ((Chipid *)0x400E0940U)
623 #define UART1 ((Uart *)0x400E0A00U)
624 #define EFC ((Efc *)0x400E0C00U)
625 #define PIOA ((Pio *)0x400E0E00U)
626 #define PIOB ((Pio *)0x400E1000U)
627 #define PIOC ((Pio *)0x400E1200U)
628 #define PIOD ((Pio *)0x400E1400U)
629 #define PIOE ((Pio *)0x400E1600U)
630 #define RSTC ((Rstc *)0x400E1800U)
631 #define SUPC ((Supc *)0x400E1810U)
632 #define RTT ((Rtt *)0x400E1830U)
633 #define WDT ((Wdt *)0x400E1850U)
634 #define RTC ((Rtc *)0x400E1860U)
635 #define GPBR ((Gpbr *)0x400E1890U)
636 #define RSWDT ((Rswdt *)0x400E1900U)
637 #define UART2 ((Uart *)0x400E1A00U)
638 #define UART3 ((Uart *)0x400E1C00U)
639 #define UART4 ((Uart *)0x400E1E00U)
640 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
641 
643 /* ************************************************************************** */
644 /* PIO DEFINITIONS FOR SAME70Q21 */
645 /* ************************************************************************** */
648 
649 #include "pio/same70q21.h"
652 /* ************************************************************************** */
653 /* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */
654 /* ************************************************************************** */
655 
656 #define IFLASH_SIZE (0x200000u)
657 #define IFLASH_PAGE_SIZE (512u)
658 #define IFLASH_LOCK_REGION_SIZE (8192u)
659 #define IFLASH_NB_OF_PAGES (4096u)
660 #define IFLASH_NB_OF_LOCK_BITS (128u)
661 #define IRAM_SIZE (0x60000u)
662 
663 #define QSPIMEM_ADDR (0x80000000u)
664 #define AXIMX_ADDR (0xA0000000u)
665 #define ITCM_ADDR (0x00000000u)
666 #define IFLASH_ADDR (0x00400000u)
667 #define IROM_ADDR (0x00800000u)
668 #define DTCM_ADDR (0x20000000u)
669 #define IRAM_ADDR (0x20400000u)
670 #define EBI_CS0_ADDR (0x60000000u)
671 #define EBI_CS1_ADDR (0x61000000u)
672 #define EBI_CS2_ADDR (0x62000000u)
673 #define EBI_CS3_ADDR (0x63000000u)
674 #define SDRAM_CS_ADDR (0x70000000u)
676 /* ************************************************************************** */
677 /* MISCELLANEOUS DEFINITIONS FOR SAME70Q21 */
678 /* ************************************************************************** */
679 
680 #define CHIP_JTAGID (0x05B3D03FUL)
681 #define CHIP_CIDR (0xA1020E00UL)
682 #define CHIP_EXID (0x00000002UL)
683 
684 /* ************************************************************************** */
685 /* ELECTRICAL DEFINITIONS FOR SAME70Q21 */
686 /* ************************************************************************** */
687 
688 /* %ATMEL_ELECTRICAL% */
689 
690 /* Device characteristics */
691 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
692 #define CHIP_FREQ_SLCK_RC (32000UL)
693 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
694 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
695 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
696 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
697 #define CHIP_FREQ_CPU_MAX (300000000UL)
698 #define CHIP_FREQ_XTAL_32K (32768UL)
699 #define CHIP_FREQ_XTAL_12M (12000000UL)
700 
701 /* Embedded Flash Read Wait State (for Worst-Case Conditions) */
702 #define CHIP_FREQ_FWS_0 (23000000UL)
703 #define CHIP_FREQ_FWS_1 (46000000UL)
704 #define CHIP_FREQ_FWS_2 (69000000UL)
705 #define CHIP_FREQ_FWS_3 (92000000UL)
706 #define CHIP_FREQ_FWS_4 (115000000UL)
707 #define CHIP_FREQ_FWS_5 (138000000UL)
708 #define CHIP_FREQ_FWS_6 (150000000UL)
710 #ifdef __cplusplus
711 }
712 #endif
713 
716 #endif /* _SAME70Q21_ */
SysTick_IRQn
Definition: same70q21.h:73
_DeviceVectors::pfnAFEC1_Handler
void * pfnAFEC1_Handler
Definition: same70j19.h:190
WDT_IRQn
Definition: same70q21.h:80
_DeviceVectors::pfnUART4_Handler
void * pfnUART4_Handler
Definition: same70n19.h:203
TC6_Handler
void TC6_Handler(void)
_DeviceVectors::pfnXDMAC_Handler
void * pfnXDMAC_Handler
Definition: same70j19.h:208
UART0_IRQn
Definition: same70q21.h:83
FPU_IRQn
Definition: same70q21.h:133
_DeviceVectors::pfnUART3_Handler
void * pfnUART3_Handler
Definition: same70n19.h:202
_DeviceVectors::pfnPWM1_Handler
void * pfnPWM1_Handler
Definition: same70j19.h:210
PIOC_Handler
void PIOC_Handler(void)
TC11_IRQn
Definition: same70q21.h:127
SPI1_Handler
void SPI1_Handler(void)
TC7_Handler
void TC7_Handler(void)
QSPI_Handler
void QSPI_Handler(void)
TC3_IRQn
Definition: same70q21.h:101
TC4_IRQn
Definition: same70q21.h:102
CCW_IRQn
Definition: same70q21.h:136
_DeviceVectors::pfnBusFault_Handler
void * pfnBusFault_Handler
Definition: same70j19.h:137
_DeviceVectors::pfnTWIHS1_Handler
void * pfnTWIHS1_Handler
Definition: same70j19.h:170
GMAC_Q1_IRQn
Definition: same70q21.h:138
_DeviceVectors::pvReserved55
void * pvReserved55
Definition: same70j19.h:205
TWIHS0_Handler
void TWIHS0_Handler(void)
_DeviceVectors::pfnPIOB_Handler
void * pfnPIOB_Handler
Definition: same70j19.h:161
MCAN0_INT1_Handler
void MCAN0_INT1_Handler(void)
DebugMon_Handler
void DebugMon_Handler(void)
USBHS_IRQn
Definition: same70q21.h:109
_DeviceVectors::pfnAFEC0_Handler
void * pfnAFEC0_Handler
Definition: same70j19.h:179
_DeviceVectors::pvReserved72
void * pvReserved72
Definition: same70j19.h:222
_DeviceVectors::pfnTC11_Handler
void * pfnTC11_Handler
Definition: same70j19.h:202
_DeviceVectors::pvReserved73
void * pvReserved73
Definition: same70j19.h:223
USART1_IRQn
Definition: same70q21.h:89
HSMCI_Handler
void HSMCI_Handler(void)
TC9_Handler
void TC9_Handler(void)
_DeviceVectors::pfnPIOE_Handler
void * pfnPIOE_Handler
Definition: same70q19.h:184
TC2_IRQn
Definition: same70q21.h:100
BusFault_IRQn
Definition: same70q21.h:68
TWIHS0_IRQn
Definition: same70q21.h:94
PendSV_Handler
void PendSV_Handler(void)
_DeviceVectors::pfnUART2_Handler
void * pfnUART2_Handler
Definition: same70j19.h:194
SDRAMC_Handler
void SDRAMC_Handler(void)
_DeviceVectors::pfnSSC_Handler
void * pfnSSC_Handler
Definition: same70j19.h:172
MCAN0_INT0_IRQn
Definition: same70q21.h:110
_DeviceVectors::pfnISI_Handler
void * pfnISI_Handler
Definition: same70j19.h:209
SSC_IRQn
Definition: same70q21.h:97
NonMaskableInt_IRQn
Definition: same70q21.h:65
_DeviceVectors::pfnHardFault_Handler
void * pfnHardFault_Handler
Definition: same70j19.h:135
TC8_IRQn
Definition: same70q21.h:124
TWIHS1_Handler
void TWIHS1_Handler(void)
EFC_Handler
void EFC_Handler(void)
_DeviceVectors::pfnMCAN1_INT0_Handler
void * pfnMCAN1_INT0_Handler
Definition: same70n19.h:194
_DeviceVectors::pfnSVC_Handler
void * pfnSVC_Handler
Definition: same70j19.h:143
AES_Handler
void AES_Handler(void)
_DeviceVectors::pfnUSART2_Handler
void * pfnUSART2_Handler
Definition: same70n19.h:172
_DeviceVectors::pvReserved71
void * pvReserved71
Definition: same70j19.h:221
UART1_IRQn
Definition: same70q21.h:84
UsageFault_IRQn
Definition: same70q21.h:69
_DeviceVectors::pfnTC4_Handler
void * pfnTC4_Handler
Definition: same70q19.h:194
_DeviceVectors::pvStack
void * pvStack
Definition: same70j19.h:130
TRNG_Handler
void TRNG_Handler(void)
SSC_Handler
void SSC_Handler(void)
Reset_Handler
void Reset_Handler(void)
This is the code that gets called on processor reset. To initialize the device, and call the main() r...
Definition: startup_same70.c:388
_DeviceVectors::pfnRSWDT_Handler
void * pfnRSWDT_Handler
Definition: same70j19.h:213
EFC_IRQn
Definition: same70q21.h:82
_DeviceVectors::pfnUSBHS_Handler
void * pfnUSBHS_Handler
Definition: same70j19.h:184
QSPI_IRQn
Definition: same70q21.h:118
SPI0_Handler
void SPI0_Handler(void)
PIOD_IRQn
Definition: same70q21.h:91
TC7_IRQn
Definition: same70q21.h:123
system_same70.h
_DeviceVectors::pfnTC6_Handler
void * pfnTC6_Handler
Definition: same70q19.h:214
MCAN0_INT1_IRQn
Definition: same70q21.h:111
_DeviceVectors::pfnCCF_Handler
void * pfnCCF_Handler
Definition: same70j19.h:215
TC5_IRQn
Definition: same70q21.h:103
_DeviceVectors::pfnUSART0_Handler
void * pfnUSART0_Handler
Definition: same70j19.h:163
TWIHS2_Handler
void TWIHS2_Handler(void)
_DeviceVectors::pfnPWM0_Handler
void * pfnPWM0_Handler
Definition: same70j19.h:181
_DeviceVectors::pfnSDRAMC_Handler
void * pfnSDRAMC_Handler
Definition: same70q19.h:229
BusFault_Handler
void BusFault_Handler(void)
Definition: rtos.c:211
_DeviceVectors::pfnGMAC_Handler
void * pfnGMAC_Handler
Definition: same70j19.h:189
PWM1_IRQn
Definition: same70q21.h:132
_DeviceVectors::pvReserved9
void * pvReserved9
Definition: same70j19.h:159
HardFault_IRQn
Definition: same70q21.h:66
PWM0_Handler
void PWM0_Handler(void)
_DeviceVectors::pfnMemManage_Handler
void * pfnMemManage_Handler
Definition: same70j19.h:136
PendSV_IRQn
Definition: same70q21.h:72
TC9_IRQn
Definition: same70q21.h:125
PIOA_IRQn
Definition: same70q21.h:85
MCAN1_INT1_Handler
void MCAN1_INT1_Handler(void)
SPI1_IRQn
Definition: same70q21.h:117
RTC_IRQn
Definition: same70q21.h:78
DebugMonitor_IRQn
Definition: same70q21.h:71
_DeviceVectors::pfnDebugMon_Handler
void * pfnDebugMon_Handler
Definition: same70j19.h:144
UART4_IRQn
Definition: same70q21.h:121
SVCall_IRQn
Definition: same70q21.h:70
_DeviceVectors::pfnPIOD_Handler
void * pfnPIOD_Handler
Definition: same70j19.h:166
AFEC1_IRQn
Definition: same70q21.h:115
USART2_Handler
void USART2_Handler(void)
Definition: d_usartDMA.c:1648
TC0_IRQn
Definition: same70q21.h:98
AFEC1_Handler
void AFEC1_Handler(void)
Interrupt handler for AFEC1.
Definition: afec.c:566
_DeviceVectors::pfnTC2_Handler
void * pfnTC2_Handler
Definition: same70j19.h:175
TC10_Handler
void TC10_Handler(void)
PMC_Handler
void PMC_Handler(void)
_DeviceVectors::pfnHSMCI_Handler
void * pfnHSMCI_Handler
Definition: same70n19.h:175
TC1_IRQn
Definition: same70q21.h:99
UART0_Handler
void UART0_Handler(void)
Definition: d_usartDMA.c:1641
UART2_Handler
void UART2_Handler(void)
Definition: d_usartDMA.c:1643
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
_DeviceVectors::pfnReset_Handler
void * pfnReset_Handler
Definition: same70j19.h:133
PIOE_IRQn
Definition: same70q21.h:92
_DeviceVectors::pfnUART1_Handler
void * pfnUART1_Handler
Definition: same70j19.h:158
USBHS_Handler
void USBHS_Handler(void)
Definition: USBD_HAL.c:1008
usbhs.h
TC0_Handler
void TC0_Handler(void)
_DeviceVectors::pfnSysTick_Handler
void * pfnSysTick_Handler
Definition: same70j19.h:147
HSMCI_IRQn
Definition: same70q21.h:93
_DeviceVectors::pfnACC_Handler
void * pfnACC_Handler
Definition: same70j19.h:183
UART3_IRQn
Definition: same70q21.h:120
_DeviceVectors::pfnWDT_Handler
void * pfnWDT_Handler
Definition: same70j19.h:154
USART0_IRQn
Definition: same70q21.h:88
_DeviceVectors::pfnICM_Handler
void * pfnICM_Handler
Definition: same70j19.h:182
PIOE_Handler
void PIOE_Handler(void)
RSTC_IRQn
Definition: same70q21.h:77
SPI0_IRQn
Definition: same70q21.h:96
_DeviceVectors::pfnTC7_Handler
void * pfnTC7_Handler
Definition: same70q19.h:215
_DeviceVectors::pfnCCW_Handler
void * pfnCCW_Handler
Definition: same70j19.h:214
RSWDT_IRQn
Definition: same70q21.h:135
TWIHS1_IRQn
Definition: same70q21.h:95
_DeviceVectors::pfnFPU_Handler
void * pfnFPU_Handler
Definition: same70j19.h:211
ACC_Handler
void ACC_Handler(void)
_DeviceVectors
Definition: same70j19.h:127
_DeviceVectors::pfnIXC_Handler
void * pfnIXC_Handler
Definition: same70j19.h:218
_DeviceVectors::pfnReserved2_Handler
void * pfnReserved2_Handler
Definition: same70j19.h:140
IXC_Handler
void IXC_Handler(void)
PIOB_IRQn
Definition: same70q21.h:86
AFEC0_Handler
void AFEC0_Handler(void)
Interrupt handler for AFEC0.
Definition: afec.c:558
_DeviceVectors::pfnReserved4_Handler
void * pfnReserved4_Handler
Definition: same70j19.h:142
UART2_IRQn
Definition: same70q21.h:119
TWIHS2_IRQn
Definition: same70q21.h:116
_DeviceVectors::pfnRTT_Handler
void * pfnRTT_Handler
Definition: same70j19.h:153
UsageFault_Handler
void UsageFault_Handler(void)
Definition: rtos.c:226
MCAN0_INT0_Handler
void MCAN0_INT0_Handler(void)
PIOA_Handler
void PIOA_Handler(void)
MCAN1_INT1_IRQn
Definition: same70q21.h:113
USART0_Handler
void USART0_Handler(void)
Definition: d_usartDMA.c:1646
_DeviceVectors::pfnUSART1_Handler
void * pfnUSART1_Handler
Definition: same70j19.h:164
UART3_Handler
void UART3_Handler(void)
Definition: d_usartDMA.c:1644
ISI_IRQn
Definition: same70q21.h:131
AES_IRQn
Definition: same70q21.h:128
CCF_Handler
void CCF_Handler(void)
_DeviceVectors::pfnTC5_Handler
void * pfnTC5_Handler
Definition: same70q19.h:195
RSTC_Handler
void RSTC_Handler(void)
CCF_IRQn
Definition: same70q21.h:137
_DeviceVectors::pfnAES_Handler
void * pfnAES_Handler
Definition: same70j19.h:206
SUPC_Handler
void SUPC_Handler(void)
RTC_Handler
void RTC_Handler(void)
RSWDT_Handler
void RSWDT_Handler(void)
TC10_IRQn
Definition: same70q21.h:126
TC6_IRQn
Definition: same70q21.h:122
AFEC0_IRQn
Definition: same70q21.h:104
_DeviceVectors::pfnPendSV_Handler
void * pfnPendSV_Handler
Definition: same70j19.h:146
_DeviceVectors::pvReserved69
void * pvReserved69
Definition: same70j19.h:219
GMAC_Q2_Handler
void GMAC_Q2_Handler(void)
MCAN1_INT0_Handler
void MCAN1_INT0_Handler(void)
_DeviceVectors::pvReserved54
void * pvReserved54
Definition: same70j19.h:204
_DeviceVectors::pfnSPI1_Handler
void * pfnSPI1_Handler
Definition: same70q19.h:209
_DeviceVectors::pfnMCAN1_INT1_Handler
void * pfnMCAN1_INT1_Handler
Definition: same70n19.h:195
MCAN1_INT0_IRQn
Definition: same70q21.h:112
DACC_Handler
void DACC_Handler(void)
UART4_Handler
void UART4_Handler(void)
Definition: d_usartDMA.c:1645
_DeviceVectors::pvReserved53
void * pvReserved53
Definition: same70j19.h:203
SUPC_IRQn
Definition: same70q21.h:76
_DeviceVectors::pfnTC0_Handler
void * pfnTC0_Handler
Definition: same70j19.h:173
ISI_Handler
void ISI_Handler(void)
_DeviceVectors::pfnTWIHS0_Handler
void * pfnTWIHS0_Handler
Definition: same70j19.h:169
USART1_Handler
void USART1_Handler(void)
Definition: d_usartDMA.c:1647
_DeviceVectors::pfnGMAC_Q1_Handler
void * pfnGMAC_Q1_Handler
Definition: same70j19.h:216
_DeviceVectors::pfnDACC_Handler
void * pfnDACC_Handler
Definition: same70j19.h:180
_DeviceVectors::pfnUART0_Handler
void * pfnUART0_Handler
Definition: same70j19.h:157
_DeviceVectors::pfnNMI_Handler
void * pfnNMI_Handler
Definition: same70j19.h:134
PIOD_Handler
void PIOD_Handler(void)
_DeviceVectors::pfnTC9_Handler
void * pfnTC9_Handler
Definition: same70j19.h:200
ICM_Handler
void ICM_Handler(void)
_DeviceVectors::pfnUsageFault_Handler
void * pfnUsageFault_Handler
Definition: same70j19.h:138
GMAC_Q1_Handler
void GMAC_Q1_Handler(void)
_DeviceVectors::pfnTC10_Handler
void * pfnTC10_Handler
Definition: same70j19.h:201
WDT_Handler
void WDT_Handler(void)
IRQn_Type
enum IRQn IRQn_Type
ICM_IRQn
Definition: same70q21.h:107
UART1_Handler
void UART1_Handler(void)
Definition: d_usartDMA.c:1642
PWM1_Handler
void PWM1_Handler(void)
ACC_IRQn
Definition: same70q21.h:108
_DeviceVectors::pfnPIOA_Handler
void * pfnPIOA_Handler
Definition: same70j19.h:160
TC11_Handler
void TC11_Handler(void)
_DeviceVectors::pfnPIOC_Handler
void * pfnPIOC_Handler
Definition: same70q19.h:179
IRQn
IRQn
Definition: same70j19.h:62
_DeviceVectors::pfnEFC_Handler
void * pfnEFC_Handler
Definition: same70j19.h:156
_DeviceVectors::pfnTRNG_Handler
void * pfnTRNG_Handler
Definition: same70j19.h:207
XDMAC_Handler
void XDMAC_Handler(void)
Definition: d_usartDMA.c:704
RTT_Handler
void RTT_Handler(void)
Definition: d_time.c:22
FPU_Handler
void FPU_Handler(void)
GMAC_Q2_IRQn
Definition: same70q21.h:139
TC4_Handler
void TC4_Handler(void)
_DeviceVectors::pfnGMAC_Q2_Handler
void * pfnGMAC_Q2_Handler
Definition: same70j19.h:217
_DeviceVectors::pfnMCAN0_INT0_Handler
void * pfnMCAN0_INT0_Handler
Definition: same70j19.h:185
TC8_Handler
void TC8_Handler(void)
PWM0_IRQn
Definition: same70q21.h:106
MemoryManagement_IRQn
Definition: same70q21.h:67
GMAC_IRQn
Definition: same70q21.h:114
_DeviceVectors::pfnMCAN0_INT1_Handler
void * pfnMCAN0_INT1_Handler
Definition: same70j19.h:186
MemManage_Handler
void MemManage_Handler(void)
Definition: rtos.c:196
TC1_Handler
void TC1_Handler(void)
_DeviceVectors::pfnTWIHS2_Handler
void * pfnTWIHS2_Handler
Definition: same70n19.h:198
_DeviceVectors::pfnRTC_Handler
void * pfnRTC_Handler
Definition: same70j19.h:152
PIOC_IRQn
Definition: same70q21.h:87
TC5_Handler
void TC5_Handler(void)
_DeviceVectors::pfnSPI0_Handler
void * pfnSPI0_Handler
Definition: same70n19.h:178
USART2_IRQn
Definition: same70q21.h:90
_DeviceVectors::pfnReserved3_Handler
void * pfnReserved3_Handler
Definition: same70j19.h:141
TRNG_IRQn
Definition: same70q21.h:129
NMI_Handler
void NMI_Handler(void)
_DeviceVectors::pfnReserved5_Handler
void * pfnReserved5_Handler
Definition: same70j19.h:145
_DeviceVectors::pfnTC1_Handler
void * pfnTC1_Handler
Definition: same70j19.h:174
CCW_Handler
void CCW_Handler(void)
SysTick_Handler
void SysTick_Handler(void)
PERIPH_COUNT_IRQn
Definition: same70q21.h:142
_DeviceVectors::pvReserved70
void * pvReserved70
Definition: same70j19.h:220
PIOB_Handler
void PIOB_Handler(void)
SVC_Handler
void SVC_Handler(void)
GMAC_Handler
void GMAC_Handler(void)
XDMAC_IRQn
Definition: same70q21.h:130
RTT_IRQn
Definition: same70q21.h:79
_DeviceVectors::pfnPMC_Handler
void * pfnPMC_Handler
Definition: same70j19.h:155
_DeviceVectors::pfnQSPI_Handler
void * pfnQSPI_Handler
Definition: same70j19.h:193
_DeviceVectors::pfnRSTC_Handler
void * pfnRSTC_Handler
Definition: same70j19.h:151
_DeviceVectors::pfnSUPC_Handler
void * pfnSUPC_Handler
Definition: same70j19.h:150
DeviceVectors
struct _DeviceVectors DeviceVectors
_DeviceVectors::pfnReserved1_Handler
void * pfnReserved1_Handler
Definition: same70j19.h:139
usbhs.h
HardFault_Handler
void HardFault_Handler(void)
Definition: rtos.c:248
IXC_IRQn
Definition: same70q21.h:140
TC3_Handler
void TC3_Handler(void)
PMC_IRQn
Definition: same70q21.h:81
_DeviceVectors::pfnTC3_Handler
void * pfnTC3_Handler
Definition: same70q19.h:193
TC2_Handler
void TC2_Handler(void)
SDRAMC_IRQn
Definition: same70q21.h:134
_DeviceVectors::pfnTC8_Handler
void * pfnTC8_Handler
Definition: same70q19.h:216
DACC_IRQn
Definition: same70q21.h:105

inertial_sense_ros
Author(s):
autogenerated on Sun Feb 28 2021 03:17:58