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Macros | |
| #define | REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) | 
| (PIOA) Peripheral Select Register  More... | |
| #define | REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) | 
| (PIOA) Additional Interrupt Modes Disable Register  More... | |
| #define | REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) | 
| (PIOA) Additional Interrupt Modes Enable Register  More... | |
| #define | REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) | 
| (PIOA) Additional Interrupt Modes Mask Register  More... | |
| #define | REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) | 
| (PIOA) Clear Output Data Register  More... | |
| #define | REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) | 
| (PIOA) PIO I/O Drive Register  More... | |
| #define | REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) | 
| (PIOA) Edge/Level Status Register  More... | |
| #define | REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) | 
| (PIOA) Edge Select Register  More... | |
| #define | REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) | 
| (PIOA) Falling Edge/Low-Level Select Register  More... | |
| #define | REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) | 
| (PIOA) Fall/Rise - Low/High Status Register  More... | |
| #define | REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) | 
| (PIOA) Interrupt Disable Register  More... | |
| #define | REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) | 
| (PIOA) Interrupt Enable Register  More... | |
| #define | REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) | 
| (PIOA) Glitch Input Filter Disable Register  More... | |
| #define | REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) | 
| (PIOA) Glitch Input Filter Enable Register  More... | |
| #define | REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) | 
| (PIOA) Input Filter Slow Clock Disable Register  More... | |
| #define | REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) | 
| (PIOA) Input Filter Slow Clock Enable Register  More... | |
| #define | REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) | 
| (PIOA) Input Filter Slow Clock Status Register  More... | |
| #define | REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) | 
| (PIOA) Glitch Input Filter Status Register  More... | |
| #define | REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) | 
| (PIOA) Interrupt Mask Register  More... | |
| #define | REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) | 
| (PIOA) Interrupt Status Register  More... | |
| #define | REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) | 
| (PIOA) Keypad Controller Debouncing Register  More... | |
| #define | REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) | 
| (PIOA) Keypad Controller Enable Register  More... | |
| #define | REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) | 
| (PIOA) Keypad Controller Interrupt Disable Register  More... | |
| #define | REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) | 
| (PIOA) Keypad Controller Interrupt Enable Register  More... | |
| #define | REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) | 
| (PIOA) Keypad Controller Interrupt Mask Register  More... | |
| #define | REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) | 
| (PIOA) Keypad Controller Key Press Register  More... | |
| #define | REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) | 
| (PIOA) Keypad Controller Key Release Register  More... | |
| #define | REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) | 
| (PIOA) Keypad Controller Row Column Register  More... | |
| #define | REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) | 
| (PIOA) Keypad Controller Status Register  More... | |
| #define | REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) | 
| (PIOA) Lock Status  More... | |
| #define | REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) | 
| (PIOA) Level Select Register  More... | |
| #define | REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) | 
| (PIOA) Multi-driver Disable Register  More... | |
| #define | REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) | 
| (PIOA) Multi-driver Enable Register  More... | |
| #define | REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) | 
| (PIOA) Multi-driver Status Register  More... | |
| #define | REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) | 
| (PIOA) Output Disable Register  More... | |
| #define | REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) | 
| (PIOA) Output Data Status Register  More... | |
| #define | REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) | 
| (PIOA) Output Enable Register  More... | |
| #define | REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) | 
| (PIOA) Output Status Register  More... | |
| #define | REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) | 
| (PIOA) Output Write Disable  More... | |
| #define | REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) | 
| (PIOA) Output Write Enable  More... | |
| #define | REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) | 
| (PIOA) Output Write Status Register  More... | |
| #define | REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) | 
| (PIOA) Parallel Capture Interrupt Disable Register  More... | |
| #define | REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) | 
| (PIOA) Parallel Capture Interrupt Enable Register  More... | |
| #define | REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) | 
| (PIOA) Parallel Capture Interrupt Mask Register  More... | |
| #define | REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) | 
| (PIOA) Parallel Capture Interrupt Status Register  More... | |
| #define | REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) | 
| (PIOA) Parallel Capture Mode Register  More... | |
| #define | REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) | 
| (PIOA) Parallel Capture Reception Holding Register  More... | |
| #define | REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) | 
| (PIOA) PIO Disable Register  More... | |
| #define | REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) | 
| (PIOA) Pin Data Status Register  More... | |
| #define | REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) | 
| (PIOA) PIO Enable Register  More... | |
| #define | REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) | 
| (PIOA) Pad Pull-down Disable Register  More... | |
| #define | REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) | 
| (PIOA) Pad Pull-down Enable Register  More... | |
| #define | REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) | 
| (PIOA) Pad Pull-down Status Register  More... | |
| #define | REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) | 
| (PIOA) PIO Status Register  More... | |
| #define | REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) | 
| (PIOA) Pull-up Disable Register  More... | |
| #define | REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) | 
| (PIOA) Pull-up Enable Register  More... | |
| #define | REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) | 
| (PIOA) Pad Pull-up Status Register  More... | |
| #define | REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) | 
| (PIOA) Rising Edge/High-Level Select Register  More... | |
| #define | REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) | 
| (PIOA) Slow Clock Divider Debouncing Register  More... | |
| #define | REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) | 
| (PIOA) Schmitt Trigger Register  More... | |
| #define | REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) | 
| (PIOA) Set Output Data Register  More... | |
| #define | REG_PIOA_VERSION (*(__I uint32_t*)0x400E0EFCU) | 
| (PIOA) Version Register  More... | |
| #define | REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) | 
| (PIOA) Write Protection Mode Register  More... | |
| #define | REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) | 
| (PIOA) Write Protection Status Register  More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file pioa.h.
| #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) | 
| #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) | 
| #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) | 
| #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) | 
| #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) | 
| #define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) | 
| #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) | 
| #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) | 
| #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) | 
| #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) | 
| #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) | 
| #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) | 
| #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) | 
| #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) | 
| #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) | 
| #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) | 
| #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) | 
| #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) | 
| #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) | 
| #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) | 
| #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) | 
| #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) | 
| #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) | 
| #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) | 
| #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) | 
| #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) | 
| #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) | 
| #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) | 
| #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) | 
| #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) | 
| #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) | 
| #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) | 
| #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) | 
| #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) | 
| #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) | 
| #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) | 
| #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) | 
| #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) | 
| #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) | 
| #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) | 
| #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) | 
| #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) | 
| #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) | 
| #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) | 
| #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) | 
| #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) | 
| #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) | 
| #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) | 
| #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) | 
| #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) | 
| #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) | 
| #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) | 
| #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) | 
| #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) | 
| #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) | 
| #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) | 
| #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) | 
| #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) | 
| #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) | 
| #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) | 
| #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) | 
| #define REG_PIOA_VERSION (*(__I uint32_t*)0x400E0EFCU) | 
| #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) |