
Go to the source code of this file.
Macros | |
| #define | REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) | 
| (USART2) Baud Rate Generator Register  More... | |
| #define | REG_USART2_CR (*(__O uint32_t*)0x4002C000U) | 
| (USART2) Control Register  More... | |
| #define | REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) | 
| (USART2) Channel Status Register  More... | |
| #define | REG_USART2_FIDI (*(__IO uint32_t*)0x4002C040U) | 
| (USART2) FI DI Ratio Register  More... | |
| #define | REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) | 
| (USART2) IC DIFF Register  More... | |
| #define | REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) | 
| (USART2) Interrupt Disable Register  More... | |
| #define | REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) | 
| (USART2) LON IDT Rx Register  More... | |
| #define | REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) | 
| (USART2) LON IDT Tx Register  More... | |
| #define | REG_USART2_IER (*(__O uint32_t*)0x4002C008U) | 
| (USART2) Interrupt Enable Register  More... | |
| #define | REG_USART2_IF (*(__IO uint32_t*)0x4002C04CU) | 
| (USART2) IrDA Filter Register  More... | |
| #define | REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) | 
| (USART2) Interrupt Mask Register  More... | |
| #define | REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) | 
| (USART2) LIN Baud Rate Register  More... | |
| #define | REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) | 
| (USART2) LIN Identifier Register  More... | |
| #define | REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) | 
| (USART2) LIN Mode Register  More... | |
| #define | REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) | 
| (USART2) LON Beta1 Rx Register  More... | |
| #define | REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) | 
| (USART2) LON Beta1 Tx Register  More... | |
| #define | REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) | 
| (USART2) LON Backlog Register  More... | |
| #define | REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) | 
| (USART2) LON Data Length Register  More... | |
| #define | REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) | 
| (USART2) LON L2HDR Register  More... | |
| #define | REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) | 
| (USART2) LON Mode Register  More... | |
| #define | REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) | 
| (USART2) LON Preamble Register  More... | |
| #define | REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) | 
| (USART2) LON Priority Register  More... | |
| #define | REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) | 
| (USART2) Manchester Configuration Register  More... | |
| #define | REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) | 
| (USART2) Mode Register  More... | |
| #define | REG_USART2_NER (*(__I uint32_t*)0x4002C044U) | 
| (USART2) Number of Errors Register  More... | |
| #define | REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) | 
| (USART2) Receive Holding Register  More... | |
| #define | REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) | 
| (USART2) Receiver Time-out Register  More... | |
| #define | REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) | 
| (USART2) Transmit Holding Register  More... | |
| #define | REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) | 
| (USART2) Transmitter Timeguard Register  More... | |
| #define | REG_USART2_VERSION (*(__I uint32_t*)0x4002C0FCU) | 
| (USART2) Version Register  More... | |
| #define | REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) | 
| (USART2) Write Protection Mode Register  More... | |
| #define | REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) | 
| (USART2) Write Protection Status Register  More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file usart2.h.
| #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) | 
| #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) | 
| #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) | 
| #define REG_USART2_FIDI (*(__IO uint32_t*)0x4002C040U) | 
| #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) | 
| #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) | 
| #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) | 
| #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) | 
| #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) | 
| #define REG_USART2_IF (*(__IO uint32_t*)0x4002C04CU) | 
| #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) | 
| #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) | 
| #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) | 
| #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) | 
| #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) | 
| #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) | 
| #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) | 
| #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) | 
| #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) | 
| #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) | 
| #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) | 
| #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) | 
| #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) | 
| #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) | 
| #define REG_USART2_NER (*(__I uint32_t*)0x4002C044U) | 
| #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) | 
| #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) | 
| #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) | 
| #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) | 
| #define REG_USART2_VERSION (*(__I uint32_t*)0x4002C0FCU) | 
| #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) |