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Macros
#define	REG_PWM1_CCNT0 ((__I uint32_t)0x4005C214U)
	(PWM1) PWM Channel Counter Register (ch_num = 0) More...

#define	REG_PWM1_CCNT1 ((__I uint32_t)0x4005C234U)
	(PWM1) PWM Channel Counter Register (ch_num = 1) More...

#define	REG_PWM1_CCNT2 ((__I uint32_t)0x4005C254U)
	(PWM1) PWM Channel Counter Register (ch_num = 2) More...

#define	REG_PWM1_CCNT3 ((__I uint32_t)0x4005C274U)
	(PWM1) PWM Channel Counter Register (ch_num = 3) More...

#define	REG_PWM1_CDTY0 ((__IO uint32_t)0x4005C204U)
	(PWM1) PWM Channel Duty Cycle Register (ch_num = 0) More...

#define	REG_PWM1_CDTY1 ((__IO uint32_t)0x4005C224U)
	(PWM1) PWM Channel Duty Cycle Register (ch_num = 1) More...

#define	REG_PWM1_CDTY2 ((__IO uint32_t)0x4005C244U)
	(PWM1) PWM Channel Duty Cycle Register (ch_num = 2) More...

#define	REG_PWM1_CDTY3 ((__IO uint32_t)0x4005C264U)
	(PWM1) PWM Channel Duty Cycle Register (ch_num = 3) More...

#define	REG_PWM1_CDTYUPD0 ((__O uint32_t)0x4005C208U)
	(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) More...

#define	REG_PWM1_CDTYUPD1 ((__O uint32_t)0x4005C228U)
	(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) More...

#define	REG_PWM1_CDTYUPD2 ((__O uint32_t)0x4005C248U)
	(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) More...

#define	REG_PWM1_CDTYUPD3 ((__O uint32_t)0x4005C268U)
	(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) More...

#define	REG_PWM1_CLK ((__IO uint32_t)0x4005C000U)
	(PWM1) PWM Clock Register More...

#define	REG_PWM1_CMPM0 ((__IO uint32_t)0x4005C138U)
	(PWM1) PWM Comparison 0 Mode Register More...

#define	REG_PWM1_CMPM1 ((__IO uint32_t)0x4005C148U)
	(PWM1) PWM Comparison 1 Mode Register More...

#define	REG_PWM1_CMPM2 ((__IO uint32_t)0x4005C158U)
	(PWM1) PWM Comparison 2 Mode Register More...

#define	REG_PWM1_CMPM3 ((__IO uint32_t)0x4005C168U)
	(PWM1) PWM Comparison 3 Mode Register More...

#define	REG_PWM1_CMPM4 ((__IO uint32_t)0x4005C178U)
	(PWM1) PWM Comparison 4 Mode Register More...

#define	REG_PWM1_CMPM5 ((__IO uint32_t)0x4005C188U)
	(PWM1) PWM Comparison 5 Mode Register More...

#define	REG_PWM1_CMPM6 ((__IO uint32_t)0x4005C198U)
	(PWM1) PWM Comparison 6 Mode Register More...

#define	REG_PWM1_CMPM7 ((__IO uint32_t)0x4005C1A8U)
	(PWM1) PWM Comparison 7 Mode Register More...

#define	REG_PWM1_CMPMUPD0 ((__O uint32_t)0x4005C13CU)
	(PWM1) PWM Comparison 0 Mode Update Register More...

#define	REG_PWM1_CMPMUPD1 ((__O uint32_t)0x4005C14CU)
	(PWM1) PWM Comparison 1 Mode Update Register More...

#define	REG_PWM1_CMPMUPD2 ((__O uint32_t)0x4005C15CU)
	(PWM1) PWM Comparison 2 Mode Update Register More...

#define	REG_PWM1_CMPMUPD3 ((__O uint32_t)0x4005C16CU)
	(PWM1) PWM Comparison 3 Mode Update Register More...

#define	REG_PWM1_CMPMUPD4 ((__O uint32_t)0x4005C17CU)
	(PWM1) PWM Comparison 4 Mode Update Register More...

#define	REG_PWM1_CMPMUPD5 ((__O uint32_t)0x4005C18CU)
	(PWM1) PWM Comparison 5 Mode Update Register More...

#define	REG_PWM1_CMPMUPD6 ((__O uint32_t)0x4005C19CU)
	(PWM1) PWM Comparison 6 Mode Update Register More...

#define	REG_PWM1_CMPMUPD7 ((__O uint32_t)0x4005C1ACU)
	(PWM1) PWM Comparison 7 Mode Update Register More...

#define	REG_PWM1_CMPV0 ((__IO uint32_t)0x4005C130U)
	(PWM1) PWM Comparison 0 Value Register More...

#define	REG_PWM1_CMPV1 ((__IO uint32_t)0x4005C140U)
	(PWM1) PWM Comparison 1 Value Register More...

#define	REG_PWM1_CMPV2 ((__IO uint32_t)0x4005C150U)
	(PWM1) PWM Comparison 2 Value Register More...

#define	REG_PWM1_CMPV3 ((__IO uint32_t)0x4005C160U)
	(PWM1) PWM Comparison 3 Value Register More...

#define	REG_PWM1_CMPV4 ((__IO uint32_t)0x4005C170U)
	(PWM1) PWM Comparison 4 Value Register More...

#define	REG_PWM1_CMPV5 ((__IO uint32_t)0x4005C180U)
	(PWM1) PWM Comparison 5 Value Register More...

#define	REG_PWM1_CMPV6 ((__IO uint32_t)0x4005C190U)
	(PWM1) PWM Comparison 6 Value Register More...

#define	REG_PWM1_CMPV7 ((__IO uint32_t)0x4005C1A0U)
	(PWM1) PWM Comparison 7 Value Register More...

#define	REG_PWM1_CMPVUPD0 ((__O uint32_t)0x4005C134U)
	(PWM1) PWM Comparison 0 Value Update Register More...

#define	REG_PWM1_CMPVUPD1 ((__O uint32_t)0x4005C144U)
	(PWM1) PWM Comparison 1 Value Update Register More...

#define	REG_PWM1_CMPVUPD2 ((__O uint32_t)0x4005C154U)
	(PWM1) PWM Comparison 2 Value Update Register More...

#define	REG_PWM1_CMPVUPD3 ((__O uint32_t)0x4005C164U)
	(PWM1) PWM Comparison 3 Value Update Register More...

#define	REG_PWM1_CMPVUPD4 ((__O uint32_t)0x4005C174U)
	(PWM1) PWM Comparison 4 Value Update Register More...

#define	REG_PWM1_CMPVUPD5 ((__O uint32_t)0x4005C184U)
	(PWM1) PWM Comparison 5 Value Update Register More...

#define	REG_PWM1_CMPVUPD6 ((__O uint32_t)0x4005C194U)
	(PWM1) PWM Comparison 6 Value Update Register More...

#define	REG_PWM1_CMPVUPD7 ((__O uint32_t)0x4005C1A4U)
	(PWM1) PWM Comparison 7 Value Update Register More...

#define	REG_PWM1_CMR0 ((__IO uint32_t)0x4005C200U)
	(PWM1) PWM Channel Mode Register (ch_num = 0) More...

#define	REG_PWM1_CMR1 ((__IO uint32_t)0x4005C220U)
	(PWM1) PWM Channel Mode Register (ch_num = 1) More...

#define	REG_PWM1_CMR2 ((__IO uint32_t)0x4005C240U)
	(PWM1) PWM Channel Mode Register (ch_num = 2) More...

#define	REG_PWM1_CMR3 ((__IO uint32_t)0x4005C260U)
	(PWM1) PWM Channel Mode Register (ch_num = 3) More...

#define	REG_PWM1_CMUPD0 ((__O uint32_t)0x4005C400U)
	(PWM1) PWM Channel Mode Update Register (ch_num = 0) More...

#define	REG_PWM1_CMUPD1 ((__O uint32_t)0x4005C420U)
	(PWM1) PWM Channel Mode Update Register (ch_num = 1) More...

#define	REG_PWM1_CMUPD2 ((__O uint32_t)0x4005C440U)
	(PWM1) PWM Channel Mode Update Register (ch_num = 2) More...

#define	REG_PWM1_CMUPD3 ((__O uint32_t)0x4005C460U)
	(PWM1) PWM Channel Mode Update Register (ch_num = 3) More...

#define	REG_PWM1_CPRD0 ((__IO uint32_t)0x4005C20CU)
	(PWM1) PWM Channel Period Register (ch_num = 0) More...

#define	REG_PWM1_CPRD1 ((__IO uint32_t)0x4005C22CU)
	(PWM1) PWM Channel Period Register (ch_num = 1) More...

#define	REG_PWM1_CPRD2 ((__IO uint32_t)0x4005C24CU)
	(PWM1) PWM Channel Period Register (ch_num = 2) More...

#define	REG_PWM1_CPRD3 ((__IO uint32_t)0x4005C26CU)
	(PWM1) PWM Channel Period Register (ch_num = 3) More...

#define	REG_PWM1_CPRDUPD0 ((__O uint32_t)0x4005C210U)
	(PWM1) PWM Channel Period Update Register (ch_num = 0) More...

#define	REG_PWM1_CPRDUPD1 ((__O uint32_t)0x4005C230U)
	(PWM1) PWM Channel Period Update Register (ch_num = 1) More...

#define	REG_PWM1_CPRDUPD2 ((__O uint32_t)0x4005C250U)
	(PWM1) PWM Channel Period Update Register (ch_num = 2) More...

#define	REG_PWM1_CPRDUPD3 ((__O uint32_t)0x4005C270U)
	(PWM1) PWM Channel Period Update Register (ch_num = 3) More...

#define	REG_PWM1_DIS ((__O uint32_t)0x4005C008U)
	(PWM1) PWM Disable Register More...

#define	REG_PWM1_DMAR ((__O uint32_t)0x4005C024U)
	(PWM1) PWM DMA Register More...

#define	REG_PWM1_DT0 ((__IO uint32_t)0x4005C218U)
	(PWM1) PWM Channel Dead Time Register (ch_num = 0) More...

#define	REG_PWM1_DT1 ((__IO uint32_t)0x4005C238U)
	(PWM1) PWM Channel Dead Time Register (ch_num = 1) More...

#define	REG_PWM1_DT2 ((__IO uint32_t)0x4005C258U)
	(PWM1) PWM Channel Dead Time Register (ch_num = 2) More...

#define	REG_PWM1_DT3 ((__IO uint32_t)0x4005C278U)
	(PWM1) PWM Channel Dead Time Register (ch_num = 3) More...

#define	REG_PWM1_DTUPD0 ((__O uint32_t)0x4005C21CU)
	(PWM1) PWM Channel Dead Time Update Register (ch_num = 0) More...

#define	REG_PWM1_DTUPD1 ((__O uint32_t)0x4005C23CU)
	(PWM1) PWM Channel Dead Time Update Register (ch_num = 1) More...

#define	REG_PWM1_DTUPD2 ((__O uint32_t)0x4005C25CU)
	(PWM1) PWM Channel Dead Time Update Register (ch_num = 2) More...

#define	REG_PWM1_DTUPD3 ((__O uint32_t)0x4005C27CU)
	(PWM1) PWM Channel Dead Time Update Register (ch_num = 3) More...

#define	REG_PWM1_ELMR ((__IO uint32_t)0x4005C07CU)
	(PWM1) PWM Event Line 0 Mode Register More...

#define	REG_PWM1_ENA ((__O uint32_t)0x4005C004U)
	(PWM1) PWM Enable Register More...

#define	REG_PWM1_ETRG1 ((__IO uint32_t)0x4005C42CU)
	(PWM1) PWM External Trigger Register (trg_num = 1) More...

#define	REG_PWM1_ETRG2 ((__IO uint32_t)0x4005C44CU)
	(PWM1) PWM External Trigger Register (trg_num = 2) More...

#define	REG_PWM1_FCR ((__O uint32_t)0x4005C064U)
	(PWM1) PWM Fault Clear Register More...

#define	REG_PWM1_FMR ((__IO uint32_t)0x4005C05CU)
	(PWM1) PWM Fault Mode Register More...

#define	REG_PWM1_FPE ((__IO uint32_t)0x4005C06CU)
	(PWM1) PWM Fault Protection Enable Register More...

#define	REG_PWM1_FPV1 ((__IO uint32_t)0x4005C068U)
	(PWM1) PWM Fault Protection Value Register 1 More...

#define	REG_PWM1_FPV2 ((__IO uint32_t)0x4005C0C0U)
	(PWM1) PWM Fault Protection Value 2 Register More...

#define	REG_PWM1_FSR ((__I uint32_t)0x4005C060U)
	(PWM1) PWM Fault Status Register More...

#define	REG_PWM1_IDR1 ((__O uint32_t)0x4005C014U)
	(PWM1) PWM Interrupt Disable Register 1 More...

#define	REG_PWM1_IDR2 ((__O uint32_t)0x4005C038U)
	(PWM1) PWM Interrupt Disable Register 2 More...

#define	REG_PWM1_IER1 ((__O uint32_t)0x4005C010U)
	(PWM1) PWM Interrupt Enable Register 1 More...

#define	REG_PWM1_IER2 ((__O uint32_t)0x4005C034U)
	(PWM1) PWM Interrupt Enable Register 2 More...

#define	REG_PWM1_IMR1 ((__I uint32_t)0x4005C018U)
	(PWM1) PWM Interrupt Mask Register 1 More...

#define	REG_PWM1_IMR2 ((__I uint32_t)0x4005C03CU)
	(PWM1) PWM Interrupt Mask Register 2 More...

#define	REG_PWM1_ISR1 ((__I uint32_t)0x4005C01CU)
	(PWM1) PWM Interrupt Status Register 1 More...

#define	REG_PWM1_ISR2 ((__I uint32_t)0x4005C040U)
	(PWM1) PWM Interrupt Status Register 2 More...

#define	REG_PWM1_LEBR1 ((__IO uint32_t)0x4005C430U)
	(PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) More...

#define	REG_PWM1_LEBR2 ((__IO uint32_t)0x4005C450U)
	(PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) More...

#define	REG_PWM1_OOV ((__IO uint32_t)0x4005C044U)
	(PWM1) PWM Output Override Value Register More...

#define	REG_PWM1_OS ((__IO uint32_t)0x4005C048U)
	(PWM1) PWM Output Selection Register More...

#define	REG_PWM1_OSC ((__O uint32_t)0x4005C050U)
	(PWM1) PWM Output Selection Clear Register More...

#define	REG_PWM1_OSCUPD ((__O uint32_t)0x4005C058U)
	(PWM1) PWM Output Selection Clear Update Register More...

#define	REG_PWM1_OSS ((__O uint32_t)0x4005C04CU)
	(PWM1) PWM Output Selection Set Register More...

#define	REG_PWM1_OSSUPD ((__O uint32_t)0x4005C054U)
	(PWM1) PWM Output Selection Set Update Register More...

#define	REG_PWM1_SCM ((__IO uint32_t)0x4005C020U)
	(PWM1) PWM Sync Channels Mode Register More...

#define	REG_PWM1_SCUC ((__IO uint32_t)0x4005C028U)
	(PWM1) PWM Sync Channels Update Control Register More...

#define	REG_PWM1_SCUP ((__IO uint32_t)0x4005C02CU)
	(PWM1) PWM Sync Channels Update Period Register More...

#define	REG_PWM1_SCUPUPD ((__O uint32_t)0x4005C030U)
	(PWM1) PWM Sync Channels Update Period Update Register More...

#define	REG_PWM1_SMMR ((__IO uint32_t)0x4005C0B0U)
	(PWM1) PWM Stepper Motor Mode Register More...

#define	REG_PWM1_SR ((__I uint32_t)0x4005C00CU)
	(PWM1) PWM Status Register More...

#define	REG_PWM1_SSPR ((__IO uint32_t)0x4005C0A0U)
	(PWM1) PWM Spread Spectrum Register More...

#define	REG_PWM1_SSPUP ((__O uint32_t)0x4005C0A4U)
	(PWM1) PWM Spread Spectrum Update Register More...

#define	REG_PWM1_VERSION ((__I uint32_t)0x4005C0FCU)
	(PWM1) Version Register More...

#define	REG_PWM1_WPCR ((__O uint32_t)0x4005C0E4U)
	(PWM1) PWM Write Protection Control Register More...

#define	REG_PWM1_WPSR ((__I uint32_t)0x4005C0E8U)
	(PWM1) PWM Write Protection Status Register More...

Detailed Description

Definition in file pwm1.h.

Macro Definition Documentation

◆ REG_PWM1_CCNT0

#define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U)

(PWM1) PWM Channel Counter Register (ch_num = 0)

Definition at line 222 of file pwm1.h.

◆ REG_PWM1_CCNT1

#define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U)

(PWM1) PWM Channel Counter Register (ch_num = 1)

Definition at line 230 of file pwm1.h.

◆ REG_PWM1_CCNT2

#define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U)

(PWM1) PWM Channel Counter Register (ch_num = 2)

Definition at line 238 of file pwm1.h.

◆ REG_PWM1_CCNT3

#define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U)

(PWM1) PWM Channel Counter Register (ch_num = 3)

Definition at line 246 of file pwm1.h.

◆ REG_PWM1_CDTY0

#define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U)

(PWM1) PWM Channel Duty Cycle Register (ch_num = 0)

Definition at line 218 of file pwm1.h.

◆ REG_PWM1_CDTY1

#define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U)

(PWM1) PWM Channel Duty Cycle Register (ch_num = 1)

Definition at line 226 of file pwm1.h.

◆ REG_PWM1_CDTY2

#define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U)

(PWM1) PWM Channel Duty Cycle Register (ch_num = 2)

Definition at line 234 of file pwm1.h.

◆ REG_PWM1_CDTY3

#define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U)

(PWM1) PWM Channel Duty Cycle Register (ch_num = 3)

Definition at line 242 of file pwm1.h.

◆ REG_PWM1_CDTYUPD0

#define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U)

(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0)

Definition at line 219 of file pwm1.h.

◆ REG_PWM1_CDTYUPD1

#define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U)

(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1)

Definition at line 227 of file pwm1.h.

◆ REG_PWM1_CDTYUPD2

#define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U)

(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2)

Definition at line 235 of file pwm1.h.

◆ REG_PWM1_CDTYUPD3

#define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U)

(PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3)

Definition at line 243 of file pwm1.h.

◆ REG_PWM1_CLK

#define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U)

(PWM1) PWM Clock Register

Definition at line 149 of file pwm1.h.

◆ REG_PWM1_CMPM0

#define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U)

(PWM1) PWM Comparison 0 Mode Register

Definition at line 187 of file pwm1.h.

◆ REG_PWM1_CMPM1

#define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U)

(PWM1) PWM Comparison 1 Mode Register

Definition at line 191 of file pwm1.h.

◆ REG_PWM1_CMPM2

#define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U)

(PWM1) PWM Comparison 2 Mode Register

Definition at line 195 of file pwm1.h.

◆ REG_PWM1_CMPM3

#define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U)

(PWM1) PWM Comparison 3 Mode Register

Definition at line 199 of file pwm1.h.

◆ REG_PWM1_CMPM4

#define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U)

(PWM1) PWM Comparison 4 Mode Register

Definition at line 203 of file pwm1.h.

◆ REG_PWM1_CMPM5

#define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U)

(PWM1) PWM Comparison 5 Mode Register

Definition at line 207 of file pwm1.h.

◆ REG_PWM1_CMPM6

#define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U)

(PWM1) PWM Comparison 6 Mode Register

Definition at line 211 of file pwm1.h.

◆ REG_PWM1_CMPM7

#define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U)

(PWM1) PWM Comparison 7 Mode Register

Definition at line 215 of file pwm1.h.

◆ REG_PWM1_CMPMUPD0

#define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU)

(PWM1) PWM Comparison 0 Mode Update Register

Definition at line 188 of file pwm1.h.

◆ REG_PWM1_CMPMUPD1

#define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU)

(PWM1) PWM Comparison 1 Mode Update Register

Definition at line 192 of file pwm1.h.

◆ REG_PWM1_CMPMUPD2

#define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU)

(PWM1) PWM Comparison 2 Mode Update Register

Definition at line 196 of file pwm1.h.

◆ REG_PWM1_CMPMUPD3

#define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU)

(PWM1) PWM Comparison 3 Mode Update Register

Definition at line 200 of file pwm1.h.

◆ REG_PWM1_CMPMUPD4

#define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU)

(PWM1) PWM Comparison 4 Mode Update Register

Definition at line 204 of file pwm1.h.

◆ REG_PWM1_CMPMUPD5

#define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU)

(PWM1) PWM Comparison 5 Mode Update Register

Definition at line 208 of file pwm1.h.

◆ REG_PWM1_CMPMUPD6

#define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU)

(PWM1) PWM Comparison 6 Mode Update Register

Definition at line 212 of file pwm1.h.

◆ REG_PWM1_CMPMUPD7

#define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU)

(PWM1) PWM Comparison 7 Mode Update Register

Definition at line 216 of file pwm1.h.

◆ REG_PWM1_CMPV0

#define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U)

(PWM1) PWM Comparison 0 Value Register

Definition at line 185 of file pwm1.h.

◆ REG_PWM1_CMPV1

#define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U)

(PWM1) PWM Comparison 1 Value Register

Definition at line 189 of file pwm1.h.

◆ REG_PWM1_CMPV2

#define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U)

(PWM1) PWM Comparison 2 Value Register

Definition at line 193 of file pwm1.h.

◆ REG_PWM1_CMPV3

#define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U)

(PWM1) PWM Comparison 3 Value Register

Definition at line 197 of file pwm1.h.

◆ REG_PWM1_CMPV4

#define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U)

(PWM1) PWM Comparison 4 Value Register

Definition at line 201 of file pwm1.h.

◆ REG_PWM1_CMPV5

#define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U)

(PWM1) PWM Comparison 5 Value Register

Definition at line 205 of file pwm1.h.

◆ REG_PWM1_CMPV6

#define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U)

(PWM1) PWM Comparison 6 Value Register

Definition at line 209 of file pwm1.h.

◆ REG_PWM1_CMPV7

#define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U)

(PWM1) PWM Comparison 7 Value Register

Definition at line 213 of file pwm1.h.

◆ REG_PWM1_CMPVUPD0

#define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U)

(PWM1) PWM Comparison 0 Value Update Register

Definition at line 186 of file pwm1.h.

◆ REG_PWM1_CMPVUPD1

#define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U)

(PWM1) PWM Comparison 1 Value Update Register

Definition at line 190 of file pwm1.h.

◆ REG_PWM1_CMPVUPD2

#define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U)

(PWM1) PWM Comparison 2 Value Update Register

Definition at line 194 of file pwm1.h.

◆ REG_PWM1_CMPVUPD3

#define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U)

(PWM1) PWM Comparison 3 Value Update Register

Definition at line 198 of file pwm1.h.

◆ REG_PWM1_CMPVUPD4

#define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U)

(PWM1) PWM Comparison 4 Value Update Register

Definition at line 202 of file pwm1.h.

◆ REG_PWM1_CMPVUPD5

#define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U)

(PWM1) PWM Comparison 5 Value Update Register

Definition at line 206 of file pwm1.h.

◆ REG_PWM1_CMPVUPD6

#define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U)

(PWM1) PWM Comparison 6 Value Update Register

Definition at line 210 of file pwm1.h.

◆ REG_PWM1_CMPVUPD7

#define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U)

(PWM1) PWM Comparison 7 Value Update Register

Definition at line 214 of file pwm1.h.

◆ REG_PWM1_CMR0

#define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U)

(PWM1) PWM Channel Mode Register (ch_num = 0)

Definition at line 217 of file pwm1.h.

◆ REG_PWM1_CMR1

#define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U)

(PWM1) PWM Channel Mode Register (ch_num = 1)

Definition at line 225 of file pwm1.h.

◆ REG_PWM1_CMR2

#define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U)

(PWM1) PWM Channel Mode Register (ch_num = 2)

Definition at line 233 of file pwm1.h.

◆ REG_PWM1_CMR3

#define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U)

(PWM1) PWM Channel Mode Register (ch_num = 3)

Definition at line 241 of file pwm1.h.

◆ REG_PWM1_CMUPD0

#define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U)

(PWM1) PWM Channel Mode Update Register (ch_num = 0)

Definition at line 249 of file pwm1.h.

◆ REG_PWM1_CMUPD1

#define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U)

(PWM1) PWM Channel Mode Update Register (ch_num = 1)

Definition at line 250 of file pwm1.h.

◆ REG_PWM1_CMUPD2

#define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U)

(PWM1) PWM Channel Mode Update Register (ch_num = 2)

Definition at line 253 of file pwm1.h.

◆ REG_PWM1_CMUPD3

#define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U)

(PWM1) PWM Channel Mode Update Register (ch_num = 3)

Definition at line 256 of file pwm1.h.

◆ REG_PWM1_CPRD0

#define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU)

(PWM1) PWM Channel Period Register (ch_num = 0)

Definition at line 220 of file pwm1.h.

◆ REG_PWM1_CPRD1

#define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU)

(PWM1) PWM Channel Period Register (ch_num = 1)

Definition at line 228 of file pwm1.h.

◆ REG_PWM1_CPRD2

#define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU)

(PWM1) PWM Channel Period Register (ch_num = 2)

Definition at line 236 of file pwm1.h.

◆ REG_PWM1_CPRD3

#define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU)

(PWM1) PWM Channel Period Register (ch_num = 3)

Definition at line 244 of file pwm1.h.

◆ REG_PWM1_CPRDUPD0

#define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U)

(PWM1) PWM Channel Period Update Register (ch_num = 0)

Definition at line 221 of file pwm1.h.

◆ REG_PWM1_CPRDUPD1

#define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U)

(PWM1) PWM Channel Period Update Register (ch_num = 1)

Definition at line 229 of file pwm1.h.

◆ REG_PWM1_CPRDUPD2

#define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U)

(PWM1) PWM Channel Period Update Register (ch_num = 2)

Definition at line 237 of file pwm1.h.

◆ REG_PWM1_CPRDUPD3

#define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U)

(PWM1) PWM Channel Period Update Register (ch_num = 3)

Definition at line 245 of file pwm1.h.

◆ REG_PWM1_DIS

#define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U)

(PWM1) PWM Disable Register

Definition at line 151 of file pwm1.h.

◆ REG_PWM1_DMAR

#define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U)

(PWM1) PWM DMA Register

Definition at line 158 of file pwm1.h.

◆ REG_PWM1_DT0

#define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U)

(PWM1) PWM Channel Dead Time Register (ch_num = 0)

Definition at line 223 of file pwm1.h.

◆ REG_PWM1_DT1

#define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U)

(PWM1) PWM Channel Dead Time Register (ch_num = 1)

Definition at line 231 of file pwm1.h.

◆ REG_PWM1_DT2

#define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U)

(PWM1) PWM Channel Dead Time Register (ch_num = 2)

Definition at line 239 of file pwm1.h.

◆ REG_PWM1_DT3

#define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U)

(PWM1) PWM Channel Dead Time Register (ch_num = 3)

Definition at line 247 of file pwm1.h.

◆ REG_PWM1_DTUPD0

#define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU)

(PWM1) PWM Channel Dead Time Update Register (ch_num = 0)

Definition at line 224 of file pwm1.h.

◆ REG_PWM1_DTUPD1

#define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU)

(PWM1) PWM Channel Dead Time Update Register (ch_num = 1)

Definition at line 232 of file pwm1.h.

◆ REG_PWM1_DTUPD2

#define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU)

(PWM1) PWM Channel Dead Time Update Register (ch_num = 2)

Definition at line 240 of file pwm1.h.

◆ REG_PWM1_DTUPD3

#define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU)

(PWM1) PWM Channel Dead Time Update Register (ch_num = 3)

Definition at line 248 of file pwm1.h.

◆ REG_PWM1_ELMR

#define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU)

(PWM1) PWM Event Line 0 Mode Register

Definition at line 177 of file pwm1.h.

◆ REG_PWM1_ENA

#define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U)

(PWM1) PWM Enable Register

Definition at line 150 of file pwm1.h.

◆ REG_PWM1_ETRG1

#define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU)

(PWM1) PWM External Trigger Register (trg_num = 1)

Definition at line 251 of file pwm1.h.

◆ REG_PWM1_ETRG2

#define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU)

(PWM1) PWM External Trigger Register (trg_num = 2)

Definition at line 254 of file pwm1.h.

◆ REG_PWM1_FCR

#define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U)

(PWM1) PWM Fault Clear Register

Definition at line 174 of file pwm1.h.

◆ REG_PWM1_FMR

#define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU)

(PWM1) PWM Fault Mode Register

Definition at line 172 of file pwm1.h.

◆ REG_PWM1_FPE

#define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU)

(PWM1) PWM Fault Protection Enable Register

Definition at line 176 of file pwm1.h.

◆ REG_PWM1_FPV1

#define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U)

(PWM1) PWM Fault Protection Value Register 1

Definition at line 175 of file pwm1.h.

◆ REG_PWM1_FPV2

#define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U)

(PWM1) PWM Fault Protection Value 2 Register

Definition at line 181 of file pwm1.h.

◆ REG_PWM1_FSR

#define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U)

(PWM1) PWM Fault Status Register

Definition at line 173 of file pwm1.h.

◆ REG_PWM1_IDR1

#define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U)

(PWM1) PWM Interrupt Disable Register 1

Definition at line 154 of file pwm1.h.

◆ REG_PWM1_IDR2

#define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U)

(PWM1) PWM Interrupt Disable Register 2

Definition at line 163 of file pwm1.h.

◆ REG_PWM1_IER1

#define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U)

(PWM1) PWM Interrupt Enable Register 1

Definition at line 153 of file pwm1.h.

◆ REG_PWM1_IER2

#define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U)

(PWM1) PWM Interrupt Enable Register 2

Definition at line 162 of file pwm1.h.

◆ REG_PWM1_IMR1

#define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U)

(PWM1) PWM Interrupt Mask Register 1

Definition at line 155 of file pwm1.h.

◆ REG_PWM1_IMR2

#define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU)

(PWM1) PWM Interrupt Mask Register 2

Definition at line 164 of file pwm1.h.

◆ REG_PWM1_ISR1

#define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU)

(PWM1) PWM Interrupt Status Register 1

Definition at line 156 of file pwm1.h.

◆ REG_PWM1_ISR2

#define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U)

(PWM1) PWM Interrupt Status Register 2

Definition at line 165 of file pwm1.h.

◆ REG_PWM1_LEBR1

#define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U)

(PWM1) PWM Leading-Edge Blanking Register (trg_num = 1)

Definition at line 252 of file pwm1.h.

◆ REG_PWM1_LEBR2

#define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U)

(PWM1) PWM Leading-Edge Blanking Register (trg_num = 2)

Definition at line 255 of file pwm1.h.

◆ REG_PWM1_OOV

#define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U)

(PWM1) PWM Output Override Value Register

Definition at line 166 of file pwm1.h.

◆ REG_PWM1_OS

#define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U)

(PWM1) PWM Output Selection Register

Definition at line 167 of file pwm1.h.

◆ REG_PWM1_OSC

#define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U)

(PWM1) PWM Output Selection Clear Register

Definition at line 169 of file pwm1.h.

◆ REG_PWM1_OSCUPD

#define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U)

(PWM1) PWM Output Selection Clear Update Register

Definition at line 171 of file pwm1.h.

◆ REG_PWM1_OSS

#define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU)

(PWM1) PWM Output Selection Set Register

Definition at line 168 of file pwm1.h.

◆ REG_PWM1_OSSUPD

#define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U)

(PWM1) PWM Output Selection Set Update Register

Definition at line 170 of file pwm1.h.

◆ REG_PWM1_SCM

#define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U)

(PWM1) PWM Sync Channels Mode Register

Definition at line 157 of file pwm1.h.

◆ REG_PWM1_SCUC

#define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U)

(PWM1) PWM Sync Channels Update Control Register

Definition at line 159 of file pwm1.h.

◆ REG_PWM1_SCUP

#define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU)

(PWM1) PWM Sync Channels Update Period Register

Definition at line 160 of file pwm1.h.

◆ REG_PWM1_SCUPUPD

#define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U)

(PWM1) PWM Sync Channels Update Period Update Register

Definition at line 161 of file pwm1.h.

◆ REG_PWM1_SMMR

#define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U)

(PWM1) PWM Stepper Motor Mode Register

Definition at line 180 of file pwm1.h.

◆ REG_PWM1_SR

#define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU)

(PWM1) PWM Status Register

Definition at line 152 of file pwm1.h.

◆ REG_PWM1_SSPR

#define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U)

(PWM1) PWM Spread Spectrum Register

Definition at line 178 of file pwm1.h.

◆ REG_PWM1_SSPUP

#define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U)

(PWM1) PWM Spread Spectrum Update Register

Definition at line 179 of file pwm1.h.

◆ REG_PWM1_VERSION

#define REG_PWM1_VERSION (*(__I uint32_t*)0x4005C0FCU)

(PWM1) Version Register

Definition at line 184 of file pwm1.h.

◆ REG_PWM1_WPCR

#define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U)

(PWM1) PWM Write Protection Control Register

Definition at line 182 of file pwm1.h.

◆ REG_PWM1_WPSR

#define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U)

(PWM1) PWM Write Protection Status Register

Definition at line 183 of file pwm1.h.

Macros