Go to the source code of this file.
Macros | |
| #define | REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) |
| (USBHS) General Control Register More... | |
| #define | REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) |
| (USBHS) Device General Control Register More... | |
| #define | REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) |
| (USBHS) Device DMA Channel Address Register (n = 1) More... | |
| #define | REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) |
| (USBHS) Device DMA Channel Address Register (n = 2) More... | |
| #define | REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) |
| (USBHS) Device DMA Channel Address Register (n = 3) More... | |
| #define | REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) |
| (USBHS) Device DMA Channel Address Register (n = 4) More... | |
| #define | REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) |
| (USBHS) Device DMA Channel Address Register (n = 5) More... | |
| #define | REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) |
| (USBHS) Device DMA Channel Address Register (n = 6) More... | |
| #define | REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) |
| (USBHS) Device DMA Channel Address Register (n = 7) More... | |
| #define | REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) |
| (USBHS) Device DMA Channel Control Register (n = 1) More... | |
| #define | REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) |
| (USBHS) Device DMA Channel Control Register (n = 2) More... | |
| #define | REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) |
| (USBHS) Device DMA Channel Control Register (n = 3) More... | |
| #define | REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) |
| (USBHS) Device DMA Channel Control Register (n = 4) More... | |
| #define | REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) |
| (USBHS) Device DMA Channel Control Register (n = 5) More... | |
| #define | REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) |
| (USBHS) Device DMA Channel Control Register (n = 6) More... | |
| #define | REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) |
| (USBHS) Device DMA Channel Control Register (n = 7) More... | |
| #define | REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) |
| (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) More... | |
| #define | REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) |
| (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) More... | |
| #define | REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) |
| (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) More... | |
| #define | REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) |
| (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) More... | |
| #define | REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) |
| (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) More... | |
| #define | REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) |
| (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) More... | |
| #define | REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) |
| (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) More... | |
| #define | REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) |
| (USBHS) Device DMA Channel Status Register (n = 1) More... | |
| #define | REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) |
| (USBHS) Device DMA Channel Status Register (n = 2) More... | |
| #define | REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) |
| (USBHS) Device DMA Channel Status Register (n = 3) More... | |
| #define | REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) |
| (USBHS) Device DMA Channel Status Register (n = 4) More... | |
| #define | REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) |
| (USBHS) Device DMA Channel Status Register (n = 5) More... | |
| #define | REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) |
| (USBHS) Device DMA Channel Status Register (n = 6) More... | |
| #define | REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) |
| (USBHS) Device DMA Channel Status Register (n = 7) More... | |
| #define | REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) |
| (USBHS) Device Endpoint Register More... | |
| #define | REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) |
| (USBHS) Device Endpoint Configuration Register (n = 0) More... | |
| #define | REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) |
| (USBHS) Device Endpoint Clear Register (n = 0) More... | |
| #define | REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) |
| (USBHS) Device Endpoint Disable Register (n = 0) More... | |
| #define | REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) |
| (USBHS) Device Endpoint Enable Register (n = 0) More... | |
| #define | REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) |
| (USBHS) Device Endpoint Set Register (n = 0) More... | |
| #define | REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) |
| (USBHS) Device Endpoint Mask Register (n = 0) More... | |
| #define | REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) |
| (USBHS) Device Endpoint Status Register (n = 0) More... | |
| #define | REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) |
| (USBHS) Device Frame Number Register More... | |
| #define | REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) |
| (USBHS) Device Global Interrupt Clear Register More... | |
| #define | REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) |
| (USBHS) Device Global Interrupt Disable Register More... | |
| #define | REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) |
| (USBHS) Device Global Interrupt Enable Register More... | |
| #define | REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) |
| (USBHS) Device Global Interrupt Set Register More... | |
| #define | REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) |
| (USBHS) Device Global Interrupt Mask Register More... | |
| #define | REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) |
| (USBHS) Device Global Interrupt Status Register More... | |
| #define | REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) |
| (USBHS) General Finite State Machine Register More... | |
| #define | REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) |
| (USBHS) Host Address 1 Register More... | |
| #define | REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) |
| (USBHS) Host Address 2 Register More... | |
| #define | REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) |
| (USBHS) Host Address 3 Register More... | |
| #define | REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) |
| (USBHS) Host General Control Register More... | |
| #define | REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) |
| (USBHS) Host DMA Channel Address Register (n = 1) More... | |
| #define | REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) |
| (USBHS) Host DMA Channel Address Register (n = 2) More... | |
| #define | REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) |
| (USBHS) Host DMA Channel Address Register (n = 3) More... | |
| #define | REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) |
| (USBHS) Host DMA Channel Address Register (n = 4) More... | |
| #define | REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) |
| (USBHS) Host DMA Channel Address Register (n = 5) More... | |
| #define | REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) |
| (USBHS) Host DMA Channel Address Register (n = 6) More... | |
| #define | REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) |
| (USBHS) Host DMA Channel Address Register (n = 7) More... | |
| #define | REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) |
| (USBHS) Host DMA Channel Control Register (n = 1) More... | |
| #define | REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) |
| (USBHS) Host DMA Channel Control Register (n = 2) More... | |
| #define | REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) |
| (USBHS) Host DMA Channel Control Register (n = 3) More... | |
| #define | REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) |
| (USBHS) Host DMA Channel Control Register (n = 4) More... | |
| #define | REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) |
| (USBHS) Host DMA Channel Control Register (n = 5) More... | |
| #define | REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) |
| (USBHS) Host DMA Channel Control Register (n = 6) More... | |
| #define | REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) |
| (USBHS) Host DMA Channel Control Register (n = 7) More... | |
| #define | REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) |
| (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) More... | |
| #define | REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) |
| (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) More... | |
| #define | REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) |
| (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) More... | |
| #define | REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) |
| (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) More... | |
| #define | REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) |
| (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) More... | |
| #define | REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) |
| (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) More... | |
| #define | REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) |
| (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) More... | |
| #define | REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) |
| (USBHS) Host DMA Channel Status Register (n = 1) More... | |
| #define | REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) |
| (USBHS) Host DMA Channel Status Register (n = 2) More... | |
| #define | REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) |
| (USBHS) Host DMA Channel Status Register (n = 3) More... | |
| #define | REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) |
| (USBHS) Host DMA Channel Status Register (n = 4) More... | |
| #define | REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) |
| (USBHS) Host DMA Channel Status Register (n = 5) More... | |
| #define | REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) |
| (USBHS) Host DMA Channel Status Register (n = 6) More... | |
| #define | REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) |
| (USBHS) Host DMA Channel Status Register (n = 7) More... | |
| #define | REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) |
| (USBHS) Host Frame Number Register More... | |
| #define | REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) |
| (USBHS) Host Global Interrupt Clear Register More... | |
| #define | REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) |
| (USBHS) Host Global Interrupt Disable Register More... | |
| #define | REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) |
| (USBHS) Host Global Interrupt Enable Register More... | |
| #define | REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) |
| (USBHS) Host Global Interrupt Set Register More... | |
| #define | REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) |
| (USBHS) Host Global Interrupt Mask Register More... | |
| #define | REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) |
| (USBHS) Host Global Interrupt Status Register More... | |
| #define | REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) |
| (USBHS) Host Pipe Register More... | |
| #define | REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) |
| (USBHS) Host Pipe Configuration Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) |
| (USBHS) Host Pipe Error Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) |
| (USBHS) Host Pipe Clear Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) |
| (USBHS) Host Pipe Disable Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) |
| (USBHS) Host Pipe Enable Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) |
| (USBHS) Host Pipe Set Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) |
| (USBHS) Host Pipe Mask Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) |
| (USBHS) Host Pipe IN Request Register (n = 0) More... | |
| #define | REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) |
| (USBHS) Host Pipe Status Register (n = 0) More... | |
| #define | REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) |
| (USBHS) General Status Clear Register More... | |
| #define | REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) |
| (USBHS) General Status Set Register More... | |
| #define | REG_USBHS_SR (*(__I uint32_t*)0x40038804U) |
| (USBHS) General Status Register More... | |
| #define | REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) |
| (USBHS) General Test A1 Register More... | |
| #define | REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) |
| (USBHS) General Test A2 Register More... | |
| #define | REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) |
| (USBHS) General Version Register More... | |
Detailed Description
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
Macro Definition Documentation
◆ REG_USBHS_CTRL
| #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) |
(USBHS) General Control Register
Definition at line 235 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVCTRL
| #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) |
(USBHS) Device General Control Register
Definition at line 142 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMAADDRESS1
| #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) |
(USBHS) Device DMA Channel Address Register (n = 1)
Definition at line 159 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMAADDRESS2
| #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) |
(USBHS) Device DMA Channel Address Register (n = 2)
Definition at line 163 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMAADDRESS3
| #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) |
(USBHS) Device DMA Channel Address Register (n = 3)
Definition at line 167 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMAADDRESS4
| #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) |
(USBHS) Device DMA Channel Address Register (n = 4)
Definition at line 171 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMAADDRESS5
| #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) |
(USBHS) Device DMA Channel Address Register (n = 5)
Definition at line 175 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMAADDRESS6
| #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) |
(USBHS) Device DMA Channel Address Register (n = 6)
Definition at line 179 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMAADDRESS7
| #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) |
(USBHS) Device DMA Channel Address Register (n = 7)
Definition at line 183 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMACONTROL1
| #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) |
(USBHS) Device DMA Channel Control Register (n = 1)
Definition at line 160 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMACONTROL2
| #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) |
(USBHS) Device DMA Channel Control Register (n = 2)
Definition at line 164 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMACONTROL3
| #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) |
(USBHS) Device DMA Channel Control Register (n = 3)
Definition at line 168 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMACONTROL4
| #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) |
(USBHS) Device DMA Channel Control Register (n = 4)
Definition at line 172 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMACONTROL5
| #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) |
(USBHS) Device DMA Channel Control Register (n = 5)
Definition at line 176 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMACONTROL6
| #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) |
(USBHS) Device DMA Channel Control Register (n = 6)
Definition at line 180 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMACONTROL7
| #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) |
(USBHS) Device DMA Channel Control Register (n = 7)
Definition at line 184 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMANXTDSC1
| #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) |
(USBHS) Device DMA Channel Next Descriptor Address Register (n = 1)
Definition at line 158 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMANXTDSC2
| #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) |
(USBHS) Device DMA Channel Next Descriptor Address Register (n = 2)
Definition at line 162 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMANXTDSC3
| #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) |
(USBHS) Device DMA Channel Next Descriptor Address Register (n = 3)
Definition at line 166 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMANXTDSC4
| #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) |
(USBHS) Device DMA Channel Next Descriptor Address Register (n = 4)
Definition at line 170 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMANXTDSC5
| #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) |
(USBHS) Device DMA Channel Next Descriptor Address Register (n = 5)
Definition at line 174 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMANXTDSC6
| #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) |
(USBHS) Device DMA Channel Next Descriptor Address Register (n = 6)
Definition at line 178 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMANXTDSC7
| #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) |
(USBHS) Device DMA Channel Next Descriptor Address Register (n = 7)
Definition at line 182 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMASTATUS1
| #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) |
(USBHS) Device DMA Channel Status Register (n = 1)
Definition at line 161 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMASTATUS2
| #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) |
(USBHS) Device DMA Channel Status Register (n = 2)
Definition at line 165 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMASTATUS3
| #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) |
(USBHS) Device DMA Channel Status Register (n = 3)
Definition at line 169 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMASTATUS4
| #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) |
(USBHS) Device DMA Channel Status Register (n = 4)
Definition at line 173 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMASTATUS5
| #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) |
(USBHS) Device DMA Channel Status Register (n = 5)
Definition at line 177 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMASTATUS6
| #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) |
(USBHS) Device DMA Channel Status Register (n = 6)
Definition at line 181 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVDMASTATUS7
| #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) |
(USBHS) Device DMA Channel Status Register (n = 7)
Definition at line 185 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPT
| #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) |
(USBHS) Device Endpoint Register
Definition at line 149 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPTCFG
| #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) |
(USBHS) Device Endpoint Configuration Register (n = 0)
Definition at line 151 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPTICR
| #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) |
(USBHS) Device Endpoint Clear Register (n = 0)
Definition at line 153 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPTIDR
| #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) |
(USBHS) Device Endpoint Disable Register (n = 0)
Definition at line 157 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPTIER
| #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) |
(USBHS) Device Endpoint Enable Register (n = 0)
Definition at line 156 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPTIFR
| #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) |
(USBHS) Device Endpoint Set Register (n = 0)
Definition at line 154 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPTIMR
| #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) |
(USBHS) Device Endpoint Mask Register (n = 0)
Definition at line 155 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVEPTISR
| #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) |
(USBHS) Device Endpoint Status Register (n = 0)
Definition at line 152 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVFNUM
| #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) |
(USBHS) Device Frame Number Register
Definition at line 150 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVICR
| #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) |
(USBHS) Device Global Interrupt Clear Register
Definition at line 144 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVIDR
| #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) |
(USBHS) Device Global Interrupt Disable Register
Definition at line 147 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVIER
| #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) |
(USBHS) Device Global Interrupt Enable Register
Definition at line 148 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVIFR
| #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) |
(USBHS) Device Global Interrupt Set Register
Definition at line 145 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVIMR
| #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) |
(USBHS) Device Global Interrupt Mask Register
Definition at line 146 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_DEVISR
| #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) |
(USBHS) Device Global Interrupt Status Register
Definition at line 143 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_FSM
| #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) |
(USBHS) General Finite State Machine Register
Definition at line 242 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTADDR1
| #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) |
(USBHS) Host Address 1 Register
Definition at line 195 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTADDR2
| #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) |
(USBHS) Host Address 2 Register
Definition at line 196 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTADDR3
| #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) |
(USBHS) Host Address 3 Register
Definition at line 197 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTCTRL
| #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) |
(USBHS) Host General Control Register
Definition at line 186 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMAADDRESS1
| #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) |
(USBHS) Host DMA Channel Address Register (n = 1)
Definition at line 208 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMAADDRESS2
| #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) |
(USBHS) Host DMA Channel Address Register (n = 2)
Definition at line 212 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMAADDRESS3
| #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) |
(USBHS) Host DMA Channel Address Register (n = 3)
Definition at line 216 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMAADDRESS4
| #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) |
(USBHS) Host DMA Channel Address Register (n = 4)
Definition at line 220 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMAADDRESS5
| #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) |
(USBHS) Host DMA Channel Address Register (n = 5)
Definition at line 224 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMAADDRESS6
| #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) |
(USBHS) Host DMA Channel Address Register (n = 6)
Definition at line 228 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMAADDRESS7
| #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) |
(USBHS) Host DMA Channel Address Register (n = 7)
Definition at line 232 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMACONTROL1
| #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) |
(USBHS) Host DMA Channel Control Register (n = 1)
Definition at line 209 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMACONTROL2
| #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) |
(USBHS) Host DMA Channel Control Register (n = 2)
Definition at line 213 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMACONTROL3
| #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) |
(USBHS) Host DMA Channel Control Register (n = 3)
Definition at line 217 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMACONTROL4
| #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) |
(USBHS) Host DMA Channel Control Register (n = 4)
Definition at line 221 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMACONTROL5
| #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) |
(USBHS) Host DMA Channel Control Register (n = 5)
Definition at line 225 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMACONTROL6
| #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) |
(USBHS) Host DMA Channel Control Register (n = 6)
Definition at line 229 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMACONTROL7
| #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) |
(USBHS) Host DMA Channel Control Register (n = 7)
Definition at line 233 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMANXTDSC1
| #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) |
(USBHS) Host DMA Channel Next Descriptor Address Register (n = 1)
Definition at line 207 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMANXTDSC2
| #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) |
(USBHS) Host DMA Channel Next Descriptor Address Register (n = 2)
Definition at line 211 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMANXTDSC3
| #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) |
(USBHS) Host DMA Channel Next Descriptor Address Register (n = 3)
Definition at line 215 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMANXTDSC4
| #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) |
(USBHS) Host DMA Channel Next Descriptor Address Register (n = 4)
Definition at line 219 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMANXTDSC5
| #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) |
(USBHS) Host DMA Channel Next Descriptor Address Register (n = 5)
Definition at line 223 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMANXTDSC6
| #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) |
(USBHS) Host DMA Channel Next Descriptor Address Register (n = 6)
Definition at line 227 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMANXTDSC7
| #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) |
(USBHS) Host DMA Channel Next Descriptor Address Register (n = 7)
Definition at line 231 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMASTATUS1
| #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) |
(USBHS) Host DMA Channel Status Register (n = 1)
Definition at line 210 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMASTATUS2
| #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) |
(USBHS) Host DMA Channel Status Register (n = 2)
Definition at line 214 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMASTATUS3
| #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) |
(USBHS) Host DMA Channel Status Register (n = 3)
Definition at line 218 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMASTATUS4
| #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) |
(USBHS) Host DMA Channel Status Register (n = 4)
Definition at line 222 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMASTATUS5
| #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) |
(USBHS) Host DMA Channel Status Register (n = 5)
Definition at line 226 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMASTATUS6
| #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) |
(USBHS) Host DMA Channel Status Register (n = 6)
Definition at line 230 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTDMASTATUS7
| #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) |
(USBHS) Host DMA Channel Status Register (n = 7)
Definition at line 234 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTFNUM
| #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) |
(USBHS) Host Frame Number Register
Definition at line 194 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTICR
| #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) |
(USBHS) Host Global Interrupt Clear Register
Definition at line 188 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTIDR
| #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) |
(USBHS) Host Global Interrupt Disable Register
Definition at line 191 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTIER
| #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) |
(USBHS) Host Global Interrupt Enable Register
Definition at line 192 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTIFR
| #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) |
(USBHS) Host Global Interrupt Set Register
Definition at line 189 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTIMR
| #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) |
(USBHS) Host Global Interrupt Mask Register
Definition at line 190 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTISR
| #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) |
(USBHS) Host Global Interrupt Status Register
Definition at line 187 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIP
| #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) |
(USBHS) Host Pipe Register
Definition at line 193 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPCFG
| #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) |
(USBHS) Host Pipe Configuration Register (n = 0)
Definition at line 198 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPERR
| #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) |
(USBHS) Host Pipe Error Register (n = 0)
Definition at line 206 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPICR
| #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) |
(USBHS) Host Pipe Clear Register (n = 0)
Definition at line 200 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPIDR
| #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) |
(USBHS) Host Pipe Disable Register (n = 0)
Definition at line 204 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPIER
| #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) |
(USBHS) Host Pipe Enable Register (n = 0)
Definition at line 203 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPIFR
| #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) |
(USBHS) Host Pipe Set Register (n = 0)
Definition at line 201 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPIMR
| #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) |
(USBHS) Host Pipe Mask Register (n = 0)
Definition at line 202 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPINRQ
| #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) |
(USBHS) Host Pipe IN Request Register (n = 0)
Definition at line 205 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_HSTPIPISR
| #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) |
(USBHS) Host Pipe Status Register (n = 0)
Definition at line 199 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_SCR
| #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) |
(USBHS) General Status Clear Register
Definition at line 237 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_SFR
| #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) |
(USBHS) General Status Set Register
Definition at line 238 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_SR
| #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) |
(USBHS) General Status Register
Definition at line 236 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_TSTA1
| #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) |
(USBHS) General Test A1 Register
Definition at line 239 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_TSTA2
| #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) |
(USBHS) General Test A2 Register
Definition at line 240 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.
◆ REG_USBHS_VERSION
| #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) |
(USBHS) General Version Register
Definition at line 241 of file EVB-2/IS_EVB-2/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h.