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Macros | |
| #define | REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) |
| (DACC) Analog Current Register More... | |
| #define | REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) |
| (DACC) Conversion Data Register More... | |
| #define | REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) |
| (DACC) Channel Disable Register More... | |
| #define | REG_DACC_CHER (*(__O uint32_t*)0x40040010U) |
| (DACC) Channel Enable Register More... | |
| #define | REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) |
| (DACC) Channel Status Register More... | |
| #define | REG_DACC_CR (*(__O uint32_t*)0x40040000U) |
| (DACC) Control Register More... | |
| #define | REG_DACC_IDR (*(__O uint32_t*)0x40040028U) |
| (DACC) Interrupt Disable Register More... | |
| #define | REG_DACC_IER (*(__O uint32_t*)0x40040024U) |
| (DACC) Interrupt Enable Register More... | |
| #define | REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) |
| (DACC) Interrupt Mask Register More... | |
| #define | REG_DACC_ISR (*(__I uint32_t*)0x40040030U) |
| (DACC) Interrupt Status Register More... | |
| #define | REG_DACC_MR (*(__IO uint32_t*)0x40040004U) |
| (DACC) Mode Register More... | |
| #define | REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) |
| (DACC) Trigger Register More... | |
| #define | REG_DACC_VERSION (*(__I uint32_t*)0x400400FCU) |
| (DACC) Version Register More... | |
| #define | REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) |
| (DACC) Write Protection Mode Register More... | |
| #define | REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) |
| (DACC) Write Protection Status Register More... | |
Detailed Description
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file instance/dacc.h.
Macro Definition Documentation
◆ REG_DACC_ACR
| #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) |
(DACC) Analog Current Register
Definition at line 67 of file instance/dacc.h.
◆ REG_DACC_CDR
| #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) |
(DACC) Conversion Data Register
Definition at line 62 of file instance/dacc.h.
◆ REG_DACC_CHDR
| #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) |
(DACC) Channel Disable Register
Definition at line 60 of file instance/dacc.h.
◆ REG_DACC_CHER
| #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) |
(DACC) Channel Enable Register
Definition at line 59 of file instance/dacc.h.
◆ REG_DACC_CHSR
| #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) |
(DACC) Channel Status Register
Definition at line 61 of file instance/dacc.h.
◆ REG_DACC_CR
| #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) |
(DACC) Control Register
Definition at line 56 of file instance/dacc.h.
◆ REG_DACC_IDR
| #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) |
(DACC) Interrupt Disable Register
Definition at line 64 of file instance/dacc.h.
◆ REG_DACC_IER
| #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) |
(DACC) Interrupt Enable Register
Definition at line 63 of file instance/dacc.h.
◆ REG_DACC_IMR
| #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) |
(DACC) Interrupt Mask Register
Definition at line 65 of file instance/dacc.h.
◆ REG_DACC_ISR
| #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) |
(DACC) Interrupt Status Register
Definition at line 66 of file instance/dacc.h.
◆ REG_DACC_MR
| #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) |
(DACC) Mode Register
Definition at line 57 of file instance/dacc.h.
◆ REG_DACC_TRIGR
| #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) |
(DACC) Trigger Register
Definition at line 58 of file instance/dacc.h.
◆ REG_DACC_VERSION
| #define REG_DACC_VERSION (*(__I uint32_t*)0x400400FCU) |
(DACC) Version Register
Definition at line 70 of file instance/dacc.h.
◆ REG_DACC_WPMR
| #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) |
(DACC) Write Protection Mode Register
Definition at line 68 of file instance/dacc.h.
◆ REG_DACC_WPSR
| #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) |
(DACC) Write Protection Status Register
Definition at line 69 of file instance/dacc.h.