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Macros | |
| #define | REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) |
| (HSMCI) Argument Register More... | |
| #define | REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) |
| (HSMCI) Block Register More... | |
| #define | REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) |
| (HSMCI) Configuration Register More... | |
| #define | REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) |
| (HSMCI) Command Register More... | |
| #define | REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) |
| (HSMCI) Control Register More... | |
| #define | REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) |
| (HSMCI) Completion Signal Timeout Register More... | |
| #define | REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) |
| (HSMCI) DMA Configuration Register More... | |
| #define | REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) |
| (HSMCI) Data Timeout Register More... | |
| #define | REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) |
| (HSMCI) FIFO Memory Aperture0 More... | |
| #define | REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) |
| (HSMCI) Interrupt Disable Register More... | |
| #define | REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) |
| (HSMCI) Interrupt Enable Register More... | |
| #define | REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) |
| (HSMCI) Interrupt Mask Register More... | |
| #define | REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) |
| (HSMCI) Mode Register More... | |
| #define | REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) |
| (HSMCI) Receive Data Register More... | |
| #define | REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) |
| (HSMCI) Response Register More... | |
| #define | REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) |
| (HSMCI) SD/SDIO Card Register More... | |
| #define | REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) |
| (HSMCI) Status Register More... | |
| #define | REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) |
| (HSMCI) Transmit Data Register More... | |
| #define | REG_HSMCI_VERSION (*(__I uint32_t*)0x400000FCU) |
| (HSMCI) Version Register More... | |
| #define | REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) |
| (HSMCI) Write Protection Mode Register More... | |
| #define | REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) |
| (HSMCI) Write Protection Status Register More... | |
Detailed Description
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file utils/cmsis/same70/include/instance/hsmci.h.
Macro Definition Documentation
◆ REG_HSMCI_ARGR
| #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) |
(HSMCI) Argument Register
Definition at line 66 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_BLKR
| #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) |
(HSMCI) Block Register
Definition at line 68 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_CFG
| #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) |
(HSMCI) Configuration Register
Definition at line 78 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_CMDR
| #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) |
(HSMCI) Command Register
Definition at line 67 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_CR
| #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) |
(HSMCI) Control Register
Definition at line 62 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_CSTOR
| #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) |
(HSMCI) Completion Signal Timeout Register
Definition at line 69 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_DMA
| #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) |
(HSMCI) DMA Configuration Register
Definition at line 77 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_DTOR
| #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) |
(HSMCI) Data Timeout Register
Definition at line 64 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_FIFO
| #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) |
(HSMCI) FIFO Memory Aperture0
Definition at line 82 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_IDR
| #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) |
(HSMCI) Interrupt Disable Register
Definition at line 75 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_IER
| #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) |
(HSMCI) Interrupt Enable Register
Definition at line 74 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_IMR
| #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) |
(HSMCI) Interrupt Mask Register
Definition at line 76 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_MR
| #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) |
(HSMCI) Mode Register
Definition at line 63 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_RDR
| #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) |
(HSMCI) Receive Data Register
Definition at line 71 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_RSPR
| #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) |
(HSMCI) Response Register
Definition at line 70 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_SDCR
| #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) |
(HSMCI) SD/SDIO Card Register
Definition at line 65 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_SR
| #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) |
(HSMCI) Status Register
Definition at line 73 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_TDR
| #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) |
(HSMCI) Transmit Data Register
Definition at line 72 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_VERSION
| #define REG_HSMCI_VERSION (*(__I uint32_t*)0x400000FCU) |
(HSMCI) Version Register
Definition at line 81 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_WPMR
| #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) |
(HSMCI) Write Protection Mode Register
Definition at line 79 of file utils/cmsis/same70/include/instance/hsmci.h.
◆ REG_HSMCI_WPSR
| #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) |
(HSMCI) Write Protection Status Register
Definition at line 80 of file utils/cmsis/same70/include/instance/hsmci.h.