This graph shows which files directly or indirectly include this file:

Macros
#define	REG_TC0_BCR ((__O uint32_t)0x4000C0C0U)
	(TC0) Block Control Register More...

#define	REG_TC0_BMR ((__IO uint32_t)0x4000C0C4U)
	(TC0) Block Mode Register More...

#define	REG_TC0_CCR0 ((__O uint32_t)0x4000C000U)
	(TC0) Channel Control Register (channel = 0) More...

#define	REG_TC0_CCR1 ((__O uint32_t)0x4000C040U)
	(TC0) Channel Control Register (channel = 1) More...

#define	REG_TC0_CCR2 ((__O uint32_t)0x4000C080U)
	(TC0) Channel Control Register (channel = 2) More...

#define	REG_TC0_CMR0 ((__IO uint32_t)0x4000C004U)
	(TC0) Channel Mode Register (channel = 0) More...

#define	REG_TC0_CMR1 ((__IO uint32_t)0x4000C044U)
	(TC0) Channel Mode Register (channel = 1) More...

#define	REG_TC0_CMR2 ((__IO uint32_t)0x4000C084U)
	(TC0) Channel Mode Register (channel = 2) More...

#define	REG_TC0_CV0 ((__I uint32_t)0x4000C010U)
	(TC0) Counter Value (channel = 0) More...

#define	REG_TC0_CV1 ((__I uint32_t)0x4000C050U)
	(TC0) Counter Value (channel = 1) More...

#define	REG_TC0_CV2 ((__I uint32_t)0x4000C090U)
	(TC0) Counter Value (channel = 2) More...

#define	REG_TC0_EMR0 ((__IO uint32_t)0x4000C030U)
	(TC0) Extended Mode Register (channel = 0) More...

#define	REG_TC0_EMR1 ((__IO uint32_t)0x4000C070U)
	(TC0) Extended Mode Register (channel = 1) More...

#define	REG_TC0_EMR2 ((__IO uint32_t)0x4000C0B0U)
	(TC0) Extended Mode Register (channel = 2) More...

#define	REG_TC0_FMR ((__IO uint32_t)0x4000C0D8U)
	(TC0) Fault Mode Register More...

#define	REG_TC0_IDR0 ((__O uint32_t)0x4000C028U)
	(TC0) Interrupt Disable Register (channel = 0) More...

#define	REG_TC0_IDR1 ((__O uint32_t)0x4000C068U)
	(TC0) Interrupt Disable Register (channel = 1) More...

#define	REG_TC0_IDR2 ((__O uint32_t)0x4000C0A8U)
	(TC0) Interrupt Disable Register (channel = 2) More...

#define	REG_TC0_IER0 ((__O uint32_t)0x4000C024U)
	(TC0) Interrupt Enable Register (channel = 0) More...

#define	REG_TC0_IER1 ((__O uint32_t)0x4000C064U)
	(TC0) Interrupt Enable Register (channel = 1) More...

#define	REG_TC0_IER2 ((__O uint32_t)0x4000C0A4U)
	(TC0) Interrupt Enable Register (channel = 2) More...

#define	REG_TC0_IMR0 ((__I uint32_t)0x4000C02CU)
	(TC0) Interrupt Mask Register (channel = 0) More...

#define	REG_TC0_IMR1 ((__I uint32_t)0x4000C06CU)
	(TC0) Interrupt Mask Register (channel = 1) More...

#define	REG_TC0_IMR2 ((__I uint32_t)0x4000C0ACU)
	(TC0) Interrupt Mask Register (channel = 2) More...

#define	REG_TC0_QIDR ((__O uint32_t)0x4000C0CCU)
	(TC0) QDEC Interrupt Disable Register More...

#define	REG_TC0_QIER ((__O uint32_t)0x4000C0C8U)
	(TC0) QDEC Interrupt Enable Register More...

#define	REG_TC0_QIMR ((__I uint32_t)0x4000C0D0U)
	(TC0) QDEC Interrupt Mask Register More...

#define	REG_TC0_QISR ((__I uint32_t)0x4000C0D4U)
	(TC0) QDEC Interrupt Status Register More...

#define	REG_TC0_RA0 ((__IO uint32_t)0x4000C014U)
	(TC0) Register A (channel = 0) More...

#define	REG_TC0_RA1 ((__IO uint32_t)0x4000C054U)
	(TC0) Register A (channel = 1) More...

#define	REG_TC0_RA2 ((__IO uint32_t)0x4000C094U)
	(TC0) Register A (channel = 2) More...

#define	REG_TC0_RAB0 ((__I uint32_t)0x4000C00CU)
	(TC0) Register AB (channel = 0) More...

#define	REG_TC0_RAB1 ((__I uint32_t)0x4000C04CU)
	(TC0) Register AB (channel = 1) More...

#define	REG_TC0_RAB2 ((__I uint32_t)0x4000C08CU)
	(TC0) Register AB (channel = 2) More...

#define	REG_TC0_RB0 ((__IO uint32_t)0x4000C018U)
	(TC0) Register B (channel = 0) More...

#define	REG_TC0_RB1 ((__IO uint32_t)0x4000C058U)
	(TC0) Register B (channel = 1) More...

#define	REG_TC0_RB2 ((__IO uint32_t)0x4000C098U)
	(TC0) Register B (channel = 2) More...

#define	REG_TC0_RC0 ((__IO uint32_t)0x4000C01CU)
	(TC0) Register C (channel = 0) More...

#define	REG_TC0_RC1 ((__IO uint32_t)0x4000C05CU)
	(TC0) Register C (channel = 1) More...

#define	REG_TC0_RC2 ((__IO uint32_t)0x4000C09CU)
	(TC0) Register C (channel = 2) More...

#define	REG_TC0_SMMR0 ((__IO uint32_t)0x4000C008U)
	(TC0) Stepper Motor Mode Register (channel = 0) More...

#define	REG_TC0_SMMR1 ((__IO uint32_t)0x4000C048U)
	(TC0) Stepper Motor Mode Register (channel = 1) More...

#define	REG_TC0_SMMR2 ((__IO uint32_t)0x4000C088U)
	(TC0) Stepper Motor Mode Register (channel = 2) More...

#define	REG_TC0_SR0 ((__I uint32_t)0x4000C020U)
	(TC0) Status Register (channel = 0) More...

#define	REG_TC0_SR1 ((__I uint32_t)0x4000C060U)
	(TC0) Status Register (channel = 1) More...

#define	REG_TC0_SR2 ((__I uint32_t)0x4000C0A0U)
	(TC0) Status Register (channel = 2) More...

#define	REG_TC0_VER ((__I uint32_t)0x4000C0FCU)
	(TC0) Version Register More...

#define	REG_TC0_WPMR ((__IO uint32_t)0x4000C0E4U)
	(TC0) Write Protection Mode Register More...

Detailed Description

Definition in file tc0.h.

Macro Definition Documentation

◆ REG_TC0_BCR

#define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U)

(TC0) Block Control Register

Definition at line 128 of file tc0.h.

◆ REG_TC0_BMR

#define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U)

(TC0) Block Mode Register

Definition at line 129 of file tc0.h.

◆ REG_TC0_CCR0

#define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U)

(TC0) Channel Control Register (channel = 0)

Definition at line 89 of file tc0.h.

◆ REG_TC0_CCR1

#define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U)

(TC0) Channel Control Register (channel = 1)

Definition at line 102 of file tc0.h.

◆ REG_TC0_CCR2

#define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U)

(TC0) Channel Control Register (channel = 2)

Definition at line 115 of file tc0.h.

◆ REG_TC0_CMR0

#define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U)

(TC0) Channel Mode Register (channel = 0)

Definition at line 90 of file tc0.h.

◆ REG_TC0_CMR1

#define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U)

(TC0) Channel Mode Register (channel = 1)

Definition at line 103 of file tc0.h.

◆ REG_TC0_CMR2

#define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U)

(TC0) Channel Mode Register (channel = 2)

Definition at line 116 of file tc0.h.

◆ REG_TC0_CV0

#define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U)

(TC0) Counter Value (channel = 0)

Definition at line 93 of file tc0.h.

◆ REG_TC0_CV1

#define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U)

(TC0) Counter Value (channel = 1)

Definition at line 106 of file tc0.h.

◆ REG_TC0_CV2

#define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U)

(TC0) Counter Value (channel = 2)

Definition at line 119 of file tc0.h.

◆ REG_TC0_EMR0

#define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U)

(TC0) Extended Mode Register (channel = 0)

Definition at line 101 of file tc0.h.

◆ REG_TC0_EMR1

#define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U)

(TC0) Extended Mode Register (channel = 1)

Definition at line 114 of file tc0.h.

◆ REG_TC0_EMR2

#define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U)

(TC0) Extended Mode Register (channel = 2)

Definition at line 127 of file tc0.h.

◆ REG_TC0_FMR

#define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U)

(TC0) Fault Mode Register

Definition at line 134 of file tc0.h.

◆ REG_TC0_IDR0

#define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U)

(TC0) Interrupt Disable Register (channel = 0)

Definition at line 99 of file tc0.h.

◆ REG_TC0_IDR1

#define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U)

(TC0) Interrupt Disable Register (channel = 1)

Definition at line 112 of file tc0.h.

◆ REG_TC0_IDR2

#define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U)

(TC0) Interrupt Disable Register (channel = 2)

Definition at line 125 of file tc0.h.

◆ REG_TC0_IER0

#define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U)

(TC0) Interrupt Enable Register (channel = 0)

Definition at line 98 of file tc0.h.

◆ REG_TC0_IER1

#define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U)

(TC0) Interrupt Enable Register (channel = 1)

Definition at line 111 of file tc0.h.

◆ REG_TC0_IER2

#define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U)

(TC0) Interrupt Enable Register (channel = 2)

Definition at line 124 of file tc0.h.

◆ REG_TC0_IMR0

#define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU)

(TC0) Interrupt Mask Register (channel = 0)

Definition at line 100 of file tc0.h.

◆ REG_TC0_IMR1

#define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU)

(TC0) Interrupt Mask Register (channel = 1)

Definition at line 113 of file tc0.h.

◆ REG_TC0_IMR2

#define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU)

(TC0) Interrupt Mask Register (channel = 2)

Definition at line 126 of file tc0.h.

◆ REG_TC0_QIDR

#define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU)

(TC0) QDEC Interrupt Disable Register

Definition at line 131 of file tc0.h.

◆ REG_TC0_QIER

#define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U)

(TC0) QDEC Interrupt Enable Register

Definition at line 130 of file tc0.h.

◆ REG_TC0_QIMR

#define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U)

(TC0) QDEC Interrupt Mask Register

Definition at line 132 of file tc0.h.

◆ REG_TC0_QISR

#define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U)

(TC0) QDEC Interrupt Status Register

Definition at line 133 of file tc0.h.

◆ REG_TC0_RA0

#define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U)

(TC0) Register A (channel = 0)

Definition at line 94 of file tc0.h.

◆ REG_TC0_RA1

#define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U)

(TC0) Register A (channel = 1)

Definition at line 107 of file tc0.h.

◆ REG_TC0_RA2

#define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U)

(TC0) Register A (channel = 2)

Definition at line 120 of file tc0.h.

◆ REG_TC0_RAB0

#define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU)

(TC0) Register AB (channel = 0)

Definition at line 92 of file tc0.h.

◆ REG_TC0_RAB1

#define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU)

(TC0) Register AB (channel = 1)

Definition at line 105 of file tc0.h.

◆ REG_TC0_RAB2

#define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU)

(TC0) Register AB (channel = 2)

Definition at line 118 of file tc0.h.

◆ REG_TC0_RB0

#define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U)

(TC0) Register B (channel = 0)

Definition at line 95 of file tc0.h.

◆ REG_TC0_RB1

#define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U)

(TC0) Register B (channel = 1)

Definition at line 108 of file tc0.h.

◆ REG_TC0_RB2

#define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U)

(TC0) Register B (channel = 2)

Definition at line 121 of file tc0.h.

◆ REG_TC0_RC0

#define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU)

(TC0) Register C (channel = 0)

Definition at line 96 of file tc0.h.

◆ REG_TC0_RC1

#define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU)

(TC0) Register C (channel = 1)

Definition at line 109 of file tc0.h.

◆ REG_TC0_RC2

#define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU)

(TC0) Register C (channel = 2)

Definition at line 122 of file tc0.h.

◆ REG_TC0_SMMR0

#define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U)

(TC0) Stepper Motor Mode Register (channel = 0)

Definition at line 91 of file tc0.h.

◆ REG_TC0_SMMR1

#define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U)

(TC0) Stepper Motor Mode Register (channel = 1)

Definition at line 104 of file tc0.h.

◆ REG_TC0_SMMR2

#define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U)

(TC0) Stepper Motor Mode Register (channel = 2)

Definition at line 117 of file tc0.h.

◆ REG_TC0_SR0

#define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U)

(TC0) Status Register (channel = 0)

Definition at line 97 of file tc0.h.

◆ REG_TC0_SR1

#define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U)

(TC0) Status Register (channel = 1)

Definition at line 110 of file tc0.h.

◆ REG_TC0_SR2

#define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U)

(TC0) Status Register (channel = 2)

Definition at line 123 of file tc0.h.

◆ REG_TC0_VER

#define REG_TC0_VER (*(__I uint32_t*)0x4000C0FCU)

(TC0) Version Register

Definition at line 136 of file tc0.h.

◆ REG_TC0_WPMR

#define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U)

(TC0) Write Protection Mode Register

Definition at line 135 of file tc0.h.

Macros