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Macros | |
| #define | REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) | 
| (PIOE) Peripheral Select Register  More... | |
| #define | REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) | 
| (PIOE) Additional Interrupt Modes Disable Register  More... | |
| #define | REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) | 
| (PIOE) Additional Interrupt Modes Enable Register  More... | |
| #define | REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) | 
| (PIOE) Additional Interrupt Modes Mask Register  More... | |
| #define | REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) | 
| (PIOE) Clear Output Data Register  More... | |
| #define | REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) | 
| (PIOE) PIO I/O Drive Register  More... | |
| #define | REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) | 
| (PIOE) Edge/Level Status Register  More... | |
| #define | REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) | 
| (PIOE) Edge Select Register  More... | |
| #define | REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) | 
| (PIOE) Falling Edge/Low-Level Select Register  More... | |
| #define | REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) | 
| (PIOE) Fall/Rise - Low/High Status Register  More... | |
| #define | REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) | 
| (PIOE) Interrupt Disable Register  More... | |
| #define | REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) | 
| (PIOE) Interrupt Enable Register  More... | |
| #define | REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) | 
| (PIOE) Glitch Input Filter Disable Register  More... | |
| #define | REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) | 
| (PIOE) Glitch Input Filter Enable Register  More... | |
| #define | REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) | 
| (PIOE) Input Filter Slow Clock Disable Register  More... | |
| #define | REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) | 
| (PIOE) Input Filter Slow Clock Enable Register  More... | |
| #define | REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) | 
| (PIOE) Input Filter Slow Clock Status Register  More... | |
| #define | REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) | 
| (PIOE) Glitch Input Filter Status Register  More... | |
| #define | REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) | 
| (PIOE) Interrupt Mask Register  More... | |
| #define | REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) | 
| (PIOE) Interrupt Status Register  More... | |
| #define | REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) | 
| (PIOE) Keypad Controller Debouncing Register  More... | |
| #define | REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) | 
| (PIOE) Keypad Controller Enable Register  More... | |
| #define | REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) | 
| (PIOE) Keypad Controller Interrupt Disable Register  More... | |
| #define | REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) | 
| (PIOE) Keypad Controller Interrupt Enable Register  More... | |
| #define | REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) | 
| (PIOE) Keypad Controller Interrupt Mask Register  More... | |
| #define | REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) | 
| (PIOE) Keypad Controller Key Press Register  More... | |
| #define | REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) | 
| (PIOE) Keypad Controller Key Release Register  More... | |
| #define | REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) | 
| (PIOE) Keypad Controller Row Column Register  More... | |
| #define | REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) | 
| (PIOE) Keypad Controller Status Register  More... | |
| #define | REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) | 
| (PIOE) Lock Status  More... | |
| #define | REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) | 
| (PIOE) Level Select Register  More... | |
| #define | REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) | 
| (PIOE) Multi-driver Disable Register  More... | |
| #define | REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) | 
| (PIOE) Multi-driver Enable Register  More... | |
| #define | REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) | 
| (PIOE) Multi-driver Status Register  More... | |
| #define | REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) | 
| (PIOE) Output Disable Register  More... | |
| #define | REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) | 
| (PIOE) Output Data Status Register  More... | |
| #define | REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) | 
| (PIOE) Output Enable Register  More... | |
| #define | REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) | 
| (PIOE) Output Status Register  More... | |
| #define | REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) | 
| (PIOE) Output Write Disable  More... | |
| #define | REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) | 
| (PIOE) Output Write Enable  More... | |
| #define | REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) | 
| (PIOE) Output Write Status Register  More... | |
| #define | REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) | 
| (PIOE) Parallel Capture Interrupt Disable Register  More... | |
| #define | REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) | 
| (PIOE) Parallel Capture Interrupt Enable Register  More... | |
| #define | REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) | 
| (PIOE) Parallel Capture Interrupt Mask Register  More... | |
| #define | REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) | 
| (PIOE) Parallel Capture Interrupt Status Register  More... | |
| #define | REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) | 
| (PIOE) Parallel Capture Mode Register  More... | |
| #define | REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) | 
| (PIOE) Parallel Capture Reception Holding Register  More... | |
| #define | REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) | 
| (PIOE) PIO Disable Register  More... | |
| #define | REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) | 
| (PIOE) Pin Data Status Register  More... | |
| #define | REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) | 
| (PIOE) PIO Enable Register  More... | |
| #define | REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) | 
| (PIOE) Pad Pull-down Disable Register  More... | |
| #define | REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) | 
| (PIOE) Pad Pull-down Enable Register  More... | |
| #define | REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) | 
| (PIOE) Pad Pull-down Status Register  More... | |
| #define | REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) | 
| (PIOE) PIO Status Register  More... | |
| #define | REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) | 
| (PIOE) Pull-up Disable Register  More... | |
| #define | REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) | 
| (PIOE) Pull-up Enable Register  More... | |
| #define | REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) | 
| (PIOE) Pad Pull-up Status Register  More... | |
| #define | REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) | 
| (PIOE) Rising Edge/High-Level Select Register  More... | |
| #define | REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) | 
| (PIOE) Slow Clock Divider Debouncing Register  More... | |
| #define | REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) | 
| (PIOE) Schmitt Trigger Register  More... | |
| #define | REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) | 
| (PIOE) Set Output Data Register  More... | |
| #define | REG_PIOE_VERSION (*(__I uint32_t*)0x400E16FCU) | 
| (PIOE) Version Register  More... | |
| #define | REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) | 
| (PIOE) Write Protection Mode Register  More... | |
| #define | REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) | 
| (PIOE) Write Protection Status Register  More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file pioe.h.
| #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) | 
| #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) | 
| #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) | 
| #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) | 
| #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) | 
| #define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) | 
| #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) | 
| #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) | 
| #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) | 
| #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) | 
| #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) | 
| #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) | 
| #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) | 
| #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) | 
| #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) | 
| #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) | 
| #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) | 
| #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) | 
| #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) | 
| #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) | 
| #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) | 
| #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) | 
| #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) | 
| #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) | 
| #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) | 
| #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) | 
| #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) | 
| #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) | 
| #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) | 
| #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) | 
| #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) | 
| #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) | 
| #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) | 
| #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) | 
| #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) | 
| #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) | 
| #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) | 
| #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) | 
| #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) | 
| #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) | 
| #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) | 
| #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) | 
| #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) | 
| #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) | 
| #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) | 
| #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) | 
| #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) | 
| #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) | 
| #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) | 
| #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) | 
| #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) | 
| #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) | 
| #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) | 
| #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) | 
| #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) | 
| #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) | 
| #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) | 
| #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) | 
| #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) | 
| #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) | 
| #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) | 
| #define REG_PIOE_VERSION (*(__I uint32_t*)0x400E16FCU) | 
| #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) |