afec.c

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#include "afec.h"
#include "sleepmgr.h"
#include "status_codes.h"
#include "sysclk.h"
#include "pmc.h"

#if defined(AFEC1)
#define NUM_OF_AFEC    (2UL)
#else
#define NUM_OF_AFEC    (1UL)
#endif

/* The gap between bit EOC15 and DRDY in interrupt register */
#if defined __SAM4E8C__  || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__
#define AFEC_INTERRUPT_GAP1                  (17UL)
#elif defined __SAM4E8E__  || defined __SAM4E16E__
#define AFEC_INTERRUPT_GAP1                  (8UL)
#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
/* The gap between bit EOC11 and DRDY in interrupt register */
#define AFEC_INTERRUPT_GAP1                  (12UL)
#endif

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
/* The gap between bit COMPE and TEMPCHG in interrupt register */
#define AFEC_INTERRUPT_GAP2                  (3UL)
#else
/* The gap between bit RXBUFF and TEMPCHG in interrupt register */
#define AFEC_INTERRUPT_GAP2                  (1UL)
#endif

/* The number of channel in channel sequence1 register */
#define AFEC_SEQ1_CHANNEL_NUM                (8UL)

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
/* The interrupt source number of temperature sensor */
#define AFEC_TEMP_INT_SOURCE_NUM             (11UL)
#else
/* The interrupt source number of temperature sensor */
#define AFEC_TEMP_INT_SOURCE_NUM             (15UL)
#endif

afec_callback_t afec_callback_pointer[NUM_OF_AFEC][_AFEC_NUM_OF_INTERRUPT_SOURCE];


static uint32_t afec_find_inst_num(Afec *const afec)
{
#if defined(AFEC1)
        if (afec == AFEC1) {
                return 1;
        }
#endif
#if defined(AFEC0)
        if (afec == AFEC0) {
                return 0;
        }
#endif
        return 0;
}

static uint32_t afec_find_pid(Afec *const afec)
{
#if defined(ID_AFEC1)
        if (afec == AFEC1) {
                return ID_AFEC1;
        }
#endif
#if defined(ID_AFEC0)
        if (afec == AFEC0) {
                return ID_AFEC0;
        }
#endif
        return ID_AFEC0;
}

static void afec_set_config(Afec *const afec, struct afec_config *config)
{
        uint32_t reg = 0;

        reg = (config->useq ? AFEC_MR_USEQ_REG_ORDER : 0) |
                #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
                        AFEC_MR_PRESCAL((config->mck / config->afec_clock )- 1) |
                        AFEC_MR_ONE |
                #else
                        (config->anach ? AFEC_MR_ANACH_ALLOWED : 0) |
                        AFEC_MR_PRESCAL(config->mck / (2 * config->afec_clock) - 1) |
                        (config->settling_time) |               
                #endif
                        AFEC_MR_TRACKTIM(config->tracktim) |
                        AFEC_MR_TRANSFER(config->transfer) |
                        (config->startup_time);

        afec->AFEC_MR = reg;

        afec->AFEC_EMR = (config->tag ? AFEC_EMR_TAG : 0) |
                        (config->resolution) |
                        (config->stm ? AFEC_EMR_STM : 0);
  #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
        afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl) | AFEC_ACR_PGA0EN | AFEC_ACR_PGA1EN;
  #else
    afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl);
  #endif
}

void afec_ch_set_config(Afec *const afec, const enum afec_channel_num channel,
                struct afec_ch_config *config)
{
        afec_ch_sanity_check(afec, channel);
        uint32_t reg = 0;

        reg = afec->AFEC_DIFFR;
        reg &= ~(0x1u << channel);
        reg |= (config->diff) ? (0x1u << channel) : 0;
        afec->AFEC_DIFFR = reg;

        reg = afec->AFEC_CGR;
        reg &= ~(0x03u << (2 * channel));
        reg |= (config->gain) << (2 * channel);
        afec->AFEC_CGR = reg;
}

void afec_temp_sensor_set_config(Afec *const afec,
                struct afec_temp_sensor_config *config)
{
        Assert(afec == AFEC0);

        uint32_t reg = 0;

        reg = ((config->rctc) ? AFEC_TEMPMR_RTCT : 0) | (config->mode);
        afec->AFEC_TEMPMR = reg;

        afec->AFEC_TEMPCWR = AFEC_TEMPCWR_TLOWTHRES(config->low_threshold) |
                        AFEC_TEMPCWR_THIGHTHRES(config->high_threshold);
                        
}

void afec_get_config_defaults(struct afec_config *const cfg)
{
        /* Sanity check argument. */
        Assert(cfg);

        cfg->resolution = AFEC_12_BITS;
        cfg->mck = sysclk_get_cpu_hz();
                cfg->afec_clock = 6000000UL;
                cfg->startup_time = AFEC_STARTUP_TIME_4;
        #if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
                cfg->settling_time = AFEC_SETTLING_TIME_0;
        #endif  
                cfg->tracktim = 2;
                cfg->transfer = 1;
                cfg->anach = true;
                cfg->useq = false;
                cfg->tag = true;
                cfg->stm = true;
                cfg->ibctl = 1;
}

void afec_ch_get_config_defaults(struct afec_ch_config *const cfg)
{
        /*Sanity check argument. */
        Assert(cfg);

        cfg->diff = false;
        cfg->gain = AFEC_GAINVALUE_1;

}

void afec_temp_sensor_get_config_defaults(
                struct afec_temp_sensor_config *const cfg)
{
        /*Sanity check argument. */
        Assert(cfg);

        cfg->rctc = false;
        cfg->mode= AFEC_TEMP_CMP_MODE_2;
        cfg->low_threshold= 0xFF;
        cfg->high_threshold= 0xFFF;
}

enum status_code afec_init(Afec *const afec, struct afec_config *config)
{
        Assert(afec);
        Assert(config);

        if ((afec_get_interrupt_status(afec) & AFEC_ISR_DRDY) == AFEC_ISR_DRDY) {
                return STATUS_ERR_BUSY;
        }

        /* Reset and configure the AFEC module */
        afec->AFEC_CR = AFEC_CR_SWRST;
        afec_set_config(afec, config);

        uint32_t i;
        if(afec == AFEC0) {
                for (i = 0; i < _AFEC_NUM_OF_INTERRUPT_SOURCE; i++){
                        afec_callback_pointer[0][i] = 0;
                }
        }
        if(afec == AFEC1) {
                for (i = 0; i < _AFEC_NUM_OF_INTERRUPT_SOURCE; i++){
                        afec_callback_pointer[1][i] = 0;
                }
        }

        return STATUS_OK;
}

void afec_set_comparison_mode(Afec *const afec,
                const enum afec_cmp_mode mode,
                const enum afec_channel_num channel, uint8_t cmp_filter)
{
        if (channel != AFEC_CHANNEL_ALL) {
                afec_ch_sanity_check(afec, channel);
        }

        uint32_t reg;

        reg = afec->AFEC_EMR;

        reg &= ~(AFEC_EMR_CMPSEL_Msk |
                        AFEC_EMR_CMPMODE_Msk |
                        AFEC_EMR_CMPFILTER_Msk);
        reg |= mode |
                        ((channel == AFEC_CHANNEL_ALL) ? AFEC_EMR_CMPALL
                        : AFEC_EMR_CMPSEL(channel)) |
                        AFEC_EMR_CMPFILTER(cmp_filter);

        afec->AFEC_EMR = reg;
}

void afec_set_power_mode(Afec *const afec,
                const enum afec_power_mode mode)
{
        uint32_t reg;

        reg = afec->AFEC_MR;

        switch(mode) {
                case AFEC_POWER_MODE_0:
                        reg &= ~(AFEC_MR_FWUP_ON | AFEC_MR_SLEEP_SLEEP);
                        break;
                case AFEC_POWER_MODE_1:
                        reg |= AFEC_MR_FWUP_ON;
                        break;
                case AFEC_POWER_MODE_2:
                        reg |= AFEC_MR_SLEEP_SLEEP;
                        reg &= ~AFEC_MR_FWUP_ON;
                        break;
        }

        afec->AFEC_MR = reg;
}

void afec_set_callback(Afec *const afec, enum afec_interrupt_source source,
                afec_callback_t callback, uint8_t irq_level)
{
        Assert(afec);
        Assert(callback);

        uint32_t i = afec_find_inst_num(afec);
        afec_callback_pointer[i][source] = callback;
        if (!i) {
                irq_register_handler(AFEC0_IRQn, irq_level);
        } else if (i == 1) {
                irq_register_handler(AFEC1_IRQn, irq_level);
        }
        /* Enable the specified interrupt source */
        afec_enable_interrupt(afec, source);
}

void afec_enable_interrupt(Afec *const afec,
                enum afec_interrupt_source interrupt_source)
{
        if (interrupt_source == AFEC_INTERRUPT_ALL) {
                afec->AFEC_IER = AFEC_INTERRUPT_ALL;
                return;
        }

        if (interrupt_source < AFEC_INTERRUPT_DATA_READY) {
          #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
                if (interrupt_source == AFEC_INTERRUPT_EOC_11) {
                        afec->AFEC_IER = 1 << AFEC_TEMP_INT_SOURCE_NUM;
          #else
                if (interrupt_source == AFEC_INTERRUPT_EOC_15) {
                        afec->AFEC_IER = 1 << AFEC_TEMP_INT_SOURCE_NUM;   
          #endif 
                } else {
                        afec->AFEC_IER = 1 << interrupt_source;
                }
        } else if (interrupt_source < AFEC_INTERRUPT_TEMP_CHANGE) {
                afec->AFEC_IER = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1);
        } else {
                afec->AFEC_IER = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1
                                + AFEC_INTERRUPT_GAP2);
        }
}

void afec_disable_interrupt(Afec *const afec,
                enum afec_interrupt_source interrupt_source)
{
        if (interrupt_source == AFEC_INTERRUPT_ALL) {
                afec->AFEC_IDR = AFEC_INTERRUPT_ALL;
                return;
        }

        if (interrupt_source < AFEC_INTERRUPT_DATA_READY) {
          #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
                if (interrupt_source == AFEC_INTERRUPT_EOC_11) {
                        afec->AFEC_IDR = 1 << AFEC_TEMP_INT_SOURCE_NUM;
          #else
                if (interrupt_source == AFEC_INTERRUPT_EOC_15) {
                        afec->AFEC_IDR = 1 << AFEC_TEMP_INT_SOURCE_NUM;   
          #endif
                } else {
                        afec->AFEC_IDR = 1 << interrupt_source;
                }
        } else if (interrupt_source < AFEC_INTERRUPT_TEMP_CHANGE) {
                afec->AFEC_IDR = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1);
        } else {
                afec->AFEC_IDR = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1
                                + AFEC_INTERRUPT_GAP2);
        }
}

static void afec_interrupt(uint8_t inst_num,
                enum afec_interrupt_source source)
{
        if (afec_callback_pointer[inst_num][source]) {
                afec_callback_pointer[inst_num][source]();
        }
}

static void afec_process_callback(Afec *const afec)
{
        volatile uint32_t status;
        uint32_t cnt, inst_num;

        status = afec_get_interrupt_status(afec) & afec_get_interrupt_mask(afec);
        inst_num = afec_find_inst_num(afec);

        for (cnt = 0; cnt < _AFEC_NUM_OF_INTERRUPT_SOURCE; cnt++) {
                if (cnt < AFEC_INTERRUPT_DATA_READY) {
                #if defined __SAM4E8C__  || defined __SAM4E16C__ || defined __SAM4E8CB__  || defined __SAM4E16CB__
                        if(cnt == AFEC_INTERRUPT_EOC_15) {
                                if (status & (1 << AFEC_TEMP_INT_SOURCE_NUM)) {
                                        afec_interrupt(inst_num, (enum afec_interrupt_source)cnt);
                                }
                        } else {
                                if (status & (1 << cnt)) {
                                        afec_interrupt(inst_num, (enum afec_interrupt_source)cnt);
                                }
                        }
                #elif defined __SAM4E8E__  || defined __SAM4E16E__ || SAMV71 || SAMV70 || SAMS70 || SAME70
                        if (status & (1 << cnt)) {
                                afec_interrupt(inst_num, (enum afec_interrupt_source)cnt);
                        }
                #endif
                } else if (cnt < AFEC_INTERRUPT_TEMP_CHANGE) {
                        if (status & (1 << (cnt + AFEC_INTERRUPT_GAP1))) {
                                afec_interrupt(inst_num, (enum afec_interrupt_source)cnt);
                        }
                } else {
                        if (status & (1 << (cnt + AFEC_INTERRUPT_GAP1 + AFEC_INTERRUPT_GAP2))) {
                                afec_interrupt(inst_num, (enum afec_interrupt_source)cnt);
                        }
                }
        }
}

void AFEC0_Handler(void)
{
        afec_process_callback(AFEC0);
}

void AFEC1_Handler(void)
{
        afec_process_callback(AFEC1);
}

void afec_enable(Afec *const afec)
{
        Assert(afec);
        uint32_t pid;

        pid = afec_find_pid(afec);
        /* Enable peripheral clock. */
        pmc_enable_periph_clk(pid);
        sleepmgr_lock_mode(SLEEPMGR_SLEEP_WFI);
}

void afec_disable(Afec *const afec)
{
        Assert(afec);
        uint32_t pid;

        pid = afec_find_pid(afec);
        /* Disable peripheral clock. */
        pmc_disable_periph_clk(pid);
        sleepmgr_unlock_mode(SLEEPMGR_SLEEP_WFI);
}

void afec_configure_sequence(Afec *const afec,
                const enum afec_channel_num ch_list[], uint8_t uc_num)
{
        uint8_t uc_counter;

        /* Set user sequence mode */
        afec->AFEC_MR |= AFEC_MR_USEQ_REG_ORDER;
        afec->AFEC_SEQ1R = 0;
        afec->AFEC_SEQ2R = 0;

        if (uc_num < AFEC_SEQ1_CHANNEL_NUM) {
                for (uc_counter = 0; uc_counter < uc_num; uc_counter++) {
                        afec->AFEC_SEQ1R |=
                                        ch_list[uc_counter] << (4 * uc_counter);
                }
        } else {
                for (uc_counter = 0; uc_counter < AFEC_SEQ1_CHANNEL_NUM; uc_counter++) {
                        afec->AFEC_SEQ1R |=
                                        ch_list[uc_counter] << (4 * uc_counter);
                }
                for (uc_counter = 0; uc_counter < uc_num - AFEC_SEQ1_CHANNEL_NUM;
                                uc_counter++) {
                        afec->AFEC_SEQ2R |=
                                        ch_list[uc_counter + AFEC_SEQ1_CHANNEL_NUM] << (4 * uc_counter);
                }
        }
}

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)

void afec_configure_auto_error_correction(Afec *const afec,
                const enum afec_channel_num channel, int16_t offsetcorr, uint16_t gaincorr)
{


        if (channel != AFEC_CHANNEL_ALL) {
                afec_ch_sanity_check(afec, channel);
        }

        uint32_t reg = 0;
        reg = afec->AFEC_CECR;
        reg = (channel == AFEC_CHANNEL_ALL)? 0 : ~(0x1u << channel);
        reg |= (channel == AFEC_CHANNEL_ALL)? AFEC_CHANNEL_ALL : (0x1u << channel);
        afec->AFEC_CECR = reg;

        afec->AFEC_COSR = AFEC_COSR_CSEL;
    afec->AFEC_CVR = AFEC_CVR_OFFSETCORR(offsetcorr) | AFEC_CVR_GAINCORR(gaincorr);              
        
}

 uint32_t afec_get_correction_value(Afec *const afec,
                const enum afec_channel_num afec_ch)
{       
        uint32_t corrected_data = 0;
        uint32_t converted_data = 0;
        
        afec_ch_sanity_check(afec, afec_ch);

        afec->AFEC_CSELR = afec_ch;
        converted_data = afec->AFEC_CDR;

        corrected_data = (converted_data + (afec->AFEC_CVR & AFEC_CVR_OFFSETCORR_Msk)) * 
                        (afec->AFEC_CVR >> AFEC_CVR_GAINCORR_Pos) / 1024u;
        return corrected_data;
        
}

void afec_set_sample_hold_mode(Afec *const afec,
                const enum afec_channel_num channel, const enum afec_sample_hold_mode mode)
{
        if (channel != AFEC_CHANNEL_ALL) {
                afec_ch_sanity_check(afec, channel);
        }
                
        uint32_t reg = 0;
        reg = afec->AFEC_SHMR;
        if (mode == AFEC_SAMPLE_HOLD_MODE_1) {
                
                reg |= (channel == AFEC_CHANNEL_ALL)? AFEC_CHANNEL_ALL : 0x1u << channel;
        }
        else {
                
                reg = (channel == AFEC_CHANNEL_ALL)? 0 : ~(0x1u << channel);
        }
        afec->AFEC_SHMR = reg;
                
}
#endif