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Macros | |
| #define | REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) | 
| (USART0) Baud Rate Generator Register  More... | |
| #define | REG_USART0_CR (*(__O uint32_t*)0x40024000U) | 
| (USART0) Control Register  More... | |
| #define | REG_USART0_CSR (*(__I uint32_t*)0x40024014U) | 
| (USART0) Channel Status Register  More... | |
| #define | REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) | 
| (USART0) FI DI Ratio Register  More... | |
| #define | REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) | 
| (USART0) IC DIFF Register  More... | |
| #define | REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) | 
| (USART0) Interrupt Disable Register  More... | |
| #define | REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) | 
| (USART0) LON IDT Rx Register  More... | |
| #define | REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) | 
| (USART0) LON IDT Tx Register  More... | |
| #define | REG_USART0_IER (*(__O uint32_t*)0x40024008U) | 
| (USART0) Interrupt Enable Register  More... | |
| #define | REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) | 
| (USART0) IrDA Filter Register  More... | |
| #define | REG_USART0_IMR (*(__I uint32_t*)0x40024010U) | 
| (USART0) Interrupt Mask Register  More... | |
| #define | REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) | 
| (USART0) LIN Baud Rate Register  More... | |
| #define | REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) | 
| (USART0) LIN Identifier Register  More... | |
| #define | REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) | 
| (USART0) LIN Mode Register  More... | |
| #define | REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) | 
| (USART0) LON Beta1 Rx Register  More... | |
| #define | REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) | 
| (USART0) LON Beta1 Tx Register  More... | |
| #define | REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) | 
| (USART0) LON Backlog Register  More... | |
| #define | REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) | 
| (USART0) LON Data Length Register  More... | |
| #define | REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) | 
| (USART0) LON L2HDR Register  More... | |
| #define | REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) | 
| (USART0) LON Mode Register  More... | |
| #define | REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) | 
| (USART0) LON Preamble Register  More... | |
| #define | REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) | 
| (USART0) LON Priority Register  More... | |
| #define | REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) | 
| (USART0) Manchester Configuration Register  More... | |
| #define | REG_USART0_MR (*(__IO uint32_t*)0x40024004U) | 
| (USART0) Mode Register  More... | |
| #define | REG_USART0_NER (*(__I uint32_t*)0x40024044U) | 
| (USART0) Number of Errors Register  More... | |
| #define | REG_USART0_RHR (*(__I uint32_t*)0x40024018U) | 
| (USART0) Receive Holding Register  More... | |
| #define | REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) | 
| (USART0) Receiver Time-out Register  More... | |
| #define | REG_USART0_THR (*(__O uint32_t*)0x4002401CU) | 
| (USART0) Transmit Holding Register  More... | |
| #define | REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) | 
| (USART0) Transmitter Timeguard Register  More... | |
| #define | REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) | 
| (USART0) Version Register  More... | |
| #define | REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) | 
| (USART0) Write Protection Mode Register  More... | |
| #define | REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) | 
| (USART0) Write Protection Status Register  More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file usart0.h.
| #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) | 
| #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) | 
| #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) | 
| #define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) | 
| #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) | 
| #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) | 
| #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) | 
| #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) | 
| #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) | 
| #define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) | 
| #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) | 
| #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) | 
| #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) | 
| #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) | 
| #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) | 
| #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) | 
| #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) | 
| #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) | 
| #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) | 
| #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) | 
| #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) | 
| #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) | 
| #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) | 
| #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) | 
| #define REG_USART0_NER (*(__I uint32_t*)0x40024044U) | 
| #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) | 
| #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) | 
| #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) | 
| #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) | 
| #define REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) | 
| #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) |