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Macros | |
| #define | REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) | 
| (USART1) Baud Rate Generator Register  More... | |
| #define | REG_USART1_CR (*(__O uint32_t*)0x40028000U) | 
| (USART1) Control Register  More... | |
| #define | REG_USART1_CSR (*(__I uint32_t*)0x40028014U) | 
| (USART1) Channel Status Register  More... | |
| #define | REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) | 
| (USART1) FI DI Ratio Register  More... | |
| #define | REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) | 
| (USART1) IC DIFF Register  More... | |
| #define | REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) | 
| (USART1) Interrupt Disable Register  More... | |
| #define | REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) | 
| (USART1) LON IDT Rx Register  More... | |
| #define | REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) | 
| (USART1) LON IDT Tx Register  More... | |
| #define | REG_USART1_IER (*(__O uint32_t*)0x40028008U) | 
| (USART1) Interrupt Enable Register  More... | |
| #define | REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) | 
| (USART1) IrDA Filter Register  More... | |
| #define | REG_USART1_IMR (*(__I uint32_t*)0x40028010U) | 
| (USART1) Interrupt Mask Register  More... | |
| #define | REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) | 
| (USART1) LIN Baud Rate Register  More... | |
| #define | REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) | 
| (USART1) LIN Identifier Register  More... | |
| #define | REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) | 
| (USART1) LIN Mode Register  More... | |
| #define | REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) | 
| (USART1) LON Beta1 Rx Register  More... | |
| #define | REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) | 
| (USART1) LON Beta1 Tx Register  More... | |
| #define | REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) | 
| (USART1) LON Backlog Register  More... | |
| #define | REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) | 
| (USART1) LON Data Length Register  More... | |
| #define | REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) | 
| (USART1) LON L2HDR Register  More... | |
| #define | REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) | 
| (USART1) LON Mode Register  More... | |
| #define | REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) | 
| (USART1) LON Preamble Register  More... | |
| #define | REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) | 
| (USART1) LON Priority Register  More... | |
| #define | REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) | 
| (USART1) Manchester Configuration Register  More... | |
| #define | REG_USART1_MR (*(__IO uint32_t*)0x40028004U) | 
| (USART1) Mode Register  More... | |
| #define | REG_USART1_NER (*(__I uint32_t*)0x40028044U) | 
| (USART1) Number of Errors Register  More... | |
| #define | REG_USART1_RHR (*(__I uint32_t*)0x40028018U) | 
| (USART1) Receive Holding Register  More... | |
| #define | REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) | 
| (USART1) Receiver Time-out Register  More... | |
| #define | REG_USART1_THR (*(__O uint32_t*)0x4002801CU) | 
| (USART1) Transmit Holding Register  More... | |
| #define | REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) | 
| (USART1) Transmitter Timeguard Register  More... | |
| #define | REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) | 
| (USART1) Version Register  More... | |
| #define | REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) | 
| (USART1) Write Protection Mode Register  More... | |
| #define | REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) | 
| (USART1) Write Protection Status Register  More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file usart1.h.
| #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) | 
| #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) | 
| #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) | 
| #define REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) | 
| #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) | 
| #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) | 
| #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) | 
| #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) | 
| #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) | 
| #define REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) | 
| #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) | 
| #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) | 
| #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) | 
| #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) | 
| #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) | 
| #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) | 
| #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) | 
| #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) | 
| #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) | 
| #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) | 
| #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) | 
| #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) | 
| #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) | 
| #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) | 
| #define REG_USART1_NER (*(__I uint32_t*)0x40028044U) | 
| #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) | 
| #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) | 
| #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) | 
| #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) | 
| #define REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) | 
| #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) |