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Macros
#define	REG_AFEC1_ACR ((__IO uint32_t)0x40064094U)
	(AFEC1) AFEC Analog Control Register More...

#define	REG_AFEC1_CDR ((__I uint32_t)0x40064068U)
	(AFEC1) AFEC Channel Data Register More...

#define	REG_AFEC1_CECR ((__IO uint32_t)0x400640D8U)
	(AFEC1) AFEC Channel Error Correction Register More...

#define	REG_AFEC1_CGR ((__IO uint32_t)0x40064054U)
	(AFEC1) AFEC Channel Gain Register More...

#define	REG_AFEC1_CHDR ((__O uint32_t)0x40064018U)
	(AFEC1) AFEC Channel Disable Register More...

#define	REG_AFEC1_CHER ((__O uint32_t)0x40064014U)
	(AFEC1) AFEC Channel Enable Register More...

#define	REG_AFEC1_CHSR ((__I uint32_t)0x4006401CU)
	(AFEC1) AFEC Channel Status Register More...

#define	REG_AFEC1_COCR ((__IO uint32_t)0x4006406CU)
	(AFEC1) AFEC Channel Offset Compensation Register More...

#define	REG_AFEC1_COSR ((__IO uint32_t)0x400640D0U)
	(AFEC1) AFEC Correction Select Register More...

#define	REG_AFEC1_CR ((__O uint32_t)0x40064000U)
	(AFEC1) AFEC Control Register More...

#define	REG_AFEC1_CSELR ((__IO uint32_t)0x40064064U)
	(AFEC1) AFEC Channel Selection Register More...

#define	REG_AFEC1_CVR ((__IO uint32_t)0x400640D4U)
	(AFEC1) AFEC Correction Values Register More...

#define	REG_AFEC1_CWR ((__IO uint32_t)0x40064050U)
	(AFEC1) AFEC Compare Window Register More...

#define	REG_AFEC1_DIFFR ((__IO uint32_t)0x40064060U)
	(AFEC1) AFEC Channel Differential Register More...

#define	REG_AFEC1_EMR ((__IO uint32_t)0x40064008U)
	(AFEC1) AFEC Extended Mode Register More...

#define	REG_AFEC1_IDR ((__O uint32_t)0x40064028U)
	(AFEC1) AFEC Interrupt Disable Register More...

#define	REG_AFEC1_IER ((__O uint32_t)0x40064024U)
	(AFEC1) AFEC Interrupt Enable Register More...

#define	REG_AFEC1_IMR ((__I uint32_t)0x4006402CU)
	(AFEC1) AFEC Interrupt Mask Register More...

#define	REG_AFEC1_ISR ((__I uint32_t)0x40064030U)
	(AFEC1) AFEC Interrupt Status Register More...

#define	REG_AFEC1_LCDR ((__I uint32_t)0x40064020U)
	(AFEC1) AFEC Last Converted Data Register More...

#define	REG_AFEC1_MR ((__IO uint32_t)0x40064004U)
	(AFEC1) AFEC Mode Register More...

#define	REG_AFEC1_OVER ((__I uint32_t)0x4006404CU)
	(AFEC1) AFEC Overrun Status Register More...

#define	REG_AFEC1_SEQ1R ((__IO uint32_t)0x4006400CU)
	(AFEC1) AFEC Channel Sequence 1 Register More...

#define	REG_AFEC1_SEQ2R ((__IO uint32_t)0x40064010U)
	(AFEC1) AFEC Channel Sequence 2 Register More...

#define	REG_AFEC1_SHMR ((__IO uint32_t)0x400640A0U)
	(AFEC1) AFEC Sample & Hold Mode Register More...

#define	REG_AFEC1_TEMPCWR ((__IO uint32_t)0x40064074U)
	(AFEC1) AFEC Temperature Compare Window Register More...

#define	REG_AFEC1_TEMPMR ((__IO uint32_t)0x40064070U)
	(AFEC1) AFEC Temperature Sensor Mode Register More...

#define	REG_AFEC1_VERSION ((__I uint32_t)0x400640FCU)
	(AFEC1) AFEC Version Register More...

#define	REG_AFEC1_WPMR ((__IO uint32_t)0x400640E4U)
	(AFEC1) AFEC Write Protection Mode Register More...

#define	REG_AFEC1_WPSR ((__I uint32_t)0x400640E8U)
	(AFEC1) AFEC Write Protection Status Register More...

Detailed Description

Definition in file afec1.h.

Macro Definition Documentation

◆ REG_AFEC1_ACR

#define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U)

(AFEC1) AFEC Analog Control Register

Definition at line 93 of file afec1.h.

◆ REG_AFEC1_CDR

#define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U)

(AFEC1) AFEC Channel Data Register

Definition at line 89 of file afec1.h.

◆ REG_AFEC1_CECR

#define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U)

(AFEC1) AFEC Channel Error Correction Register

Definition at line 97 of file afec1.h.

◆ REG_AFEC1_CGR

#define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U)

(AFEC1) AFEC Channel Gain Register

Definition at line 86 of file afec1.h.

◆ REG_AFEC1_CHDR

#define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U)

(AFEC1) AFEC Channel Disable Register

Definition at line 77 of file afec1.h.

◆ REG_AFEC1_CHER

#define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U)

(AFEC1) AFEC Channel Enable Register

Definition at line 76 of file afec1.h.

◆ REG_AFEC1_CHSR

#define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU)

(AFEC1) AFEC Channel Status Register

Definition at line 78 of file afec1.h.

◆ REG_AFEC1_COCR

#define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU)

(AFEC1) AFEC Channel Offset Compensation Register

Definition at line 90 of file afec1.h.

◆ REG_AFEC1_COSR

#define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U)

(AFEC1) AFEC Correction Select Register

Definition at line 95 of file afec1.h.

◆ REG_AFEC1_CR

#define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U)

(AFEC1) AFEC Control Register

Definition at line 71 of file afec1.h.

◆ REG_AFEC1_CSELR

#define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U)

(AFEC1) AFEC Channel Selection Register

Definition at line 88 of file afec1.h.

◆ REG_AFEC1_CVR

#define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U)

(AFEC1) AFEC Correction Values Register

Definition at line 96 of file afec1.h.

◆ REG_AFEC1_CWR

#define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U)

(AFEC1) AFEC Compare Window Register

Definition at line 85 of file afec1.h.

◆ REG_AFEC1_DIFFR

#define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U)

(AFEC1) AFEC Channel Differential Register

Definition at line 87 of file afec1.h.

◆ REG_AFEC1_EMR

#define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U)

(AFEC1) AFEC Extended Mode Register

Definition at line 73 of file afec1.h.

◆ REG_AFEC1_IDR

#define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U)

(AFEC1) AFEC Interrupt Disable Register

Definition at line 81 of file afec1.h.

◆ REG_AFEC1_IER

#define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U)

(AFEC1) AFEC Interrupt Enable Register

Definition at line 80 of file afec1.h.

◆ REG_AFEC1_IMR

#define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU)

(AFEC1) AFEC Interrupt Mask Register

Definition at line 82 of file afec1.h.

◆ REG_AFEC1_ISR

#define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U)

(AFEC1) AFEC Interrupt Status Register

Definition at line 83 of file afec1.h.

◆ REG_AFEC1_LCDR

#define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U)

(AFEC1) AFEC Last Converted Data Register

Definition at line 79 of file afec1.h.

◆ REG_AFEC1_MR

#define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U)

(AFEC1) AFEC Mode Register

Definition at line 72 of file afec1.h.

◆ REG_AFEC1_OVER

#define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU)

(AFEC1) AFEC Overrun Status Register

Definition at line 84 of file afec1.h.

◆ REG_AFEC1_SEQ1R

#define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU)

(AFEC1) AFEC Channel Sequence 1 Register

Definition at line 74 of file afec1.h.

◆ REG_AFEC1_SEQ2R

#define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U)

(AFEC1) AFEC Channel Sequence 2 Register

Definition at line 75 of file afec1.h.

◆ REG_AFEC1_SHMR

#define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U)

(AFEC1) AFEC Sample & Hold Mode Register

Definition at line 94 of file afec1.h.

◆ REG_AFEC1_TEMPCWR

#define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U)

(AFEC1) AFEC Temperature Compare Window Register

Definition at line 92 of file afec1.h.

◆ REG_AFEC1_TEMPMR

#define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U)

(AFEC1) AFEC Temperature Sensor Mode Register

Definition at line 91 of file afec1.h.

◆ REG_AFEC1_VERSION

#define REG_AFEC1_VERSION (*(__I uint32_t*)0x400640FCU)

(AFEC1) AFEC Version Register

Definition at line 100 of file afec1.h.

◆ REG_AFEC1_WPMR

#define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U)

(AFEC1) AFEC Write Protection Mode Register

Definition at line 98 of file afec1.h.

◆ REG_AFEC1_WPSR

#define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U)

(AFEC1) AFEC Write Protection Status Register

Definition at line 99 of file afec1.h.

Macros