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Macros
#define	REG_TC2_BCR ((__O uint32_t)0x400140C0U)
	(TC2) Block Control Register More...

#define	REG_TC2_BMR ((__IO uint32_t)0x400140C4U)
	(TC2) Block Mode Register More...

#define	REG_TC2_CCR0 ((__O uint32_t)0x40014000U)
	(TC2) Channel Control Register (channel = 0) More...

#define	REG_TC2_CCR1 ((__O uint32_t)0x40014040U)
	(TC2) Channel Control Register (channel = 1) More...

#define	REG_TC2_CCR2 ((__O uint32_t)0x40014080U)
	(TC2) Channel Control Register (channel = 2) More...

#define	REG_TC2_CMR0 ((__IO uint32_t)0x40014004U)
	(TC2) Channel Mode Register (channel = 0) More...

#define	REG_TC2_CMR1 ((__IO uint32_t)0x40014044U)
	(TC2) Channel Mode Register (channel = 1) More...

#define	REG_TC2_CMR2 ((__IO uint32_t)0x40014084U)
	(TC2) Channel Mode Register (channel = 2) More...

#define	REG_TC2_CV0 ((__I uint32_t)0x40014010U)
	(TC2) Counter Value (channel = 0) More...

#define	REG_TC2_CV1 ((__I uint32_t)0x40014050U)
	(TC2) Counter Value (channel = 1) More...

#define	REG_TC2_CV2 ((__I uint32_t)0x40014090U)
	(TC2) Counter Value (channel = 2) More...

#define	REG_TC2_EMR0 ((__IO uint32_t)0x40014030U)
	(TC2) Extended Mode Register (channel = 0) More...

#define	REG_TC2_EMR1 ((__IO uint32_t)0x40014070U)
	(TC2) Extended Mode Register (channel = 1) More...

#define	REG_TC2_EMR2 ((__IO uint32_t)0x400140B0U)
	(TC2) Extended Mode Register (channel = 2) More...

#define	REG_TC2_FMR ((__IO uint32_t)0x400140D8U)
	(TC2) Fault Mode Register More...

#define	REG_TC2_IDR0 ((__O uint32_t)0x40014028U)
	(TC2) Interrupt Disable Register (channel = 0) More...

#define	REG_TC2_IDR1 ((__O uint32_t)0x40014068U)
	(TC2) Interrupt Disable Register (channel = 1) More...

#define	REG_TC2_IDR2 ((__O uint32_t)0x400140A8U)
	(TC2) Interrupt Disable Register (channel = 2) More...

#define	REG_TC2_IER0 ((__O uint32_t)0x40014024U)
	(TC2) Interrupt Enable Register (channel = 0) More...

#define	REG_TC2_IER1 ((__O uint32_t)0x40014064U)
	(TC2) Interrupt Enable Register (channel = 1) More...

#define	REG_TC2_IER2 ((__O uint32_t)0x400140A4U)
	(TC2) Interrupt Enable Register (channel = 2) More...

#define	REG_TC2_IMR0 ((__I uint32_t)0x4001402CU)
	(TC2) Interrupt Mask Register (channel = 0) More...

#define	REG_TC2_IMR1 ((__I uint32_t)0x4001406CU)
	(TC2) Interrupt Mask Register (channel = 1) More...

#define	REG_TC2_IMR2 ((__I uint32_t)0x400140ACU)
	(TC2) Interrupt Mask Register (channel = 2) More...

#define	REG_TC2_QIDR ((__O uint32_t)0x400140CCU)
	(TC2) QDEC Interrupt Disable Register More...

#define	REG_TC2_QIER ((__O uint32_t)0x400140C8U)
	(TC2) QDEC Interrupt Enable Register More...

#define	REG_TC2_QIMR ((__I uint32_t)0x400140D0U)
	(TC2) QDEC Interrupt Mask Register More...

#define	REG_TC2_QISR ((__I uint32_t)0x400140D4U)
	(TC2) QDEC Interrupt Status Register More...

#define	REG_TC2_RA0 ((__IO uint32_t)0x40014014U)
	(TC2) Register A (channel = 0) More...

#define	REG_TC2_RA1 ((__IO uint32_t)0x40014054U)
	(TC2) Register A (channel = 1) More...

#define	REG_TC2_RA2 ((__IO uint32_t)0x40014094U)
	(TC2) Register A (channel = 2) More...

#define	REG_TC2_RAB0 ((__I uint32_t)0x4001400CU)
	(TC2) Register AB (channel = 0) More...

#define	REG_TC2_RAB1 ((__I uint32_t)0x4001404CU)
	(TC2) Register AB (channel = 1) More...

#define	REG_TC2_RAB2 ((__I uint32_t)0x4001408CU)
	(TC2) Register AB (channel = 2) More...

#define	REG_TC2_RB0 ((__IO uint32_t)0x40014018U)
	(TC2) Register B (channel = 0) More...

#define	REG_TC2_RB1 ((__IO uint32_t)0x40014058U)
	(TC2) Register B (channel = 1) More...

#define	REG_TC2_RB2 ((__IO uint32_t)0x40014098U)
	(TC2) Register B (channel = 2) More...

#define	REG_TC2_RC0 ((__IO uint32_t)0x4001401CU)
	(TC2) Register C (channel = 0) More...

#define	REG_TC2_RC1 ((__IO uint32_t)0x4001405CU)
	(TC2) Register C (channel = 1) More...

#define	REG_TC2_RC2 ((__IO uint32_t)0x4001409CU)
	(TC2) Register C (channel = 2) More...

#define	REG_TC2_SMMR0 ((__IO uint32_t)0x40014008U)
	(TC2) Stepper Motor Mode Register (channel = 0) More...

#define	REG_TC2_SMMR1 ((__IO uint32_t)0x40014048U)
	(TC2) Stepper Motor Mode Register (channel = 1) More...

#define	REG_TC2_SMMR2 ((__IO uint32_t)0x40014088U)
	(TC2) Stepper Motor Mode Register (channel = 2) More...

#define	REG_TC2_SR0 ((__I uint32_t)0x40014020U)
	(TC2) Status Register (channel = 0) More...

#define	REG_TC2_SR1 ((__I uint32_t)0x40014060U)
	(TC2) Status Register (channel = 1) More...

#define	REG_TC2_SR2 ((__I uint32_t)0x400140A0U)
	(TC2) Status Register (channel = 2) More...

#define	REG_TC2_VER ((__I uint32_t)0x400140FCU)
	(TC2) Version Register More...

#define	REG_TC2_WPMR ((__IO uint32_t)0x400140E4U)
	(TC2) Write Protection Mode Register More...

Detailed Description

Definition in file tc2.h.

Macro Definition Documentation

◆ REG_TC2_BCR

#define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U)

(TC2) Block Control Register

Definition at line 128 of file tc2.h.

◆ REG_TC2_BMR

#define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U)

(TC2) Block Mode Register

Definition at line 129 of file tc2.h.

◆ REG_TC2_CCR0

#define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U)

(TC2) Channel Control Register (channel = 0)

Definition at line 89 of file tc2.h.

◆ REG_TC2_CCR1

#define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U)

(TC2) Channel Control Register (channel = 1)

Definition at line 102 of file tc2.h.

◆ REG_TC2_CCR2

#define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U)

(TC2) Channel Control Register (channel = 2)

Definition at line 115 of file tc2.h.

◆ REG_TC2_CMR0

#define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U)

(TC2) Channel Mode Register (channel = 0)

Definition at line 90 of file tc2.h.

◆ REG_TC2_CMR1

#define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U)

(TC2) Channel Mode Register (channel = 1)

Definition at line 103 of file tc2.h.

◆ REG_TC2_CMR2

#define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U)

(TC2) Channel Mode Register (channel = 2)

Definition at line 116 of file tc2.h.

◆ REG_TC2_CV0

#define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U)

(TC2) Counter Value (channel = 0)

Definition at line 93 of file tc2.h.

◆ REG_TC2_CV1

#define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U)

(TC2) Counter Value (channel = 1)

Definition at line 106 of file tc2.h.

◆ REG_TC2_CV2

#define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U)

(TC2) Counter Value (channel = 2)

Definition at line 119 of file tc2.h.

◆ REG_TC2_EMR0

#define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U)

(TC2) Extended Mode Register (channel = 0)

Definition at line 101 of file tc2.h.

◆ REG_TC2_EMR1

#define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U)

(TC2) Extended Mode Register (channel = 1)

Definition at line 114 of file tc2.h.

◆ REG_TC2_EMR2

#define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U)

(TC2) Extended Mode Register (channel = 2)

Definition at line 127 of file tc2.h.

◆ REG_TC2_FMR

#define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U)

(TC2) Fault Mode Register

Definition at line 134 of file tc2.h.

◆ REG_TC2_IDR0

#define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U)

(TC2) Interrupt Disable Register (channel = 0)

Definition at line 99 of file tc2.h.

◆ REG_TC2_IDR1

#define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U)

(TC2) Interrupt Disable Register (channel = 1)

Definition at line 112 of file tc2.h.

◆ REG_TC2_IDR2

#define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U)

(TC2) Interrupt Disable Register (channel = 2)

Definition at line 125 of file tc2.h.

◆ REG_TC2_IER0

#define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U)

(TC2) Interrupt Enable Register (channel = 0)

Definition at line 98 of file tc2.h.

◆ REG_TC2_IER1

#define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U)

(TC2) Interrupt Enable Register (channel = 1)

Definition at line 111 of file tc2.h.

◆ REG_TC2_IER2

#define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U)

(TC2) Interrupt Enable Register (channel = 2)

Definition at line 124 of file tc2.h.

◆ REG_TC2_IMR0

#define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU)

(TC2) Interrupt Mask Register (channel = 0)

Definition at line 100 of file tc2.h.

◆ REG_TC2_IMR1

#define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU)

(TC2) Interrupt Mask Register (channel = 1)

Definition at line 113 of file tc2.h.

◆ REG_TC2_IMR2

#define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU)

(TC2) Interrupt Mask Register (channel = 2)

Definition at line 126 of file tc2.h.

◆ REG_TC2_QIDR

#define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU)

(TC2) QDEC Interrupt Disable Register

Definition at line 131 of file tc2.h.

◆ REG_TC2_QIER

#define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U)

(TC2) QDEC Interrupt Enable Register

Definition at line 130 of file tc2.h.

◆ REG_TC2_QIMR

#define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U)

(TC2) QDEC Interrupt Mask Register

Definition at line 132 of file tc2.h.

◆ REG_TC2_QISR

#define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U)

(TC2) QDEC Interrupt Status Register

Definition at line 133 of file tc2.h.

◆ REG_TC2_RA0

#define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U)

(TC2) Register A (channel = 0)

Definition at line 94 of file tc2.h.

◆ REG_TC2_RA1

#define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U)

(TC2) Register A (channel = 1)

Definition at line 107 of file tc2.h.

◆ REG_TC2_RA2

#define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U)

(TC2) Register A (channel = 2)

Definition at line 120 of file tc2.h.

◆ REG_TC2_RAB0

#define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU)

(TC2) Register AB (channel = 0)

Definition at line 92 of file tc2.h.

◆ REG_TC2_RAB1

#define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU)

(TC2) Register AB (channel = 1)

Definition at line 105 of file tc2.h.

◆ REG_TC2_RAB2

#define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU)

(TC2) Register AB (channel = 2)

Definition at line 118 of file tc2.h.

◆ REG_TC2_RB0

#define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U)

(TC2) Register B (channel = 0)

Definition at line 95 of file tc2.h.

◆ REG_TC2_RB1

#define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U)

(TC2) Register B (channel = 1)

Definition at line 108 of file tc2.h.

◆ REG_TC2_RB2

#define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U)

(TC2) Register B (channel = 2)

Definition at line 121 of file tc2.h.

◆ REG_TC2_RC0

#define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU)

(TC2) Register C (channel = 0)

Definition at line 96 of file tc2.h.

◆ REG_TC2_RC1

#define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU)

(TC2) Register C (channel = 1)

Definition at line 109 of file tc2.h.

◆ REG_TC2_RC2

#define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU)

(TC2) Register C (channel = 2)

Definition at line 122 of file tc2.h.

◆ REG_TC2_SMMR0

#define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U)

(TC2) Stepper Motor Mode Register (channel = 0)

Definition at line 91 of file tc2.h.

◆ REG_TC2_SMMR1

#define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U)

(TC2) Stepper Motor Mode Register (channel = 1)

Definition at line 104 of file tc2.h.

◆ REG_TC2_SMMR2

#define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U)

(TC2) Stepper Motor Mode Register (channel = 2)

Definition at line 117 of file tc2.h.

◆ REG_TC2_SR0

#define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U)

(TC2) Status Register (channel = 0)

Definition at line 97 of file tc2.h.

◆ REG_TC2_SR1

#define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U)

(TC2) Status Register (channel = 1)

Definition at line 110 of file tc2.h.

◆ REG_TC2_SR2

#define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U)

(TC2) Status Register (channel = 2)

Definition at line 123 of file tc2.h.

◆ REG_TC2_VER

#define REG_TC2_VER (*(__I uint32_t*)0x400140FCU)

(TC2) Version Register

Definition at line 136 of file tc2.h.

◆ REG_TC2_WPMR

#define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U)

(TC2) Write Protection Mode Register

Definition at line 135 of file tc2.h.

Macros