This graph shows which files directly or indirectly include this file:

Macros
#define	REG_MCAN1_BTP ((__IO uint32_t)0x4003401CU)
	(MCAN1) Bit Timing and Prescaler Register More...

#define	REG_MCAN1_CCCR ((__IO uint32_t)0x40034018U)
	(MCAN1) CC Control Register More...

#define	REG_MCAN1_CREL ((__I uint32_t)0x40034000U)
	(MCAN1) Core Release Register More...

#define	REG_MCAN1_CUST ((__IO uint32_t)0x40034008U)
	(MCAN1) Customer Register More...

#define	REG_MCAN1_DBTP ((__IO uint32_t)0x4003400CU)
	(MCAN1) Data Bit Timing and Prescaler Register More...

#define	REG_MCAN1_ECR ((__I uint32_t)0x40034040U)
	(MCAN1) Error Counter Register More...

#define	REG_MCAN1_ENDN ((__I uint32_t)0x40034004U)
	(MCAN1) Endian Register More...

#define	REG_MCAN1_FBTP ((__IO uint32_t)0x4003400CU)
	(MCAN1) Fast Bit Timing and Prescaler Register More...

#define	REG_MCAN1_GFC ((__IO uint32_t)0x40034080U)
	(MCAN1) Global Filter Configuration Register More...

#define	REG_MCAN1_HPMS ((__I uint32_t)0x40034094U)
	(MCAN1) High Priority Message Status Register More...

#define	REG_MCAN1_IE ((__IO uint32_t)0x40034054U)
	(MCAN1) Interrupt Enable Register More...

#define	REG_MCAN1_ILE ((__IO uint32_t)0x4003405CU)
	(MCAN1) Interrupt Line Enable Register More...

#define	REG_MCAN1_ILS ((__IO uint32_t)0x40034058U)
	(MCAN1) Interrupt Line Select Register More...

#define	REG_MCAN1_IR ((__IO uint32_t)0x40034050U)
	(MCAN1) Interrupt Register More...

#define	REG_MCAN1_NBTP ((__IO uint32_t)0x4003401CU)
	(MCAN1) Nominal Bit Timing and Prescaler Register More...

#define	REG_MCAN1_NDAT1 ((__IO uint32_t)0x40034098U)
	(MCAN1) New Data 1 Register More...

#define	REG_MCAN1_NDAT2 ((__IO uint32_t)0x4003409CU)
	(MCAN1) New Data 2 Register More...

#define	REG_MCAN1_PSR ((__I uint32_t)0x40034044U)
	(MCAN1) Protocol Status Register More...

#define	REG_MCAN1_RWD ((__IO uint32_t)0x40034014U)
	(MCAN1) RAM Watchdog Register More...

#define	REG_MCAN1_RXBC ((__IO uint32_t)0x400340ACU)
	(MCAN1) Receive Rx Buffer Configuration Register More...

#define	REG_MCAN1_RXESC ((__IO uint32_t)0x400340BCU)
	(MCAN1) Receive Buffer / FIFO Element Size Configuration Register More...

#define	REG_MCAN1_RXF0A ((__IO uint32_t)0x400340A8U)
	(MCAN1) Receive FIFO 0 Acknowledge Register More...

#define	REG_MCAN1_RXF0C ((__IO uint32_t)0x400340A0U)
	(MCAN1) Receive FIFO 0 Configuration Register More...

#define	REG_MCAN1_RXF0S ((__I uint32_t)0x400340A4U)
	(MCAN1) Receive FIFO 0 Status Register More...

#define	REG_MCAN1_RXF1A ((__IO uint32_t)0x400340B8U)
	(MCAN1) Receive FIFO 1 Acknowledge Register More...

#define	REG_MCAN1_RXF1C ((__IO uint32_t)0x400340B0U)
	(MCAN1) Receive FIFO 1 Configuration Register More...

#define	REG_MCAN1_RXF1S ((__I uint32_t)0x400340B4U)
	(MCAN1) Receive FIFO 1 Status Register More...

#define	REG_MCAN1_SIDFC ((__IO uint32_t)0x40034084U)
	(MCAN1) Standard ID Filter Configuration Register More...

#define	REG_MCAN1_TDCR ((__IO uint32_t)0x40034048U)
	(MCAN1) Transmit Delay Compensation Register More...

#define	REG_MCAN1_TEST ((__IO uint32_t)0x40034010U)
	(MCAN1) Test Register More...

#define	REG_MCAN1_TOCC ((__IO uint32_t)0x40034028U)
	(MCAN1) Timeout Counter Configuration Register More...

#define	REG_MCAN1_TOCV ((__IO uint32_t)0x4003402CU)
	(MCAN1) Timeout Counter Value Register More...

#define	REG_MCAN1_TSCC ((__IO uint32_t)0x40034020U)
	(MCAN1) Timestamp Counter Configuration Register More...

#define	REG_MCAN1_TSCV ((__IO uint32_t)0x40034024U)
	(MCAN1) Timestamp Counter Value Register More...

#define	REG_MCAN1_TXBAR ((__IO uint32_t)0x400340D0U)
	(MCAN1) Transmit Buffer Add Request Register More...

#define	REG_MCAN1_TXBC ((__IO uint32_t)0x400340C0U)
	(MCAN1) Transmit Buffer Configuration Register More...

#define	REG_MCAN1_TXBCF ((__I uint32_t)0x400340DCU)
	(MCAN1) Transmit Buffer Cancellation Finished Register More...

#define	REG_MCAN1_TXBCIE ((__IO uint32_t)0x400340E4U)
	(MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register More...

#define	REG_MCAN1_TXBCR ((__IO uint32_t)0x400340D4U)
	(MCAN1) Transmit Buffer Cancellation Request Register More...

#define	REG_MCAN1_TXBRP ((__I uint32_t)0x400340CCU)
	(MCAN1) Transmit Buffer Request Pending Register More...

#define	REG_MCAN1_TXBTIE ((__IO uint32_t)0x400340E0U)
	(MCAN1) Transmit Buffer Transmission Interrupt Enable Register More...

#define	REG_MCAN1_TXBTO ((__I uint32_t)0x400340D8U)
	(MCAN1) Transmit Buffer Transmission Occurred Register More...

#define	REG_MCAN1_TXEFA ((__IO uint32_t)0x400340F8U)
	(MCAN1) Transmit Event FIFO Acknowledge Register More...

#define	REG_MCAN1_TXEFC ((__IO uint32_t)0x400340F0U)
	(MCAN1) Transmit Event FIFO Configuration Register More...

#define	REG_MCAN1_TXEFS ((__I uint32_t)0x400340F4U)
	(MCAN1) Transmit Event FIFO Status Register More...

#define	REG_MCAN1_TXESC ((__IO uint32_t)0x400340C8U)
	(MCAN1) Transmit Buffer Element Size Configuration Register More...

#define	REG_MCAN1_TXFQS ((__I uint32_t)0x400340C4U)
	(MCAN1) Transmit FIFO/Queue Status Register More...

#define	REG_MCAN1_XIDAM ((__IO uint32_t)0x40034090U)
	(MCAN1) Extended ID AND Mask Register More...

#define	REG_MCAN1_XIDFC ((__IO uint32_t)0x40034088U)
	(MCAN1) Extended ID Filter Configuration Register More...

Detailed Description

Definition in file mcan1.h.

Macro Definition Documentation

◆ REG_MCAN1_BTP

#define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU)

(MCAN1) Bit Timing and Prescaler Register

Definition at line 98 of file mcan1.h.

◆ REG_MCAN1_CCCR

#define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U)

(MCAN1) CC Control Register

Definition at line 97 of file mcan1.h.

◆ REG_MCAN1_CREL

#define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U)

(MCAN1) Core Release Register

Definition at line 90 of file mcan1.h.

◆ REG_MCAN1_CUST

#define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U)

(MCAN1) Customer Register

Definition at line 92 of file mcan1.h.

◆ REG_MCAN1_DBTP

#define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU)

(MCAN1) Data Bit Timing and Prescaler Register

Definition at line 94 of file mcan1.h.

◆ REG_MCAN1_ECR

#define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U)

(MCAN1) Error Counter Register

Definition at line 104 of file mcan1.h.

◆ REG_MCAN1_ENDN

#define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U)

(MCAN1) Endian Register

Definition at line 91 of file mcan1.h.

◆ REG_MCAN1_FBTP

#define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU)

(MCAN1) Fast Bit Timing and Prescaler Register

Definition at line 93 of file mcan1.h.

◆ REG_MCAN1_GFC

#define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U)

(MCAN1) Global Filter Configuration Register

Definition at line 111 of file mcan1.h.

◆ REG_MCAN1_HPMS

#define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U)

(MCAN1) High Priority Message Status Register

Definition at line 115 of file mcan1.h.

◆ REG_MCAN1_IE

#define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U)

(MCAN1) Interrupt Enable Register

Definition at line 108 of file mcan1.h.

◆ REG_MCAN1_ILE

#define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU)

(MCAN1) Interrupt Line Enable Register

Definition at line 110 of file mcan1.h.

◆ REG_MCAN1_ILS

#define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U)

(MCAN1) Interrupt Line Select Register

Definition at line 109 of file mcan1.h.

◆ REG_MCAN1_IR

#define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U)

(MCAN1) Interrupt Register

Definition at line 107 of file mcan1.h.

◆ REG_MCAN1_NBTP

#define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU)

(MCAN1) Nominal Bit Timing and Prescaler Register

Definition at line 99 of file mcan1.h.

◆ REG_MCAN1_NDAT1

#define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U)

(MCAN1) New Data 1 Register

Definition at line 116 of file mcan1.h.

◆ REG_MCAN1_NDAT2

#define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU)

(MCAN1) New Data 2 Register

Definition at line 117 of file mcan1.h.

◆ REG_MCAN1_PSR

#define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U)

(MCAN1) Protocol Status Register

Definition at line 105 of file mcan1.h.

◆ REG_MCAN1_RWD

#define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U)

(MCAN1) RAM Watchdog Register

Definition at line 96 of file mcan1.h.

◆ REG_MCAN1_RXBC

#define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU)

(MCAN1) Receive Rx Buffer Configuration Register

Definition at line 121 of file mcan1.h.

◆ REG_MCAN1_RXESC

#define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU)

(MCAN1) Receive Buffer / FIFO Element Size Configuration Register

Definition at line 125 of file mcan1.h.

◆ REG_MCAN1_RXF0A

#define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U)

(MCAN1) Receive FIFO 0 Acknowledge Register

Definition at line 120 of file mcan1.h.

◆ REG_MCAN1_RXF0C

#define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U)

(MCAN1) Receive FIFO 0 Configuration Register

Definition at line 118 of file mcan1.h.

◆ REG_MCAN1_RXF0S

#define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U)

(MCAN1) Receive FIFO 0 Status Register

Definition at line 119 of file mcan1.h.

◆ REG_MCAN1_RXF1A

#define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U)

(MCAN1) Receive FIFO 1 Acknowledge Register

Definition at line 124 of file mcan1.h.

◆ REG_MCAN1_RXF1C

#define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U)

(MCAN1) Receive FIFO 1 Configuration Register

Definition at line 122 of file mcan1.h.

◆ REG_MCAN1_RXF1S

#define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U)

(MCAN1) Receive FIFO 1 Status Register

Definition at line 123 of file mcan1.h.

◆ REG_MCAN1_SIDFC

#define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U)

(MCAN1) Standard ID Filter Configuration Register

Definition at line 112 of file mcan1.h.

◆ REG_MCAN1_TDCR

#define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U)

(MCAN1) Transmit Delay Compensation Register

Definition at line 106 of file mcan1.h.

◆ REG_MCAN1_TEST

#define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U)

(MCAN1) Test Register

Definition at line 95 of file mcan1.h.

◆ REG_MCAN1_TOCC

#define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U)

(MCAN1) Timeout Counter Configuration Register

Definition at line 102 of file mcan1.h.

◆ REG_MCAN1_TOCV

#define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU)

(MCAN1) Timeout Counter Value Register

Definition at line 103 of file mcan1.h.

◆ REG_MCAN1_TSCC

#define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U)

(MCAN1) Timestamp Counter Configuration Register

Definition at line 100 of file mcan1.h.

◆ REG_MCAN1_TSCV

#define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U)

(MCAN1) Timestamp Counter Value Register

Definition at line 101 of file mcan1.h.

◆ REG_MCAN1_TXBAR

#define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U)

(MCAN1) Transmit Buffer Add Request Register

Definition at line 130 of file mcan1.h.

◆ REG_MCAN1_TXBC

#define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U)

(MCAN1) Transmit Buffer Configuration Register

Definition at line 126 of file mcan1.h.

◆ REG_MCAN1_TXBCF

#define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU)

(MCAN1) Transmit Buffer Cancellation Finished Register

Definition at line 133 of file mcan1.h.

◆ REG_MCAN1_TXBCIE

#define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U)

(MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register

Definition at line 135 of file mcan1.h.

◆ REG_MCAN1_TXBCR

#define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U)

(MCAN1) Transmit Buffer Cancellation Request Register

Definition at line 131 of file mcan1.h.

◆ REG_MCAN1_TXBRP

#define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU)

(MCAN1) Transmit Buffer Request Pending Register

Definition at line 129 of file mcan1.h.

◆ REG_MCAN1_TXBTIE

#define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U)

(MCAN1) Transmit Buffer Transmission Interrupt Enable Register

Definition at line 134 of file mcan1.h.

◆ REG_MCAN1_TXBTO

#define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U)

(MCAN1) Transmit Buffer Transmission Occurred Register

Definition at line 132 of file mcan1.h.

◆ REG_MCAN1_TXEFA

#define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U)

(MCAN1) Transmit Event FIFO Acknowledge Register

Definition at line 138 of file mcan1.h.

◆ REG_MCAN1_TXEFC

#define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U)

(MCAN1) Transmit Event FIFO Configuration Register

Definition at line 136 of file mcan1.h.

◆ REG_MCAN1_TXEFS

#define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U)

(MCAN1) Transmit Event FIFO Status Register

Definition at line 137 of file mcan1.h.

◆ REG_MCAN1_TXESC

#define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U)

(MCAN1) Transmit Buffer Element Size Configuration Register

Definition at line 128 of file mcan1.h.

◆ REG_MCAN1_TXFQS

#define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U)

(MCAN1) Transmit FIFO/Queue Status Register

Definition at line 127 of file mcan1.h.

◆ REG_MCAN1_XIDAM

#define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U)

(MCAN1) Extended ID AND Mask Register

Definition at line 114 of file mcan1.h.

◆ REG_MCAN1_XIDFC

#define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U)

(MCAN1) Extended ID Filter Configuration Register

Definition at line 113 of file mcan1.h.

Macros