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Macros | |
| #define | REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) |
| (XDMAC) Channel Block Control Register (chid = 0) More... | |
| #define | REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) |
| (XDMAC) Channel Block Control Register (chid = 1) More... | |
| #define | REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) |
| (XDMAC) Channel Block Control Register (chid = 10) More... | |
| #define | REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) |
| (XDMAC) Channel Block Control Register (chid = 11) More... | |
| #define | REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) |
| (XDMAC) Channel Block Control Register (chid = 12) More... | |
| #define | REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) |
| (XDMAC) Channel Block Control Register (chid = 13) More... | |
| #define | REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) |
| (XDMAC) Channel Block Control Register (chid = 14) More... | |
| #define | REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) |
| (XDMAC) Channel Block Control Register (chid = 15) More... | |
| #define | REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) |
| (XDMAC) Channel Block Control Register (chid = 16) More... | |
| #define | REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) |
| (XDMAC) Channel Block Control Register (chid = 17) More... | |
| #define | REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) |
| (XDMAC) Channel Block Control Register (chid = 18) More... | |
| #define | REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) |
| (XDMAC) Channel Block Control Register (chid = 19) More... | |
| #define | REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) |
| (XDMAC) Channel Block Control Register (chid = 2) More... | |
| #define | REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) |
| (XDMAC) Channel Block Control Register (chid = 20) More... | |
| #define | REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) |
| (XDMAC) Channel Block Control Register (chid = 21) More... | |
| #define | REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) |
| (XDMAC) Channel Block Control Register (chid = 22) More... | |
| #define | REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) |
| (XDMAC) Channel Block Control Register (chid = 23) More... | |
| #define | REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) |
| (XDMAC) Channel Block Control Register (chid = 3) More... | |
| #define | REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) |
| (XDMAC) Channel Block Control Register (chid = 4) More... | |
| #define | REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) |
| (XDMAC) Channel Block Control Register (chid = 5) More... | |
| #define | REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) |
| (XDMAC) Channel Block Control Register (chid = 6) More... | |
| #define | REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) |
| (XDMAC) Channel Block Control Register (chid = 7) More... | |
| #define | REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) |
| (XDMAC) Channel Block Control Register (chid = 8) More... | |
| #define | REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) |
| (XDMAC) Channel Block Control Register (chid = 9) More... | |
| #define | REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) |
| (XDMAC) Channel Configuration Register (chid = 0) More... | |
| #define | REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) |
| (XDMAC) Channel Configuration Register (chid = 1) More... | |
| #define | REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) |
| (XDMAC) Channel Configuration Register (chid = 10) More... | |
| #define | REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) |
| (XDMAC) Channel Configuration Register (chid = 11) More... | |
| #define | REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) |
| (XDMAC) Channel Configuration Register (chid = 12) More... | |
| #define | REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) |
| (XDMAC) Channel Configuration Register (chid = 13) More... | |
| #define | REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) |
| (XDMAC) Channel Configuration Register (chid = 14) More... | |
| #define | REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) |
| (XDMAC) Channel Configuration Register (chid = 15) More... | |
| #define | REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) |
| (XDMAC) Channel Configuration Register (chid = 16) More... | |
| #define | REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) |
| (XDMAC) Channel Configuration Register (chid = 17) More... | |
| #define | REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) |
| (XDMAC) Channel Configuration Register (chid = 18) More... | |
| #define | REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) |
| (XDMAC) Channel Configuration Register (chid = 19) More... | |
| #define | REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) |
| (XDMAC) Channel Configuration Register (chid = 2) More... | |
| #define | REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) |
| (XDMAC) Channel Configuration Register (chid = 20) More... | |
| #define | REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) |
| (XDMAC) Channel Configuration Register (chid = 21) More... | |
| #define | REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) |
| (XDMAC) Channel Configuration Register (chid = 22) More... | |
| #define | REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) |
| (XDMAC) Channel Configuration Register (chid = 23) More... | |
| #define | REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) |
| (XDMAC) Channel Configuration Register (chid = 3) More... | |
| #define | REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) |
| (XDMAC) Channel Configuration Register (chid = 4) More... | |
| #define | REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) |
| (XDMAC) Channel Configuration Register (chid = 5) More... | |
| #define | REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) |
| (XDMAC) Channel Configuration Register (chid = 6) More... | |
| #define | REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) |
| (XDMAC) Channel Configuration Register (chid = 7) More... | |
| #define | REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) |
| (XDMAC) Channel Configuration Register (chid = 8) More... | |
| #define | REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) |
| (XDMAC) Channel Configuration Register (chid = 9) More... | |
| #define | REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) |
| (XDMAC) Channel Destination Address Register (chid = 0) More... | |
| #define | REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) |
| (XDMAC) Channel Destination Address Register (chid = 1) More... | |
| #define | REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) |
| (XDMAC) Channel Destination Address Register (chid = 10) More... | |
| #define | REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) |
| (XDMAC) Channel Destination Address Register (chid = 11) More... | |
| #define | REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) |
| (XDMAC) Channel Destination Address Register (chid = 12) More... | |
| #define | REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) |
| (XDMAC) Channel Destination Address Register (chid = 13) More... | |
| #define | REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) |
| (XDMAC) Channel Destination Address Register (chid = 14) More... | |
| #define | REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) |
| (XDMAC) Channel Destination Address Register (chid = 15) More... | |
| #define | REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) |
| (XDMAC) Channel Destination Address Register (chid = 16) More... | |
| #define | REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) |
| (XDMAC) Channel Destination Address Register (chid = 17) More... | |
| #define | REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) |
| (XDMAC) Channel Destination Address Register (chid = 18) More... | |
| #define | REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) |
| (XDMAC) Channel Destination Address Register (chid = 19) More... | |
| #define | REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) |
| (XDMAC) Channel Destination Address Register (chid = 2) More... | |
| #define | REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) |
| (XDMAC) Channel Destination Address Register (chid = 20) More... | |
| #define | REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) |
| (XDMAC) Channel Destination Address Register (chid = 21) More... | |
| #define | REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) |
| (XDMAC) Channel Destination Address Register (chid = 22) More... | |
| #define | REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) |
| (XDMAC) Channel Destination Address Register (chid = 23) More... | |
| #define | REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) |
| (XDMAC) Channel Destination Address Register (chid = 3) More... | |
| #define | REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) |
| (XDMAC) Channel Destination Address Register (chid = 4) More... | |
| #define | REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) |
| (XDMAC) Channel Destination Address Register (chid = 5) More... | |
| #define | REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) |
| (XDMAC) Channel Destination Address Register (chid = 6) More... | |
| #define | REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) |
| (XDMAC) Channel Destination Address Register (chid = 7) More... | |
| #define | REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) |
| (XDMAC) Channel Destination Address Register (chid = 8) More... | |
| #define | REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) |
| (XDMAC) Channel Destination Address Register (chid = 9) More... | |
| #define | REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) More... | |
| #define | REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) More... | |
| #define | REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) More... | |
| #define | REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) More... | |
| #define | REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) More... | |
| #define | REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) More... | |
| #define | REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) More... | |
| #define | REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) More... | |
| #define | REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) More... | |
| #define | REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) More... | |
| #define | REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) More... | |
| #define | REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) More... | |
| #define | REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) More... | |
| #define | REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) More... | |
| #define | REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) More... | |
| #define | REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) More... | |
| #define | REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) More... | |
| #define | REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) More... | |
| #define | REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) More... | |
| #define | REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) More... | |
| #define | REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) More... | |
| #define | REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) More... | |
| #define | REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) More... | |
| #define | REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) |
| (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) More... | |
| #define | REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 0) More... | |
| #define | REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 1) More... | |
| #define | REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 10) More... | |
| #define | REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 11) More... | |
| #define | REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 12) More... | |
| #define | REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 13) More... | |
| #define | REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 14) More... | |
| #define | REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 15) More... | |
| #define | REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 16) More... | |
| #define | REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 17) More... | |
| #define | REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 18) More... | |
| #define | REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 19) More... | |
| #define | REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 2) More... | |
| #define | REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 20) More... | |
| #define | REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 21) More... | |
| #define | REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 22) More... | |
| #define | REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 23) More... | |
| #define | REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 3) More... | |
| #define | REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 4) More... | |
| #define | REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 5) More... | |
| #define | REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 6) More... | |
| #define | REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 7) More... | |
| #define | REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 8) More... | |
| #define | REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) |
| (XDMAC) Channel Destination Microblock Stride (chid = 9) More... | |
| #define | REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 0) More... | |
| #define | REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 1) More... | |
| #define | REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 10) More... | |
| #define | REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 11) More... | |
| #define | REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 12) More... | |
| #define | REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 13) More... | |
| #define | REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 14) More... | |
| #define | REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 15) More... | |
| #define | REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 16) More... | |
| #define | REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 17) More... | |
| #define | REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 18) More... | |
| #define | REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 19) More... | |
| #define | REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 2) More... | |
| #define | REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 20) More... | |
| #define | REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 21) More... | |
| #define | REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 22) More... | |
| #define | REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 23) More... | |
| #define | REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 3) More... | |
| #define | REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 4) More... | |
| #define | REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 5) More... | |
| #define | REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 6) More... | |
| #define | REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 7) More... | |
| #define | REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 8) More... | |
| #define | REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) |
| (XDMAC) Channel Interrupt Disable Register (chid = 9) More... | |
| #define | REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 0) More... | |
| #define | REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 1) More... | |
| #define | REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 10) More... | |
| #define | REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 11) More... | |
| #define | REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 12) More... | |
| #define | REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 13) More... | |
| #define | REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 14) More... | |
| #define | REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 15) More... | |
| #define | REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 16) More... | |
| #define | REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 17) More... | |
| #define | REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 18) More... | |
| #define | REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 19) More... | |
| #define | REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 2) More... | |
| #define | REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 20) More... | |
| #define | REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 21) More... | |
| #define | REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 22) More... | |
| #define | REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 23) More... | |
| #define | REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 3) More... | |
| #define | REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 4) More... | |
| #define | REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 5) More... | |
| #define | REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 6) More... | |
| #define | REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 7) More... | |
| #define | REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 8) More... | |
| #define | REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) |
| (XDMAC) Channel Interrupt Enable Register (chid = 9) More... | |
| #define | REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 0) More... | |
| #define | REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 1) More... | |
| #define | REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 10) More... | |
| #define | REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 11) More... | |
| #define | REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 12) More... | |
| #define | REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 13) More... | |
| #define | REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 14) More... | |
| #define | REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 15) More... | |
| #define | REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 16) More... | |
| #define | REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 17) More... | |
| #define | REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 18) More... | |
| #define | REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 19) More... | |
| #define | REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 2) More... | |
| #define | REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 20) More... | |
| #define | REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 21) More... | |
| #define | REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 22) More... | |
| #define | REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 23) More... | |
| #define | REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 3) More... | |
| #define | REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 4) More... | |
| #define | REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 5) More... | |
| #define | REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 6) More... | |
| #define | REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 7) More... | |
| #define | REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 8) More... | |
| #define | REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) |
| (XDMAC) Channel Interrupt Mask Register (chid = 9) More... | |
| #define | REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 0) More... | |
| #define | REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 1) More... | |
| #define | REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) |
| (XDMAC) Channel Interrupt Status Register (chid = 10) More... | |
| #define | REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 11) More... | |
| #define | REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 12) More... | |
| #define | REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 13) More... | |
| #define | REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) |
| (XDMAC) Channel Interrupt Status Register (chid = 14) More... | |
| #define | REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 15) More... | |
| #define | REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 16) More... | |
| #define | REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 17) More... | |
| #define | REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) |
| (XDMAC) Channel Interrupt Status Register (chid = 18) More... | |
| #define | REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 19) More... | |
| #define | REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) |
| (XDMAC) Channel Interrupt Status Register (chid = 2) More... | |
| #define | REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 20) More... | |
| #define | REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 21) More... | |
| #define | REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) |
| (XDMAC) Channel Interrupt Status Register (chid = 22) More... | |
| #define | REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 23) More... | |
| #define | REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 3) More... | |
| #define | REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 4) More... | |
| #define | REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 5) More... | |
| #define | REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) |
| (XDMAC) Channel Interrupt Status Register (chid = 6) More... | |
| #define | REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 7) More... | |
| #define | REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 8) More... | |
| #define | REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) |
| (XDMAC) Channel Interrupt Status Register (chid = 9) More... | |
| #define | REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 0) More... | |
| #define | REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 1) More... | |
| #define | REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 10) More... | |
| #define | REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 11) More... | |
| #define | REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 12) More... | |
| #define | REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 13) More... | |
| #define | REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 14) More... | |
| #define | REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 15) More... | |
| #define | REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 16) More... | |
| #define | REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 17) More... | |
| #define | REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 18) More... | |
| #define | REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 19) More... | |
| #define | REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 2) More... | |
| #define | REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 20) More... | |
| #define | REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 21) More... | |
| #define | REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 22) More... | |
| #define | REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 23) More... | |
| #define | REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 3) More... | |
| #define | REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 4) More... | |
| #define | REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 5) More... | |
| #define | REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 6) More... | |
| #define | REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 7) More... | |
| #define | REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 8) More... | |
| #define | REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) |
| (XDMAC) Channel Next Descriptor Address Register (chid = 9) More... | |
| #define | REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 0) More... | |
| #define | REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 1) More... | |
| #define | REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 10) More... | |
| #define | REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 11) More... | |
| #define | REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 12) More... | |
| #define | REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 13) More... | |
| #define | REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 14) More... | |
| #define | REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 15) More... | |
| #define | REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 16) More... | |
| #define | REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 17) More... | |
| #define | REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 18) More... | |
| #define | REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 19) More... | |
| #define | REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 2) More... | |
| #define | REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 20) More... | |
| #define | REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 21) More... | |
| #define | REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 22) More... | |
| #define | REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 23) More... | |
| #define | REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 3) More... | |
| #define | REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 4) More... | |
| #define | REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 5) More... | |
| #define | REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 6) More... | |
| #define | REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 7) More... | |
| #define | REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 8) More... | |
| #define | REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) |
| (XDMAC) Channel Next Descriptor Control Register (chid = 9) More... | |
| #define | REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) |
| (XDMAC) Channel Source Address Register (chid = 0) More... | |
| #define | REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) |
| (XDMAC) Channel Source Address Register (chid = 1) More... | |
| #define | REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) |
| (XDMAC) Channel Source Address Register (chid = 10) More... | |
| #define | REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) |
| (XDMAC) Channel Source Address Register (chid = 11) More... | |
| #define | REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) |
| (XDMAC) Channel Source Address Register (chid = 12) More... | |
| #define | REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) |
| (XDMAC) Channel Source Address Register (chid = 13) More... | |
| #define | REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) |
| (XDMAC) Channel Source Address Register (chid = 14) More... | |
| #define | REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) |
| (XDMAC) Channel Source Address Register (chid = 15) More... | |
| #define | REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) |
| (XDMAC) Channel Source Address Register (chid = 16) More... | |
| #define | REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) |
| (XDMAC) Channel Source Address Register (chid = 17) More... | |
| #define | REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) |
| (XDMAC) Channel Source Address Register (chid = 18) More... | |
| #define | REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) |
| (XDMAC) Channel Source Address Register (chid = 19) More... | |
| #define | REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) |
| (XDMAC) Channel Source Address Register (chid = 2) More... | |
| #define | REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) |
| (XDMAC) Channel Source Address Register (chid = 20) More... | |
| #define | REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) |
| (XDMAC) Channel Source Address Register (chid = 21) More... | |
| #define | REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) |
| (XDMAC) Channel Source Address Register (chid = 22) More... | |
| #define | REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) |
| (XDMAC) Channel Source Address Register (chid = 23) More... | |
| #define | REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) |
| (XDMAC) Channel Source Address Register (chid = 3) More... | |
| #define | REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) |
| (XDMAC) Channel Source Address Register (chid = 4) More... | |
| #define | REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) |
| (XDMAC) Channel Source Address Register (chid = 5) More... | |
| #define | REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) |
| (XDMAC) Channel Source Address Register (chid = 6) More... | |
| #define | REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) |
| (XDMAC) Channel Source Address Register (chid = 7) More... | |
| #define | REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) |
| (XDMAC) Channel Source Address Register (chid = 8) More... | |
| #define | REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) |
| (XDMAC) Channel Source Address Register (chid = 9) More... | |
| #define | REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) |
| (XDMAC) Channel Source Microblock Stride (chid = 0) More... | |
| #define | REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) |
| (XDMAC) Channel Source Microblock Stride (chid = 1) More... | |
| #define | REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) |
| (XDMAC) Channel Source Microblock Stride (chid = 10) More... | |
| #define | REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) |
| (XDMAC) Channel Source Microblock Stride (chid = 11) More... | |
| #define | REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) |
| (XDMAC) Channel Source Microblock Stride (chid = 12) More... | |
| #define | REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) |
| (XDMAC) Channel Source Microblock Stride (chid = 13) More... | |
| #define | REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) |
| (XDMAC) Channel Source Microblock Stride (chid = 14) More... | |
| #define | REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) |
| (XDMAC) Channel Source Microblock Stride (chid = 15) More... | |
| #define | REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) |
| (XDMAC) Channel Source Microblock Stride (chid = 16) More... | |
| #define | REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) |
| (XDMAC) Channel Source Microblock Stride (chid = 17) More... | |
| #define | REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) |
| (XDMAC) Channel Source Microblock Stride (chid = 18) More... | |
| #define | REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) |
| (XDMAC) Channel Source Microblock Stride (chid = 19) More... | |
| #define | REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) |
| (XDMAC) Channel Source Microblock Stride (chid = 2) More... | |
| #define | REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) |
| (XDMAC) Channel Source Microblock Stride (chid = 20) More... | |
| #define | REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) |
| (XDMAC) Channel Source Microblock Stride (chid = 21) More... | |
| #define | REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) |
| (XDMAC) Channel Source Microblock Stride (chid = 22) More... | |
| #define | REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) |
| (XDMAC) Channel Source Microblock Stride (chid = 23) More... | |
| #define | REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) |
| (XDMAC) Channel Source Microblock Stride (chid = 3) More... | |
| #define | REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) |
| (XDMAC) Channel Source Microblock Stride (chid = 4) More... | |
| #define | REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) |
| (XDMAC) Channel Source Microblock Stride (chid = 5) More... | |
| #define | REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) |
| (XDMAC) Channel Source Microblock Stride (chid = 6) More... | |
| #define | REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) |
| (XDMAC) Channel Source Microblock Stride (chid = 7) More... | |
| #define | REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) |
| (XDMAC) Channel Source Microblock Stride (chid = 8) More... | |
| #define | REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) |
| (XDMAC) Channel Source Microblock Stride (chid = 9) More... | |
| #define | REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) |
| (XDMAC) Channel Microblock Control Register (chid = 0) More... | |
| #define | REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) |
| (XDMAC) Channel Microblock Control Register (chid = 1) More... | |
| #define | REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) |
| (XDMAC) Channel Microblock Control Register (chid = 10) More... | |
| #define | REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) |
| (XDMAC) Channel Microblock Control Register (chid = 11) More... | |
| #define | REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) |
| (XDMAC) Channel Microblock Control Register (chid = 12) More... | |
| #define | REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) |
| (XDMAC) Channel Microblock Control Register (chid = 13) More... | |
| #define | REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) |
| (XDMAC) Channel Microblock Control Register (chid = 14) More... | |
| #define | REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) |
| (XDMAC) Channel Microblock Control Register (chid = 15) More... | |
| #define | REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) |
| (XDMAC) Channel Microblock Control Register (chid = 16) More... | |
| #define | REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) |
| (XDMAC) Channel Microblock Control Register (chid = 17) More... | |
| #define | REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) |
| (XDMAC) Channel Microblock Control Register (chid = 18) More... | |
| #define | REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) |
| (XDMAC) Channel Microblock Control Register (chid = 19) More... | |
| #define | REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) |
| (XDMAC) Channel Microblock Control Register (chid = 2) More... | |
| #define | REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) |
| (XDMAC) Channel Microblock Control Register (chid = 20) More... | |
| #define | REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) |
| (XDMAC) Channel Microblock Control Register (chid = 21) More... | |
| #define | REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) |
| (XDMAC) Channel Microblock Control Register (chid = 22) More... | |
| #define | REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) |
| (XDMAC) Channel Microblock Control Register (chid = 23) More... | |
| #define | REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) |
| (XDMAC) Channel Microblock Control Register (chid = 3) More... | |
| #define | REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) |
| (XDMAC) Channel Microblock Control Register (chid = 4) More... | |
| #define | REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) |
| (XDMAC) Channel Microblock Control Register (chid = 5) More... | |
| #define | REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) |
| (XDMAC) Channel Microblock Control Register (chid = 6) More... | |
| #define | REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) |
| (XDMAC) Channel Microblock Control Register (chid = 7) More... | |
| #define | REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) |
| (XDMAC) Channel Microblock Control Register (chid = 8) More... | |
| #define | REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) |
| (XDMAC) Channel Microblock Control Register (chid = 9) More... | |
| #define | REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) |
| (XDMAC) Global Configuration Register More... | |
| #define | REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) |
| (XDMAC) Global Channel Disable Register More... | |
| #define | REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) |
| (XDMAC) Global Channel Enable Register More... | |
| #define | REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) |
| (XDMAC) Global Interrupt Disable Register More... | |
| #define | REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) |
| (XDMAC) Global Interrupt Enable Register More... | |
| #define | REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) |
| (XDMAC) Global Interrupt Mask Register More... | |
| #define | REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) |
| (XDMAC) Global Interrupt Status Register More... | |
| #define | REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) |
| (XDMAC) Global Channel Read Suspend Register More... | |
| #define | REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) |
| (XDMAC) Global Channel Read Write Resume Register More... | |
| #define | REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) |
| (XDMAC) Global Channel Read Write Suspend Register More... | |
| #define | REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) |
| (XDMAC) Global Channel Status Register More... | |
| #define | REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) |
| (XDMAC) Global Channel Software Flush Request Register More... | |
| #define | REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) |
| (XDMAC) Global Channel Software Request Register More... | |
| #define | REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) |
| (XDMAC) Global Channel Software Request Status Register More... | |
| #define | REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) |
| (XDMAC) Global Type Register More... | |
| #define | REG_XDMAC_GWAC (*(__I uint32_t*)0x40078008U) |
| (XDMAC) Global Weighted Arbiter Configuration Register More... | |
| #define | REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) |
| (XDMAC) Global Channel Write Suspend Register More... | |
| #define | REG_XDMAC_VERSION (*(__IO uint32_t*)0x40078FFCU) |
| (XDMAC) XDMAC Version Register More... | |
Detailed Description
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file utils/cmsis/same70/include/instance/xdmac.h.
Macro Definition Documentation
◆ REG_XDMAC_CBC0
| #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) |
(XDMAC) Channel Block Control Register (chid = 0)
Definition at line 421 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC1
| #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) |
(XDMAC) Channel Block Control Register (chid = 1)
Definition at line 435 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC10
| #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) |
(XDMAC) Channel Block Control Register (chid = 10)
Definition at line 561 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC11
| #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) |
(XDMAC) Channel Block Control Register (chid = 11)
Definition at line 575 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC12
| #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) |
(XDMAC) Channel Block Control Register (chid = 12)
Definition at line 589 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC13
| #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) |
(XDMAC) Channel Block Control Register (chid = 13)
Definition at line 603 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC14
| #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) |
(XDMAC) Channel Block Control Register (chid = 14)
Definition at line 617 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC15
| #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) |
(XDMAC) Channel Block Control Register (chid = 15)
Definition at line 631 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC16
| #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) |
(XDMAC) Channel Block Control Register (chid = 16)
Definition at line 645 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC17
| #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) |
(XDMAC) Channel Block Control Register (chid = 17)
Definition at line 659 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC18
| #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) |
(XDMAC) Channel Block Control Register (chid = 18)
Definition at line 673 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC19
| #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) |
(XDMAC) Channel Block Control Register (chid = 19)
Definition at line 687 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC2
| #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) |
(XDMAC) Channel Block Control Register (chid = 2)
Definition at line 449 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC20
| #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) |
(XDMAC) Channel Block Control Register (chid = 20)
Definition at line 701 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC21
| #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) |
(XDMAC) Channel Block Control Register (chid = 21)
Definition at line 715 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC22
| #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) |
(XDMAC) Channel Block Control Register (chid = 22)
Definition at line 729 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC23
| #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) |
(XDMAC) Channel Block Control Register (chid = 23)
Definition at line 743 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC3
| #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) |
(XDMAC) Channel Block Control Register (chid = 3)
Definition at line 463 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC4
| #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) |
(XDMAC) Channel Block Control Register (chid = 4)
Definition at line 477 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC5
| #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) |
(XDMAC) Channel Block Control Register (chid = 5)
Definition at line 491 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC6
| #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) |
(XDMAC) Channel Block Control Register (chid = 6)
Definition at line 505 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC7
| #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) |
(XDMAC) Channel Block Control Register (chid = 7)
Definition at line 519 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC8
| #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) |
(XDMAC) Channel Block Control Register (chid = 8)
Definition at line 533 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CBC9
| #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) |
(XDMAC) Channel Block Control Register (chid = 9)
Definition at line 547 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC0
| #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) |
(XDMAC) Channel Configuration Register (chid = 0)
Definition at line 422 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC1
| #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) |
(XDMAC) Channel Configuration Register (chid = 1)
Definition at line 436 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC10
| #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) |
(XDMAC) Channel Configuration Register (chid = 10)
Definition at line 562 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC11
| #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) |
(XDMAC) Channel Configuration Register (chid = 11)
Definition at line 576 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC12
| #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) |
(XDMAC) Channel Configuration Register (chid = 12)
Definition at line 590 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC13
| #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) |
(XDMAC) Channel Configuration Register (chid = 13)
Definition at line 604 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC14
| #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) |
(XDMAC) Channel Configuration Register (chid = 14)
Definition at line 618 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC15
| #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) |
(XDMAC) Channel Configuration Register (chid = 15)
Definition at line 632 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC16
| #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) |
(XDMAC) Channel Configuration Register (chid = 16)
Definition at line 646 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC17
| #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) |
(XDMAC) Channel Configuration Register (chid = 17)
Definition at line 660 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC18
| #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) |
(XDMAC) Channel Configuration Register (chid = 18)
Definition at line 674 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC19
| #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) |
(XDMAC) Channel Configuration Register (chid = 19)
Definition at line 688 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC2
| #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) |
(XDMAC) Channel Configuration Register (chid = 2)
Definition at line 450 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC20
| #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) |
(XDMAC) Channel Configuration Register (chid = 20)
Definition at line 702 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC21
| #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) |
(XDMAC) Channel Configuration Register (chid = 21)
Definition at line 716 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC22
| #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) |
(XDMAC) Channel Configuration Register (chid = 22)
Definition at line 730 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC23
| #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) |
(XDMAC) Channel Configuration Register (chid = 23)
Definition at line 744 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC3
| #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) |
(XDMAC) Channel Configuration Register (chid = 3)
Definition at line 464 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC4
| #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) |
(XDMAC) Channel Configuration Register (chid = 4)
Definition at line 478 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC5
| #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) |
(XDMAC) Channel Configuration Register (chid = 5)
Definition at line 492 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC6
| #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) |
(XDMAC) Channel Configuration Register (chid = 6)
Definition at line 506 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC7
| #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) |
(XDMAC) Channel Configuration Register (chid = 7)
Definition at line 520 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC8
| #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) |
(XDMAC) Channel Configuration Register (chid = 8)
Definition at line 534 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CC9
| #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) |
(XDMAC) Channel Configuration Register (chid = 9)
Definition at line 548 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA0
| #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) |
(XDMAC) Channel Destination Address Register (chid = 0)
Definition at line 417 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA1
| #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) |
(XDMAC) Channel Destination Address Register (chid = 1)
Definition at line 431 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA10
| #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) |
(XDMAC) Channel Destination Address Register (chid = 10)
Definition at line 557 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA11
| #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) |
(XDMAC) Channel Destination Address Register (chid = 11)
Definition at line 571 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA12
| #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) |
(XDMAC) Channel Destination Address Register (chid = 12)
Definition at line 585 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA13
| #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) |
(XDMAC) Channel Destination Address Register (chid = 13)
Definition at line 599 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA14
| #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) |
(XDMAC) Channel Destination Address Register (chid = 14)
Definition at line 613 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA15
| #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) |
(XDMAC) Channel Destination Address Register (chid = 15)
Definition at line 627 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA16
| #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) |
(XDMAC) Channel Destination Address Register (chid = 16)
Definition at line 641 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA17
| #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) |
(XDMAC) Channel Destination Address Register (chid = 17)
Definition at line 655 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA18
| #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) |
(XDMAC) Channel Destination Address Register (chid = 18)
Definition at line 669 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA19
| #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) |
(XDMAC) Channel Destination Address Register (chid = 19)
Definition at line 683 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA2
| #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) |
(XDMAC) Channel Destination Address Register (chid = 2)
Definition at line 445 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA20
| #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) |
(XDMAC) Channel Destination Address Register (chid = 20)
Definition at line 697 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA21
| #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) |
(XDMAC) Channel Destination Address Register (chid = 21)
Definition at line 711 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA22
| #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) |
(XDMAC) Channel Destination Address Register (chid = 22)
Definition at line 725 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA23
| #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) |
(XDMAC) Channel Destination Address Register (chid = 23)
Definition at line 739 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA3
| #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) |
(XDMAC) Channel Destination Address Register (chid = 3)
Definition at line 459 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA4
| #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) |
(XDMAC) Channel Destination Address Register (chid = 4)
Definition at line 473 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA5
| #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) |
(XDMAC) Channel Destination Address Register (chid = 5)
Definition at line 487 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA6
| #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) |
(XDMAC) Channel Destination Address Register (chid = 6)
Definition at line 501 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA7
| #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) |
(XDMAC) Channel Destination Address Register (chid = 7)
Definition at line 515 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA8
| #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) |
(XDMAC) Channel Destination Address Register (chid = 8)
Definition at line 529 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDA9
| #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) |
(XDMAC) Channel Destination Address Register (chid = 9)
Definition at line 543 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP0
| #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 0)
Definition at line 423 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP1
| #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 1)
Definition at line 437 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP10
| #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 10)
Definition at line 563 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP11
| #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 11)
Definition at line 577 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP12
| #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 12)
Definition at line 591 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP13
| #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 13)
Definition at line 605 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP14
| #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 14)
Definition at line 619 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP15
| #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 15)
Definition at line 633 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP16
| #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 16)
Definition at line 647 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP17
| #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 17)
Definition at line 661 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP18
| #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 18)
Definition at line 675 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP19
| #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 19)
Definition at line 689 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP2
| #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 2)
Definition at line 451 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP20
| #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 20)
Definition at line 703 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP21
| #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 21)
Definition at line 717 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP22
| #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 22)
Definition at line 731 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP23
| #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 23)
Definition at line 745 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP3
| #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 3)
Definition at line 465 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP4
| #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 4)
Definition at line 479 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP5
| #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 5)
Definition at line 493 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP6
| #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 6)
Definition at line 507 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP7
| #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 7)
Definition at line 521 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP8
| #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 8)
Definition at line 535 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDS_MSP9
| #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) |
(XDMAC) Channel Data Stride Memory Set Pattern (chid = 9)
Definition at line 549 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS0
| #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) |
(XDMAC) Channel Destination Microblock Stride (chid = 0)
Definition at line 425 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS1
| #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) |
(XDMAC) Channel Destination Microblock Stride (chid = 1)
Definition at line 439 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS10
| #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) |
(XDMAC) Channel Destination Microblock Stride (chid = 10)
Definition at line 565 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS11
| #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) |
(XDMAC) Channel Destination Microblock Stride (chid = 11)
Definition at line 579 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS12
| #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) |
(XDMAC) Channel Destination Microblock Stride (chid = 12)
Definition at line 593 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS13
| #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) |
(XDMAC) Channel Destination Microblock Stride (chid = 13)
Definition at line 607 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS14
| #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) |
(XDMAC) Channel Destination Microblock Stride (chid = 14)
Definition at line 621 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS15
| #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) |
(XDMAC) Channel Destination Microblock Stride (chid = 15)
Definition at line 635 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS16
| #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) |
(XDMAC) Channel Destination Microblock Stride (chid = 16)
Definition at line 649 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS17
| #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) |
(XDMAC) Channel Destination Microblock Stride (chid = 17)
Definition at line 663 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS18
| #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) |
(XDMAC) Channel Destination Microblock Stride (chid = 18)
Definition at line 677 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS19
| #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) |
(XDMAC) Channel Destination Microblock Stride (chid = 19)
Definition at line 691 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS2
| #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) |
(XDMAC) Channel Destination Microblock Stride (chid = 2)
Definition at line 453 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS20
| #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) |
(XDMAC) Channel Destination Microblock Stride (chid = 20)
Definition at line 705 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS21
| #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) |
(XDMAC) Channel Destination Microblock Stride (chid = 21)
Definition at line 719 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS22
| #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) |
(XDMAC) Channel Destination Microblock Stride (chid = 22)
Definition at line 733 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS23
| #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) |
(XDMAC) Channel Destination Microblock Stride (chid = 23)
Definition at line 747 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS3
| #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) |
(XDMAC) Channel Destination Microblock Stride (chid = 3)
Definition at line 467 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS4
| #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) |
(XDMAC) Channel Destination Microblock Stride (chid = 4)
Definition at line 481 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS5
| #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) |
(XDMAC) Channel Destination Microblock Stride (chid = 5)
Definition at line 495 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS6
| #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) |
(XDMAC) Channel Destination Microblock Stride (chid = 6)
Definition at line 509 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS7
| #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) |
(XDMAC) Channel Destination Microblock Stride (chid = 7)
Definition at line 523 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS8
| #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) |
(XDMAC) Channel Destination Microblock Stride (chid = 8)
Definition at line 537 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CDUS9
| #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) |
(XDMAC) Channel Destination Microblock Stride (chid = 9)
Definition at line 551 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID0
| #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) |
(XDMAC) Channel Interrupt Disable Register (chid = 0)
Definition at line 413 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID1
| #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) |
(XDMAC) Channel Interrupt Disable Register (chid = 1)
Definition at line 427 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID10
| #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) |
(XDMAC) Channel Interrupt Disable Register (chid = 10)
Definition at line 553 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID11
| #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) |
(XDMAC) Channel Interrupt Disable Register (chid = 11)
Definition at line 567 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID12
| #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) |
(XDMAC) Channel Interrupt Disable Register (chid = 12)
Definition at line 581 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID13
| #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) |
(XDMAC) Channel Interrupt Disable Register (chid = 13)
Definition at line 595 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID14
| #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) |
(XDMAC) Channel Interrupt Disable Register (chid = 14)
Definition at line 609 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID15
| #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) |
(XDMAC) Channel Interrupt Disable Register (chid = 15)
Definition at line 623 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID16
| #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) |
(XDMAC) Channel Interrupt Disable Register (chid = 16)
Definition at line 637 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID17
| #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) |
(XDMAC) Channel Interrupt Disable Register (chid = 17)
Definition at line 651 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID18
| #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) |
(XDMAC) Channel Interrupt Disable Register (chid = 18)
Definition at line 665 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID19
| #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) |
(XDMAC) Channel Interrupt Disable Register (chid = 19)
Definition at line 679 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID2
| #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) |
(XDMAC) Channel Interrupt Disable Register (chid = 2)
Definition at line 441 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID20
| #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) |
(XDMAC) Channel Interrupt Disable Register (chid = 20)
Definition at line 693 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID21
| #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) |
(XDMAC) Channel Interrupt Disable Register (chid = 21)
Definition at line 707 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID22
| #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) |
(XDMAC) Channel Interrupt Disable Register (chid = 22)
Definition at line 721 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID23
| #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) |
(XDMAC) Channel Interrupt Disable Register (chid = 23)
Definition at line 735 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID3
| #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) |
(XDMAC) Channel Interrupt Disable Register (chid = 3)
Definition at line 455 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID4
| #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) |
(XDMAC) Channel Interrupt Disable Register (chid = 4)
Definition at line 469 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID5
| #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) |
(XDMAC) Channel Interrupt Disable Register (chid = 5)
Definition at line 483 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID6
| #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) |
(XDMAC) Channel Interrupt Disable Register (chid = 6)
Definition at line 497 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID7
| #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) |
(XDMAC) Channel Interrupt Disable Register (chid = 7)
Definition at line 511 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID8
| #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) |
(XDMAC) Channel Interrupt Disable Register (chid = 8)
Definition at line 525 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CID9
| #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) |
(XDMAC) Channel Interrupt Disable Register (chid = 9)
Definition at line 539 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE0
| #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) |
(XDMAC) Channel Interrupt Enable Register (chid = 0)
Definition at line 412 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE1
| #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) |
(XDMAC) Channel Interrupt Enable Register (chid = 1)
Definition at line 426 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE10
| #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) |
(XDMAC) Channel Interrupt Enable Register (chid = 10)
Definition at line 552 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE11
| #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) |
(XDMAC) Channel Interrupt Enable Register (chid = 11)
Definition at line 566 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE12
| #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) |
(XDMAC) Channel Interrupt Enable Register (chid = 12)
Definition at line 580 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE13
| #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) |
(XDMAC) Channel Interrupt Enable Register (chid = 13)
Definition at line 594 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE14
| #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) |
(XDMAC) Channel Interrupt Enable Register (chid = 14)
Definition at line 608 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE15
| #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) |
(XDMAC) Channel Interrupt Enable Register (chid = 15)
Definition at line 622 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE16
| #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) |
(XDMAC) Channel Interrupt Enable Register (chid = 16)
Definition at line 636 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE17
| #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) |
(XDMAC) Channel Interrupt Enable Register (chid = 17)
Definition at line 650 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE18
| #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) |
(XDMAC) Channel Interrupt Enable Register (chid = 18)
Definition at line 664 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE19
| #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) |
(XDMAC) Channel Interrupt Enable Register (chid = 19)
Definition at line 678 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE2
| #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) |
(XDMAC) Channel Interrupt Enable Register (chid = 2)
Definition at line 440 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE20
| #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) |
(XDMAC) Channel Interrupt Enable Register (chid = 20)
Definition at line 692 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE21
| #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) |
(XDMAC) Channel Interrupt Enable Register (chid = 21)
Definition at line 706 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE22
| #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) |
(XDMAC) Channel Interrupt Enable Register (chid = 22)
Definition at line 720 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE23
| #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) |
(XDMAC) Channel Interrupt Enable Register (chid = 23)
Definition at line 734 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE3
| #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) |
(XDMAC) Channel Interrupt Enable Register (chid = 3)
Definition at line 454 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE4
| #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) |
(XDMAC) Channel Interrupt Enable Register (chid = 4)
Definition at line 468 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE5
| #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) |
(XDMAC) Channel Interrupt Enable Register (chid = 5)
Definition at line 482 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE6
| #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) |
(XDMAC) Channel Interrupt Enable Register (chid = 6)
Definition at line 496 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE7
| #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) |
(XDMAC) Channel Interrupt Enable Register (chid = 7)
Definition at line 510 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE8
| #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) |
(XDMAC) Channel Interrupt Enable Register (chid = 8)
Definition at line 524 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIE9
| #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) |
(XDMAC) Channel Interrupt Enable Register (chid = 9)
Definition at line 538 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM0
| #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) |
(XDMAC) Channel Interrupt Mask Register (chid = 0)
Definition at line 414 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM1
| #define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) |
(XDMAC) Channel Interrupt Mask Register (chid = 1)
Definition at line 428 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM10
| #define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) |
(XDMAC) Channel Interrupt Mask Register (chid = 10)
Definition at line 554 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM11
| #define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) |
(XDMAC) Channel Interrupt Mask Register (chid = 11)
Definition at line 568 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM12
| #define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) |
(XDMAC) Channel Interrupt Mask Register (chid = 12)
Definition at line 582 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM13
| #define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) |
(XDMAC) Channel Interrupt Mask Register (chid = 13)
Definition at line 596 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM14
| #define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) |
(XDMAC) Channel Interrupt Mask Register (chid = 14)
Definition at line 610 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM15
| #define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) |
(XDMAC) Channel Interrupt Mask Register (chid = 15)
Definition at line 624 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM16
| #define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) |
(XDMAC) Channel Interrupt Mask Register (chid = 16)
Definition at line 638 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM17
| #define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) |
(XDMAC) Channel Interrupt Mask Register (chid = 17)
Definition at line 652 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM18
| #define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) |
(XDMAC) Channel Interrupt Mask Register (chid = 18)
Definition at line 666 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM19
| #define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) |
(XDMAC) Channel Interrupt Mask Register (chid = 19)
Definition at line 680 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM2
| #define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) |
(XDMAC) Channel Interrupt Mask Register (chid = 2)
Definition at line 442 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM20
| #define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) |
(XDMAC) Channel Interrupt Mask Register (chid = 20)
Definition at line 694 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM21
| #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) |
(XDMAC) Channel Interrupt Mask Register (chid = 21)
Definition at line 708 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM22
| #define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) |
(XDMAC) Channel Interrupt Mask Register (chid = 22)
Definition at line 722 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM23
| #define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) |
(XDMAC) Channel Interrupt Mask Register (chid = 23)
Definition at line 736 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM3
| #define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) |
(XDMAC) Channel Interrupt Mask Register (chid = 3)
Definition at line 456 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM4
| #define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) |
(XDMAC) Channel Interrupt Mask Register (chid = 4)
Definition at line 470 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM5
| #define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) |
(XDMAC) Channel Interrupt Mask Register (chid = 5)
Definition at line 484 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM6
| #define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) |
(XDMAC) Channel Interrupt Mask Register (chid = 6)
Definition at line 498 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM7
| #define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) |
(XDMAC) Channel Interrupt Mask Register (chid = 7)
Definition at line 512 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM8
| #define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) |
(XDMAC) Channel Interrupt Mask Register (chid = 8)
Definition at line 526 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIM9
| #define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) |
(XDMAC) Channel Interrupt Mask Register (chid = 9)
Definition at line 540 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS0
| #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) |
(XDMAC) Channel Interrupt Status Register (chid = 0)
Definition at line 415 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS1
| #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) |
(XDMAC) Channel Interrupt Status Register (chid = 1)
Definition at line 429 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS10
| #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) |
(XDMAC) Channel Interrupt Status Register (chid = 10)
Definition at line 555 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS11
| #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) |
(XDMAC) Channel Interrupt Status Register (chid = 11)
Definition at line 569 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS12
| #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) |
(XDMAC) Channel Interrupt Status Register (chid = 12)
Definition at line 583 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS13
| #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) |
(XDMAC) Channel Interrupt Status Register (chid = 13)
Definition at line 597 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS14
| #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) |
(XDMAC) Channel Interrupt Status Register (chid = 14)
Definition at line 611 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS15
| #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) |
(XDMAC) Channel Interrupt Status Register (chid = 15)
Definition at line 625 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS16
| #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) |
(XDMAC) Channel Interrupt Status Register (chid = 16)
Definition at line 639 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS17
| #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) |
(XDMAC) Channel Interrupt Status Register (chid = 17)
Definition at line 653 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS18
| #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) |
(XDMAC) Channel Interrupt Status Register (chid = 18)
Definition at line 667 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS19
| #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) |
(XDMAC) Channel Interrupt Status Register (chid = 19)
Definition at line 681 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS2
| #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) |
(XDMAC) Channel Interrupt Status Register (chid = 2)
Definition at line 443 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS20
| #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) |
(XDMAC) Channel Interrupt Status Register (chid = 20)
Definition at line 695 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS21
| #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) |
(XDMAC) Channel Interrupt Status Register (chid = 21)
Definition at line 709 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS22
| #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) |
(XDMAC) Channel Interrupt Status Register (chid = 22)
Definition at line 723 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS23
| #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) |
(XDMAC) Channel Interrupt Status Register (chid = 23)
Definition at line 737 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS3
| #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) |
(XDMAC) Channel Interrupt Status Register (chid = 3)
Definition at line 457 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS4
| #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) |
(XDMAC) Channel Interrupt Status Register (chid = 4)
Definition at line 471 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS5
| #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) |
(XDMAC) Channel Interrupt Status Register (chid = 5)
Definition at line 485 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS6
| #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) |
(XDMAC) Channel Interrupt Status Register (chid = 6)
Definition at line 499 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS7
| #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) |
(XDMAC) Channel Interrupt Status Register (chid = 7)
Definition at line 513 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS8
| #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) |
(XDMAC) Channel Interrupt Status Register (chid = 8)
Definition at line 527 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CIS9
| #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) |
(XDMAC) Channel Interrupt Status Register (chid = 9)
Definition at line 541 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA0
| #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 0)
Definition at line 418 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA1
| #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 1)
Definition at line 432 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA10
| #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 10)
Definition at line 558 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA11
| #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 11)
Definition at line 572 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA12
| #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 12)
Definition at line 586 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA13
| #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 13)
Definition at line 600 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA14
| #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 14)
Definition at line 614 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA15
| #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 15)
Definition at line 628 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA16
| #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 16)
Definition at line 642 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA17
| #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 17)
Definition at line 656 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA18
| #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 18)
Definition at line 670 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA19
| #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 19)
Definition at line 684 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA2
| #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 2)
Definition at line 446 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA20
| #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 20)
Definition at line 698 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA21
| #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 21)
Definition at line 712 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA22
| #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 22)
Definition at line 726 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA23
| #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 23)
Definition at line 740 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA3
| #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 3)
Definition at line 460 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA4
| #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 4)
Definition at line 474 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA5
| #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 5)
Definition at line 488 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA6
| #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 6)
Definition at line 502 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA7
| #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 7)
Definition at line 516 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA8
| #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 8)
Definition at line 530 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDA9
| #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) |
(XDMAC) Channel Next Descriptor Address Register (chid = 9)
Definition at line 544 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC0
| #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 0)
Definition at line 419 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC1
| #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 1)
Definition at line 433 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC10
| #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 10)
Definition at line 559 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC11
| #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 11)
Definition at line 573 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC12
| #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 12)
Definition at line 587 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC13
| #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 13)
Definition at line 601 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC14
| #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 14)
Definition at line 615 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC15
| #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 15)
Definition at line 629 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC16
| #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 16)
Definition at line 643 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC17
| #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 17)
Definition at line 657 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC18
| #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 18)
Definition at line 671 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC19
| #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 19)
Definition at line 685 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC2
| #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 2)
Definition at line 447 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC20
| #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 20)
Definition at line 699 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC21
| #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 21)
Definition at line 713 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC22
| #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 22)
Definition at line 727 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC23
| #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 23)
Definition at line 741 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC3
| #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 3)
Definition at line 461 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC4
| #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 4)
Definition at line 475 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC5
| #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 5)
Definition at line 489 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC6
| #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 6)
Definition at line 503 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC7
| #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 7)
Definition at line 517 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC8
| #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 8)
Definition at line 531 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CNDC9
| #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) |
(XDMAC) Channel Next Descriptor Control Register (chid = 9)
Definition at line 545 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA0
| #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) |
(XDMAC) Channel Source Address Register (chid = 0)
Definition at line 416 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA1
| #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) |
(XDMAC) Channel Source Address Register (chid = 1)
Definition at line 430 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA10
| #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) |
(XDMAC) Channel Source Address Register (chid = 10)
Definition at line 556 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA11
| #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) |
(XDMAC) Channel Source Address Register (chid = 11)
Definition at line 570 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA12
| #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) |
(XDMAC) Channel Source Address Register (chid = 12)
Definition at line 584 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA13
| #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) |
(XDMAC) Channel Source Address Register (chid = 13)
Definition at line 598 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA14
| #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) |
(XDMAC) Channel Source Address Register (chid = 14)
Definition at line 612 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA15
| #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) |
(XDMAC) Channel Source Address Register (chid = 15)
Definition at line 626 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA16
| #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) |
(XDMAC) Channel Source Address Register (chid = 16)
Definition at line 640 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA17
| #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) |
(XDMAC) Channel Source Address Register (chid = 17)
Definition at line 654 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA18
| #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) |
(XDMAC) Channel Source Address Register (chid = 18)
Definition at line 668 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA19
| #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) |
(XDMAC) Channel Source Address Register (chid = 19)
Definition at line 682 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA2
| #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) |
(XDMAC) Channel Source Address Register (chid = 2)
Definition at line 444 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA20
| #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) |
(XDMAC) Channel Source Address Register (chid = 20)
Definition at line 696 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA21
| #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) |
(XDMAC) Channel Source Address Register (chid = 21)
Definition at line 710 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA22
| #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) |
(XDMAC) Channel Source Address Register (chid = 22)
Definition at line 724 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA23
| #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) |
(XDMAC) Channel Source Address Register (chid = 23)
Definition at line 738 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA3
| #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) |
(XDMAC) Channel Source Address Register (chid = 3)
Definition at line 458 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA4
| #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) |
(XDMAC) Channel Source Address Register (chid = 4)
Definition at line 472 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA5
| #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) |
(XDMAC) Channel Source Address Register (chid = 5)
Definition at line 486 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA6
| #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) |
(XDMAC) Channel Source Address Register (chid = 6)
Definition at line 500 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA7
| #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) |
(XDMAC) Channel Source Address Register (chid = 7)
Definition at line 514 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA8
| #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) |
(XDMAC) Channel Source Address Register (chid = 8)
Definition at line 528 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSA9
| #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) |
(XDMAC) Channel Source Address Register (chid = 9)
Definition at line 542 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS0
| #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) |
(XDMAC) Channel Source Microblock Stride (chid = 0)
Definition at line 424 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS1
| #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) |
(XDMAC) Channel Source Microblock Stride (chid = 1)
Definition at line 438 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS10
| #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) |
(XDMAC) Channel Source Microblock Stride (chid = 10)
Definition at line 564 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS11
| #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) |
(XDMAC) Channel Source Microblock Stride (chid = 11)
Definition at line 578 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS12
| #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) |
(XDMAC) Channel Source Microblock Stride (chid = 12)
Definition at line 592 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS13
| #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) |
(XDMAC) Channel Source Microblock Stride (chid = 13)
Definition at line 606 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS14
| #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) |
(XDMAC) Channel Source Microblock Stride (chid = 14)
Definition at line 620 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS15
| #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) |
(XDMAC) Channel Source Microblock Stride (chid = 15)
Definition at line 634 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS16
| #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) |
(XDMAC) Channel Source Microblock Stride (chid = 16)
Definition at line 648 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS17
| #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) |
(XDMAC) Channel Source Microblock Stride (chid = 17)
Definition at line 662 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS18
| #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) |
(XDMAC) Channel Source Microblock Stride (chid = 18)
Definition at line 676 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS19
| #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) |
(XDMAC) Channel Source Microblock Stride (chid = 19)
Definition at line 690 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS2
| #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) |
(XDMAC) Channel Source Microblock Stride (chid = 2)
Definition at line 452 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS20
| #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) |
(XDMAC) Channel Source Microblock Stride (chid = 20)
Definition at line 704 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS21
| #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) |
(XDMAC) Channel Source Microblock Stride (chid = 21)
Definition at line 718 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS22
| #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) |
(XDMAC) Channel Source Microblock Stride (chid = 22)
Definition at line 732 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS23
| #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) |
(XDMAC) Channel Source Microblock Stride (chid = 23)
Definition at line 746 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS3
| #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) |
(XDMAC) Channel Source Microblock Stride (chid = 3)
Definition at line 466 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS4
| #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) |
(XDMAC) Channel Source Microblock Stride (chid = 4)
Definition at line 480 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS5
| #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) |
(XDMAC) Channel Source Microblock Stride (chid = 5)
Definition at line 494 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS6
| #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) |
(XDMAC) Channel Source Microblock Stride (chid = 6)
Definition at line 508 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS7
| #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) |
(XDMAC) Channel Source Microblock Stride (chid = 7)
Definition at line 522 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS8
| #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) |
(XDMAC) Channel Source Microblock Stride (chid = 8)
Definition at line 536 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CSUS9
| #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) |
(XDMAC) Channel Source Microblock Stride (chid = 9)
Definition at line 550 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC0
| #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) |
(XDMAC) Channel Microblock Control Register (chid = 0)
Definition at line 420 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC1
| #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) |
(XDMAC) Channel Microblock Control Register (chid = 1)
Definition at line 434 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC10
| #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) |
(XDMAC) Channel Microblock Control Register (chid = 10)
Definition at line 560 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC11
| #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) |
(XDMAC) Channel Microblock Control Register (chid = 11)
Definition at line 574 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC12
| #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) |
(XDMAC) Channel Microblock Control Register (chid = 12)
Definition at line 588 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC13
| #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) |
(XDMAC) Channel Microblock Control Register (chid = 13)
Definition at line 602 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC14
| #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) |
(XDMAC) Channel Microblock Control Register (chid = 14)
Definition at line 616 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC15
| #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) |
(XDMAC) Channel Microblock Control Register (chid = 15)
Definition at line 630 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC16
| #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) |
(XDMAC) Channel Microblock Control Register (chid = 16)
Definition at line 644 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC17
| #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) |
(XDMAC) Channel Microblock Control Register (chid = 17)
Definition at line 658 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC18
| #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) |
(XDMAC) Channel Microblock Control Register (chid = 18)
Definition at line 672 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC19
| #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) |
(XDMAC) Channel Microblock Control Register (chid = 19)
Definition at line 686 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC2
| #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) |
(XDMAC) Channel Microblock Control Register (chid = 2)
Definition at line 448 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC20
| #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) |
(XDMAC) Channel Microblock Control Register (chid = 20)
Definition at line 700 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC21
| #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) |
(XDMAC) Channel Microblock Control Register (chid = 21)
Definition at line 714 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC22
| #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) |
(XDMAC) Channel Microblock Control Register (chid = 22)
Definition at line 728 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC23
| #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) |
(XDMAC) Channel Microblock Control Register (chid = 23)
Definition at line 742 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC3
| #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) |
(XDMAC) Channel Microblock Control Register (chid = 3)
Definition at line 462 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC4
| #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) |
(XDMAC) Channel Microblock Control Register (chid = 4)
Definition at line 476 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC5
| #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) |
(XDMAC) Channel Microblock Control Register (chid = 5)
Definition at line 490 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC6
| #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) |
(XDMAC) Channel Microblock Control Register (chid = 6)
Definition at line 504 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC7
| #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) |
(XDMAC) Channel Microblock Control Register (chid = 7)
Definition at line 518 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC8
| #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) |
(XDMAC) Channel Microblock Control Register (chid = 8)
Definition at line 532 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_CUBC9
| #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) |
(XDMAC) Channel Microblock Control Register (chid = 9)
Definition at line 546 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GCFG
| #define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) |
(XDMAC) Global Configuration Register
Definition at line 396 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GD
| #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) |
(XDMAC) Global Channel Disable Register
Definition at line 403 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GE
| #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) |
(XDMAC) Global Channel Enable Register
Definition at line 402 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GID
| #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) |
(XDMAC) Global Interrupt Disable Register
Definition at line 399 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GIE
| #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) |
(XDMAC) Global Interrupt Enable Register
Definition at line 398 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GIM
| #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) |
(XDMAC) Global Interrupt Mask Register
Definition at line 400 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GIS
| #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) |
(XDMAC) Global Interrupt Status Register
Definition at line 401 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GRS
| #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) |
(XDMAC) Global Channel Read Suspend Register
Definition at line 405 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GRWR
| #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) |
(XDMAC) Global Channel Read Write Resume Register
Definition at line 408 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GRWS
| #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) |
(XDMAC) Global Channel Read Write Suspend Register
Definition at line 407 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GS
| #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) |
(XDMAC) Global Channel Status Register
Definition at line 404 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GSWF
| #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) |
(XDMAC) Global Channel Software Flush Request Register
Definition at line 411 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GSWR
| #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) |
(XDMAC) Global Channel Software Request Register
Definition at line 409 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GSWS
| #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) |
(XDMAC) Global Channel Software Request Status Register
Definition at line 410 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GTYPE
| #define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) |
(XDMAC) Global Type Register
Definition at line 395 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GWAC
| #define REG_XDMAC_GWAC (*(__I uint32_t*)0x40078008U) |
(XDMAC) Global Weighted Arbiter Configuration Register
Definition at line 397 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_GWS
| #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) |
(XDMAC) Global Channel Write Suspend Register
Definition at line 406 of file utils/cmsis/same70/include/instance/xdmac.h.
◆ REG_XDMAC_VERSION
| #define REG_XDMAC_VERSION (*(__IO uint32_t*)0x40078FFCU) |
(XDMAC) XDMAC Version Register
Definition at line 748 of file utils/cmsis/same70/include/instance/xdmac.h.