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Macros | |
| #define | REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) | 
| (TWIHS0) Control Register  More... | |
| #define | REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) | 
| (TWIHS0) Clock Waveform Generator Register  More... | |
| #define | REG_TWIHS0_DR (*(__I uint32_t*)0x400180D0U) | 
| (TWIHS0) Debug Register  More... | |
| #define | REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) | 
| (TWIHS0) Filter Register  More... | |
| #define | REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) | 
| (TWIHS0) Internal Address Register  More... | |
| #define | REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) | 
| (TWIHS0) Interrupt Disable Register  More... | |
| #define | REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) | 
| (TWIHS0) Interrupt Enable Register  More... | |
| #define | REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) | 
| (TWIHS0) Interrupt Mask Register  More... | |
| #define | REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) | 
| (TWIHS0) Master Mode Register  More... | |
| #define | REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) | 
| (TWIHS0) Receive Holding Register  More... | |
| #define | REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) | 
| (TWIHS0) SMBus Timing Register  More... | |
| #define | REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) | 
| (TWIHS0) Slave Mode Register  More... | |
| #define | REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) | 
| (TWIHS0) Status Register  More... | |
| #define | REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) | 
| (TWIHS0) SleepWalking Matching Register  More... | |
| #define | REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) | 
| (TWIHS0) Transmit Holding Register  More... | |
| #define | REG_TWIHS0_VER (*(__I uint32_t*)0x400180FCU) | 
| (TWIHS0) Version Register  More... | |
| #define | REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) | 
| (TWIHS0) Write Protection Mode Register  More... | |
| #define | REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) | 
| (TWIHS0) Write Protection Status Register  More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file twihs0.h.
| #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) | 
| #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) | 
| #define REG_TWIHS0_DR (*(__I uint32_t*)0x400180D0U) | 
| #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) | 
| #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) | 
| #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) | 
| #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) | 
| #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) | 
| #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) | 
| #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) | 
| #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) | 
| #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) | 
| #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) | 
| #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) | 
| #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) | 
| #define REG_TWIHS0_VER (*(__I uint32_t*)0x400180FCU) | 
| #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) |