same70j21.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70J21_
36 #define _SAME70J21_
37 
46 
47 #ifdef __cplusplus
48  extern "C" {
49 #endif
50 
51 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
52 #include <stdint.h>
53 #endif
54 
55 /* ************************************************************************** */
56 /* CMSIS DEFINITIONS FOR SAME70J21 */
57 /* ************************************************************************** */
60 
62 typedef enum IRQn
63 {
64 /****** Cortex-M7 Processor Exceptions Numbers ******************************/
68  BusFault_IRQn = -11,
70  SVCall_IRQn = -5,
72  PendSV_IRQn = -2,
73  SysTick_IRQn = -1,
74 /****** SAME70J21 specific Interrupt Numbers *********************************/
75 
76  SUPC_IRQn = 0,
77  RSTC_IRQn = 1,
78  RTC_IRQn = 2,
79  RTT_IRQn = 3,
80  WDT_IRQn = 4,
81  PMC_IRQn = 5,
82  EFC_IRQn = 6,
83  UART0_IRQn = 7,
84  UART1_IRQn = 8,
85  PIOA_IRQn = 10,
86  PIOB_IRQn = 11,
87  USART0_IRQn = 13,
88  USART1_IRQn = 14,
89  PIOD_IRQn = 16,
90  TWIHS0_IRQn = 19,
91  TWIHS1_IRQn = 20,
92  SSC_IRQn = 22,
93  TC0_IRQn = 23,
94  TC1_IRQn = 24,
95  TC2_IRQn = 25,
96  AFEC0_IRQn = 29,
97  DACC_IRQn = 30,
98  PWM0_IRQn = 31,
99  ICM_IRQn = 32,
100  ACC_IRQn = 33,
101  USBHS_IRQn = 34,
104  GMAC_IRQn = 39,
105  AFEC1_IRQn = 40,
106  QSPI_IRQn = 43,
107  UART2_IRQn = 44,
108  TC9_IRQn = 50,
109  TC10_IRQn = 51,
110  TC11_IRQn = 52,
111  AES_IRQn = 56,
112  TRNG_IRQn = 57,
113  XDMAC_IRQn = 58,
114  ISI_IRQn = 59,
115  PWM1_IRQn = 60,
116  FPU_IRQn = 61,
117  RSWDT_IRQn = 63,
118  CCW_IRQn = 64,
119  CCF_IRQn = 65,
122  IXC_IRQn = 68,
125 } IRQn_Type;
126 
127 typedef struct _DeviceVectors
128 {
129  /* Stack pointer */
130  void* pvStack;
131 
132  /* Cortex-M handlers */
133  void* pfnReset_Handler;
134  void* pfnNMI_Handler;
135  void* pfnHardFault_Handler;
136  void* pfnMemManage_Handler;
137  void* pfnBusFault_Handler;
138  void* pfnUsageFault_Handler;
139  void* pfnReserved1_Handler;
140  void* pfnReserved2_Handler;
141  void* pfnReserved3_Handler;
142  void* pfnReserved4_Handler;
143  void* pfnSVC_Handler;
144  void* pfnDebugMon_Handler;
145  void* pfnReserved5_Handler;
146  void* pfnPendSV_Handler;
147  void* pfnSysTick_Handler;
148 
149  /* Peripheral handlers */
150  void* pfnSUPC_Handler; /* 0 Supply Controller */
151  void* pfnRSTC_Handler; /* 1 Reset Controller */
152  void* pfnRTC_Handler; /* 2 Real Time Clock */
153  void* pfnRTT_Handler; /* 3 Real Time Timer */
154  void* pfnWDT_Handler; /* 4 Watchdog Timer */
155  void* pfnPMC_Handler; /* 5 Power Management Controller */
156  void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
157  void* pfnUART0_Handler; /* 7 UART 0 */
158  void* pfnUART1_Handler; /* 8 UART 1 */
159  void* pvReserved9;
160  void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
161  void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
162  void* pvReserved12;
163  void* pfnUSART0_Handler; /* 13 USART 0 */
164  void* pfnUSART1_Handler; /* 14 USART 1 */
165  void* pvReserved15;
166  void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
167  void* pvReserved17;
168  void* pvReserved18;
169  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
170  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
171  void* pvReserved21;
172  void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
173  void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
174  void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
175  void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
176  void* pvReserved26;
177  void* pvReserved27;
178  void* pvReserved28;
179  void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
180  void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
181  void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
182  void* pfnICM_Handler; /* 32 Integrity Check Monitor */
183  void* pfnACC_Handler; /* 33 Analog Comparator */
184  void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
185  void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */
186  void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */
187  void* pvReserved37;
188  void* pvReserved38;
189  void* pfnGMAC_Handler; /* 39 Ethernet MAC */
190  void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
191  void* pvReserved41;
192  void* pvReserved42;
193  void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
194  void* pfnUART2_Handler; /* 44 UART 2 */
195  void* pvReserved45;
196  void* pvReserved46;
197  void* pvReserved47;
198  void* pvReserved48;
199  void* pvReserved49;
200  void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
201  void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
202  void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
203  void* pvReserved53;
204  void* pvReserved54;
205  void* pvReserved55;
206  void* pfnAES_Handler; /* 56 AES */
207  void* pfnTRNG_Handler; /* 57 True Random Generator */
208  void* pfnXDMAC_Handler; /* 58 DMA */
209  void* pfnISI_Handler; /* 59 Camera Interface */
210  void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
211  void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */
212  void* pvReserved62;
213  void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
214  void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */
215  void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */
216  void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */
217  void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */
218  void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */
219  void* pvReserved69;
220  void* pvReserved70;
221  void* pvReserved71;
222  void* pvReserved72;
223  void* pvReserved73;
224 } DeviceVectors;
225 
226 /* Cortex-M7 core handlers */
227 void Reset_Handler ( void );
228 void NMI_Handler ( void );
229 void HardFault_Handler ( void );
230 void MemManage_Handler ( void );
231 void BusFault_Handler ( void );
232 void UsageFault_Handler ( void );
233 void SVC_Handler ( void );
234 void DebugMon_Handler ( void );
235 void PendSV_Handler ( void );
236 void SysTick_Handler ( void );
237 
238 /* Peripherals handlers */
239 void ACC_Handler ( void );
240 void AES_Handler ( void );
241 void AFEC0_Handler ( void );
242 void AFEC1_Handler ( void );
243 void CCF_Handler ( void );
244 void CCW_Handler ( void );
245 void EFC_Handler ( void );
246 void FPU_Handler ( void );
247 void GMAC_Handler ( void );
248 void ICM_Handler ( void );
249 void ISI_Handler ( void );
250 void IXC_Handler ( void );
251 void MCAN0_INT0_Handler ( void );
252 void MCAN0_INT1_Handler ( void );
253 void PIOA_Handler ( void );
254 void PIOB_Handler ( void );
255 void PIOD_Handler ( void );
256 void PMC_Handler ( void );
257 void PWM0_Handler ( void );
258 void PWM1_Handler ( void );
259 void GMAC_Q1_Handler ( void );
260 void GMAC_Q2_Handler ( void );
261 void QSPI_Handler ( void );
262 void RSTC_Handler ( void );
263 void RSWDT_Handler ( void );
264 void RTC_Handler ( void );
265 void RTT_Handler ( void );
266 void SSC_Handler ( void );
267 void SUPC_Handler ( void );
268 void TC0_Handler ( void );
269 void TC1_Handler ( void );
270 void TC2_Handler ( void );
271 void TC9_Handler ( void );
272 void TC10_Handler ( void );
273 void TC11_Handler ( void );
274 void TRNG_Handler ( void );
275 void TWIHS0_Handler ( void );
276 void TWIHS1_Handler ( void );
277 void UART0_Handler ( void );
278 void UART1_Handler ( void );
279 void UART2_Handler ( void );
280 void USART0_Handler ( void );
281 void USART1_Handler ( void );
282 void USBHS_Handler ( void );
283 void WDT_Handler ( void );
284 void XDMAC_Handler ( void );
285 
290 #define __CM7_REV 0x0000
291 #define __MPU_PRESENT 1
292 #define __NVIC_PRIO_BITS 3
293 #define __FPU_PRESENT 1
294 #define __FPU_DP 1
295 #define __ICACHE_PRESENT 1
296 #define __DCACHE_PRESENT 1
297 #define __DTCM_PRESENT 1
298 #define __ITCM_PRESENT 1
299 #define __Vendor_SysTickConfig 0
300 #define __SAM_M7_REVB 0
302 /*
303  * \brief CMSIS includes
304  */
305 
306 #include <core_cm7.h>
307 #if !defined DONT_USE_CMSIS_INIT
308 #include "system_same70.h"
309 #endif /* DONT_USE_CMSIS_INIT */
310 
313 /* ************************************************************************** */
315 /* ************************************************************************** */
318 
319 #include "component/acc.h"
320 #include "component/aes.h"
321 #include "component/afec.h"
322 #include "component/chipid.h"
323 #include "component/efc.h"
324 #include "component/gmac.h"
325 #include "component/gpbr.h"
326 #include "component/dacc.h"
327 #include "component/icm.h"
328 #include "component/isi.h"
329 #include "component/matrix.h"
330 #include "component/mcan.h"
331 #include "component/pio.h"
332 #include "component/pmc.h"
333 #include "component/pwm.h"
334 #include "component/qspi.h"
335 #include "component/rstc.h"
336 #include "component/rswdt.h"
337 #include "component/rtc.h"
338 #include "component/rtt.h"
339 #include "component/ssc.h"
340 #include "component/supc.h"
341 #include "component/tc.h"
342 #include "component/trng.h"
343 #include "component/twihs.h"
344 #include "component/uart.h"
345 #include "component/usart.h"
346 #include "component/usbhs.h"
347 #include "component/utmi.h"
348 #include "component/wdt.h"
349 #include "component/xdmac.h"
352 /* ************************************************************************** */
353 /* REGISTER ACCESS DEFINITIONS FOR SAME70J21 */
354 /* ************************************************************************** */
357 
358 #include "instance/ssc.h"
359 #include "instance/tc0.h"
360 #include "instance/twihs0.h"
361 #include "instance/twihs1.h"
362 #include "instance/pwm0.h"
363 #include "instance/usart0.h"
364 #include "instance/usart1.h"
365 #include "instance/mcan0.h"
366 #include "instance/usbhs.h"
367 #include "instance/afec0.h"
368 #include "instance/dacc.h"
369 #include "instance/acc.h"
370 #include "instance/icm.h"
371 #include "instance/isi.h"
372 #include "instance/gmac.h"
373 #include "instance/tc3.h"
374 #include "instance/pwm1.h"
375 #include "instance/afec1.h"
376 #include "instance/aes.h"
377 #include "instance/trng.h"
378 #include "instance/xdmac.h"
379 #include "instance/qspi.h"
380 #include "instance/matrix.h"
381 #include "instance/utmi.h"
382 #include "instance/pmc.h"
383 #include "instance/uart0.h"
384 #include "instance/chipid.h"
385 #include "instance/uart1.h"
386 #include "instance/efc.h"
387 #include "instance/pioa.h"
388 #include "instance/piob.h"
389 #include "instance/piod.h"
390 #include "instance/rstc.h"
391 #include "instance/supc.h"
392 #include "instance/rtt.h"
393 #include "instance/wdt.h"
394 #include "instance/rtc.h"
395 #include "instance/gpbr.h"
396 #include "instance/rswdt.h"
397 #include "instance/uart2.h"
400 /* ************************************************************************** */
401 /* PERIPHERAL ID DEFINITIONS FOR SAME70J21 */
402 /* ************************************************************************** */
405 
406 #define ID_SUPC ( 0)
407 #define ID_RSTC ( 1)
408 #define ID_RTC ( 2)
409 #define ID_RTT ( 3)
410 #define ID_WDT ( 4)
411 #define ID_PMC ( 5)
412 #define ID_EFC ( 6)
413 #define ID_UART0 ( 7)
414 #define ID_UART1 ( 8)
415 #define ID_PIOA (10)
416 #define ID_PIOB (11)
417 #define ID_USART0 (13)
418 #define ID_USART1 (14)
419 #define ID_PIOD (16)
420 #define ID_TWIHS0 (19)
421 #define ID_TWIHS1 (20)
422 #define ID_SSC (22)
423 #define ID_TC0 (23)
424 #define ID_TC1 (24)
425 #define ID_TC2 (25)
426 #define ID_AFEC0 (29)
427 #define ID_DACC (30)
428 #define ID_PWM0 (31)
429 #define ID_ICM (32)
430 #define ID_ACC (33)
431 #define ID_USBHS (34)
432 #define ID_MCAN0 (35)
433 #define ID_MCAN1 (37)
434 #define ID_GMAC (39)
435 #define ID_AFEC1 (40)
436 #define ID_QSPI (43)
437 #define ID_UART2 (44)
438 #define ID_TC9 (50)
439 #define ID_TC10 (51)
440 #define ID_TC11 (52)
441 #define ID_AES (56)
442 #define ID_TRNG (57)
443 #define ID_XDMAC (58)
444 #define ID_ISI (59)
445 #define ID_PWM1 (60)
446 #define ID_RSWDT (63)
447 #define ID_IXC (68)
449 #define ID_PERIPH_COUNT (74)
451 
452 /* ************************************************************************** */
453 /* BASE ADDRESS DEFINITIONS FOR SAME70J21 */
454 /* ************************************************************************** */
457 
458 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
459 #define SSC (0x40004000U)
460 #define TC0 (0x4000C000U)
461 #define TWIHS0 (0x40018000U)
462 #define TWIHS1 (0x4001C000U)
463 #define PWM0 (0x40020000U)
464 #define USART0 (0x40024000U)
465 #define USART1 (0x40028000U)
466 #define MCAN0 (0x40030000U)
467 #define MCAN1 (0x40034000U)
468 #define USBHS (0x40038000U)
469 #define AFEC0 (0x4003C000U)
470 #define DACC (0x40040000U)
471 #define ACC (0x40044000U)
472 #define ICM (0x40048000U)
473 #define ISI (0x4004C000U)
474 #define GMAC (0x40050000U)
475 #define TC3 (0x40054000U)
476 #define PWM1 (0x4005C000U)
477 #define AFEC1 (0x40064000U)
478 #define AES (0x4006C000U)
479 #define TRNG (0x40070000U)
480 #define XDMAC (0x40078000U)
481 #define QSPI (0x4007C000U)
482 #define MATRIX (0x40088000U)
483 #define UTMI (0x400E0400U)
484 #define PMC (0x400E0600U)
485 #define UART0 (0x400E0800U)
486 #define CHIPID (0x400E0940U)
487 #define UART1 (0x400E0A00U)
488 #define EFC (0x400E0C00U)
489 #define PIOA (0x400E0E00U)
490 #define PIOB (0x400E1000U)
491 #define PIOD (0x400E1400U)
492 #define RSTC (0x400E1800U)
493 #define SUPC (0x400E1810U)
494 #define RTT (0x400E1830U)
495 #define WDT (0x400E1850U)
496 #define RTC (0x400E1860U)
497 #define GPBR (0x400E1890U)
498 #define RSWDT (0x400E1900U)
499 #define UART2 (0x400E1A00U)
500 #else
501 #define SSC ((Ssc *)0x40004000U)
502 #define TC0 ((Tc *)0x4000C000U)
503 #define TWIHS0 ((Twihs *)0x40018000U)
504 #define TWIHS1 ((Twihs *)0x4001C000U)
505 #define PWM0 ((Pwm *)0x40020000U)
506 #define USART0 ((Usart *)0x40024000U)
507 #define USART1 ((Usart *)0x40028000U)
508 #define MCAN0 ((Mcan *)0x40030000U)
509 #define MCAN1 ((Mcan *)0x40034000U)
510 #define USBHS ((Usbhs *)0x40038000U)
511 #define AFEC0 ((Afec *)0x4003C000U)
512 #define DACC ((Dacc *)0x40040000U)
513 #define ACC ((Acc *)0x40044000U)
514 #define ICM ((Icm *)0x40048000U)
515 #define ISI ((Isi *)0x4004C000U)
516 #define GMAC ((Gmac *)0x40050000U)
517 #define TC3 ((Tc *)0x40054000U)
518 #define PWM1 ((Pwm *)0x4005C000U)
519 #define AFEC1 ((Afec *)0x40064000U)
520 #define AES ((Aes *)0x4006C000U)
521 #define TRNG ((Trng *)0x40070000U)
522 #define XDMAC ((Xdmac *)0x40078000U)
523 #define QSPI ((Qspi *)0x4007C000U)
524 #define MATRIX ((Matrix *)0x40088000U)
525 #define UTMI ((Utmi *)0x400E0400U)
526 #define PMC ((Pmc *)0x400E0600U)
527 #define UART0 ((Uart *)0x400E0800U)
528 #define CHIPID ((Chipid *)0x400E0940U)
529 #define UART1 ((Uart *)0x400E0A00U)
530 #define EFC ((Efc *)0x400E0C00U)
531 #define PIOA ((Pio *)0x400E0E00U)
532 #define PIOB ((Pio *)0x400E1000U)
533 #define PIOD ((Pio *)0x400E1400U)
534 #define RSTC ((Rstc *)0x400E1800U)
535 #define SUPC ((Supc *)0x400E1810U)
536 #define RTT ((Rtt *)0x400E1830U)
537 #define WDT ((Wdt *)0x400E1850U)
538 #define RTC ((Rtc *)0x400E1860U)
539 #define GPBR ((Gpbr *)0x400E1890U)
540 #define RSWDT ((Rswdt *)0x400E1900U)
541 #define UART2 ((Uart *)0x400E1A00U)
542 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
543 
545 /* ************************************************************************** */
546 /* PIO DEFINITIONS FOR SAME70J21 */
547 /* ************************************************************************** */
550 
551 #include "pio/same70j21.h"
554 /* ************************************************************************** */
555 /* MEMORY MAPPING DEFINITIONS FOR SAME70J21 */
556 /* ************************************************************************** */
557 
558 #define IFLASH_SIZE (0x200000u)
559 #define IFLASH_PAGE_SIZE (512u)
560 #define IFLASH_LOCK_REGION_SIZE (8192u)
561 #define IFLASH_NB_OF_PAGES (4096u)
562 #define IFLASH_NB_OF_LOCK_BITS (128u)
563 #define IRAM_SIZE (0x60000u)
564 
565 #define QSPIMEM_ADDR (0x80000000u)
566 #define AXIMX_ADDR (0xA0000000u)
567 #define ITCM_ADDR (0x00000000u)
568 #define IFLASH_ADDR (0x00400000u)
569 #define IROM_ADDR (0x00800000u)
570 #define DTCM_ADDR (0x20000000u)
571 #define IRAM_ADDR (0x20400000u)
572 #define EBI_CS0_ADDR (0x60000000u)
573 #define EBI_CS1_ADDR (0x61000000u)
574 #define EBI_CS2_ADDR (0x62000000u)
575 #define EBI_CS3_ADDR (0x63000000u)
576 #define SDRAM_CS_ADDR (0x70000000u)
578 /* ************************************************************************** */
579 /* MISCELLANEOUS DEFINITIONS FOR SAME70J21 */
580 /* ************************************************************************** */
581 
582 #define CHIP_JTAGID (0x05B3D03FUL)
583 #define CHIP_CIDR (0xA1020E00UL)
584 #define CHIP_EXID (0x00000000UL)
585 
586 /* ************************************************************************** */
587 /* ELECTRICAL DEFINITIONS FOR SAME70J21 */
588 /* ************************************************************************** */
589 
590 /* %ATMEL_ELECTRICAL% */
591 
592 /* Device characteristics */
593 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
594 #define CHIP_FREQ_SLCK_RC (32000UL)
595 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
596 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
597 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
598 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
599 #define CHIP_FREQ_CPU_MAX (300000000UL)
600 #define CHIP_FREQ_XTAL_32K (32768UL)
601 #define CHIP_FREQ_XTAL_12M (12000000UL)
602 
603 /* Embedded Flash Read Wait State (for Worst-Case Conditions) */
604 #define CHIP_FREQ_FWS_0 (23000000UL)
605 #define CHIP_FREQ_FWS_1 (46000000UL)
606 #define CHIP_FREQ_FWS_2 (69000000UL)
607 #define CHIP_FREQ_FWS_3 (92000000UL)
608 #define CHIP_FREQ_FWS_4 (115000000UL)
609 #define CHIP_FREQ_FWS_5 (138000000UL)
610 #define CHIP_FREQ_FWS_6 (150000000UL)
612 #ifdef __cplusplus
613 }
614 #endif
615 
618 #endif /* _SAME70J21_ */
struct _DeviceVectors DeviceVectors
void * pvReserved62
Definition: same70j19.h:212
void * pfnAFEC1_Handler
Definition: same70j19.h:190
void RTT_Handler(void)
Definition: d_time.c:22
void HardFault_Handler(void)
Definition: rtos.c:248
void TWIHS0_Handler(void)
void * pfnXDMAC_Handler
Definition: same70j19.h:208
void * pfnPWM1_Handler
Definition: same70j19.h:210
void * pfnBusFault_Handler
Definition: same70j19.h:137
void * pfnTWIHS1_Handler
Definition: same70j19.h:170
void * pvReserved55
Definition: same70j19.h:205
void * pfnPIOB_Handler
Definition: same70j19.h:161
void WDT_Handler(void)
void ISI_Handler(void)
void * pfnAFEC0_Handler
Definition: same70j19.h:179
void UART1_Handler(void)
Definition: d_usartDMA.c:1642
void * pvReserved45
Definition: same70j19.h:195
void * pvReserved72
Definition: same70j19.h:222
void * pfnTC11_Handler
Definition: same70j19.h:202
void * pvReserved73
Definition: same70j19.h:223
void * pfnUART2_Handler
Definition: same70j19.h:194
void * pfnSSC_Handler
Definition: same70j19.h:172
void TC10_Handler(void)
void * pfnISI_Handler
Definition: same70j19.h:209
void * pfnHardFault_Handler
Definition: same70j19.h:135
void EFC_Handler(void)
void * pfnSVC_Handler
Definition: same70j19.h:143
void * pvReserved71
Definition: same70j19.h:221
void TC9_Handler(void)
void MemManage_Handler(void)
Definition: rtos.c:196
void * pvStack
Definition: same70j19.h:130
void BusFault_Handler(void)
Definition: rtos.c:211
void PIOB_Handler(void)
void TRNG_Handler(void)
void * pfnRSWDT_Handler
Definition: same70j19.h:213
void AFEC1_Handler(void)
Interrupt handler for AFEC1.
Definition: afec.c:566
void * pfnUSBHS_Handler
Definition: same70j19.h:184
void PMC_Handler(void)
void * pfnCCF_Handler
Definition: same70j19.h:215
void MCAN0_INT1_Handler(void)
void * pvReserved48
Definition: same70j19.h:198
void * pfnUSART0_Handler
Definition: same70j19.h:163
void * pfnPWM0_Handler
Definition: same70j19.h:181
void * pfnGMAC_Handler
Definition: same70j19.h:189
void * pvReserved9
Definition: same70j19.h:159
void * pfnMemManage_Handler
Definition: same70j19.h:136
void Reset_Handler(void)
This is the code that gets called on processor reset. To initialize the device, and call the main() r...
void TWIHS1_Handler(void)
void * pfnDebugMon_Handler
Definition: same70j19.h:144
void * pvReserved26
Definition: same70j19.h:176
void * pfnPIOD_Handler
Definition: same70j19.h:166
void XDMAC_Handler(void)
Definition: d_usartDMA.c:704
void * pfnTC2_Handler
Definition: same70j19.h:175
void UART0_Handler(void)
Definition: d_usartDMA.c:1641
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
void SSC_Handler(void)
void * pfnReset_Handler
Definition: same70j19.h:133
enum IRQn IRQn_Type
void * pvReserved42
Definition: same70j19.h:192
void TC11_Handler(void)
void * pvReserved21
Definition: same70j19.h:171
void * pfnUART1_Handler
Definition: same70j19.h:158
void * pfnSysTick_Handler
Definition: same70j19.h:147
void SUPC_Handler(void)
void * pfnACC_Handler
Definition: same70j19.h:183
void * pfnWDT_Handler
Definition: same70j19.h:154
void * pfnICM_Handler
Definition: same70j19.h:182
void * pfnCCW_Handler
Definition: same70j19.h:214
void * pfnFPU_Handler
Definition: same70j19.h:211
void * pfnIXC_Handler
Definition: same70j19.h:218
void * pfnReserved2_Handler
Definition: same70j19.h:140
void * pfnReserved4_Handler
Definition: same70j19.h:142
void ICM_Handler(void)
void CCF_Handler(void)
void * pvReserved47
Definition: same70j19.h:197
void * pfnRTT_Handler
Definition: same70j19.h:153
void NMI_Handler(void)
void ACC_Handler(void)
void PIOA_Handler(void)
void CCW_Handler(void)
void * pfnUSART1_Handler
Definition: same70j19.h:164
void * pfnAES_Handler
Definition: same70j19.h:206
void SVC_Handler(void)
void USBHS_Handler(void)
Definition: USBD_HAL.c:1008
void * pvReserved27
Definition: same70j19.h:177
void * pfnPendSV_Handler
Definition: same70j19.h:146
void * pvReserved69
Definition: same70j19.h:219
void * pvReserved54
Definition: same70j19.h:204
void AFEC0_Handler(void)
Interrupt handler for AFEC0.
Definition: afec.c:558
void QSPI_Handler(void)
void * pvReserved53
Definition: same70j19.h:203
void * pfnTC0_Handler
Definition: same70j19.h:173
void * pvReserved18
Definition: same70j19.h:168
void UART2_Handler(void)
Definition: d_usartDMA.c:1643
void * pfnTWIHS0_Handler
Definition: same70j19.h:169
void * pfnGMAC_Q1_Handler
Definition: same70j19.h:216
void * pfnDACC_Handler
Definition: same70j19.h:180
void * pfnUART0_Handler
Definition: same70j19.h:157
void * pfnNMI_Handler
Definition: same70j19.h:134
void * pfnTC9_Handler
Definition: same70j19.h:200
void DebugMon_Handler(void)
void * pfnUsageFault_Handler
Definition: same70j19.h:138
void * pvReserved41
Definition: same70j19.h:191
void * pfnTC10_Handler
Definition: same70j19.h:201
void GMAC_Q1_Handler(void)
void PWM0_Handler(void)
void SysTick_Handler(void)
void PendSV_Handler(void)
void * pfnPIOA_Handler
Definition: same70j19.h:160
void TC0_Handler(void)
IRQn
Definition: same70j19.h:62
void * pfnEFC_Handler
Definition: same70j19.h:156
void * pfnTRNG_Handler
Definition: same70j19.h:207
void * pvReserved46
Definition: same70j19.h:196
void * pvReserved38
Definition: same70j19.h:188
void * pvReserved17
Definition: same70j19.h:167
void * pfnGMAC_Q2_Handler
Definition: same70j19.h:217
void * pfnMCAN0_INT0_Handler
Definition: same70j19.h:185
void * pfnMCAN0_INT1_Handler
Definition: same70j19.h:186
void * pfnRTC_Handler
Definition: same70j19.h:152
void TC1_Handler(void)
void MCAN0_INT0_Handler(void)
void IXC_Handler(void)
void * pfnReserved3_Handler
Definition: same70j19.h:141
void * pvReserved15
Definition: same70j19.h:165
void RSTC_Handler(void)
void * pfnReserved5_Handler
Definition: same70j19.h:145
void FPU_Handler(void)
void * pvReserved49
Definition: same70j19.h:199
void * pfnTC1_Handler
Definition: same70j19.h:174
void USART1_Handler(void)
Definition: d_usartDMA.c:1647
void GMAC_Handler(void)
void * pvReserved70
Definition: same70j19.h:220
void TC2_Handler(void)
void * pvReserved12
Definition: same70j19.h:162
void RSWDT_Handler(void)
void * pfnPMC_Handler
Definition: same70j19.h:155
void USART0_Handler(void)
Definition: d_usartDMA.c:1646
void * pfnQSPI_Handler
Definition: same70j19.h:193
void * pfnRSTC_Handler
Definition: same70j19.h:151
void * pfnSUPC_Handler
Definition: same70j19.h:150
void GMAC_Q2_Handler(void)
void * pfnReserved1_Handler
Definition: same70j19.h:139
void UsageFault_Handler(void)
Definition: rtos.c:226
void AES_Handler(void)
void PIOD_Handler(void)
void RTC_Handler(void)
void * pvReserved37
Definition: same70j19.h:187
void * pvReserved28
Definition: same70j19.h:178
void PWM1_Handler(void)


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Author(s):
autogenerated on Sun Feb 28 2021 03:17:58