Classes | Macros | Typedefs | Enumerations | Functions
same70q19b.h File Reference
#include <stdint.h>
#include <core_cm7.h>
#include "system_same70.h"
#include "component/acc.h"
#include "component/aes.h"
#include "component/afec.h"
#include "component/chipid.h"
#include "component/dacc.h"
#include "component/efc.h"
#include "component/gmac.h"
#include "component/gpbr.h"
#include "component/hsmci.h"
#include "component/i2sc.h"
#include "component/icm.h"
#include "component/isi.h"
#include "component/matrix.h"
#include "component/mcan.h"
#include "component/pio.h"
#include "component/pmc.h"
#include "component/pwm.h"
#include "component/qspi.h"
#include "component/rstc.h"
#include "component/rswdt.h"
#include "component/rtc.h"
#include "component/rtt.h"
#include "component/sdramc.h"
#include "component/smc.h"
#include "component/spi.h"
#include "component/ssc.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/trng.h"
#include "component/twihs.h"
#include "component/uart.h"
#include "component/usart.h"
#include "component/usbhs.h"
#include "component/utmi.h"
#include "component/wdt.h"
#include "component/xdmac.h"
#include "instance/hsmci.h"
#include "instance/ssc.h"
#include "instance/spi0.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/twihs0.h"
#include "instance/twihs1.h"
#include "instance/pwm0.h"
#include "instance/usart0.h"
#include "instance/usart1.h"
#include "instance/usart2.h"
#include "instance/mcan0.h"
#include "instance/mcan1.h"
#include "instance/usbhs.h"
#include "instance/afec0.h"
#include "instance/dacc.h"
#include "instance/acc.h"
#include "instance/icm.h"
#include "instance/isi.h"
#include "instance/gmac.h"
#include "instance/tc3.h"
#include "instance/spi1.h"
#include "instance/pwm1.h"
#include "instance/twihs2.h"
#include "instance/afec1.h"
#include "instance/aes.h"
#include "instance/trng.h"
#include "instance/xdmac.h"
#include "instance/qspi.h"
#include "instance/smc.h"
#include "instance/sdramc.h"
#include "instance/matrix.h"
#include "instance/i2sc0.h"
#include "instance/i2sc1.h"
#include "instance/utmi.h"
#include "instance/pmc.h"
#include "instance/uart0.h"
#include "instance/chipid.h"
#include "instance/uart1.h"
#include "instance/efc.h"
#include "instance/pioa.h"
#include "instance/piob.h"
#include "instance/pioc.h"
#include "instance/piod.h"
#include "instance/pioe.h"
#include "instance/rstc.h"
#include "instance/supc.h"
#include "instance/rtt.h"
#include "instance/wdt.h"
#include "instance/rtc.h"
#include "instance/gpbr.h"
#include "instance/rswdt.h"
#include "instance/uart2.h"
#include "instance/uart3.h"
#include "instance/uart4.h"
#include "pio/same70q19b.h"

Go to the source code of this file.

Classes

struct  _DeviceVectors
 

Macros

#define __CM7_REV   0x0000
 Configuration of the Cortex-M7 Processor and Core Peripherals. More...
 
#define __DCACHE_PRESENT   1
 
#define __DTCM_PRESENT   1
 
#define __FPU_DP   1
 
#define __FPU_PRESENT   1
 
#define __ICACHE_PRESENT   1
 
#define __ITCM_PRESENT   1
 
#define __MPU_PRESENT   1
 
#define __NVIC_PRIO_BITS   3
 
#define __SAM_M7_REVB   1
 
#define __Vendor_SysTickConfig   0
 
#define ACC   ((Acc *)0x40044000U)
 (ACC ) Base Address More...
 
#define AES   ((Aes *)0x4006C000U)
 (AES ) Base Address More...
 
#define AFEC0   ((Afec *)0x4003C000U)
 (AFEC0 ) Base Address More...
 
#define AFEC1   ((Afec *)0x40064000U)
 (AFEC1 ) Base Address More...
 
#define AXIMX_ADDR   (0xA0000000u)
 
#define CHIP_CIDR   (0xA10D0A01UL)
 
#define CHIP_EXID   (0x00000002UL)
 
#define CHIP_FREQ_CPU_MAX   (300000000UL)
 
#define CHIP_FREQ_FWS_0   (23000000UL)
 Maximum operating frequency when FWS is 0. More...
 
#define CHIP_FREQ_FWS_1   (46000000UL)
 Maximum operating frequency when FWS is 1. More...
 
#define CHIP_FREQ_FWS_2   (69000000UL)
 Maximum operating frequency when FWS is 2. More...
 
#define CHIP_FREQ_FWS_3   (92000000UL)
 Maximum operating frequency when FWS is 3. More...
 
#define CHIP_FREQ_FWS_4   (115000000UL)
 Maximum operating frequency when FWS is 4. More...
 
#define CHIP_FREQ_FWS_5   (138000000UL)
 Maximum operating frequency when FWS is 5. More...
 
#define CHIP_FREQ_FWS_6   (150000000UL)
 Maximum operating frequency when FWS is 6. More...
 
#define CHIP_FREQ_MAINCK_RC_12MHZ   (12000000UL)
 
#define CHIP_FREQ_MAINCK_RC_4MHZ   (4000000UL)
 
#define CHIP_FREQ_MAINCK_RC_8MHZ   (8000000UL)
 
#define CHIP_FREQ_SLCK_RC   (32000UL)
 
#define CHIP_FREQ_SLCK_RC_MAX   (44000UL)
 
#define CHIP_FREQ_SLCK_RC_MIN   (20000UL)
 
#define CHIP_FREQ_XTAL_12M   (12000000UL)
 
#define CHIP_FREQ_XTAL_32K   (32768UL)
 
#define CHIP_JTAGID   (0x05B3D03FUL)
 
#define CHIPID   ((Chipid *)0x400E0940U)
 (CHIPID) Base Address More...
 
#define DACC   ((Dacc *)0x40040000U)
 (DACC ) Base Address More...
 
#define DTCM_ADDR   (0x20000000u)
 
#define EBI_CS0_ADDR   (0x60000000u)
 
#define EBI_CS1_ADDR   (0x61000000u)
 
#define EBI_CS2_ADDR   (0x62000000u)
 
#define EBI_CS3_ADDR   (0x63000000u)
 
#define EFC   ((Efc *)0x400E0C00U)
 (EFC ) Base Address More...
 
#define GMAC   ((Gmac *)0x40050000U)
 (GMAC ) Base Address More...
 
#define GPBR   ((Gpbr *)0x400E1890U)
 (GPBR ) Base Address More...
 
#define HSMCI   ((Hsmci *)0x40000000U)
 (HSMCI ) Base Address More...
 
#define I2SC0   ((I2sc *)0x4008C000U)
 (I2SC0 ) Base Address More...
 
#define I2SC1   ((I2sc *)0x40090000U)
 (I2SC1 ) Base Address More...
 
#define ICM   ((Icm *)0x40048000U)
 (ICM ) Base Address More...
 
#define ID_ACC   (33)
 Analog Comparator (ACC) More...
 
#define ID_AES   (56)
 AES (AES) More...
 
#define ID_AFEC0   (29)
 Analog Front End 0 (AFEC0) More...
 
#define ID_AFEC1   (40)
 Analog Front End 1 (AFEC1) More...
 
#define ID_DACC   (30)
 Digital To Analog Converter (DACC) More...
 
#define ID_EFC   ( 6)
 Enhanced Embedded Flash Controller (EFC) More...
 
#define ID_GMAC   (39)
 Ethernet MAC (GMAC) More...
 
#define ID_HSMCI   (18)
 Multimedia Card Interface (HSMCI) More...
 
#define ID_I2SC0   (69)
 Inter-IC Sound controller (I2SC0) More...
 
#define ID_I2SC1   (70)
 Inter-IC Sound controller (I2SC1) More...
 
#define ID_ICM   (32)
 Integrity Check Monitor (ICM) More...
 
#define ID_ISI   (59)
 Camera Interface (ISI) More...
 
#define ID_IXC   (68)
 Floating Point Unit - IXC (ARM) More...
 
#define ID_MCAN0   (35)
 MCAN Controller 0 (MCAN0) More...
 
#define ID_MCAN1   (37)
 MCAN Controller 1 (MCAN1) More...
 
#define ID_PERIPH_COUNT   (74)
 Number of peripheral IDs. More...
 
#define ID_PIOA   (10)
 Parallel I/O Controller A (PIOA) More...
 
#define ID_PIOB   (11)
 Parallel I/O Controller B (PIOB) More...
 
#define ID_PIOC   (12)
 Parallel I/O Controller C (PIOC) More...
 
#define ID_PIOD   (16)
 Parallel I/O Controller D (PIOD) More...
 
#define ID_PIOE   (17)
 Parallel I/O Controller E (PIOE) More...
 
#define ID_PMC   ( 5)
 Power Management Controller (PMC) More...
 
#define ID_PWM0   (31)
 Pulse Width Modulation 0 (PWM0) More...
 
#define ID_PWM1   (60)
 Pulse Width Modulation 1 (PWM1) More...
 
#define ID_QSPI   (43)
 Quad I/O Serial Peripheral Interface (QSPI) More...
 
#define ID_RSTC   ( 1)
 Reset Controller (RSTC) More...
 
#define ID_RSWDT   (63)
 Reinforced Secure Watchdog Timer (RSWDT) More...
 
#define ID_RTC   ( 2)
 Real Time Clock (RTC) More...
 
#define ID_RTT   ( 3)
 Real Time Timer (RTT) More...
 
#define ID_SDRAMC   (62)
 SDRAM Controller (SDRAMC) More...
 
#define ID_SMC   ( 9)
 Static Memory Controller (SMC) More...
 
#define ID_SPI0   (21)
 Serial Peripheral Interface 0 (SPI0) More...
 
#define ID_SPI1   (42)
 Serial Peripheral Interface 1 (SPI1) More...
 
#define ID_SSC   (22)
 Synchronous Serial Controller (SSC) More...
 
#define ID_SUPC   ( 0)
 Supply Controller (SUPC) More...
 
#define ID_TC0   (23)
 Timer/Counter 0 (TC0) More...
 
#define ID_TC1   (24)
 Timer/Counter 1 (TC1) More...
 
#define ID_TC10   (51)
 Timer/Counter 10 (TC10) More...
 
#define ID_TC11   (52)
 Timer/Counter 11 (TC11) More...
 
#define ID_TC2   (25)
 Timer/Counter 2 (TC2) More...
 
#define ID_TC3   (26)
 Timer/Counter 3 (TC3) More...
 
#define ID_TC4   (27)
 Timer/Counter 4 (TC4) More...
 
#define ID_TC5   (28)
 Timer/Counter 5 (TC5) More...
 
#define ID_TC6   (47)
 Timer/Counter 6 (TC6) More...
 
#define ID_TC7   (48)
 Timer/Counter 7 (TC7) More...
 
#define ID_TC8   (49)
 Timer/Counter 8 (TC8) More...
 
#define ID_TC9   (50)
 Timer/Counter 9 (TC9) More...
 
#define ID_TRNG   (57)
 True Random Generator (TRNG) More...
 
#define ID_TWIHS0   (19)
 Two Wire Interface 0 HS (TWIHS0) More...
 
#define ID_TWIHS1   (20)
 Two Wire Interface 1 HS (TWIHS1) More...
 
#define ID_TWIHS2   (41)
 Two Wire Interface 2 HS (TWIHS2) More...
 
#define ID_UART0   ( 7)
 UART 0 (UART0) More...
 
#define ID_UART1   ( 8)
 UART 1 (UART1) More...
 
#define ID_UART2   (44)
 UART 2 (UART2) More...
 
#define ID_UART3   (45)
 UART 3 (UART3) More...
 
#define ID_UART4   (46)
 UART 4 (UART4) More...
 
#define ID_USART0   (13)
 USART 0 (USART0) More...
 
#define ID_USART1   (14)
 USART 1 (USART1) More...
 
#define ID_USART2   (15)
 USART 2 (USART2) More...
 
#define ID_USBHS   (34)
 USB Host / Device Controller (USBHS) More...
 
#define ID_WDT   ( 4)
 Watchdog Timer (WDT) More...
 
#define ID_XDMAC   (58)
 DMA (XDMAC) More...
 
#define IFLASH_ADDR   (0x00400000u)
 
#define IFLASH_LOCK_REGION_SIZE   (8192u)
 
#define IFLASH_NB_OF_LOCK_BITS   (32u)
 
#define IFLASH_NB_OF_PAGES   (1024u)
 
#define IFLASH_PAGE_SIZE   (512u)
 
#define IFLASH_SIZE   (0x80000u)
 
#define IRAM_ADDR   (0x20400000u)
 
#define IRAM_SIZE   (0x40000u)
 
#define IROM_ADDR   (0x00800000u)
 
#define ISI   ((Isi *)0x4004C000U)
 (ISI ) Base Address More...
 
#define ITCM_ADDR   (0x00000000u)
 
#define MATRIX   ((Matrix *)0x40088000U)
 (MATRIX) Base Address More...
 
#define MCAN0   ((Mcan *)0x40030000U)
 (MCAN0 ) Base Address More...
 
#define MCAN1   ((Mcan *)0x40034000U)
 (MCAN1 ) Base Address More...
 
#define PIOA   ((Pio *)0x400E0E00U)
 (PIOA ) Base Address More...
 
#define PIOB   ((Pio *)0x400E1000U)
 (PIOB ) Base Address More...
 
#define PIOC   ((Pio *)0x400E1200U)
 (PIOC ) Base Address More...
 
#define PIOD   ((Pio *)0x400E1400U)
 (PIOD ) Base Address More...
 
#define PIOE   ((Pio *)0x400E1600U)
 (PIOE ) Base Address More...
 
#define PMC   ((Pmc *)0x400E0600U)
 (PMC ) Base Address More...
 
#define PWM0   ((Pwm *)0x40020000U)
 (PWM0 ) Base Address More...
 
#define PWM1   ((Pwm *)0x4005C000U)
 (PWM1 ) Base Address More...
 
#define QSPI   ((Qspi *)0x4007C000U)
 (QSPI ) Base Address More...
 
#define QSPIMEM_ADDR   (0x80000000u)
 
#define RSTC   ((Rstc *)0x400E1800U)
 (RSTC ) Base Address More...
 
#define RSWDT   ((Rswdt *)0x400E1900U)
 (RSWDT ) Base Address More...
 
#define RTC   ((Rtc *)0x400E1860U)
 (RTC ) Base Address More...
 
#define RTT   ((Rtt *)0x400E1830U)
 (RTT ) Base Address More...
 
#define SDRAM_CS_ADDR   (0x70000000u)
 
#define SDRAMC   ((Sdramc *)0x40084000U)
 (SDRAMC) Base Address More...
 
#define SMC   ((Smc *)0x40080000U)
 (SMC ) Base Address More...
 
#define SPI0   ((Spi *)0x40008000U)
 (SPI0 ) Base Address More...
 
#define SPI1   ((Spi *)0x40058000U)
 (SPI1 ) Base Address More...
 
#define SSC   ((Ssc *)0x40004000U)
 (SSC ) Base Address More...
 
#define SUPC   ((Supc *)0x400E1810U)
 (SUPC ) Base Address More...
 
#define TC0   ((Tc *)0x4000C000U)
 (TC0 ) Base Address More...
 
#define TC1   ((Tc *)0x40010000U)
 (TC1 ) Base Address More...
 
#define TC2   ((Tc *)0x40014000U)
 (TC2 ) Base Address More...
 
#define TC3   ((Tc *)0x40054000U)
 (TC3 ) Base Address More...
 
#define TRNG   ((Trng *)0x40070000U)
 (TRNG ) Base Address More...
 
#define TWIHS0   ((Twihs *)0x40018000U)
 (TWIHS0) Base Address More...
 
#define TWIHS1   ((Twihs *)0x4001C000U)
 (TWIHS1) Base Address More...
 
#define TWIHS2   ((Twihs *)0x40060000U)
 (TWIHS2) Base Address More...
 
#define UART0   ((Uart *)0x400E0800U)
 (UART0 ) Base Address More...
 
#define UART1   ((Uart *)0x400E0A00U)
 (UART1 ) Base Address More...
 
#define UART2   ((Uart *)0x400E1A00U)
 (UART2 ) Base Address More...
 
#define UART3   ((Uart *)0x400E1C00U)
 (UART3 ) Base Address More...
 
#define UART4   ((Uart *)0x400E1E00U)
 (UART4 ) Base Address More...
 
#define USART0   ((Usart *)0x40024000U)
 (USART0) Base Address More...
 
#define USART1   ((Usart *)0x40028000U)
 (USART1) Base Address More...
 
#define USART2   ((Usart *)0x4002C000U)
 (USART2) Base Address More...
 
#define USBHS   ((Usbhs *)0x40038000U)
 (USBHS ) Base Address More...
 
#define UTMI   ((Utmi *)0x400E0400U)
 (UTMI ) Base Address More...
 
#define WDT   ((Wdt *)0x400E1850U)
 (WDT ) Base Address More...
 
#define XDMAC   ((Xdmac *)0x40078000U)
 (XDMAC ) Base Address More...
 

Typedefs

typedef struct _DeviceVectors DeviceVectors
 
typedef enum IRQn IRQn_Type
 

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2,
  RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6,
  UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11,
  USART0_IRQn = 13, USART1_IRQn = 14, PIOD_IRQn = 16, TWIHS0_IRQn = 19,
  TWIHS1_IRQn = 20, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24,
  TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31,
  ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35,
  MCAN0_INT1_IRQn = 36, GMAC_IRQn = 39, AFEC1_IRQn = 40, QSPI_IRQn = 43,
  UART2_IRQn = 44, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52,
  AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59,
  PWM1_IRQn = 60, FPU_IRQn = 61, RSWDT_IRQn = 63, CCW_IRQn = 64,
  CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68,
  PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1,
  RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5,
  EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10,
  PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, PIOD_IRQn = 16,
  TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SSC_IRQn = 22, TC0_IRQn = 23,
  TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30,
  PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34,
  MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, GMAC_IRQn = 39, AFEC1_IRQn = 40,
  QSPI_IRQn = 43, UART2_IRQn = 44, TC9_IRQn = 50, TC10_IRQn = 51,
  TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58,
  ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61, RSWDT_IRQn = 63,
  CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67,
  IXC_IRQn = 68, GMAC_Q3_IRQn = 71, GMAC_Q4_IRQn = 72, GMAC_Q5_IRQn = 73,
  PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1,
  RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5,
  EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10,
  PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, PIOD_IRQn = 16,
  TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SSC_IRQn = 22, TC0_IRQn = 23,
  TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30,
  PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34,
  MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, GMAC_IRQn = 39, AFEC1_IRQn = 40,
  QSPI_IRQn = 43, UART2_IRQn = 44, TC9_IRQn = 50, TC10_IRQn = 51,
  TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58,
  ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61, RSWDT_IRQn = 63,
  CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67,
  IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0,
  RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4,
  PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8,
  PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14,
  PIOD_IRQn = 16, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SSC_IRQn = 22,
  TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29,
  DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33,
  USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, GMAC_IRQn = 39,
  AFEC1_IRQn = 40, QSPI_IRQn = 43, UART2_IRQn = 44, TC9_IRQn = 50,
  TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57,
  XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61,
  RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66,
  GMAC_Q2_IRQn = 67, IXC_IRQn = 68, GMAC_Q3_IRQn = 71, GMAC_Q4_IRQn = 72,
  GMAC_Q5_IRQn = 73, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0,
  RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4,
  PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8,
  PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14,
  PIOD_IRQn = 16, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SSC_IRQn = 22,
  TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29,
  DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33,
  USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, GMAC_IRQn = 39,
  AFEC1_IRQn = 40, QSPI_IRQn = 43, UART2_IRQn = 44, TC9_IRQn = 50,
  TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57,
  XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61,
  RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66,
  GMAC_Q2_IRQn = 67, IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3,
  WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7,
  UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13,
  USART1_IRQn = 14, PIOD_IRQn = 16, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20,
  SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25,
  AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32,
  ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36,
  GMAC_IRQn = 39, AFEC1_IRQn = 40, QSPI_IRQn = 43, UART2_IRQn = 44,
  TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56,
  TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60,
  FPU_IRQn = 61, RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65,
  GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68, GMAC_Q3_IRQn = 71,
  GMAC_Q4_IRQn = 72, GMAC_Q5_IRQn = 73, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3,
  WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7,
  UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13,
  USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18,
  TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22,
  TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29,
  DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33,
  USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37,
  MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41,
  QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46,
  TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56,
  TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60,
  FPU_IRQn = 61, RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65,
  GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2,
  RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6,
  UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11,
  USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16,
  HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21,
  SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25,
  AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32,
  ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36,
  MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40,
  TWIHS2_IRQn = 41, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45,
  UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52,
  AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59,
  PWM1_IRQn = 60, FPU_IRQn = 61, RSWDT_IRQn = 63, CCW_IRQn = 64,
  CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68,
  I2SC0_IRQn = 69, GMAC_Q3_IRQn = 71, GMAC_Q4_IRQn = 72, GMAC_Q5_IRQn = 73,
  PERIPH_COUNT_IRQn = 71, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1,
  RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5,
  EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10,
  PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15,
  PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20,
  SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24,
  TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31,
  ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35,
  MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39,
  AFEC1_IRQn = 40, TWIHS2_IRQn = 41, QSPI_IRQn = 43, UART2_IRQn = 44,
  UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51,
  TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58,
  ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61, RSWDT_IRQn = 63,
  CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67,
  IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0,
  RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4,
  PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8,
  PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14,
  USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19,
  TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23,
  TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30,
  PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34,
  MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38,
  GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, QSPI_IRQn = 43,
  UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50,
  TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57,
  XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61,
  RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66,
  GMAC_Q2_IRQn = 67, IXC_IRQn = 68, I2SC0_IRQn = 69, GMAC_Q3_IRQn = 71,
  GMAC_Q4_IRQn = 72, GMAC_Q5_IRQn = 73, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3,
  WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7,
  UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13,
  USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18,
  TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22,
  TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29,
  DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33,
  USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37,
  MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41,
  QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46,
  TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56,
  TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60,
  FPU_IRQn = 61, RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65,
  GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2,
  RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6,
  UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11,
  USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16,
  HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21,
  SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25,
  AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32,
  ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36,
  MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40,
  TWIHS2_IRQn = 41, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45,
  UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52,
  AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59,
  PWM1_IRQn = 60, FPU_IRQn = 61, RSWDT_IRQn = 63, CCW_IRQn = 64,
  CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68,
  I2SC0_IRQn = 69, GMAC_Q3_IRQn = 71, GMAC_Q4_IRQn = 72, GMAC_Q5_IRQn = 73,
  PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1,
  RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5,
  EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10,
  PIOB_IRQn = 11, PIOC_IRQn = 12, USART0_IRQn = 13, USART1_IRQn = 14,
  USART2_IRQn = 15, PIOD_IRQn = 16, PIOE_IRQn = 17, HSMCI_IRQn = 18,
  TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22,
  TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, TC3_IRQn = 26,
  TC4_IRQn = 27, TC5_IRQn = 28, AFEC0_IRQn = 29, DACC_IRQn = 30,
  PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34,
  MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38,
  GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42,
  QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46,
  TC6_IRQn = 47, TC7_IRQn = 48, TC8_IRQn = 49, TC9_IRQn = 50,
  TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57,
  XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61,
  SDRAMC_IRQn = 62, RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65,
  GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2,
  RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6,
  UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11,
  PIOC_IRQn = 12, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15,
  PIOD_IRQn = 16, PIOE_IRQn = 17, HSMCI_IRQn = 18, TWIHS0_IRQn = 19,
  TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23,
  TC1_IRQn = 24, TC2_IRQn = 25, TC3_IRQn = 26, TC4_IRQn = 27,
  TC5_IRQn = 28, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31,
  ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35,
  MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39,
  AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43,
  UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC6_IRQn = 47,
  TC7_IRQn = 48, TC8_IRQn = 49, TC9_IRQn = 50, TC10_IRQn = 51,
  TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58,
  ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61, SDRAMC_IRQn = 62,
  RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66,
  GMAC_Q2_IRQn = 67, IXC_IRQn = 68, I2SC0_IRQn = 69, I2SC1_IRQn = 70,
  GMAC_Q3_IRQn = 71, GMAC_Q4_IRQn = 72, GMAC_Q5_IRQn = 73, PERIPH_COUNT_IRQn = 74,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2,
  RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6,
  UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11,
  PIOC_IRQn = 12, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15,
  PIOD_IRQn = 16, PIOE_IRQn = 17, HSMCI_IRQn = 18, TWIHS0_IRQn = 19,
  TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23,
  TC1_IRQn = 24, TC2_IRQn = 25, TC3_IRQn = 26, TC4_IRQn = 27,
  TC5_IRQn = 28, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31,
  ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35,
  MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39,
  AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43,
  UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC6_IRQn = 47,
  TC7_IRQn = 48, TC8_IRQn = 49, TC9_IRQn = 50, TC10_IRQn = 51,
  TC11_IRQn = 52, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58,
  ISI_IRQn = 59, PWM1_IRQn = 60, FPU_IRQn = 61, SDRAMC_IRQn = 62,
  RSWDT_IRQn = 63, CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66,
  GMAC_Q2_IRQn = 67, IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3,
  WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7,
  UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, PIOC_IRQn = 12,
  USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16,
  PIOE_IRQn = 17, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20,
  SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24,
  TC2_IRQn = 25, TC3_IRQn = 26, TC4_IRQn = 27, TC5_IRQn = 28,
  AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32,
  ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36,
  MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40,
  TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44,
  UART3_IRQn = 45, UART4_IRQn = 46, TC6_IRQn = 47, TC7_IRQn = 48,
  TC8_IRQn = 49, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52,
  AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59,
  PWM1_IRQn = 60, FPU_IRQn = 61, SDRAMC_IRQn = 62, RSWDT_IRQn = 63,
  CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67,
  IXC_IRQn = 68, I2SC0_IRQn = 69, I2SC1_IRQn = 70, GMAC_Q3_IRQn = 71,
  GMAC_Q4_IRQn = 72, GMAC_Q5_IRQn = 73, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3,
  WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7,
  UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, PIOC_IRQn = 12,
  USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16,
  PIOE_IRQn = 17, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20,
  SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24,
  TC2_IRQn = 25, TC3_IRQn = 26, TC4_IRQn = 27, TC5_IRQn = 28,
  AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32,
  ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36,
  MCAN1_INT0_IRQn = 37, MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40,
  TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44,
  UART3_IRQn = 45, UART4_IRQn = 46, TC6_IRQn = 47, TC7_IRQn = 48,
  TC8_IRQn = 49, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52,
  AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59,
  PWM1_IRQn = 60, FPU_IRQn = 61, SDRAMC_IRQn = 62, RSWDT_IRQn = 63,
  CCW_IRQn = 64, CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67,
  IXC_IRQn = 68, PERIPH_COUNT_IRQn = 74, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0,
  RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4,
  PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8,
  PIOA_IRQn = 10, PIOB_IRQn = 11, PIOC_IRQn = 12, USART0_IRQn = 13,
  USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, PIOE_IRQn = 17,
  HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21,
  SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25,
  TC3_IRQn = 26, TC4_IRQn = 27, TC5_IRQn = 28, AFEC0_IRQn = 29,
  DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33,
  USBHS_IRQn = 34, MCAN0_INT0_IRQn = 35, MCAN0_INT1_IRQn = 36, MCAN1_INT0_IRQn = 37,
  MCAN1_INT1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41,
  SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45,
  UART4_IRQn = 46, TC6_IRQn = 47, TC7_IRQn = 48, TC8_IRQn = 49,
  TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, AES_IRQn = 56,
  TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60,
  FPU_IRQn = 61, SDRAMC_IRQn = 62, RSWDT_IRQn = 63, CCW_IRQn = 64,
  CCF_IRQn = 65, GMAC_Q1_IRQn = 66, GMAC_Q2_IRQn = 67, IXC_IRQn = 68,
  I2SC0_IRQn = 69, I2SC1_IRQn = 70, GMAC_Q3_IRQn = 71, GMAC_Q4_IRQn = 72,
  GMAC_Q5_IRQn = 73, PERIPH_COUNT_IRQn = 74
}
 

Functions

void ACC_Handler (void)
 
void AES_Handler (void)
 
void AFEC0_Handler (void)
 Interrupt handler for AFEC0. More...
 
void AFEC1_Handler (void)
 Interrupt handler for AFEC1. More...
 
void BusFault_Handler (void)
 
void CCF_Handler (void)
 
void CCW_Handler (void)
 
void DACC_Handler (void)
 
void DebugMon_Handler (void)
 
void EFC_Handler (void)
 
void FPU_Handler (void)
 
void GMAC_Handler (void)
 
void GMAC_Q1_Handler (void)
 
void GMAC_Q2_Handler (void)
 
void GMAC_Q3_Handler (void)
 
void GMAC_Q4_Handler (void)
 
void GMAC_Q5_Handler (void)
 
void HardFault_Handler (void)
 
void HSMCI_Handler (void)
 
void I2SC0_Handler (void)
 
void I2SC1_Handler (void)
 
void ICM_Handler (void)
 
void ISI_Handler (void)
 
void IXC_Handler (void)
 
void MCAN0_INT0_Handler (void)
 
void MCAN0_INT1_Handler (void)
 
void MCAN1_INT0_Handler (void)
 
void MCAN1_INT1_Handler (void)
 
void MemManage_Handler (void)
 
void NMI_Handler (void)
 
void PendSV_Handler (void)
 
void PIOA_Handler (void)
 
void PIOB_Handler (void)
 
void PIOC_Handler (void)
 
void PIOD_Handler (void)
 
void PIOE_Handler (void)
 
void PMC_Handler (void)
 
void PWM0_Handler (void)
 
void PWM1_Handler (void)
 
void QSPI_Handler (void)
 
void Reset_Handler (void)
 This is the code that gets called on processor reset. To initialize the device, and call the main() routine. More...
 
void RSTC_Handler (void)
 
void RSWDT_Handler (void)
 
void RTC_Handler (void)
 
void RTT_Handler (void)
 
void SDRAMC_Handler (void)
 
void SPI0_Handler (void)
 
void SPI1_Handler (void)
 
void SSC_Handler (void)
 
void SUPC_Handler (void)
 
void SVC_Handler (void)
 
void SysTick_Handler (void)
 
void TC0_Handler (void)
 
void TC10_Handler (void)
 
void TC11_Handler (void)
 
void TC1_Handler (void)
 
void TC2_Handler (void)
 
void TC3_Handler (void)
 
void TC4_Handler (void)
 
void TC5_Handler (void)
 
void TC6_Handler (void)
 
void TC7_Handler (void)
 
void TC8_Handler (void)
 
void TC9_Handler (void)
 
void TRNG_Handler (void)
 
void TWIHS0_Handler (void)
 
void TWIHS1_Handler (void)
 
void TWIHS2_Handler (void)
 
void UART0_Handler (void)
 
void UART1_Handler (void)
 
void UART2_Handler (void)
 
void UART3_Handler (void)
 
void UART4_Handler (void)
 
void UsageFault_Handler (void)
 
void USART0_Handler (void)
 
void USART1_Handler (void)
 
void USART2_Handler (void)
 
void USBHS_Handler (void)
 
void WDT_Handler (void)
 
void XDMAC_Handler (void)
 

Detailed Description

Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.

Definition in file same70q19b.h.


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Author(s):
autogenerated on Sun Feb 28 2021 03:18:00