mcan0.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_MCAN0_INSTANCE_
36 #define _SAME70_MCAN0_INSTANCE_
37 
38 /* ========== Register definition for MCAN0 peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_MCAN0_CREL (0x40030000U)
41  #define REG_MCAN0_ENDN (0x40030004U)
42  #define REG_MCAN0_CUST (0x40030008U)
43  #define REG_MCAN0_FBTP (0x4003000CU)
44  #define REG_MCAN0_DBTP (0x4003000CU)
45  #define REG_MCAN0_TEST (0x40030010U)
46  #define REG_MCAN0_RWD (0x40030014U)
47  #define REG_MCAN0_CCCR (0x40030018U)
48  #define REG_MCAN0_BTP (0x4003001CU)
49  #define REG_MCAN0_NBTP (0x4003001CU)
50  #define REG_MCAN0_TSCC (0x40030020U)
51  #define REG_MCAN0_TSCV (0x40030024U)
52  #define REG_MCAN0_TOCC (0x40030028U)
53  #define REG_MCAN0_TOCV (0x4003002CU)
54  #define REG_MCAN0_ECR (0x40030040U)
55  #define REG_MCAN0_PSR (0x40030044U)
56  #define REG_MCAN0_TDCR (0x40030048U)
57  #define REG_MCAN0_IR (0x40030050U)
58  #define REG_MCAN0_IE (0x40030054U)
59  #define REG_MCAN0_ILS (0x40030058U)
60  #define REG_MCAN0_ILE (0x4003005CU)
61  #define REG_MCAN0_GFC (0x40030080U)
62  #define REG_MCAN0_SIDFC (0x40030084U)
63  #define REG_MCAN0_XIDFC (0x40030088U)
64  #define REG_MCAN0_XIDAM (0x40030090U)
65  #define REG_MCAN0_HPMS (0x40030094U)
66  #define REG_MCAN0_NDAT1 (0x40030098U)
67  #define REG_MCAN0_NDAT2 (0x4003009CU)
68  #define REG_MCAN0_RXF0C (0x400300A0U)
69  #define REG_MCAN0_RXF0S (0x400300A4U)
70  #define REG_MCAN0_RXF0A (0x400300A8U)
71  #define REG_MCAN0_RXBC (0x400300ACU)
72  #define REG_MCAN0_RXF1C (0x400300B0U)
73  #define REG_MCAN0_RXF1S (0x400300B4U)
74  #define REG_MCAN0_RXF1A (0x400300B8U)
75  #define REG_MCAN0_RXESC (0x400300BCU)
76  #define REG_MCAN0_TXBC (0x400300C0U)
77  #define REG_MCAN0_TXFQS (0x400300C4U)
78  #define REG_MCAN0_TXESC (0x400300C8U)
79  #define REG_MCAN0_TXBRP (0x400300CCU)
80  #define REG_MCAN0_TXBAR (0x400300D0U)
81  #define REG_MCAN0_TXBCR (0x400300D4U)
82  #define REG_MCAN0_TXBTO (0x400300D8U)
83  #define REG_MCAN0_TXBCF (0x400300DCU)
84  #define REG_MCAN0_TXBTIE (0x400300E0U)
85  #define REG_MCAN0_TXBCIE (0x400300E4U)
86  #define REG_MCAN0_TXEFC (0x400300F0U)
87  #define REG_MCAN0_TXEFS (0x400300F4U)
88  #define REG_MCAN0_TXEFA (0x400300F8U)
89 #else
90  #define REG_MCAN0_CREL (*(__I uint32_t*)0x40030000U)
91  #define REG_MCAN0_ENDN (*(__I uint32_t*)0x40030004U)
92  #define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U)
93  #define REG_MCAN0_FBTP (*(__IO uint32_t*)0x4003000CU)
94  #define REG_MCAN0_DBTP (*(__IO uint32_t*)0x4003000CU)
95  #define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U)
96  #define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U)
97  #define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U)
98  #define REG_MCAN0_BTP (*(__IO uint32_t*)0x4003001CU)
99  #define REG_MCAN0_NBTP (*(__IO uint32_t*)0x4003001CU)
100  #define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U)
101  #define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U)
102  #define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U)
103  #define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU)
104  #define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U)
105  #define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U)
106  #define REG_MCAN0_TDCR (*(__IO uint32_t*)0x40030048U)
107  #define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U)
108  #define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U)
109  #define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U)
110  #define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU)
111  #define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U)
112  #define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U)
113  #define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U)
114  #define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U)
115  #define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U)
116  #define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U)
117  #define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU)
118  #define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U)
119  #define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U)
120  #define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U)
121  #define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU)
122  #define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U)
123  #define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U)
124  #define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U)
125  #define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU)
126  #define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U)
127  #define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U)
128  #define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U)
129  #define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU)
130  #define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U)
131  #define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U)
132  #define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U)
133  #define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU)
134  #define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U)
135  #define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U)
136  #define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U)
137  #define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U)
138  #define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U)
139 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
140 
141 #endif /* _SAME70_MCAN0_INSTANCE_ */

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autogenerated on Sun Feb 28 2021 03:17:58