component/trng.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_TRNG_COMPONENT_
36 #define _SAME70_TRNG_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t TRNG_CR;
48  __I uint32_t Reserved1[3];
49  __O uint32_t TRNG_IER;
50  __O uint32_t TRNG_IDR;
51  __I uint32_t TRNG_IMR;
52  __I uint32_t TRNG_ISR;
53  __I uint32_t Reserved2[12];
54  __I uint32_t TRNG_ODATA;
55  __I uint32_t Reserved3[42];
56  __I uint32_t TRNG_VERSION;
57 } Trng;
58 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
59 /* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
60 #define TRNG_CR_ENABLE (0x1u << 0)
61 #define TRNG_CR_KEY_Pos 8
62 #define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos)
63 #define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
64 #define TRNG_CR_KEY_PASSWD (0x524E47u << 8)
65 /* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
66 #define TRNG_IER_DATRDY (0x1u << 0)
67 /* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
68 #define TRNG_IDR_DATRDY (0x1u << 0)
69 /* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
70 #define TRNG_IMR_DATRDY (0x1u << 0)
71 /* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
72 #define TRNG_ISR_DATRDY (0x1u << 0)
73 /* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
74 #define TRNG_ODATA_ODATA_Pos 0
75 #define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos)
76 /* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */
77 #define TRNG_VERSION_VERSION_Pos 0
78 #define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos)
79 #define TRNG_VERSION_MFN_Pos 16
80 #define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos)
83 
84 
85 #endif /* _SAME70_TRNG_COMPONENT_ */
__O uint32_t TRNG_IDR
(Trng Offset: 0x14) Interrupt Disable Register
#define __O
Definition: core_cm7.h:265
Trng hardware registers.
__O uint32_t TRNG_CR
(Trng Offset: 0x00) Control Register
__I uint32_t TRNG_ODATA
(Trng Offset: 0x50) Output Data Register
__I uint32_t TRNG_IMR
(Trng Offset: 0x18) Interrupt Mask Register
__O uint32_t TRNG_IER
(Trng Offset: 0x10) Interrupt Enable Register
__I uint32_t TRNG_VERSION
(Trng Offset: 0xFC) Version Register
#define __I
Definition: core_cm7.h:263
__I uint32_t TRNG_ISR
(Trng Offset: 0x1C) Interrupt Status Register


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autogenerated on Sun Feb 28 2021 03:17:58