component/qspi.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70_QSPI_COMPONENT_
#define _SAME70_QSPI_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __O  uint32_t QSPI_CR;       
  __IO uint32_t QSPI_MR;       
  __I  uint32_t QSPI_RDR;      
  __O  uint32_t QSPI_TDR;      
  __I  uint32_t QSPI_SR;       
  __O  uint32_t QSPI_IER;      
  __O  uint32_t QSPI_IDR;      
  __I  uint32_t QSPI_IMR;      
  __IO uint32_t QSPI_SCR;      
  __I  uint32_t Reserved1[3];
  __IO uint32_t QSPI_IAR;      
  __IO uint32_t QSPI_ICR;      
  __IO uint32_t QSPI_IFR;      
  __I  uint32_t Reserved2[1];
  __IO uint32_t QSPI_SMR;      
  __O  uint32_t QSPI_SKR;      
  __I  uint32_t Reserved3[39];
  __IO uint32_t QSPI_WPMR;     
  __I  uint32_t QSPI_WPSR;     
  __I  uint32_t Reserved4[4];
  __I  uint32_t QSPI_VERSION;  
} Qspi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
#define QSPI_CR_QSPIEN (0x1u << 0) 
#define QSPI_CR_QSPIDIS (0x1u << 1) 
#define QSPI_CR_SWRST (0x1u << 7) 
#define QSPI_CR_LASTXFER (0x1u << 24) 
/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
#define QSPI_MR_SMM (0x1u << 0) 
#define   QSPI_MR_SMM_SPI (0x0u << 0) 
#define   QSPI_MR_SMM_MEMORY (0x1u << 0) 
#define QSPI_MR_LLB (0x1u << 1) 
#define   QSPI_MR_LLB_DISABLED (0x0u << 1) 
#define   QSPI_MR_LLB_ENABLED (0x1u << 1) 
#define QSPI_MR_WDRBT (0x1u << 2) 
#define   QSPI_MR_WDRBT_DISABLED (0x0u << 2) 
#define   QSPI_MR_WDRBT_ENABLED (0x1u << 2) 
#define QSPI_MR_CSMODE_Pos 4
#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) 
#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
#define   QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) 
#define   QSPI_MR_CSMODE_LASTXFER (0x1u << 4) 
#define   QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) 
#define QSPI_MR_NBBITS_Pos 8
#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) 
#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
#define   QSPI_MR_NBBITS_8_BIT (0x0u << 8) 
#define   QSPI_MR_NBBITS_9_BIT (0x1u << 8) 
#define   QSPI_MR_NBBITS_10_BIT (0x2u << 8) 
#define   QSPI_MR_NBBITS_11_BIT (0x3u << 8) 
#define   QSPI_MR_NBBITS_12_BIT (0x4u << 8) 
#define   QSPI_MR_NBBITS_13_BIT (0x5u << 8) 
#define   QSPI_MR_NBBITS_14_BIT (0x6u << 8) 
#define   QSPI_MR_NBBITS_15_BIT (0x7u << 8) 
#define   QSPI_MR_NBBITS_16_BIT (0x8u << 8) 
#define QSPI_MR_DLYBCT_Pos 16
#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) 
#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
#define QSPI_MR_DLYCS_Pos 24
#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) 
#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
#define QSPI_RDR_RD_Pos 0
#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) 
/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
#define QSPI_TDR_TD_Pos 0
#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) 
#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
#define QSPI_SR_RDRF (0x1u << 0) 
#define QSPI_SR_TDRE (0x1u << 1) 
#define QSPI_SR_TXEMPTY (0x1u << 2) 
#define QSPI_SR_OVRES (0x1u << 3) 
#define QSPI_SR_CSR (0x1u << 8) 
#define QSPI_SR_CSS (0x1u << 9) 
#define QSPI_SR_INSTRE (0x1u << 10) 
#define QSPI_SR_QSPIENS (0x1u << 24) 
/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
#define QSPI_IER_RDRF (0x1u << 0) 
#define QSPI_IER_TDRE (0x1u << 1) 
#define QSPI_IER_TXEMPTY (0x1u << 2) 
#define QSPI_IER_OVRES (0x1u << 3) 
#define QSPI_IER_CSR (0x1u << 8) 
#define QSPI_IER_CSS (0x1u << 9) 
#define QSPI_IER_INSTRE (0x1u << 10) 
/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
#define QSPI_IDR_RDRF (0x1u << 0) 
#define QSPI_IDR_TDRE (0x1u << 1) 
#define QSPI_IDR_TXEMPTY (0x1u << 2) 
#define QSPI_IDR_OVRES (0x1u << 3) 
#define QSPI_IDR_CSR (0x1u << 8) 
#define QSPI_IDR_CSS (0x1u << 9) 
#define QSPI_IDR_INSTRE (0x1u << 10) 
/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
#define QSPI_IMR_RDRF (0x1u << 0) 
#define QSPI_IMR_TDRE (0x1u << 1) 
#define QSPI_IMR_TXEMPTY (0x1u << 2) 
#define QSPI_IMR_OVRES (0x1u << 3) 
#define QSPI_IMR_CSR (0x1u << 8) 
#define QSPI_IMR_CSS (0x1u << 9) 
#define QSPI_IMR_INSTRE (0x1u << 10) 
/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
#define QSPI_SCR_CPOL (0x1u << 0) 
#define QSPI_SCR_CPHA (0x1u << 1) 
#define QSPI_SCR_SCBR_Pos 8
#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) 
#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
#define QSPI_SCR_DLYBS_Pos 16
#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) 
#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
#define QSPI_IAR_ADDR_Pos 0
#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) 
#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
#define QSPI_ICR_INST_Pos 0
#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) 
#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
#define QSPI_ICR_OPT_Pos 16
#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) 
#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
#define QSPI_IFR_WIDTH_Pos 0
#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) 
#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
#define   QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) 
#define   QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) 
#define   QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) 
#define   QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) 
#define   QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) 
#define   QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) 
#define   QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) 
#define QSPI_IFR_INSTEN (0x1u << 4) 
#define QSPI_IFR_ADDREN (0x1u << 5) 
#define QSPI_IFR_OPTEN (0x1u << 6) 
#define QSPI_IFR_DATAEN (0x1u << 7) 
#define QSPI_IFR_OPTL_Pos 8
#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) 
#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
#define   QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) 
#define   QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) 
#define   QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) 
#define   QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) 
#define QSPI_IFR_ADDRL (0x1u << 10) 
#define   QSPI_IFR_ADDRL_24_BIT (0x0u << 10) 
#define   QSPI_IFR_ADDRL_32_BIT (0x1u << 10) 
#define QSPI_IFR_TFRTYP_Pos 12
#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) 
#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
#define   QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) 
#define   QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) 
#define   QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) 
#define   QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) 
#define QSPI_IFR_CRM (0x1u << 14) 
#define   QSPI_IFR_CRM_DISABLED (0x0u << 14) 
#define   QSPI_IFR_CRM_ENABLED (0x1u << 14) 
#define QSPI_IFR_NBDUM_Pos 16
#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) 
#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
#define QSPI_SMR_SCREN (0x1u << 0) 
#define   QSPI_SMR_SCREN_DISABLED (0x0u << 0) 
#define   QSPI_SMR_SCREN_ENABLED (0x1u << 0) 
#define QSPI_SMR_RVDIS (0x1u << 1) 
/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
#define QSPI_SKR_USRK_Pos 0
#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) 
#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
#define QSPI_WPMR_WPEN (0x1u << 0) 
#define QSPI_WPMR_WPKEY_Pos 8
#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) 
#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
#define   QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) 
/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
#define QSPI_WPSR_WPVS (0x1u << 0) 
#define QSPI_WPSR_WPVSRC_Pos 8
#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) 
/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */
#define QSPI_VERSION_VERSION_Pos 0
#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) 
#define QSPI_VERSION_MFN_Pos 16
#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) 


#endif /* _SAME70_QSPI_COMPONENT_ */