tc2.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70_TC2_INSTANCE_
#define _SAME70_TC2_INSTANCE_

/* ========== Register definition for TC2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  #define REG_TC2_CCR0                   (0x40014000U) 
  #define REG_TC2_CMR0                   (0x40014004U) 
  #define REG_TC2_SMMR0                  (0x40014008U) 
  #define REG_TC2_RAB0                   (0x4001400CU) 
  #define REG_TC2_CV0                    (0x40014010U) 
  #define REG_TC2_RA0                    (0x40014014U) 
  #define REG_TC2_RB0                    (0x40014018U) 
  #define REG_TC2_RC0                    (0x4001401CU) 
  #define REG_TC2_SR0                    (0x40014020U) 
  #define REG_TC2_IER0                   (0x40014024U) 
  #define REG_TC2_IDR0                   (0x40014028U) 
  #define REG_TC2_IMR0                   (0x4001402CU) 
  #define REG_TC2_EMR0                   (0x40014030U) 
  #define REG_TC2_CCR1                   (0x40014040U) 
  #define REG_TC2_CMR1                   (0x40014044U) 
  #define REG_TC2_SMMR1                  (0x40014048U) 
  #define REG_TC2_RAB1                   (0x4001404CU) 
  #define REG_TC2_CV1                    (0x40014050U) 
  #define REG_TC2_RA1                    (0x40014054U) 
  #define REG_TC2_RB1                    (0x40014058U) 
  #define REG_TC2_RC1                    (0x4001405CU) 
  #define REG_TC2_SR1                    (0x40014060U) 
  #define REG_TC2_IER1                   (0x40014064U) 
  #define REG_TC2_IDR1                   (0x40014068U) 
  #define REG_TC2_IMR1                   (0x4001406CU) 
  #define REG_TC2_EMR1                   (0x40014070U) 
  #define REG_TC2_CCR2                   (0x40014080U) 
  #define REG_TC2_CMR2                   (0x40014084U) 
  #define REG_TC2_SMMR2                  (0x40014088U) 
  #define REG_TC2_RAB2                   (0x4001408CU) 
  #define REG_TC2_CV2                    (0x40014090U) 
  #define REG_TC2_RA2                    (0x40014094U) 
  #define REG_TC2_RB2                    (0x40014098U) 
  #define REG_TC2_RC2                    (0x4001409CU) 
  #define REG_TC2_SR2                    (0x400140A0U) 
  #define REG_TC2_IER2                   (0x400140A4U) 
  #define REG_TC2_IDR2                   (0x400140A8U) 
  #define REG_TC2_IMR2                   (0x400140ACU) 
  #define REG_TC2_EMR2                   (0x400140B0U) 
  #define REG_TC2_BCR                    (0x400140C0U) 
  #define REG_TC2_BMR                    (0x400140C4U) 
  #define REG_TC2_QIER                   (0x400140C8U) 
  #define REG_TC2_QIDR                   (0x400140CCU) 
  #define REG_TC2_QIMR                   (0x400140D0U) 
  #define REG_TC2_QISR                   (0x400140D4U) 
  #define REG_TC2_FMR                    (0x400140D8U) 
  #define REG_TC2_WPMR                   (0x400140E4U) 
  #define REG_TC2_VER                    (0x400140FCU) 
#else
  #define REG_TC2_CCR0  (*(__O  uint32_t*)0x40014000U) 
  #define REG_TC2_CMR0  (*(__IO uint32_t*)0x40014004U) 
  #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) 
  #define REG_TC2_RAB0  (*(__I  uint32_t*)0x4001400CU) 
  #define REG_TC2_CV0   (*(__I  uint32_t*)0x40014010U) 
  #define REG_TC2_RA0   (*(__IO uint32_t*)0x40014014U) 
  #define REG_TC2_RB0   (*(__IO uint32_t*)0x40014018U) 
  #define REG_TC2_RC0   (*(__IO uint32_t*)0x4001401CU) 
  #define REG_TC2_SR0   (*(__I  uint32_t*)0x40014020U) 
  #define REG_TC2_IER0  (*(__O  uint32_t*)0x40014024U) 
  #define REG_TC2_IDR0  (*(__O  uint32_t*)0x40014028U) 
  #define REG_TC2_IMR0  (*(__I  uint32_t*)0x4001402CU) 
  #define REG_TC2_EMR0  (*(__IO uint32_t*)0x40014030U) 
  #define REG_TC2_CCR1  (*(__O  uint32_t*)0x40014040U) 
  #define REG_TC2_CMR1  (*(__IO uint32_t*)0x40014044U) 
  #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) 
  #define REG_TC2_RAB1  (*(__I  uint32_t*)0x4001404CU) 
  #define REG_TC2_CV1   (*(__I  uint32_t*)0x40014050U) 
  #define REG_TC2_RA1   (*(__IO uint32_t*)0x40014054U) 
  #define REG_TC2_RB1   (*(__IO uint32_t*)0x40014058U) 
  #define REG_TC2_RC1   (*(__IO uint32_t*)0x4001405CU) 
  #define REG_TC2_SR1   (*(__I  uint32_t*)0x40014060U) 
  #define REG_TC2_IER1  (*(__O  uint32_t*)0x40014064U) 
  #define REG_TC2_IDR1  (*(__O  uint32_t*)0x40014068U) 
  #define REG_TC2_IMR1  (*(__I  uint32_t*)0x4001406CU) 
  #define REG_TC2_EMR1  (*(__IO uint32_t*)0x40014070U) 
  #define REG_TC2_CCR2  (*(__O  uint32_t*)0x40014080U) 
  #define REG_TC2_CMR2  (*(__IO uint32_t*)0x40014084U) 
  #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) 
  #define REG_TC2_RAB2  (*(__I  uint32_t*)0x4001408CU) 
  #define REG_TC2_CV2   (*(__I  uint32_t*)0x40014090U) 
  #define REG_TC2_RA2   (*(__IO uint32_t*)0x40014094U) 
  #define REG_TC2_RB2   (*(__IO uint32_t*)0x40014098U) 
  #define REG_TC2_RC2   (*(__IO uint32_t*)0x4001409CU) 
  #define REG_TC2_SR2   (*(__I  uint32_t*)0x400140A0U) 
  #define REG_TC2_IER2  (*(__O  uint32_t*)0x400140A4U) 
  #define REG_TC2_IDR2  (*(__O  uint32_t*)0x400140A8U) 
  #define REG_TC2_IMR2  (*(__I  uint32_t*)0x400140ACU) 
  #define REG_TC2_EMR2  (*(__IO uint32_t*)0x400140B0U) 
  #define REG_TC2_BCR   (*(__O  uint32_t*)0x400140C0U) 
  #define REG_TC2_BMR   (*(__IO uint32_t*)0x400140C4U) 
  #define REG_TC2_QIER  (*(__O  uint32_t*)0x400140C8U) 
  #define REG_TC2_QIDR  (*(__O  uint32_t*)0x400140CCU) 
  #define REG_TC2_QIMR  (*(__I  uint32_t*)0x400140D0U) 
  #define REG_TC2_QISR  (*(__I  uint32_t*)0x400140D4U) 
  #define REG_TC2_FMR   (*(__IO uint32_t*)0x400140D8U) 
  #define REG_TC2_WPMR  (*(__IO uint32_t*)0x400140E4U) 
  #define REG_TC2_VER   (*(__I  uint32_t*)0x400140FCU) 
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#endif /* _SAME70_TC2_INSTANCE_ */