instance/isi.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70_ISI_INSTANCE_
#define _SAME70_ISI_INSTANCE_

/* ========== Register definition for ISI peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  #define REG_ISI_CFG1                        (0x4004C000U) 
  #define REG_ISI_CFG2                        (0x4004C004U) 
  #define REG_ISI_PSIZE                       (0x4004C008U) 
  #define REG_ISI_PDECF                       (0x4004C00CU) 
  #define REG_ISI_Y2R_SET0                    (0x4004C010U) 
  #define REG_ISI_Y2R_SET1                    (0x4004C014U) 
  #define REG_ISI_R2Y_SET0                    (0x4004C018U) 
  #define REG_ISI_R2Y_SET1                    (0x4004C01CU) 
  #define REG_ISI_R2Y_SET2                    (0x4004C020U) 
  #define REG_ISI_CR                          (0x4004C024U) 
  #define REG_ISI_SR                          (0x4004C028U) 
  #define REG_ISI_IER                         (0x4004C02CU) 
  #define REG_ISI_IDR                         (0x4004C030U) 
  #define REG_ISI_IMR                         (0x4004C034U) 
  #define REG_ISI_DMA_CHER                    (0x4004C038U) 
  #define REG_ISI_DMA_CHDR                    (0x4004C03CU) 
  #define REG_ISI_DMA_CHSR                    (0x4004C040U) 
  #define REG_ISI_DMA_P_ADDR                  (0x4004C044U) 
  #define REG_ISI_DMA_P_CTRL                  (0x4004C048U) 
  #define REG_ISI_DMA_P_DSCR                  (0x4004C04CU) 
  #define REG_ISI_DMA_C_ADDR                  (0x4004C050U) 
  #define REG_ISI_DMA_C_CTRL                  (0x4004C054U) 
  #define REG_ISI_DMA_C_DSCR                  (0x4004C058U) 
  #define REG_ISI_WPMR                        (0x4004C0E4U) 
  #define REG_ISI_WPSR                        (0x4004C0E8U) 
  #define REG_ISI_VERSION                     (0x4004C0FCU) 
#else
  #define REG_ISI_CFG1       (*(__IO uint32_t*)0x4004C000U) 
  #define REG_ISI_CFG2       (*(__IO uint32_t*)0x4004C004U) 
  #define REG_ISI_PSIZE      (*(__IO uint32_t*)0x4004C008U) 
  #define REG_ISI_PDECF      (*(__IO uint32_t*)0x4004C00CU) 
  #define REG_ISI_Y2R_SET0   (*(__IO uint32_t*)0x4004C010U) 
  #define REG_ISI_Y2R_SET1   (*(__IO uint32_t*)0x4004C014U) 
  #define REG_ISI_R2Y_SET0   (*(__IO uint32_t*)0x4004C018U) 
  #define REG_ISI_R2Y_SET1   (*(__IO uint32_t*)0x4004C01CU) 
  #define REG_ISI_R2Y_SET2   (*(__IO uint32_t*)0x4004C020U) 
  #define REG_ISI_CR         (*(__O  uint32_t*)0x4004C024U) 
  #define REG_ISI_SR         (*(__I  uint32_t*)0x4004C028U) 
  #define REG_ISI_IER        (*(__O  uint32_t*)0x4004C02CU) 
  #define REG_ISI_IDR        (*(__O  uint32_t*)0x4004C030U) 
  #define REG_ISI_IMR        (*(__I  uint32_t*)0x4004C034U) 
  #define REG_ISI_DMA_CHER   (*(__O  uint32_t*)0x4004C038U) 
  #define REG_ISI_DMA_CHDR   (*(__O  uint32_t*)0x4004C03CU) 
  #define REG_ISI_DMA_CHSR   (*(__I  uint32_t*)0x4004C040U) 
  #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) 
  #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) 
  #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) 
  #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) 
  #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) 
  #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) 
  #define REG_ISI_WPMR       (*(__IO uint32_t*)0x4004C0E4U) 
  #define REG_ISI_WPSR       (*(__I  uint32_t*)0x4004C0E8U) 
  #define REG_ISI_VERSION    (*(__I  uint32_t*)0x4004C0FCU) 
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#endif /* _SAME70_ISI_INSTANCE_ */