Dacc hardware registers. More...

#include <dacc.h>

Public Attributes
__IO uint32_t	DACC_ACR
	(Dacc Offset: 0x94) Analog Current Register More...

__O uint32_t	DACC_CDR [2]
	(Dacc Offset: 0x1C) Conversion Data Register More...

__O uint32_t	DACC_CHDR
	(Dacc Offset: 0x14) Channel Disable Register More...

__O uint32_t	DACC_CHER
	(Dacc Offset: 0x10) Channel Enable Register More...

__I uint32_t	DACC_CHSR
	(Dacc Offset: 0x18) Channel Status Register More...

__O uint32_t	DACC_CR
	(Dacc Offset: 0x00) Control Register More...

__O uint32_t	DACC_IDR
	(Dacc Offset: 0x28) Interrupt Disable Register More...

__O uint32_t	DACC_IER
	(Dacc Offset: 0x24) Interrupt Enable Register More...

__I uint32_t	DACC_IMR
	(Dacc Offset: 0x2C) Interrupt Mask Register More...

__I uint32_t	DACC_ISR
	(Dacc Offset: 0x30) Interrupt Status Register More...

__IO uint32_t	DACC_MR
	(Dacc Offset: 0x04) Mode Register More...

__IO uint32_t	DACC_TRIGR
	(Dacc Offset: 0x08) Trigger Register More...

__I uint32_t	DACC_VERSION
	(Dacc Offset: 0xFC) Version Register More...

__IO uint32_t	DACC_WPMR
	(Dacc Offset: 0xE4) Write Protection Mode Register More...

__I uint32_t	DACC_WPSR
	(Dacc Offset: 0xE8) Write Protection Status Register More...

__I uint32_t	Reserved1 [1]

__I uint32_t	Reserved2 [24]

__I uint32_t	Reserved3 [19]

__I uint32_t	Reserved4 [4]

Detailed Description

Dacc hardware registers.

Definition at line 46 of file component/dacc.h.

Member Data Documentation

◆ DACC_ACR

__IO uint32_t Dacc::DACC_ACR

(Dacc Offset: 0x94) Analog Current Register

Definition at line 60 of file component/dacc.h.

◆ DACC_CDR

__O uint32_t Dacc::DACC_CDR[2]

(Dacc Offset: 0x1C) Conversion Data Register

Definition at line 54 of file component/dacc.h.

◆ DACC_CHDR

__O uint32_t Dacc::DACC_CHDR

(Dacc Offset: 0x14) Channel Disable Register

Definition at line 52 of file component/dacc.h.

◆ DACC_CHER

__O uint32_t Dacc::DACC_CHER

(Dacc Offset: 0x10) Channel Enable Register

Definition at line 51 of file component/dacc.h.

◆ DACC_CHSR

__I uint32_t Dacc::DACC_CHSR

(Dacc Offset: 0x18) Channel Status Register

Definition at line 53 of file component/dacc.h.

◆ DACC_CR

__O uint32_t Dacc::DACC_CR

(Dacc Offset: 0x00) Control Register

Definition at line 47 of file component/dacc.h.

◆ DACC_IDR

__O uint32_t Dacc::DACC_IDR

(Dacc Offset: 0x28) Interrupt Disable Register

Definition at line 56 of file component/dacc.h.

◆ DACC_IER

__O uint32_t Dacc::DACC_IER

(Dacc Offset: 0x24) Interrupt Enable Register

Definition at line 55 of file component/dacc.h.

◆ DACC_IMR

__I uint32_t Dacc::DACC_IMR

(Dacc Offset: 0x2C) Interrupt Mask Register

Definition at line 57 of file component/dacc.h.

◆ DACC_ISR

__I uint32_t Dacc::DACC_ISR

(Dacc Offset: 0x30) Interrupt Status Register

Definition at line 58 of file component/dacc.h.

◆ DACC_MR

__IO uint32_t Dacc::DACC_MR

(Dacc Offset: 0x04) Mode Register

Definition at line 48 of file component/dacc.h.

◆ DACC_TRIGR

__IO uint32_t Dacc::DACC_TRIGR

(Dacc Offset: 0x08) Trigger Register

Definition at line 49 of file component/dacc.h.

◆ DACC_VERSION

__I uint32_t Dacc::DACC_VERSION

(Dacc Offset: 0xFC) Version Register

Definition at line 65 of file component/dacc.h.

◆ DACC_WPMR

__IO uint32_t Dacc::DACC_WPMR

(Dacc Offset: 0xE4) Write Protection Mode Register

Definition at line 62 of file component/dacc.h.

◆ DACC_WPSR

__I uint32_t Dacc::DACC_WPSR

(Dacc Offset: 0xE8) Write Protection Status Register

Definition at line 63 of file component/dacc.h.

◆ Reserved1

__I uint32_t Dacc::Reserved1[1]

Definition at line 50 of file component/dacc.h.

◆ Reserved2

__I uint32_t Dacc::Reserved2[24]

Definition at line 59 of file component/dacc.h.

◆ Reserved3

__I uint32_t Dacc::Reserved3[19]

Definition at line 61 of file component/dacc.h.

◆ Reserved4

__I uint32_t Dacc::Reserved4[4]

Definition at line 64 of file component/dacc.h.

The documentation for this struct was generated from the following file:

component/dacc.h

Public Attributes