mcan1.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_MCAN1_INSTANCE_
36 #define _SAME70_MCAN1_INSTANCE_
37 
38 /* ========== Register definition for MCAN1 peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_MCAN1_CREL (0x40034000U)
41  #define REG_MCAN1_ENDN (0x40034004U)
42  #define REG_MCAN1_CUST (0x40034008U)
43  #define REG_MCAN1_FBTP (0x4003400CU)
44  #define REG_MCAN1_DBTP (0x4003400CU)
45  #define REG_MCAN1_TEST (0x40034010U)
46  #define REG_MCAN1_RWD (0x40034014U)
47  #define REG_MCAN1_CCCR (0x40034018U)
48  #define REG_MCAN1_BTP (0x4003401CU)
49  #define REG_MCAN1_NBTP (0x4003401CU)
50  #define REG_MCAN1_TSCC (0x40034020U)
51  #define REG_MCAN1_TSCV (0x40034024U)
52  #define REG_MCAN1_TOCC (0x40034028U)
53  #define REG_MCAN1_TOCV (0x4003402CU)
54  #define REG_MCAN1_ECR (0x40034040U)
55  #define REG_MCAN1_PSR (0x40034044U)
56  #define REG_MCAN1_TDCR (0x40034048U)
57  #define REG_MCAN1_IR (0x40034050U)
58  #define REG_MCAN1_IE (0x40034054U)
59  #define REG_MCAN1_ILS (0x40034058U)
60  #define REG_MCAN1_ILE (0x4003405CU)
61  #define REG_MCAN1_GFC (0x40034080U)
62  #define REG_MCAN1_SIDFC (0x40034084U)
63  #define REG_MCAN1_XIDFC (0x40034088U)
64  #define REG_MCAN1_XIDAM (0x40034090U)
65  #define REG_MCAN1_HPMS (0x40034094U)
66  #define REG_MCAN1_NDAT1 (0x40034098U)
67  #define REG_MCAN1_NDAT2 (0x4003409CU)
68  #define REG_MCAN1_RXF0C (0x400340A0U)
69  #define REG_MCAN1_RXF0S (0x400340A4U)
70  #define REG_MCAN1_RXF0A (0x400340A8U)
71  #define REG_MCAN1_RXBC (0x400340ACU)
72  #define REG_MCAN1_RXF1C (0x400340B0U)
73  #define REG_MCAN1_RXF1S (0x400340B4U)
74  #define REG_MCAN1_RXF1A (0x400340B8U)
75  #define REG_MCAN1_RXESC (0x400340BCU)
76  #define REG_MCAN1_TXBC (0x400340C0U)
77  #define REG_MCAN1_TXFQS (0x400340C4U)
78  #define REG_MCAN1_TXESC (0x400340C8U)
79  #define REG_MCAN1_TXBRP (0x400340CCU)
80  #define REG_MCAN1_TXBAR (0x400340D0U)
81  #define REG_MCAN1_TXBCR (0x400340D4U)
82  #define REG_MCAN1_TXBTO (0x400340D8U)
83  #define REG_MCAN1_TXBCF (0x400340DCU)
84  #define REG_MCAN1_TXBTIE (0x400340E0U)
85  #define REG_MCAN1_TXBCIE (0x400340E4U)
86  #define REG_MCAN1_TXEFC (0x400340F0U)
87  #define REG_MCAN1_TXEFS (0x400340F4U)
88  #define REG_MCAN1_TXEFA (0x400340F8U)
89 #else
90  #define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U)
91  #define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U)
92  #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U)
93  #define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU)
94  #define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU)
95  #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U)
96  #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U)
97  #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U)
98  #define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU)
99  #define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU)
100  #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U)
101  #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U)
102  #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U)
103  #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU)
104  #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U)
105  #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U)
106  #define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U)
107  #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U)
108  #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U)
109  #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U)
110  #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU)
111  #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U)
112  #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U)
113  #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U)
114  #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U)
115  #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U)
116  #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U)
117  #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU)
118  #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U)
119  #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U)
120  #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U)
121  #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU)
122  #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U)
123  #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U)
124  #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U)
125  #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU)
126  #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U)
127  #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U)
128  #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U)
129  #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU)
130  #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U)
131  #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U)
132  #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U)
133  #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU)
134  #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U)
135  #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U)
136  #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U)
137  #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U)
138  #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U)
139 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
140 
141 #endif /* _SAME70_MCAN1_INSTANCE_ */

inertial_sense_ros
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autogenerated on Sun Feb 28 2021 03:17:58