instance/sdramc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_SDRAMC_INSTANCE_
36 #define _SAME70_SDRAMC_INSTANCE_
37 
38 /* ========== Register definition for SDRAMC peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_SDRAMC_MR (0x40084000U)
41  #define REG_SDRAMC_TR (0x40084004U)
42  #define REG_SDRAMC_CR (0x40084008U)
43  #define REG_SDRAMC_LPR (0x40084010U)
44  #define REG_SDRAMC_IER (0x40084014U)
45  #define REG_SDRAMC_IDR (0x40084018U)
46  #define REG_SDRAMC_IMR (0x4008401CU)
47  #define REG_SDRAMC_ISR (0x40084020U)
48  #define REG_SDRAMC_MDR (0x40084024U)
49  #define REG_SDRAMC_CFR1 (0x40084028U)
50  #define REG_SDRAMC_OCMS (0x4008402CU)
51  #define REG_SDRAMC_OCMS_KEY1 (0x40084030U)
52  #define REG_SDRAMC_OCMS_KEY2 (0x40084034U)
53  #define REG_SDRAMC_VERSION (0x400840FCU)
54 #else
55  #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U)
56  #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U)
57  #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U)
58  #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U)
59  #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U)
60  #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U)
61  #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU)
62  #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U)
63  #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U)
64  #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U)
65  #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU)
66  #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U)
67  #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U)
68  #define REG_SDRAMC_VERSION (*(__I uint32_t*)0x400840FCU)
69 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
70 
71 #endif /* _SAME70_SDRAMC_INSTANCE_ */

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autogenerated on Sun Feb 28 2021 03:17:58