Go to the documentation of this file. 35 #ifndef _SAME70_PWM1_INSTANCE_ 36 #define _SAME70_PWM1_INSTANCE_ 39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 #define REG_PWM1_CLK (0x4005C000U) 41 #define REG_PWM1_ENA (0x4005C004U) 42 #define REG_PWM1_DIS (0x4005C008U) 43 #define REG_PWM1_SR (0x4005C00CU) 44 #define REG_PWM1_IER1 (0x4005C010U) 45 #define REG_PWM1_IDR1 (0x4005C014U) 46 #define REG_PWM1_IMR1 (0x4005C018U) 47 #define REG_PWM1_ISR1 (0x4005C01CU) 48 #define REG_PWM1_SCM (0x4005C020U) 49 #define REG_PWM1_DMAR (0x4005C024U) 50 #define REG_PWM1_SCUC (0x4005C028U) 51 #define REG_PWM1_SCUP (0x4005C02CU) 52 #define REG_PWM1_SCUPUPD (0x4005C030U) 53 #define REG_PWM1_IER2 (0x4005C034U) 54 #define REG_PWM1_IDR2 (0x4005C038U) 55 #define REG_PWM1_IMR2 (0x4005C03CU) 56 #define REG_PWM1_ISR2 (0x4005C040U) 57 #define REG_PWM1_OOV (0x4005C044U) 58 #define REG_PWM1_OS (0x4005C048U) 59 #define REG_PWM1_OSS (0x4005C04CU) 60 #define REG_PWM1_OSC (0x4005C050U) 61 #define REG_PWM1_OSSUPD (0x4005C054U) 62 #define REG_PWM1_OSCUPD (0x4005C058U) 63 #define REG_PWM1_FMR (0x4005C05CU) 64 #define REG_PWM1_FSR (0x4005C060U) 65 #define REG_PWM1_FCR (0x4005C064U) 66 #define REG_PWM1_FPV1 (0x4005C068U) 67 #define REG_PWM1_FPE (0x4005C06CU) 68 #define REG_PWM1_ELMR (0x4005C07CU) 69 #define REG_PWM1_SSPR (0x4005C0A0U) 70 #define REG_PWM1_SSPUP (0x4005C0A4U) 71 #define REG_PWM1_SMMR (0x4005C0B0U) 72 #define REG_PWM1_FPV2 (0x4005C0C0U) 73 #define REG_PWM1_WPCR (0x4005C0E4U) 74 #define REG_PWM1_WPSR (0x4005C0E8U) 75 #define REG_PWM1_VERSION (0x4005C0FCU) 76 #define REG_PWM1_CMPV0 (0x4005C130U) 77 #define REG_PWM1_CMPVUPD0 (0x4005C134U) 78 #define REG_PWM1_CMPM0 (0x4005C138U) 79 #define REG_PWM1_CMPMUPD0 (0x4005C13CU) 80 #define REG_PWM1_CMPV1 (0x4005C140U) 81 #define REG_PWM1_CMPVUPD1 (0x4005C144U) 82 #define REG_PWM1_CMPM1 (0x4005C148U) 83 #define REG_PWM1_CMPMUPD1 (0x4005C14CU) 84 #define REG_PWM1_CMPV2 (0x4005C150U) 85 #define REG_PWM1_CMPVUPD2 (0x4005C154U) 86 #define REG_PWM1_CMPM2 (0x4005C158U) 87 #define REG_PWM1_CMPMUPD2 (0x4005C15CU) 88 #define REG_PWM1_CMPV3 (0x4005C160U) 89 #define REG_PWM1_CMPVUPD3 (0x4005C164U) 90 #define REG_PWM1_CMPM3 (0x4005C168U) 91 #define REG_PWM1_CMPMUPD3 (0x4005C16CU) 92 #define REG_PWM1_CMPV4 (0x4005C170U) 93 #define REG_PWM1_CMPVUPD4 (0x4005C174U) 94 #define REG_PWM1_CMPM4 (0x4005C178U) 95 #define REG_PWM1_CMPMUPD4 (0x4005C17CU) 96 #define REG_PWM1_CMPV5 (0x4005C180U) 97 #define REG_PWM1_CMPVUPD5 (0x4005C184U) 98 #define REG_PWM1_CMPM5 (0x4005C188U) 99 #define REG_PWM1_CMPMUPD5 (0x4005C18CU) 100 #define REG_PWM1_CMPV6 (0x4005C190U) 101 #define REG_PWM1_CMPVUPD6 (0x4005C194U) 102 #define REG_PWM1_CMPM6 (0x4005C198U) 103 #define REG_PWM1_CMPMUPD6 (0x4005C19CU) 104 #define REG_PWM1_CMPV7 (0x4005C1A0U) 105 #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) 106 #define REG_PWM1_CMPM7 (0x4005C1A8U) 107 #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) 108 #define REG_PWM1_CMR0 (0x4005C200U) 109 #define REG_PWM1_CDTY0 (0x4005C204U) 110 #define REG_PWM1_CDTYUPD0 (0x4005C208U) 111 #define REG_PWM1_CPRD0 (0x4005C20CU) 112 #define REG_PWM1_CPRDUPD0 (0x4005C210U) 113 #define REG_PWM1_CCNT0 (0x4005C214U) 114 #define REG_PWM1_DT0 (0x4005C218U) 115 #define REG_PWM1_DTUPD0 (0x4005C21CU) 116 #define REG_PWM1_CMR1 (0x4005C220U) 117 #define REG_PWM1_CDTY1 (0x4005C224U) 118 #define REG_PWM1_CDTYUPD1 (0x4005C228U) 119 #define REG_PWM1_CPRD1 (0x4005C22CU) 120 #define REG_PWM1_CPRDUPD1 (0x4005C230U) 121 #define REG_PWM1_CCNT1 (0x4005C234U) 122 #define REG_PWM1_DT1 (0x4005C238U) 123 #define REG_PWM1_DTUPD1 (0x4005C23CU) 124 #define REG_PWM1_CMR2 (0x4005C240U) 125 #define REG_PWM1_CDTY2 (0x4005C244U) 126 #define REG_PWM1_CDTYUPD2 (0x4005C248U) 127 #define REG_PWM1_CPRD2 (0x4005C24CU) 128 #define REG_PWM1_CPRDUPD2 (0x4005C250U) 129 #define REG_PWM1_CCNT2 (0x4005C254U) 130 #define REG_PWM1_DT2 (0x4005C258U) 131 #define REG_PWM1_DTUPD2 (0x4005C25CU) 132 #define REG_PWM1_CMR3 (0x4005C260U) 133 #define REG_PWM1_CDTY3 (0x4005C264U) 134 #define REG_PWM1_CDTYUPD3 (0x4005C268U) 135 #define REG_PWM1_CPRD3 (0x4005C26CU) 136 #define REG_PWM1_CPRDUPD3 (0x4005C270U) 137 #define REG_PWM1_CCNT3 (0x4005C274U) 138 #define REG_PWM1_DT3 (0x4005C278U) 139 #define REG_PWM1_DTUPD3 (0x4005C27CU) 140 #define REG_PWM1_CMUPD0 (0x4005C400U) 141 #define REG_PWM1_CMUPD1 (0x4005C420U) 142 #define REG_PWM1_ETRG1 (0x4005C42CU) 143 #define REG_PWM1_LEBR1 (0x4005C430U) 144 #define REG_PWM1_CMUPD2 (0x4005C440U) 145 #define REG_PWM1_ETRG2 (0x4005C44CU) 146 #define REG_PWM1_LEBR2 (0x4005C450U) 147 #define REG_PWM1_CMUPD3 (0x4005C460U) 149 #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) 150 #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) 151 #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) 152 #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) 153 #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) 154 #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) 155 #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) 156 #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) 157 #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) 158 #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) 159 #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) 160 #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) 161 #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) 162 #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) 163 #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) 164 #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) 165 #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) 166 #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) 167 #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) 168 #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) 169 #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) 170 #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) 171 #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) 172 #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) 173 #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) 174 #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) 175 #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) 176 #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) 177 #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) 178 #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) 179 #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) 180 #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) 181 #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) 182 #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) 183 #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) 184 #define REG_PWM1_VERSION (*(__I uint32_t*)0x4005C0FCU) 185 #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) 186 #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) 187 #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) 188 #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) 189 #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) 190 #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) 191 #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) 192 #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) 193 #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) 194 #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) 195 #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) 196 #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) 197 #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) 198 #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) 199 #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) 200 #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) 201 #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) 202 #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) 203 #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) 204 #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) 205 #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) 206 #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) 207 #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) 208 #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) 209 #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) 210 #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) 211 #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) 212 #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) 213 #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) 214 #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) 215 #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) 216 #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) 217 #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) 218 #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) 219 #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) 220 #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) 221 #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) 222 #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) 223 #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) 224 #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) 225 #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) 226 #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) 227 #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) 228 #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) 229 #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) 230 #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) 231 #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) 232 #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) 233 #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) 234 #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) 235 #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) 236 #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) 237 #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) 238 #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) 239 #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) 240 #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) 241 #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) 242 #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) 243 #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) 244 #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) 245 #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) 246 #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) 247 #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) 248 #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) 249 #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) 250 #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) 251 #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) 252 #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) 253 #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) 254 #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) 255 #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) 256 #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U)