i2sc.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70_I2SC_COMPONENT_
#define _SAME70_I2SC_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __O  uint32_t I2SC_CR;      
  __IO uint32_t I2SC_MR;      
  __I  uint32_t I2SC_SR;      
  __O  uint32_t I2SC_SCR;     
  __O  uint32_t I2SC_SSR;     
  __O  uint32_t I2SC_IER;     
  __O  uint32_t I2SC_IDR;     
  __I  uint32_t I2SC_IMR;     
  __I  uint32_t I2SC_RHR;     
  __O  uint32_t I2SC_THR;     
  __I  uint32_t I2SC_VERSION; 
} I2sc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */
#define I2SC_CR_RXEN (0x1u << 0) 
#define I2SC_CR_RXDIS (0x1u << 1) 
#define I2SC_CR_CKEN (0x1u << 2) 
#define I2SC_CR_CKDIS (0x1u << 3) 
#define I2SC_CR_TXEN (0x1u << 4) 
#define I2SC_CR_TXDIS (0x1u << 5) 
#define I2SC_CR_SWRST (0x1u << 7) 
/* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */
#define I2SC_MR_MODE (0x1u << 0) 
#define   I2SC_MR_MODE_SLAVE (0x0u << 0) 
#define   I2SC_MR_MODE_MASTER (0x1u << 0) 
#define I2SC_MR_DATALENGTH_Pos 2
#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos) 
#define I2SC_MR_DATALENGTH(value) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)))
#define   I2SC_MR_DATALENGTH_32_BITS (0x0u << 2) 
#define   I2SC_MR_DATALENGTH_24_BITS (0x1u << 2) 
#define   I2SC_MR_DATALENGTH_20_BITS (0x2u << 2) 
#define   I2SC_MR_DATALENGTH_18_BITS (0x3u << 2) 
#define   I2SC_MR_DATALENGTH_16_BITS (0x4u << 2) 
#define   I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2) 
#define   I2SC_MR_DATALENGTH_8_BITS (0x6u << 2) 
#define   I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2) 
#define I2SC_MR_FORMAT_Pos 6
#define I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos) 
#define I2SC_MR_FORMAT(value) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos)))
#define   I2SC_MR_FORMAT_I2S (0x0u << 6) 
#define   I2SC_MR_FORMAT_LJ (0x1u << 6) 
#define I2SC_MR_RXMONO (0x1u << 8) 
#define I2SC_MR_RXDMA (0x1u << 9) 
#define I2SC_MR_RXLOOP (0x1u << 10) 
#define I2SC_MR_TXMONO (0x1u << 12) 
#define I2SC_MR_TXDMA (0x1u << 13) 
#define I2SC_MR_TXSAME (0x1u << 14) 
#define I2SC_MR_IMCKDIV_Pos 16
#define I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos) 
#define I2SC_MR_IMCKDIV(value) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)))
#define I2SC_MR_IMCKFS_Pos 24
#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos) 
#define I2SC_MR_IMCKFS(value) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)))
#define   I2SC_MR_IMCKFS_M2SF32 (0x0u << 24) 
#define   I2SC_MR_IMCKFS_M2SF64 (0x1u << 24) 
#define   I2SC_MR_IMCKFS_M2SF96 (0x2u << 24) 
#define   I2SC_MR_IMCKFS_M2SF128 (0x3u << 24) 
#define   I2SC_MR_IMCKFS_M2SF192 (0x5u << 24) 
#define   I2SC_MR_IMCKFS_M2SF256 (0x7u << 24) 
#define   I2SC_MR_IMCKFS_M2SF384 (0xBu << 24) 
#define   I2SC_MR_IMCKFS_M2SF512 (0xFu << 24) 
#define   I2SC_MR_IMCKFS_M2SF768 (0x17u << 24) 
#define   I2SC_MR_IMCKFS_M2SF1024 (0x1Fu << 24) 
#define   I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24) 
#define   I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24) 
#define I2SC_MR_IMCKMODE (0x1u << 30) 
#define I2SC_MR_IWS (0x1u << 31) 
/* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */
#define I2SC_SR_RXEN (0x1u << 0) 
#define I2SC_SR_RXRDY (0x1u << 1) 
#define I2SC_SR_RXOR (0x1u << 2) 
#define I2SC_SR_TXEN (0x1u << 4) 
#define I2SC_SR_TXRDY (0x1u << 5) 
#define I2SC_SR_TXUR (0x1u << 6) 
#define I2SC_SR_RXORCH_Pos 8
#define I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos) 
#define I2SC_SR_TXURCH_Pos 20
#define I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos) 
/* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */
#define I2SC_SCR_RXOR (0x1u << 2) 
#define I2SC_SCR_TXUR (0x1u << 6) 
#define I2SC_SCR_RXORCH_Pos 8
#define I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos) 
#define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)))
#define I2SC_SCR_TXURCH_Pos 20
#define I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos) 
#define I2SC_SCR_TXURCH(value) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)))
/* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */
#define I2SC_SSR_RXOR (0x1u << 2) 
#define I2SC_SSR_TXUR (0x1u << 6) 
#define I2SC_SSR_RXORCH_Pos 8
#define I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos) 
#define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)))
#define I2SC_SSR_TXURCH_Pos 20
#define I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos) 
#define I2SC_SSR_TXURCH(value) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)))
/* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */
#define I2SC_IER_RXRDY (0x1u << 1) 
#define I2SC_IER_RXOR (0x1u << 2) 
#define I2SC_IER_TXRDY (0x1u << 5) 
#define I2SC_IER_TXUR (0x1u << 6) 
/* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */
#define I2SC_IDR_RXRDY (0x1u << 1) 
#define I2SC_IDR_RXOR (0x1u << 2) 
#define I2SC_IDR_TXRDY (0x1u << 5) 
#define I2SC_IDR_TXUR (0x1u << 6) 
/* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */
#define I2SC_IMR_RXRDY (0x1u << 1) 
#define I2SC_IMR_RXOR (0x1u << 2) 
#define I2SC_IMR_TXRDY (0x1u << 5) 
#define I2SC_IMR_TXUR (0x1u << 6) 
/* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */
#define I2SC_RHR_RHR_Pos 0
#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos) 
/* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */
#define I2SC_THR_THR_Pos 0
#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos) 
#define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)))
/* -------- I2SC_VERSION : (I2SC Offset: 0x28) Version Register -------- */
#define I2SC_VERSION_VERSION_Pos 0
#define I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos) 
#define I2SC_VERSION_MFN_Pos 16
#define I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos) 


#endif /* _SAME70_I2SC_COMPONENT_ */