Go to the documentation of this file. 35 #ifndef _SAME70_SSC_INSTANCE_ 36 #define _SAME70_SSC_INSTANCE_ 39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 #define REG_SSC_CR (0x40004000U) 41 #define REG_SSC_CMR (0x40004004U) 42 #define REG_SSC_RCMR (0x40004010U) 43 #define REG_SSC_RFMR (0x40004014U) 44 #define REG_SSC_TCMR (0x40004018U) 45 #define REG_SSC_TFMR (0x4000401CU) 46 #define REG_SSC_RHR (0x40004020U) 47 #define REG_SSC_THR (0x40004024U) 48 #define REG_SSC_RSHR (0x40004030U) 49 #define REG_SSC_TSHR (0x40004034U) 50 #define REG_SSC_RC0R (0x40004038U) 51 #define REG_SSC_RC1R (0x4000403CU) 52 #define REG_SSC_SR (0x40004040U) 53 #define REG_SSC_IER (0x40004044U) 54 #define REG_SSC_IDR (0x40004048U) 55 #define REG_SSC_IMR (0x4000404CU) 56 #define REG_SSC_WPMR (0x400040E4U) 57 #define REG_SSC_WPSR (0x400040E8U) 58 #define REG_SSC_VERSION (0x400040FCU) 60 #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) 61 #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) 62 #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) 63 #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) 64 #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) 65 #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) 66 #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) 67 #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) 68 #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) 69 #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) 70 #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) 71 #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) 72 #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) 73 #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) 74 #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) 75 #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) 76 #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) 77 #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) 78 #define REG_SSC_VERSION (*(__I uint32_t*)0x400040FCU)