#include <pwm.h>

Public Attributes
PwmCh_num	PWM_CH_NUM [PWMCH_NUM_NUMBER]
	(Pwm Offset: 0x200) ch_num = 0 .. 3 More...

__IO uint32_t	PWM_CLK
	(Pwm Offset: 0x00) PWM Clock Register More...

PwmCmp	PWM_CMP [PWMCMP_NUMBER]
	(Pwm Offset: 0x130) 0 .. 7 More...

__O uint32_t	PWM_CMUPD0
	(Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) More...

__O uint32_t	PWM_CMUPD1
	(Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) More...

__O uint32_t	PWM_CMUPD2
	(Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) More...

__O uint32_t	PWM_CMUPD3
	(Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) More...

__O uint32_t	PWM_DIS
	(Pwm Offset: 0x08) PWM Disable Register More...

__O uint32_t	PWM_DMAR
	(Pwm Offset: 0x24) PWM DMA Register More...

__IO uint32_t	PWM_ELMR [8]
	(Pwm Offset: 0x7C) PWM Event Line 0 Mode Register More...

__O uint32_t	PWM_ENA
	(Pwm Offset: 0x04) PWM Enable Register More...

__IO uint32_t	PWM_ETRG1
	(Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) More...

__IO uint32_t	PWM_ETRG2
	(Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) More...

__O uint32_t	PWM_FCR
	(Pwm Offset: 0x64) PWM Fault Clear Register More...

__IO uint32_t	PWM_FMR
	(Pwm Offset: 0x5C) PWM Fault Mode Register More...

__IO uint32_t	PWM_FPE
	(Pwm Offset: 0x6C) PWM Fault Protection Enable Register More...

__IO uint32_t	PWM_FPV1
	(Pwm Offset: 0x68) PWM Fault Protection Value Register 1 More...

__IO uint32_t	PWM_FPV2
	(Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register More...

__I uint32_t	PWM_FSR
	(Pwm Offset: 0x60) PWM Fault Status Register More...

__O uint32_t	PWM_IDR1
	(Pwm Offset: 0x14) PWM Interrupt Disable Register 1 More...

__O uint32_t	PWM_IDR2
	(Pwm Offset: 0x38) PWM Interrupt Disable Register 2 More...

__O uint32_t	PWM_IER1
	(Pwm Offset: 0x10) PWM Interrupt Enable Register 1 More...

__O uint32_t	PWM_IER2
	(Pwm Offset: 0x34) PWM Interrupt Enable Register 2 More...

__I uint32_t	PWM_IMR1
	(Pwm Offset: 0x18) PWM Interrupt Mask Register 1 More...

__I uint32_t	PWM_IMR2
	(Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 More...

__I uint32_t	PWM_ISR1
	(Pwm Offset: 0x1C) PWM Interrupt Status Register 1 More...

__I uint32_t	PWM_ISR2
	(Pwm Offset: 0x40) PWM Interrupt Status Register 2 More...

__IO uint32_t	PWM_LEBR1
	(Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) More...

__IO uint32_t	PWM_LEBR2
	(Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) More...

__IO uint32_t	PWM_OOV
	(Pwm Offset: 0x44) PWM Output Override Value Register More...

__IO uint32_t	PWM_OS
	(Pwm Offset: 0x48) PWM Output Selection Register More...

__O uint32_t	PWM_OSC
	(Pwm Offset: 0x50) PWM Output Selection Clear Register More...

__O uint32_t	PWM_OSCUPD
	(Pwm Offset: 0x58) PWM Output Selection Clear Update Register More...

__O uint32_t	PWM_OSS
	(Pwm Offset: 0x4C) PWM Output Selection Set Register More...

__O uint32_t	PWM_OSSUPD
	(Pwm Offset: 0x54) PWM Output Selection Set Update Register More...

__IO uint32_t	PWM_SCM
	(Pwm Offset: 0x20) PWM Sync Channels Mode Register More...

__IO uint32_t	PWM_SCUC
	(Pwm Offset: 0x28) PWM Sync Channels Update Control Register More...

__IO uint32_t	PWM_SCUP
	(Pwm Offset: 0x2C) PWM Sync Channels Update Period Register More...

__O uint32_t	PWM_SCUPUPD
	(Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register More...

__IO uint32_t	PWM_SMMR
	(Pwm Offset: 0xB0) PWM Stepper Motor Mode Register More...

__I uint32_t	PWM_SR
	(Pwm Offset: 0x0C) PWM Status Register More...

__IO uint32_t	PWM_SSPR
	(Pwm Offset: 0xA0) PWM Spread Spectrum Register More...

__O uint32_t	PWM_SSPUP
	(Pwm Offset: 0xA4) PWM Spread Spectrum Update Register More...

__I uint32_t	PWM_VERSION
	(Pwm Offset: 0xFC) Version Register More...

__O uint32_t	PWM_WPCR
	(Pwm Offset: 0xE4) PWM Write Protection Control Register More...

__I uint32_t	PWM_WPSR
	(Pwm Offset: 0xE8) PWM Write Protection Status Register More...

__I uint32_t	Reserved1 [3]

__I uint32_t	Reserved10 [7]

__I uint32_t	Reserved11 [2]

__I uint32_t	Reserved12 [3]

__I uint32_t	Reserved13 [2]

__I uint32_t	Reserved14 [3]

__I uint32_t	Reserved2 [1]

__I uint32_t	Reserved3 [2]

__I uint32_t	Reserved4 [3]

__I uint32_t	Reserved5 [8]

__I uint32_t	Reserved6 [4]

__I uint32_t	Reserved7 [12]

__I uint32_t	Reserved8 [20]

__I uint32_t	Reserved9 [96]

Detailed Description

Definition at line 66 of file pwm.h.

Member Data Documentation

◆ PWM_CH_NUM

PwmCh_num Pwm::PWM_CH_NUM[PWMCH_NUM_NUMBER]

(Pwm Offset: 0x200) ch_num = 0 .. 3

Definition at line 112 of file pwm.h.

◆ PWM_CLK

__IO uint32_t Pwm::PWM_CLK

(Pwm Offset: 0x00) PWM Clock Register

Definition at line 67 of file pwm.h.

◆ PWM_CMP

PwmCmp Pwm::PWM_CMP[PWMCMP_NUMBER]

(Pwm Offset: 0x130) 0 .. 7

Definition at line 110 of file pwm.h.

◆ PWM_CMUPD0

__O uint32_t Pwm::PWM_CMUPD0

(Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0)

Definition at line 114 of file pwm.h.

◆ PWM_CMUPD1

__O uint32_t Pwm::PWM_CMUPD1

(Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1)

Definition at line 116 of file pwm.h.

◆ PWM_CMUPD2

__O uint32_t Pwm::PWM_CMUPD2

(Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2)

Definition at line 121 of file pwm.h.

◆ PWM_CMUPD3

__O uint32_t Pwm::PWM_CMUPD3

(Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3)

Definition at line 126 of file pwm.h.

◆ PWM_DIS

__O uint32_t Pwm::PWM_DIS

(Pwm Offset: 0x08) PWM Disable Register

Definition at line 69 of file pwm.h.

◆ PWM_DMAR

__O uint32_t Pwm::PWM_DMAR

(Pwm Offset: 0x24) PWM DMA Register

Definition at line 76 of file pwm.h.

◆ PWM_ELMR

__IO uint32_t Pwm::PWM_ELMR[8]

(Pwm Offset: 0x7C) PWM Event Line 0 Mode Register

Definition at line 96 of file pwm.h.

◆ PWM_ENA

__O uint32_t Pwm::PWM_ENA

(Pwm Offset: 0x04) PWM Enable Register

Definition at line 68 of file pwm.h.

◆ PWM_ETRG1

__IO uint32_t Pwm::PWM_ETRG1

(Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1)

Definition at line 118 of file pwm.h.

◆ PWM_ETRG2

__IO uint32_t Pwm::PWM_ETRG2

(Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2)

Definition at line 123 of file pwm.h.

◆ PWM_FCR

__O uint32_t Pwm::PWM_FCR

(Pwm Offset: 0x64) PWM Fault Clear Register

Definition at line 92 of file pwm.h.

◆ PWM_FMR

__IO uint32_t Pwm::PWM_FMR

(Pwm Offset: 0x5C) PWM Fault Mode Register

Definition at line 90 of file pwm.h.

◆ PWM_FPE

__IO uint32_t Pwm::PWM_FPE

(Pwm Offset: 0x6C) PWM Fault Protection Enable Register

Definition at line 94 of file pwm.h.

◆ PWM_FPV1

__IO uint32_t Pwm::PWM_FPV1

(Pwm Offset: 0x68) PWM Fault Protection Value Register 1

Definition at line 93 of file pwm.h.

◆ PWM_FPV2

__IO uint32_t Pwm::PWM_FPV2

(Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register

Definition at line 103 of file pwm.h.

◆ PWM_FSR

__I uint32_t Pwm::PWM_FSR

(Pwm Offset: 0x60) PWM Fault Status Register

Definition at line 91 of file pwm.h.

◆ PWM_IDR1

__O uint32_t Pwm::PWM_IDR1

(Pwm Offset: 0x14) PWM Interrupt Disable Register 1

Definition at line 72 of file pwm.h.

◆ PWM_IDR2

__O uint32_t Pwm::PWM_IDR2

(Pwm Offset: 0x38) PWM Interrupt Disable Register 2

Definition at line 81 of file pwm.h.

◆ PWM_IER1

__O uint32_t Pwm::PWM_IER1

(Pwm Offset: 0x10) PWM Interrupt Enable Register 1

Definition at line 71 of file pwm.h.

◆ PWM_IER2

__O uint32_t Pwm::PWM_IER2

(Pwm Offset: 0x34) PWM Interrupt Enable Register 2

Definition at line 80 of file pwm.h.

◆ PWM_IMR1

__I uint32_t Pwm::PWM_IMR1

(Pwm Offset: 0x18) PWM Interrupt Mask Register 1

Definition at line 73 of file pwm.h.

◆ PWM_IMR2

__I uint32_t Pwm::PWM_IMR2

(Pwm Offset: 0x3C) PWM Interrupt Mask Register 2

Definition at line 82 of file pwm.h.

◆ PWM_ISR1

__I uint32_t Pwm::PWM_ISR1

(Pwm Offset: 0x1C) PWM Interrupt Status Register 1

Definition at line 74 of file pwm.h.

◆ PWM_ISR2

__I uint32_t Pwm::PWM_ISR2

(Pwm Offset: 0x40) PWM Interrupt Status Register 2

Definition at line 83 of file pwm.h.

◆ PWM_LEBR1

__IO uint32_t Pwm::PWM_LEBR1

(Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1)

Definition at line 119 of file pwm.h.

◆ PWM_LEBR2

__IO uint32_t Pwm::PWM_LEBR2

(Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2)

Definition at line 124 of file pwm.h.

◆ PWM_OOV

__IO uint32_t Pwm::PWM_OOV

(Pwm Offset: 0x44) PWM Output Override Value Register

Definition at line 84 of file pwm.h.

◆ PWM_OS

__IO uint32_t Pwm::PWM_OS

(Pwm Offset: 0x48) PWM Output Selection Register

Definition at line 85 of file pwm.h.

◆ PWM_OSC

__O uint32_t Pwm::PWM_OSC

(Pwm Offset: 0x50) PWM Output Selection Clear Register

Definition at line 87 of file pwm.h.

◆ PWM_OSCUPD

__O uint32_t Pwm::PWM_OSCUPD

(Pwm Offset: 0x58) PWM Output Selection Clear Update Register

Definition at line 89 of file pwm.h.

◆ PWM_OSS

__O uint32_t Pwm::PWM_OSS

(Pwm Offset: 0x4C) PWM Output Selection Set Register

Definition at line 86 of file pwm.h.

◆ PWM_OSSUPD

__O uint32_t Pwm::PWM_OSSUPD

(Pwm Offset: 0x54) PWM Output Selection Set Update Register

Definition at line 88 of file pwm.h.

◆ PWM_SCM

__IO uint32_t Pwm::PWM_SCM

(Pwm Offset: 0x20) PWM Sync Channels Mode Register

Definition at line 75 of file pwm.h.

◆ PWM_SCUC

__IO uint32_t Pwm::PWM_SCUC

(Pwm Offset: 0x28) PWM Sync Channels Update Control Register

Definition at line 77 of file pwm.h.

◆ PWM_SCUP

__IO uint32_t Pwm::PWM_SCUP

(Pwm Offset: 0x2C) PWM Sync Channels Update Period Register

Definition at line 78 of file pwm.h.

◆ PWM_SCUPUPD

__O uint32_t Pwm::PWM_SCUPUPD

(Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register

Definition at line 79 of file pwm.h.

◆ PWM_SMMR

__IO uint32_t Pwm::PWM_SMMR

(Pwm Offset: 0xB0) PWM Stepper Motor Mode Register

Definition at line 101 of file pwm.h.

◆ PWM_SR

__I uint32_t Pwm::PWM_SR

(Pwm Offset: 0x0C) PWM Status Register

Definition at line 70 of file pwm.h.

◆ PWM_SSPR

__IO uint32_t Pwm::PWM_SSPR

(Pwm Offset: 0xA0) PWM Spread Spectrum Register

Definition at line 98 of file pwm.h.

◆ PWM_SSPUP

__O uint32_t Pwm::PWM_SSPUP

(Pwm Offset: 0xA4) PWM Spread Spectrum Update Register

Definition at line 99 of file pwm.h.

◆ PWM_VERSION

__I uint32_t Pwm::PWM_VERSION

(Pwm Offset: 0xFC) Version Register

Definition at line 108 of file pwm.h.

◆ PWM_WPCR

__O uint32_t Pwm::PWM_WPCR

(Pwm Offset: 0xE4) PWM Write Protection Control Register

Definition at line 105 of file pwm.h.

◆ PWM_WPSR

__I uint32_t Pwm::PWM_WPSR

(Pwm Offset: 0xE8) PWM Write Protection Status Register

Definition at line 106 of file pwm.h.

◆ Reserved1

__I uint32_t Pwm::Reserved1[3]

Definition at line 95 of file pwm.h.

◆ Reserved10

__I uint32_t Pwm::Reserved10[7]

Definition at line 115 of file pwm.h.

◆ Reserved11

__I uint32_t Pwm::Reserved11[2]

Definition at line 117 of file pwm.h.

◆ Reserved12

__I uint32_t Pwm::Reserved12[3]

Definition at line 120 of file pwm.h.

◆ Reserved13

__I uint32_t Pwm::Reserved13[2]

Definition at line 122 of file pwm.h.

◆ Reserved14

__I uint32_t Pwm::Reserved14[3]

Definition at line 125 of file pwm.h.

◆ Reserved2

__I uint32_t Pwm::Reserved2[1]

Definition at line 97 of file pwm.h.

◆ Reserved3

__I uint32_t Pwm::Reserved3[2]

Definition at line 100 of file pwm.h.

◆ Reserved4

__I uint32_t Pwm::Reserved4[3]

Definition at line 102 of file pwm.h.

◆ Reserved5

__I uint32_t Pwm::Reserved5[8]

Definition at line 104 of file pwm.h.

◆ Reserved6

__I uint32_t Pwm::Reserved6[4]

Definition at line 107 of file pwm.h.

◆ Reserved7

__I uint32_t Pwm::Reserved7[12]

Definition at line 109 of file pwm.h.

◆ Reserved8

__I uint32_t Pwm::Reserved8[20]

Definition at line 111 of file pwm.h.

◆ Reserved9

__I uint32_t Pwm::Reserved9[96]

Definition at line 113 of file pwm.h.

The documentation for this struct was generated from the following file:

pwm.h

Public Attributes