component/matrix.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70_MATRIX_COMPONENT_
#define _SAME70_MATRIX_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __IO uint32_t MATRIX_PRAS; 
  __IO uint32_t MATRIX_PRBS; 
} MatrixPr;
#define MATRIXPR_NUMBER 9
typedef struct {
  __IO uint32_t MATRIX_MCFG0;               
  __IO uint32_t MATRIX_MCFG1;               
  __IO uint32_t MATRIX_MCFG2;               
  __IO uint32_t MATRIX_MCFG3;               
  __IO uint32_t MATRIX_MCFG4;               
  __IO uint32_t MATRIX_MCFG5;               
  __IO uint32_t MATRIX_MCFG6;               
  __I  uint32_t Reserved1[1];
  __IO uint32_t MATRIX_MCFG8;               
  __IO uint32_t MATRIX_MCFG9;               
  __IO uint32_t MATRIX_MCFG10;              
  __IO uint32_t MATRIX_MCFG11;              
  __IO uint32_t MATRIX_MCFG12;              
  __I  uint32_t Reserved2[3];
  __IO uint32_t MATRIX_SCFG[9];             
  __I  uint32_t Reserved3[7];
       MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; 
  __I  uint32_t Reserved4[14];
  __IO uint32_t MATRIX_MRCR;                
  __I  uint32_t Reserved5[3];
  __IO uint32_t CCFG_CAN0;                  
  __IO uint32_t CCFG_SYSIO;                 
  __IO uint32_t CCFG_PCCR;                  
  __IO uint32_t CCFG_DYNCFG;                
  __I  uint32_t Reserved6[1];
  __IO uint32_t CCFG_SMCNFCS;               
  __I  uint32_t Reserved7[47];
  __IO uint32_t MATRIX_WPMR;                
  __I  uint32_t MATRIX_WPSR;                
  __I  uint32_t Reserved8[4];
  __I  uint32_t MATRIX_VERSION;             
} Matrix;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
#define MATRIX_MCFG0_ULBT_Pos 0
#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) 
#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
#define   MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
#define MATRIX_MCFG1_ULBT_Pos 0
#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) 
#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
#define   MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
#define MATRIX_MCFG2_ULBT_Pos 0
#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) 
#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
#define   MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
#define MATRIX_MCFG3_ULBT_Pos 0
#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) 
#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
#define   MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
#define MATRIX_MCFG4_ULBT_Pos 0
#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) 
#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
#define   MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
#define MATRIX_MCFG5_ULBT_Pos 0
#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) 
#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
#define   MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
#define MATRIX_MCFG6_ULBT_Pos 0
#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) 
#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
#define   MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
#define MATRIX_MCFG8_ULBT_Pos 0
#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) 
#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
#define   MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */
#define MATRIX_MCFG9_ULBT_Pos 0
#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos) 
#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos)))
#define   MATRIX_MCFG9_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG9_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG9_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG9_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG9_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG9_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG9_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG9_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG10 : (MATRIX Offset: 0x0028) Master Configuration Register 10 -------- */
#define MATRIX_MCFG10_ULBT_Pos 0
#define MATRIX_MCFG10_ULBT_Msk (0x7u << MATRIX_MCFG10_ULBT_Pos) 
#define MATRIX_MCFG10_ULBT(value) ((MATRIX_MCFG10_ULBT_Msk & ((value) << MATRIX_MCFG10_ULBT_Pos)))
#define   MATRIX_MCFG10_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG10_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG10_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG10_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG10_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG10_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG10_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG10_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG11 : (MATRIX Offset: 0x002C) Master Configuration Register 11 -------- */
#define MATRIX_MCFG11_ULBT_Pos 0
#define MATRIX_MCFG11_ULBT_Msk (0x7u << MATRIX_MCFG11_ULBT_Pos) 
#define MATRIX_MCFG11_ULBT(value) ((MATRIX_MCFG11_ULBT_Msk & ((value) << MATRIX_MCFG11_ULBT_Pos)))
#define   MATRIX_MCFG11_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG11_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG11_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG11_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG11_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG11_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG11_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG11_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) 
#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) 
#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
#define   MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) 
#define   MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) 
#define   MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) 
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) 
#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */
#define MATRIX_PRAS_M0PR_Pos 0
#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) 
#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
#define MATRIX_PRAS_M1PR_Pos 4
#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) 
#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
#define MATRIX_PRAS_M2PR_Pos 8
#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) 
#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
#define MATRIX_PRAS_M3PR_Pos 12
#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) 
#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
#define MATRIX_PRAS_M4PR_Pos 16
#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) 
#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
#define MATRIX_PRAS_M5PR_Pos 20
#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) 
#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
#define MATRIX_PRAS_M6PR_Pos 24
#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) 
#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */
#define MATRIX_PRBS_M8PR_Pos 0
#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) 
#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
#define MATRIX_PRBS_M9PR_Pos 4
#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) 
#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
#define MATRIX_PRBS_M10PR_Pos 8
#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) 
#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
#define MATRIX_PRBS_M11PR_Pos 12
#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) 
#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
#define MATRIX_PRBS_M12PR_Pos 16
#define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos) 
#define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)))
/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
#define MATRIX_MRCR_RCB0 (0x1u << 0) 
#define MATRIX_MRCR_RCB1 (0x1u << 1) 
#define MATRIX_MRCR_RCB2 (0x1u << 2) 
#define MATRIX_MRCR_RCB3 (0x1u << 3) 
#define MATRIX_MRCR_RCB4 (0x1u << 4) 
#define MATRIX_MRCR_RCB5 (0x1u << 5) 
#define MATRIX_MRCR_RCB6 (0x1u << 6) 
#define MATRIX_MRCR_RCB8 (0x1u << 8) 
#define MATRIX_MRCR_RCB9 (0x1u << 9) 
#define MATRIX_MRCR_RCB10 (0x1u << 10) 
#define MATRIX_MRCR_RCB11 (0x1u << 11) 
#define MATRIX_MRCR_RCB12 (0x1u << 12) 
/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */
#define CCFG_CAN0_CAN0DMABA_Pos 16
#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) 
#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)))
/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */
#define CCFG_SYSIO_SYSIO4 (0x1u << 4) 
#define CCFG_SYSIO_SYSIO5 (0x1u << 5) 
#define CCFG_SYSIO_SYSIO6 (0x1u << 6) 
#define CCFG_SYSIO_SYSIO7 (0x1u << 7) 
#define CCFG_SYSIO_SYSIO12 (0x1u << 12) 
#define CCFG_SYSIO_CAN1DMABA_Pos 16
#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) 
#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)))
/* -------- CCFG_PCCR : (MATRIX Offset: 0x0118) Peripheral Clock Configuration Register -------- */
#define CCFG_PCCR_TC0CC (0x1u << 20) 
#define CCFG_PCCR_I2SC0CC (0x1u << 21) 
#define CCFG_PCCR_I2SC1CC (0x1u << 22) 
/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */
#define CCFG_DYNCKG_MATCKG  (0x1u << 0) 
#define CCFG_DYNCKG_BRIDCKG (0x1u << 1) 
#define CCFG_DYNCKG_EFCCKG  (0x1u << 2) 
/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) 
#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) 
#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) 
#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) 
#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) 
/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
#define MATRIX_WPMR_WPEN (0x1u << 0) 
#define MATRIX_WPMR_WPKEY_Pos 8
#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) 
#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
#define   MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) 
/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
#define MATRIX_WPSR_WPVS (0x1u << 0) 
#define MATRIX_WPSR_WPVSRC_Pos 8
#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) 
/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */
#define MATRIX_VERSION_VERSION_Pos 0
#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) 
#define MATRIX_VERSION_MFN_Pos 16
#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) 


#endif /* _SAME70_MATRIX_COMPONENT_ */