Go to the documentation of this file. 35 #ifndef _SAME70_TWIHS1_INSTANCE_ 36 #define _SAME70_TWIHS1_INSTANCE_ 39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 #define REG_TWIHS1_CR (0x4001C000U) 41 #define REG_TWIHS1_MMR (0x4001C004U) 42 #define REG_TWIHS1_SMR (0x4001C008U) 43 #define REG_TWIHS1_IADR (0x4001C00CU) 44 #define REG_TWIHS1_CWGR (0x4001C010U) 45 #define REG_TWIHS1_SR (0x4001C020U) 46 #define REG_TWIHS1_IER (0x4001C024U) 47 #define REG_TWIHS1_IDR (0x4001C028U) 48 #define REG_TWIHS1_IMR (0x4001C02CU) 49 #define REG_TWIHS1_RHR (0x4001C030U) 50 #define REG_TWIHS1_THR (0x4001C034U) 51 #define REG_TWIHS1_SMBTR (0x4001C038U) 52 #define REG_TWIHS1_FILTR (0x4001C044U) 53 #define REG_TWIHS1_SWMR (0x4001C04CU) 54 #define REG_TWIHS1_DR (0x4001C0D0U) 55 #define REG_TWIHS1_WPMR (0x4001C0E4U) 56 #define REG_TWIHS1_WPSR (0x4001C0E8U) 57 #define REG_TWIHS1_VER (0x4001C0FCU) 59 #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) 60 #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) 61 #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) 62 #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) 63 #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) 64 #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) 65 #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) 66 #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) 67 #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) 68 #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) 69 #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) 70 #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) 71 #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) 72 #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) 73 #define REG_TWIHS1_DR (*(__I uint32_t*)0x4001C0D0U) 74 #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) 75 #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) 76 #define REG_TWIHS1_VER (*(__I uint32_t*)0x4001C0FCU)