Aes hardware registers. More...
#include <aes.h>
Public Attributes | |
| __IO uint32_t | AES_AADLENR |
| (Aes Offset: 0x70) Additional Authenticated Data Length Register More... | |
| __IO uint32_t | AES_CLENR |
| (Aes Offset: 0x74) Plaintext/Ciphertext Length Register More... | |
| __O uint32_t | AES_CR |
| (Aes Offset: 0x00) Control Register More... | |
| __I uint32_t | AES_CTRR |
| (Aes Offset: 0x98) GCM Encryption Counter Value Register More... | |
| __IO uint32_t | AES_GCMHR [4] |
| (Aes Offset: 0x9C) GCM H Word Register More... | |
| __IO uint32_t | AES_GHASHR [4] |
| (Aes Offset: 0x78) GCM Intermediate Hash Word Register More... | |
| __O uint32_t | AES_IDATAR [4] |
| (Aes Offset: 0x40) Input Data Register More... | |
| __O uint32_t | AES_IDR |
| (Aes Offset: 0x14) Interrupt Disable Register More... | |
| __O uint32_t | AES_IER |
| (Aes Offset: 0x10) Interrupt Enable Register More... | |
| __I uint32_t | AES_IMR |
| (Aes Offset: 0x18) Interrupt Mask Register More... | |
| __I uint32_t | AES_ISR |
| (Aes Offset: 0x1C) Interrupt Status Register More... | |
| __O uint32_t | AES_IVR [4] |
| (Aes Offset: 0x60) Initialization Vector Register More... | |
| __O uint32_t | AES_KEYWR [8] |
| (Aes Offset: 0x20) Key Word Register More... | |
| __IO uint32_t | AES_MR |
| (Aes Offset: 0x04) Mode Register More... | |
| __I uint32_t | AES_ODATAR [4] |
| (Aes Offset: 0x50) Output Data Register More... | |
| __I uint32_t | AES_TAGR [4] |
| (Aes Offset: 0x88) GCM Authentication Tag Word Register More... | |
| __I uint32_t | AES_VERSION |
| (Aes Offset: 0xFC) Version Register More... | |
| __I uint32_t | Reserved1 [2] |
| __I uint32_t | Reserved2 [20] |
Aes hardware registers.
Definition at line 46 of file component/aes.h.
| __IO uint32_t Aes::AES_AADLENR |
(Aes Offset: 0x70) Additional Authenticated Data Length Register
Definition at line 58 of file component/aes.h.
| __IO uint32_t Aes::AES_CLENR |
(Aes Offset: 0x74) Plaintext/Ciphertext Length Register
Definition at line 59 of file component/aes.h.
| __O uint32_t Aes::AES_CR |
(Aes Offset: 0x00) Control Register
Definition at line 47 of file component/aes.h.
| __I uint32_t Aes::AES_CTRR |
(Aes Offset: 0x98) GCM Encryption Counter Value Register
Definition at line 62 of file component/aes.h.
| __IO uint32_t Aes::AES_GCMHR[4] |
(Aes Offset: 0x9C) GCM H Word Register
Definition at line 63 of file component/aes.h.
| __IO uint32_t Aes::AES_GHASHR[4] |
(Aes Offset: 0x78) GCM Intermediate Hash Word Register
Definition at line 60 of file component/aes.h.
| __O uint32_t Aes::AES_IDATAR[4] |
(Aes Offset: 0x40) Input Data Register
Definition at line 55 of file component/aes.h.
| __O uint32_t Aes::AES_IDR |
(Aes Offset: 0x14) Interrupt Disable Register
Definition at line 51 of file component/aes.h.
| __O uint32_t Aes::AES_IER |
(Aes Offset: 0x10) Interrupt Enable Register
Definition at line 50 of file component/aes.h.
| __I uint32_t Aes::AES_IMR |
(Aes Offset: 0x18) Interrupt Mask Register
Definition at line 52 of file component/aes.h.
| __I uint32_t Aes::AES_ISR |
(Aes Offset: 0x1C) Interrupt Status Register
Definition at line 53 of file component/aes.h.
| __O uint32_t Aes::AES_IVR[4] |
(Aes Offset: 0x60) Initialization Vector Register
Definition at line 57 of file component/aes.h.
| __O uint32_t Aes::AES_KEYWR[8] |
(Aes Offset: 0x20) Key Word Register
Definition at line 54 of file component/aes.h.
| __IO uint32_t Aes::AES_MR |
(Aes Offset: 0x04) Mode Register
Definition at line 48 of file component/aes.h.
| __I uint32_t Aes::AES_ODATAR[4] |
(Aes Offset: 0x50) Output Data Register
Definition at line 56 of file component/aes.h.
| __I uint32_t Aes::AES_TAGR[4] |
(Aes Offset: 0x88) GCM Authentication Tag Word Register
Definition at line 61 of file component/aes.h.
| __I uint32_t Aes::AES_VERSION |
(Aes Offset: 0xFC) Version Register
Definition at line 65 of file component/aes.h.
| __I uint32_t Aes::Reserved1[2] |
Definition at line 49 of file component/aes.h.
| __I uint32_t Aes::Reserved2[20] |
Definition at line 64 of file component/aes.h.