core_cm7.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_CM7_H_GENERIC
43 #define __CORE_CM7_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
49 #include "board_opt.h"
50 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
72 /* CMSIS CM7 definitions */
73 #define __CM7_CMSIS_VERSION_MAIN (0x04)
74 #define __CM7_CMSIS_VERSION_SUB (0x00)
75 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
76  __CM7_CMSIS_VERSION_SUB )
78 #define __CORTEX_M (0x07)
81 #if defined ( __CC_ARM )
82  #define __ASM __asm
83  #define __INLINE __inline
84  #define __STATIC_INLINE static __inline
85 
86 #elif defined ( __GNUC__ )
87  #define __ASM __asm
88  #define __INLINE inline
89  #define __STATIC_INLINE static inline
90 
91 #elif defined ( __ICCARM__ )
92  #define __ASM __asm
93  #define __INLINE inline
94  #define __STATIC_INLINE static inline
95 
96 #elif defined ( __TMS470__ )
97  #define __ASM __asm
98  #define __STATIC_INLINE static inline
99 
100 #elif defined ( __TASKING__ )
101  #define __ASM __asm
102  #define __INLINE inline
103  #define __STATIC_INLINE static inline
104 
105 #elif defined ( __CSMC__ )
106  #define __packed
107  #define __ASM _asm
108  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
109  #define __STATIC_INLINE static inline
110 
111 #endif
112 
116 #if defined ( __CC_ARM )
117  #if defined __TARGET_FPU_VFP
118  #if (__FPU_PRESENT == 1)
119  #define __FPU_USED 1
120  #else
121  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
122  #define __FPU_USED 0
123  #endif
124  #else
125  #define __FPU_USED 0
126  #endif
127 
128 #elif defined ( __GNUC__ )
129  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
130  #if (__FPU_PRESENT == 1)
131  #define __FPU_USED 1
132  #else
133  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #define __FPU_USED 0
135  #endif
136  #else
137  #define __FPU_USED 0
138  #endif
139 
140 #elif defined ( __ICCARM__ )
141  #if defined __ARMVFP__
142  #if (__FPU_PRESENT == 1)
143  #define __FPU_USED 1
144  #else
145  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
146  #define __FPU_USED 0
147  #endif
148  #else
149  #define __FPU_USED 0
150  #endif
151 
152 #elif defined ( __TMS470__ )
153  #if defined __TI_VFP_SUPPORT__
154  #if (__FPU_PRESENT == 1)
155  #define __FPU_USED 1
156  #else
157  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
158  #define __FPU_USED 0
159  #endif
160  #else
161  #define __FPU_USED 0
162  #endif
163 
164 #elif defined ( __TASKING__ )
165  #if defined __FPU_VFP__
166  #if (__FPU_PRESENT == 1)
167  #define __FPU_USED 1
168  #else
169  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
170  #define __FPU_USED 0
171  #endif
172  #else
173  #define __FPU_USED 0
174  #endif
175 
176 #elif defined ( __CSMC__ ) /* Cosmic */
177  #if ( __CSMC__ & 0x400) // FPU present for parser
178  #if (__FPU_PRESENT == 1)
179  #define __FPU_USED 1
180  #else
181  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
182  #define __FPU_USED 0
183  #endif
184  #else
185  #define __FPU_USED 0
186  #endif
187 #endif
188 
189 #include <stdint.h> /* standard types definitions */
190 #include <core_cmInstr.h> /* Core Instruction Access */
191 #include <core_cmFunc.h> /* Core Function Access */
192 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
193 
194 #ifdef __cplusplus
195 }
196 #endif
197 
198 #endif /* __CORE_CM7_H_GENERIC */
199 
200 #ifndef __CMSIS_GENERIC
201 
202 #ifndef __CORE_CM7_H_DEPENDANT
203 #define __CORE_CM7_H_DEPENDANT
204 
205 #ifdef __cplusplus
206  extern "C" {
207 #endif
208 
209 /* check device defines and use defaults */
210 #if defined __CHECK_DEVICE_DEFINES
211  #ifndef __CM7_REV
212  #define __CM7_REV 0x0000
213  #warning "__CM7_REV not defined in device header file; using default!"
214  #endif
215 
216  #ifndef __FPU_PRESENT
217  #define __FPU_PRESENT 0
218  #warning "__FPU_PRESENT not defined in device header file; using default!"
219  #endif
220 
221  #ifndef __MPU_PRESENT
222  #define __MPU_PRESENT 0
223  #warning "__MPU_PRESENT not defined in device header file; using default!"
224  #endif
225 
226  #ifndef __ICACHE_PRESENT
227  #define __ICACHE_PRESENT 0
228  #warning "__ICACHE_PRESENT not defined in device header file; using default!"
229  #endif
230 
231  #ifndef __DCACHE_PRESENT
232  #define __DCACHE_PRESENT 0
233  #warning "__DCACHE_PRESENT not defined in device header file; using default!"
234  #endif
235 
236  #ifndef __DTCM_PRESENT
237  #define __DTCM_PRESENT 0
238  #warning "__DTCM_PRESENT not defined in device header file; using default!"
239  #endif
240 
241  #ifndef __NVIC_PRIO_BITS
242  #define __NVIC_PRIO_BITS 3
243  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
244  #endif
245 
246  #ifndef __Vendor_SysTickConfig
247  #define __Vendor_SysTickConfig 0
248  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
249  #endif
250 #endif
251 
252 /* IO definitions (access restrictions to peripheral registers) */
260 #ifdef __cplusplus
261  #define __I volatile
262 #else
263  #define __I volatile const
264 #endif
265 #define __O volatile
266 #define __IO volatile
268 
272 /*******************************************************************************
273  * Register Abstraction
274  Core Register contain:
275  - Core Register
276  - Core NVIC Register
277  - Core SCB Register
278  - Core SysTick Register
279  - Core Debug Register
280  - Core MPU Register
281  - Core FPU Register
282  ******************************************************************************/
283 
295 typedef union
296 {
297  struct
298  {
299 #if (__CORTEX_M != 0x07)
300  uint32_t _reserved0:27;
301 #else
302  uint32_t _reserved0:16;
303  uint32_t GE:4;
304  uint32_t _reserved1:7;
305 #endif
306  uint32_t Q:1;
307  uint32_t V:1;
308  uint32_t C:1;
309  uint32_t Z:1;
310  uint32_t N:1;
311  } b;
312  uint32_t w;
313 } APSR_Type;
314 
315 
318 typedef union
319 {
320  struct
321  {
322  uint32_t ISR:9;
323  uint32_t _reserved0:23;
324  } b;
325  uint32_t w;
326 } IPSR_Type;
327 
328 
331 typedef union
332 {
333  struct
334  {
335  uint32_t ISR:9;
336 #if (__CORTEX_M != 0x07)
337  uint32_t _reserved0:15;
338 #else
339  uint32_t _reserved0:7;
340  uint32_t GE:4;
341  uint32_t _reserved1:4;
342 #endif
343  uint32_t T:1;
344  uint32_t IT:2;
345  uint32_t Q:1;
346  uint32_t V:1;
347  uint32_t C:1;
348  uint32_t Z:1;
349  uint32_t N:1;
350  } b;
351  uint32_t w;
352 } xPSR_Type;
353 
354 
357 typedef union
358 {
359  struct
360  {
361  uint32_t nPRIV:1;
362  uint32_t SPSEL:1;
363  uint32_t FPCA:1;
364  uint32_t _reserved0:29;
365  } b;
366  uint32_t w;
367 } CONTROL_Type;
368 
380 typedef struct
381 {
382  __IO uint32_t ISER[8];
383  uint32_t RESERVED0[24];
384  __IO uint32_t ICER[8];
385  uint32_t RSERVED1[24];
386  __IO uint32_t ISPR[8];
387  uint32_t RESERVED2[24];
388  __IO uint32_t ICPR[8];
389  uint32_t RESERVED3[24];
390  __IO uint32_t IABR[8];
391  uint32_t RESERVED4[56];
392  __IO uint8_t IP[240];
393  uint32_t RESERVED5[644];
394  __O uint32_t STIR;
395 } NVIC_Type;
396 
397 /* Software Triggered Interrupt Register Definitions */
398 #define NVIC_STIR_INTID_Pos 0
399 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
401 
412 typedef struct
413 {
414  __I uint32_t CPUID;
415  __IO uint32_t ICSR;
416  __IO uint32_t VTOR;
417  __IO uint32_t AIRCR;
418  __IO uint32_t SCR;
419  __IO uint32_t CCR;
420  __IO uint8_t SHPR[12];
421  __IO uint32_t SHCSR;
422  __IO uint32_t CFSR;
423  __IO uint32_t HFSR;
424  __IO uint32_t DFSR;
425  __IO uint32_t MMFAR;
426  __IO uint32_t BFAR;
427  __IO uint32_t AFSR;
428  __I uint32_t ID_PFR[2];
429  __I uint32_t ID_DFR;
430  __I uint32_t ID_AFR;
431  __I uint32_t ID_MFR[4];
432  __I uint32_t ID_ISAR[5];
433  uint32_t RESERVED0[1];
434  __I uint32_t CLIDR;
435  __I uint32_t CTR;
436  __I uint32_t CCSIDR;
437  __IO uint32_t CSSELR;
438  __IO uint32_t CPACR;
439  uint32_t RESERVED3[93];
440  __O uint32_t STIR;
441  uint32_t RESERVED4[15];
442  __I uint32_t MVFR0;
443  __I uint32_t MVFR1;
444  __I uint32_t MVFR2;
445  uint32_t RESERVED5[1];
446  __O uint32_t ICIALLU;
447  uint32_t RESERVED6[1];
448  __O uint32_t ICIMVAU;
449  __O uint32_t DCIMVAU;
450  __O uint32_t DCISW;
451  __O uint32_t DCCMVAU;
452  __O uint32_t DCCMVAC;
453  __O uint32_t DCCSW;
454  __O uint32_t DCCIMVAC;
455  __O uint32_t DCCISW;
456  uint32_t RESERVED7[6];
457  __IO uint32_t ITCMCR;
458  __IO uint32_t DTCMCR;
459  __IO uint32_t AHBPCR;
460  __IO uint32_t CACR;
461  __IO uint32_t AHBSCR;
462  uint32_t RESERVED8[1];
463  __IO uint32_t ABFSR;
464 } SCB_Type;
465 
466 /* SCB CPUID Register Definitions */
467 #define SCB_CPUID_IMPLEMENTER_Pos 24
468 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
470 #define SCB_CPUID_VARIANT_Pos 20
471 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
473 #define SCB_CPUID_ARCHITECTURE_Pos 16
474 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
476 #define SCB_CPUID_PARTNO_Pos 4
477 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
479 #define SCB_CPUID_REVISION_Pos 0
480 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
482 /* SCB Interrupt Control State Register Definitions */
483 #define SCB_ICSR_NMIPENDSET_Pos 31
484 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
486 #define SCB_ICSR_PENDSVSET_Pos 28
487 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
489 #define SCB_ICSR_PENDSVCLR_Pos 27
490 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
492 #define SCB_ICSR_PENDSTSET_Pos 26
493 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
495 #define SCB_ICSR_PENDSTCLR_Pos 25
496 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
498 #define SCB_ICSR_ISRPREEMPT_Pos 23
499 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
501 #define SCB_ICSR_ISRPENDING_Pos 22
502 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
504 #define SCB_ICSR_VECTPENDING_Pos 12
505 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
507 #define SCB_ICSR_RETTOBASE_Pos 11
508 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
510 #define SCB_ICSR_VECTACTIVE_Pos 0
511 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
513 /* SCB Vector Table Offset Register Definitions */
514 #define SCB_VTOR_TBLOFF_Pos 7
515 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
517 /* SCB Application Interrupt and Reset Control Register Definitions */
518 #define SCB_AIRCR_VECTKEY_Pos 16
519 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
521 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
522 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
524 #define SCB_AIRCR_ENDIANESS_Pos 15
525 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
527 #define SCB_AIRCR_PRIGROUP_Pos 8
528 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
530 #define SCB_AIRCR_SYSRESETREQ_Pos 2
531 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
533 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
534 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
536 #define SCB_AIRCR_VECTRESET_Pos 0
537 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
539 /* SCB System Control Register Definitions */
540 #define SCB_SCR_SEVONPEND_Pos 4
541 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
543 #define SCB_SCR_SLEEPDEEP_Pos 2
544 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
546 #define SCB_SCR_SLEEPONEXIT_Pos 1
547 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
549 /* SCB Configuration Control Register Definitions */
550 #define SCB_CCR_BP_Pos 18
551 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
553 #define SCB_CCR_IC_Pos 17
554 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
556 #define SCB_CCR_DC_Pos 16
557 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
559 #define SCB_CCR_STKALIGN_Pos 9
560 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
562 #define SCB_CCR_BFHFNMIGN_Pos 8
563 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
565 #define SCB_CCR_DIV_0_TRP_Pos 4
566 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
568 #define SCB_CCR_UNALIGN_TRP_Pos 3
569 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
571 #define SCB_CCR_USERSETMPEND_Pos 1
572 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
574 #define SCB_CCR_NONBASETHRDENA_Pos 0
575 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
577 /* SCB System Handler Control and State Register Definitions */
578 #define SCB_SHCSR_USGFAULTENA_Pos 18
579 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
581 #define SCB_SHCSR_BUSFAULTENA_Pos 17
582 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
584 #define SCB_SHCSR_MEMFAULTENA_Pos 16
585 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
587 #define SCB_SHCSR_SVCALLPENDED_Pos 15
588 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
590 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
591 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
593 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
594 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
596 #define SCB_SHCSR_USGFAULTPENDED_Pos 12
597 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
599 #define SCB_SHCSR_SYSTICKACT_Pos 11
600 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
602 #define SCB_SHCSR_PENDSVACT_Pos 10
603 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
605 #define SCB_SHCSR_MONITORACT_Pos 8
606 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
608 #define SCB_SHCSR_SVCALLACT_Pos 7
609 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
611 #define SCB_SHCSR_USGFAULTACT_Pos 3
612 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
614 #define SCB_SHCSR_BUSFAULTACT_Pos 1
615 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
617 #define SCB_SHCSR_MEMFAULTACT_Pos 0
618 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
620 /* SCB Configurable Fault Status Registers Definitions */
621 #define SCB_CFSR_USGFAULTSR_Pos 16
622 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
624 #define SCB_CFSR_BUSFAULTSR_Pos 8
625 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
627 #define SCB_CFSR_MEMFAULTSR_Pos 0
628 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
630 /* SCB Hard Fault Status Registers Definitions */
631 #define SCB_HFSR_DEBUGEVT_Pos 31
632 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
634 #define SCB_HFSR_FORCED_Pos 30
635 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
637 #define SCB_HFSR_VECTTBL_Pos 1
638 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
640 /* SCB Debug Fault Status Register Definitions */
641 #define SCB_DFSR_EXTERNAL_Pos 4
642 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
644 #define SCB_DFSR_VCATCH_Pos 3
645 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
647 #define SCB_DFSR_DWTTRAP_Pos 2
648 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
650 #define SCB_DFSR_BKPT_Pos 1
651 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
653 #define SCB_DFSR_HALTED_Pos 0
654 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
656 /* Cache Level ID register */
657 #define SCB_CLIDR_LOUU_Pos 27
658 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
660 #define SCB_CLIDR_LOC_Pos 24
661 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos)
663 /* Cache Type register */
664 #define SCB_CTR_FORMAT_Pos 29
665 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
667 #define SCB_CTR_CWG_Pos 24
668 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
670 #define SCB_CTR_ERG_Pos 20
671 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
673 #define SCB_CTR_DMINLINE_Pos 16
674 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
676 #define SCB_CTR_IMINLINE_Pos 0
677 #define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos)
679 /* Cache Size ID Register */
680 #define SCB_CCSIDR_WT_Pos 31
681 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos)
683 #define SCB_CCSIDR_WB_Pos 30
684 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos)
686 #define SCB_CCSIDR_RA_Pos 29
687 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos)
689 #define SCB_CCSIDR_WA_Pos 28
690 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos)
692 #define SCB_CCSIDR_NUMSETS_Pos 13
693 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
695 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3
696 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
698 #define SCB_CCSIDR_LINESIZE_Pos 0
699 #define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos)
701 /* Cache Size Selection Register */
702 #define SCB_CSSELR_LEVEL_Pos 0
703 #define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos)
705 #define SCB_CSSELR_IND_Pos 0
706 #define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos)
708 /* SCB Software Triggered Interrupt Register */
709 #define SCB_STIR_INTID_Pos 0
710 #define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos)
712 /* Instruction Tightly-Coupled Memory Control Register*/
713 #define SCB_ITCMCR_SZ_Pos 3
714 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
716 #define SCB_ITCMCR_RETEN_Pos 2
717 #define SCB_ITCMCR_RETEN_Msk (0x1UL << SCB_ITCMCR_RETEN_Pos)
719 #define SCB_ITCMCR_RMW_Pos 1
720 #define SCB_ITCMCR_RMW_Msk (0x1UL << SCB_ITCMCR_RMW_Pos)
722 #define SCB_ITCMCR_EN_Pos 0
723 #define SCB_ITCMCR_EN_Msk (0x1UL << SCB_ITCMCR_EN_Pos)
725 /* Data Tightly-Coupled Memory Control Registers */
726 #define SCB_DTCMCR_SZ_Pos 3
727 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
729 #define SCB_DTCMCR_RETEN_Pos 2
730 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
732 #define SCB_DTCMCR_RMW_Pos 1
733 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
735 #define SCB_DTCMCR_EN_Pos 0
736 #define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos)
738 /* AHBP Control Register */
739 #define SCB_AHBPCR_SZ_Pos 1
740 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
742 #define SCB_AHBPCR_EN_Pos 0
743 #define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos)
745 /* L1 Cache Control Register */
746 #define SCB_CACR_FORCEWT_Pos 2
747 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
749 #define SCB_CACR_ECCEN_Pos 1
750 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
752 #define SCB_CACR_SIWT_Pos 0
753 #define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos)
755 /* AHBS control register */
756 #define SCB_AHBSCR_INITCOUNT_Pos 11
757 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
759 #define SCB_AHBSCR_TPRI_Pos 2
760 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
762 #define SCB_AHBSCR_CTL_Pos 0
763 #define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos)
765 /* Auxiliary Bus Fault Status Register */
766 #define SCB_ABFSR_AXIMTYPE_Pos 8
767 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
769 #define SCB_ABFSR_EPPB_Pos 4
770 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
772 #define SCB_ABFSR_AXIM_Pos 3
773 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
775 #define SCB_ABFSR_AHBP_Pos 2
776 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
778 #define SCB_ABFSR_DTCM_Pos 1
779 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
781 #define SCB_ABFSR_ITCM_Pos 0
782 #define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos)
784 
795 typedef struct
796 {
797  uint32_t RESERVED0[1];
798  __I uint32_t ICTR;
799  __IO uint32_t ACTLR;
800 } SCnSCB_Type;
801 
802 /* Interrupt Controller Type Register Definitions */
803 #define SCnSCB_ICTR_INTLINESNUM_Pos 0
804 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
806 /* Auxiliary Control Register Definitions */
807 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12
808 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
810 #define SCnSCB_ACTLR_DISRAMODE_Pos 11
811 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
813 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10
814 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
816 #define SCnSCB_ACTLR_DISFOLD_Pos 2
817 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
819 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0
820 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
822 
833 typedef struct
834 {
835  __IO uint32_t CTRL;
836  __IO uint32_t LOAD;
837  __IO uint32_t VAL;
838  __I uint32_t CALIB;
839 } SysTick_Type;
840 
841 /* SysTick Control / Status Register Definitions */
842 #define SysTick_CTRL_COUNTFLAG_Pos 16
843 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
845 #define SysTick_CTRL_CLKSOURCE_Pos 2
846 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
848 #define SysTick_CTRL_TICKINT_Pos 1
849 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
851 #define SysTick_CTRL_ENABLE_Pos 0
852 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
854 /* SysTick Reload Register Definitions */
855 #define SysTick_LOAD_RELOAD_Pos 0
856 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
858 /* SysTick Current Register Definitions */
859 #define SysTick_VAL_CURRENT_Pos 0
860 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
862 /* SysTick Calibration Register Definitions */
863 #define SysTick_CALIB_NOREF_Pos 31
864 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
866 #define SysTick_CALIB_SKEW_Pos 30
867 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
869 #define SysTick_CALIB_TENMS_Pos 0
870 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
872 
883 typedef struct
884 {
885  __O union
886  {
887  __O uint8_t u8;
888  __O uint16_t u16;
889  __O uint32_t u32;
890  } PORT [32];
891  uint32_t RESERVED0[864];
892  __IO uint32_t TER;
893  uint32_t RESERVED1[15];
894  __IO uint32_t TPR;
895  uint32_t RESERVED2[15];
896  __IO uint32_t TCR;
897  uint32_t RESERVED3[29];
898  __O uint32_t IWR;
899  __I uint32_t IRR;
900  __IO uint32_t IMCR;
901  uint32_t RESERVED4[43];
902  __O uint32_t LAR;
903  __I uint32_t LSR;
904  uint32_t RESERVED5[6];
905  __I uint32_t PID4;
906  __I uint32_t PID5;
907  __I uint32_t PID6;
908  __I uint32_t PID7;
909  __I uint32_t PID0;
910  __I uint32_t PID1;
911  __I uint32_t PID2;
912  __I uint32_t PID3;
913  __I uint32_t CID0;
914  __I uint32_t CID1;
915  __I uint32_t CID2;
916  __I uint32_t CID3;
917 } ITM_Type;
918 
919 /* ITM Trace Privilege Register Definitions */
920 #define ITM_TPR_PRIVMASK_Pos 0
921 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
923 /* ITM Trace Control Register Definitions */
924 #define ITM_TCR_BUSY_Pos 23
925 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
927 #define ITM_TCR_TraceBusID_Pos 16
928 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
930 #define ITM_TCR_GTSFREQ_Pos 10
931 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
933 #define ITM_TCR_TSPrescale_Pos 8
934 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
936 #define ITM_TCR_SWOENA_Pos 4
937 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
939 #define ITM_TCR_DWTENA_Pos 3
940 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
942 #define ITM_TCR_SYNCENA_Pos 2
943 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
945 #define ITM_TCR_TSENA_Pos 1
946 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
948 #define ITM_TCR_ITMENA_Pos 0
949 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
951 /* ITM Integration Write Register Definitions */
952 #define ITM_IWR_ATVALIDM_Pos 0
953 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos)
955 /* ITM Integration Read Register Definitions */
956 #define ITM_IRR_ATREADYM_Pos 0
957 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos)
959 /* ITM Integration Mode Control Register Definitions */
960 #define ITM_IMCR_INTEGRATION_Pos 0
961 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos)
963 /* ITM Lock Status Register Definitions */
964 #define ITM_LSR_ByteAcc_Pos 2
965 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
967 #define ITM_LSR_Access_Pos 1
968 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
970 #define ITM_LSR_Present_Pos 0
971 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos)
973  /* end of group CMSIS_ITM */
974 
975 
984 typedef struct
985 {
986  __IO uint32_t CTRL;
987  __IO uint32_t CYCCNT;
988  __IO uint32_t CPICNT;
989  __IO uint32_t EXCCNT;
990  __IO uint32_t SLEEPCNT;
991  __IO uint32_t LSUCNT;
992  __IO uint32_t FOLDCNT;
993  __I uint32_t PCSR;
994  __IO uint32_t COMP0;
995  __IO uint32_t MASK0;
996  __IO uint32_t FUNCTION0;
997  uint32_t RESERVED0[1];
998  __IO uint32_t COMP1;
999  __IO uint32_t MASK1;
1000  __IO uint32_t FUNCTION1;
1001  uint32_t RESERVED1[1];
1002  __IO uint32_t COMP2;
1003  __IO uint32_t MASK2;
1004  __IO uint32_t FUNCTION2;
1005  uint32_t RESERVED2[1];
1006  __IO uint32_t COMP3;
1007  __IO uint32_t MASK3;
1008  __IO uint32_t FUNCTION3;
1009  uint32_t RESERVED3[981];
1010  __O uint32_t LAR;
1011  __I uint32_t LSR;
1012 } DWT_Type;
1013 
1014 /* DWT Control Register Definitions */
1015 #define DWT_CTRL_NUMCOMP_Pos 28
1016 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1018 #define DWT_CTRL_NOTRCPKT_Pos 27
1019 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1021 #define DWT_CTRL_NOEXTTRIG_Pos 26
1022 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1024 #define DWT_CTRL_NOCYCCNT_Pos 25
1025 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1027 #define DWT_CTRL_NOPRFCNT_Pos 24
1028 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1030 #define DWT_CTRL_CYCEVTENA_Pos 22
1031 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1033 #define DWT_CTRL_FOLDEVTENA_Pos 21
1034 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1036 #define DWT_CTRL_LSUEVTENA_Pos 20
1037 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1039 #define DWT_CTRL_SLEEPEVTENA_Pos 19
1040 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1042 #define DWT_CTRL_EXCEVTENA_Pos 18
1043 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1045 #define DWT_CTRL_CPIEVTENA_Pos 17
1046 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1048 #define DWT_CTRL_EXCTRCENA_Pos 16
1049 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1051 #define DWT_CTRL_PCSAMPLENA_Pos 12
1052 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1054 #define DWT_CTRL_SYNCTAP_Pos 10
1055 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1057 #define DWT_CTRL_CYCTAP_Pos 9
1058 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1060 #define DWT_CTRL_POSTINIT_Pos 5
1061 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1063 #define DWT_CTRL_POSTPRESET_Pos 1
1064 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1066 #define DWT_CTRL_CYCCNTENA_Pos 0
1067 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
1069 /* DWT CPI Count Register Definitions */
1070 #define DWT_CPICNT_CPICNT_Pos 0
1071 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
1073 /* DWT Exception Overhead Count Register Definitions */
1074 #define DWT_EXCCNT_EXCCNT_Pos 0
1075 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
1077 /* DWT Sleep Count Register Definitions */
1078 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0
1079 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
1081 /* DWT LSU Count Register Definitions */
1082 #define DWT_LSUCNT_LSUCNT_Pos 0
1083 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
1085 /* DWT Folded-instruction Count Register Definitions */
1086 #define DWT_FOLDCNT_FOLDCNT_Pos 0
1087 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
1089 /* DWT Comparator Mask Register Definitions */
1090 #define DWT_MASK_MASK_Pos 0
1091 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
1093 /* DWT Comparator Function Register Definitions */
1094 #define DWT_FUNCTION_MATCHED_Pos 24
1095 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1097 #define DWT_FUNCTION_DATAVADDR1_Pos 16
1098 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1100 #define DWT_FUNCTION_DATAVADDR0_Pos 12
1101 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1103 #define DWT_FUNCTION_DATAVSIZE_Pos 10
1104 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1106 #define DWT_FUNCTION_LNK1ENA_Pos 9
1107 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1109 #define DWT_FUNCTION_DATAVMATCH_Pos 8
1110 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1112 #define DWT_FUNCTION_CYCMATCH_Pos 7
1113 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1115 #define DWT_FUNCTION_EMITRANGE_Pos 5
1116 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1118 #define DWT_FUNCTION_FUNCTION_Pos 0
1119 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
1121  /* end of group CMSIS_DWT */
1122 
1123 
1132 typedef struct
1133 {
1134  __IO uint32_t SSPSR;
1135  __IO uint32_t CSPSR;
1136  uint32_t RESERVED0[2];
1137  __IO uint32_t ACPR;
1138  uint32_t RESERVED1[55];
1139  __IO uint32_t SPPR;
1140  uint32_t RESERVED2[131];
1141  __I uint32_t FFSR;
1142  __IO uint32_t FFCR;
1143  __I uint32_t FSCR;
1144  uint32_t RESERVED3[759];
1145  __I uint32_t TRIGGER;
1146  __I uint32_t FIFO0;
1147  __I uint32_t ITATBCTR2;
1148  uint32_t RESERVED4[1];
1149  __I uint32_t ITATBCTR0;
1150  __I uint32_t FIFO1;
1151  __IO uint32_t ITCTRL;
1152  uint32_t RESERVED5[39];
1153  __IO uint32_t CLAIMSET;
1154  __IO uint32_t CLAIMCLR;
1155  uint32_t RESERVED7[8];
1156  __I uint32_t DEVID;
1157  __I uint32_t DEVTYPE;
1158 } TPI_Type;
1159 
1160 /* TPI Asynchronous Clock Prescaler Register Definitions */
1161 #define TPI_ACPR_PRESCALER_Pos 0
1162 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
1164 /* TPI Selected Pin Protocol Register Definitions */
1165 #define TPI_SPPR_TXMODE_Pos 0
1166 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
1168 /* TPI Formatter and Flush Status Register Definitions */
1169 #define TPI_FFSR_FtNonStop_Pos 3
1170 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1172 #define TPI_FFSR_TCPresent_Pos 2
1173 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1175 #define TPI_FFSR_FtStopped_Pos 1
1176 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1178 #define TPI_FFSR_FlInProg_Pos 0
1179 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
1181 /* TPI Formatter and Flush Control Register Definitions */
1182 #define TPI_FFCR_TrigIn_Pos 8
1183 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1185 #define TPI_FFCR_EnFCont_Pos 1
1186 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1188 /* TPI TRIGGER Register Definitions */
1189 #define TPI_TRIGGER_TRIGGER_Pos 0
1190 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
1192 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1193 #define TPI_FIFO0_ITM_ATVALID_Pos 29
1194 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1196 #define TPI_FIFO0_ITM_bytecount_Pos 27
1197 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1199 #define TPI_FIFO0_ETM_ATVALID_Pos 26
1200 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1202 #define TPI_FIFO0_ETM_bytecount_Pos 24
1203 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1205 #define TPI_FIFO0_ETM2_Pos 16
1206 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1208 #define TPI_FIFO0_ETM1_Pos 8
1209 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1211 #define TPI_FIFO0_ETM0_Pos 0
1212 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
1214 /* TPI ITATBCTR2 Register Definitions */
1215 #define TPI_ITATBCTR2_ATREADY_Pos 0
1216 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
1218 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1219 #define TPI_FIFO1_ITM_ATVALID_Pos 29
1220 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1222 #define TPI_FIFO1_ITM_bytecount_Pos 27
1223 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1225 #define TPI_FIFO1_ETM_ATVALID_Pos 26
1226 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1228 #define TPI_FIFO1_ETM_bytecount_Pos 24
1229 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1231 #define TPI_FIFO1_ITM2_Pos 16
1232 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1234 #define TPI_FIFO1_ITM1_Pos 8
1235 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1237 #define TPI_FIFO1_ITM0_Pos 0
1238 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
1240 /* TPI ITATBCTR0 Register Definitions */
1241 #define TPI_ITATBCTR0_ATREADY_Pos 0
1242 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
1244 /* TPI Integration Mode Control Register Definitions */
1245 #define TPI_ITCTRL_Mode_Pos 0
1246 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
1248 /* TPI DEVID Register Definitions */
1249 #define TPI_DEVID_NRZVALID_Pos 11
1250 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1252 #define TPI_DEVID_MANCVALID_Pos 10
1253 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1255 #define TPI_DEVID_PTINVALID_Pos 9
1256 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1258 #define TPI_DEVID_MinBufSz_Pos 6
1259 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1261 #define TPI_DEVID_AsynClkIn_Pos 5
1262 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1264 #define TPI_DEVID_NrTraceInput_Pos 0
1265 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
1267 /* TPI DEVTYPE Register Definitions */
1268 #define TPI_DEVTYPE_SubType_Pos 0
1269 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
1271 #define TPI_DEVTYPE_MajorType_Pos 4
1272 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1274  /* end of group CMSIS_TPI */
1275 
1276 
1277 #if (__MPU_PRESENT == 1)
1278 
1286 typedef struct
1287 {
1288  __I uint32_t TYPE;
1289  __IO uint32_t CTRL;
1290  __IO uint32_t RNR;
1291  __IO uint32_t RBAR;
1292  __IO uint32_t RASR;
1293  __IO uint32_t RBAR_A1;
1294  __IO uint32_t RASR_A1;
1295  __IO uint32_t RBAR_A2;
1296  __IO uint32_t RASR_A2;
1297  __IO uint32_t RBAR_A3;
1298  __IO uint32_t RASR_A3;
1299 } MPU_Type;
1300 
1301 /* MPU Type Register */
1302 #define MPU_TYPE_IREGION_Pos 16
1303 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1305 #define MPU_TYPE_DREGION_Pos 8
1306 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1308 #define MPU_TYPE_SEPARATE_Pos 0
1309 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
1311 /* MPU Control Register */
1312 #define MPU_CTRL_PRIVDEFENA_Pos 2
1313 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1315 #define MPU_CTRL_HFNMIENA_Pos 1
1316 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1318 #define MPU_CTRL_ENABLE_Pos 0
1319 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
1321 /* MPU Region Number Register */
1322 #define MPU_RNR_REGION_Pos 0
1323 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
1325 /* MPU Region Base Address Register */
1326 #define MPU_RBAR_ADDR_Pos 5
1327 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1329 #define MPU_RBAR_VALID_Pos 4
1330 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1332 #define MPU_RBAR_REGION_Pos 0
1333 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
1335 /* MPU Region Attribute and Size Register */
1336 #define MPU_RASR_ATTRS_Pos 16
1337 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1339 #define MPU_RASR_XN_Pos 28
1340 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1342 #define MPU_RASR_AP_Pos 24
1343 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1345 #define MPU_RASR_TEX_Pos 19
1346 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1348 #define MPU_RASR_S_Pos 18
1349 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1351 #define MPU_RASR_C_Pos 17
1352 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1354 #define MPU_RASR_B_Pos 16
1355 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1357 #define MPU_RASR_SRD_Pos 8
1358 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1360 #define MPU_RASR_SIZE_Pos 1
1361 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1363 #define MPU_RASR_ENABLE_Pos 0
1364 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
1366 
1367 #endif
1368 
1369 
1370 #if (__FPU_PRESENT == 1)
1371 
1379 typedef struct
1380 {
1381  uint32_t RESERVED0[1];
1382  __IO uint32_t FPCCR;
1383  __IO uint32_t FPCAR;
1384  __IO uint32_t FPDSCR;
1385  __I uint32_t MVFR0;
1386  __I uint32_t MVFR1;
1387  __I uint32_t MVFR2;
1388 } FPU_Type;
1389 
1390 /* Floating-Point Context Control Register */
1391 #define FPU_FPCCR_ASPEN_Pos 31
1392 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1394 #define FPU_FPCCR_LSPEN_Pos 30
1395 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1397 #define FPU_FPCCR_MONRDY_Pos 8
1398 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1400 #define FPU_FPCCR_BFRDY_Pos 6
1401 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1403 #define FPU_FPCCR_MMRDY_Pos 5
1404 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1406 #define FPU_FPCCR_HFRDY_Pos 4
1407 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1409 #define FPU_FPCCR_THREAD_Pos 3
1410 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1412 #define FPU_FPCCR_USER_Pos 1
1413 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1415 #define FPU_FPCCR_LSPACT_Pos 0
1416 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos)
1418 /* Floating-Point Context Address Register */
1419 #define FPU_FPCAR_ADDRESS_Pos 3
1420 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1422 /* Floating-Point Default Status Control Register */
1423 #define FPU_FPDSCR_AHP_Pos 26
1424 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1426 #define FPU_FPDSCR_DN_Pos 25
1427 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1429 #define FPU_FPDSCR_FZ_Pos 24
1430 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1432 #define FPU_FPDSCR_RMode_Pos 22
1433 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1435 /* Media and FP Feature Register 0 */
1436 #define FPU_MVFR0_FP_rounding_modes_Pos 28
1437 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1439 #define FPU_MVFR0_Short_vectors_Pos 24
1440 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1442 #define FPU_MVFR0_Square_root_Pos 20
1443 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1445 #define FPU_MVFR0_Divide_Pos 16
1446 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1448 #define FPU_MVFR0_FP_excep_trapping_Pos 12
1449 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1451 #define FPU_MVFR0_Double_precision_Pos 8
1452 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1454 #define FPU_MVFR0_Single_precision_Pos 4
1455 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1457 #define FPU_MVFR0_A_SIMD_registers_Pos 0
1458 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)
1460 /* Media and FP Feature Register 1 */
1461 #define FPU_MVFR1_FP_fused_MAC_Pos 28
1462 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1464 #define FPU_MVFR1_FP_HPFP_Pos 24
1465 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1467 #define FPU_MVFR1_D_NaN_mode_Pos 4
1468 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1470 #define FPU_MVFR1_FtZ_mode_Pos 0
1471 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos)
1473 /* Media and FP Feature Register 2 */
1474 
1476 #endif
1477 
1478 
1487 typedef struct
1488 {
1489  __IO uint32_t DHCSR;
1490  __O uint32_t DCRSR;
1491  __IO uint32_t DCRDR;
1492  __IO uint32_t DEMCR;
1493 } CoreDebug_Type;
1494 
1495 /* Debug Halting Control and Status Register */
1496 #define CoreDebug_DHCSR_DBGKEY_Pos 16
1497 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1499 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
1500 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1502 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
1503 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1505 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
1506 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1508 #define CoreDebug_DHCSR_S_SLEEP_Pos 18
1509 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1511 #define CoreDebug_DHCSR_S_HALT_Pos 17
1512 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1514 #define CoreDebug_DHCSR_S_REGRDY_Pos 16
1515 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1517 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
1518 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1520 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
1521 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1523 #define CoreDebug_DHCSR_C_STEP_Pos 2
1524 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1526 #define CoreDebug_DHCSR_C_HALT_Pos 1
1527 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1529 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
1530 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
1532 /* Debug Core Register Selector Register */
1533 #define CoreDebug_DCRSR_REGWnR_Pos 16
1534 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1536 #define CoreDebug_DCRSR_REGSEL_Pos 0
1537 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
1539 /* Debug Exception and Monitor Control Register */
1540 #define CoreDebug_DEMCR_TRCENA_Pos 24
1541 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1543 #define CoreDebug_DEMCR_MON_REQ_Pos 19
1544 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1546 #define CoreDebug_DEMCR_MON_STEP_Pos 18
1547 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1549 #define CoreDebug_DEMCR_MON_PEND_Pos 17
1550 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1552 #define CoreDebug_DEMCR_MON_EN_Pos 16
1553 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1555 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
1556 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1558 #define CoreDebug_DEMCR_VC_INTERR_Pos 9
1559 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1561 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
1562 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1564 #define CoreDebug_DEMCR_VC_STATERR_Pos 7
1565 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1567 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
1568 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1570 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
1571 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1573 #define CoreDebug_DEMCR_VC_MMERR_Pos 4
1574 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1576 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
1577 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
1579 
1588 /* Memory mapping of Cortex-M4 Hardware */
1589 #define SCS_BASE (0xE000E000UL)
1590 #define ITM_BASE (0xE0000000UL)
1591 #define DWT_BASE (0xE0001000UL)
1592 #define TPI_BASE (0xE0040000UL)
1593 #define CoreDebug_BASE (0xE000EDF0UL)
1594 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1595 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1596 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1598 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1599 #define SCB ((SCB_Type *) SCB_BASE )
1600 #define SysTick ((SysTick_Type *) SysTick_BASE )
1601 #define NVIC ((NVIC_Type *) NVIC_BASE )
1602 #define ITM ((ITM_Type *) ITM_BASE )
1603 #define DWT ((DWT_Type *) DWT_BASE )
1604 #define TPI ((TPI_Type *) TPI_BASE )
1605 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1607 #if (__MPU_PRESENT == 1)
1608  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1609  #define MPU ((MPU_Type *) MPU_BASE )
1610 #endif
1611 
1612 #if (__FPU_PRESENT == 1)
1613  #define FPU_BASE (SCS_BASE + 0x0F30UL)
1614  #define FPU ((FPU_Type *) FPU_BASE )
1615 #endif
1616 
1621 /*******************************************************************************
1622  * Hardware Abstraction Layer
1623  Core Function Interface contains:
1624  - Core NVIC Functions
1625  - Core SysTick Functions
1626  - Core Debug Functions
1627  - Core Register Access Functions
1628  ******************************************************************************/
1634 /* ########################## NVIC functions #################################### */
1651 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1652 {
1653  uint32_t reg_value;
1654  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1655 
1656  reg_value = SCB->AIRCR; /* read old register configuration */
1657  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1658  reg_value = (reg_value |
1659  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1660  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1661  SCB->AIRCR = reg_value;
1662 }
1663 
1664 
1671 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1672 {
1673  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1674 }
1675 
1676 
1683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1684 {
1685 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
1686  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
1687 }
1688 
1689 
1696 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1697 {
1698  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1699 }
1700 
1701 
1712 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1713 {
1714  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1715 }
1716 
1717 
1724 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1725 {
1726  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1727 }
1728 
1729 
1736 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1737 {
1738  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1739 }
1740 
1741 
1751 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1752 {
1753  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1754 }
1755 
1756 
1766 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1767 {
1768  if(IRQn < 0) {
1769  SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1770  else {
1771  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1772 }
1773 
1774 
1786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1787 {
1788 
1789  if(IRQn < 0) {
1790  return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1791  else {
1792  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1793 }
1794 
1795 
1808 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1809 {
1810  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1811  uint32_t PreemptPriorityBits;
1812  uint32_t SubPriorityBits;
1813 
1814  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1815  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1816 
1817  return (
1818  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1819  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1820  );
1821 }
1822 
1823 
1836 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1837 {
1838  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1839  uint32_t PreemptPriorityBits;
1840  uint32_t SubPriorityBits;
1841 
1842  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1843  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1844 
1845  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1846  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1847 }
1848 
1849 
1854 __STATIC_INLINE void NVIC_SystemReset(void)
1855 {
1856  __DSB(); /* Ensure all outstanding memory accesses included
1857  buffered write are completed before reset */
1858  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1859  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1860  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1861  __DSB(); /* Ensure completion of memory access */
1862  while(1); /* wait until reset */
1863 }
1864 
1868 /* ########################## Cache functions #################################### */
1875 /* Cache Size ID Register Macros */
1876 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
1877 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
1878 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )
1879 
1880 
1885 __STATIC_INLINE void SCB_EnableICache(void)
1886 {
1887  #if (__ICACHE_PRESENT == 1)
1888  __DSB();
1889  __ISB();
1890  SCB->ICIALLU = 0; // invalidate I-Cache
1891  SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache
1892  __DSB();
1893  __ISB();
1894  #endif
1895 }
1896 
1897 
1902 __STATIC_INLINE void SCB_DisableICache(void)
1903 {
1904  #if (__ICACHE_PRESENT == 1)
1905  __DSB();
1906  __ISB();
1907  SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache
1908  SCB->ICIALLU = 0; // invalidate I-Cache
1909  __DSB();
1910  __ISB();
1911  #endif
1912 }
1913 
1914 
1919 __STATIC_INLINE void SCB_InvalidateICache(void)
1920 {
1921  #if (__ICACHE_PRESENT == 1)
1922  __DSB();
1923  __ISB();
1924  SCB->ICIALLU = 0;
1925  __DSB();
1926  __ISB();
1927  #endif
1928 }
1929 
1930 
1935 __STATIC_INLINE void SCB_EnableDCache(void)
1936 {
1937  #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1)
1938  uint32_t ccsidr, sshift, wshift, sw;
1939  uint32_t sets, ways;
1940 
1941  ccsidr = SCB->CCSIDR;
1942  sets = CCSIDR_SETS(ccsidr);
1943  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
1944  ways = CCSIDR_WAYS(ccsidr);
1945  wshift = __CLZ(ways) & 0x1f;
1946 
1947  __DSB();
1948 
1949  do { // invalidate D-Cache
1950  int32_t tmpways = ways;
1951  do {
1952  sw = ((tmpways << wshift) | (sets << sshift));
1953  SCB->DCISW = sw;
1954  } while(tmpways--);
1955  } while(sets--);
1956  __DSB();
1957 
1958  SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache
1959 
1960  __DSB();
1961  __ISB();
1962  #endif
1963 }
1964 
1965 
1970 __STATIC_INLINE void SCB_DisableDCache(void)
1971 {
1972  #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1)
1973  uint32_t ccsidr, sshift, wshift, sw;
1974  uint32_t sets, ways;
1975 
1976  ccsidr = SCB->CCSIDR;
1977  sets = CCSIDR_SETS(ccsidr);
1978  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
1979  ways = CCSIDR_WAYS(ccsidr);
1980  wshift = __CLZ(ways) & 0x1f;
1981 
1982  __DSB();
1983 
1984  SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache
1985 
1986  do { // clean & invalidate D-Cache
1987  int32_t tmpways = ways;
1988  do {
1989  sw = ((tmpways << wshift) | (sets << sshift));
1990  SCB->DCCISW = sw;
1991  } while(tmpways--);
1992  } while(sets--);
1993 
1994 
1995  __DSB();
1996  __ISB();
1997  #endif
1998 }
1999 
2000 
2005 __STATIC_INLINE void SCB_InvalidateDCache(void)
2006 {
2007  #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1)
2008  uint32_t ccsidr, sshift, wshift, sw;
2009  uint32_t sets, ways;
2010 
2011  ccsidr = SCB->CCSIDR;
2012  sets = CCSIDR_SETS(ccsidr);
2013  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
2014  ways = CCSIDR_WAYS(ccsidr);
2015  wshift = __CLZ(ways) & 0x1f;
2016 
2017  __DSB();
2018 
2019  do { // invalidate D-Cache
2020  int32_t tmpways = ways;
2021  do {
2022  sw = ((tmpways << wshift) | (sets << sshift));
2023  SCB->DCISW = sw;
2024  } while(tmpways--);
2025  } while(sets--);
2026 
2027  __DSB();
2028  __ISB();
2029  #endif
2030 }
2031 
2032 
2037 __STATIC_INLINE void SCB_CleanDCache(void)
2038 {
2039  #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1)
2040  uint32_t ccsidr, sshift, wshift, sw;
2041  uint32_t sets, ways;
2042 
2043  ccsidr = SCB->CCSIDR;
2044  sets = CCSIDR_SETS(ccsidr);
2045  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
2046  ways = CCSIDR_WAYS(ccsidr);
2047  wshift = __CLZ(ways) & 0x1f;
2048 
2049  __DSB();
2050 
2051  do { // clean D-Cache
2052  int32_t tmpways = ways;
2053  do {
2054  sw = ((tmpways << wshift) | (sets << sshift));
2055  SCB->DCCSW = sw;
2056  } while(tmpways--);
2057  } while(sets--);
2058 
2059  __DSB();
2060  __ISB();
2061  #endif
2062 }
2063 
2064 
2069 __STATIC_INLINE void SCB_CleanInvalidateDCache(void)
2070 {
2071  #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1)
2072  uint32_t ccsidr, sshift, wshift, sw;
2073  uint32_t sets, ways;
2074 
2075  ccsidr = SCB->CCSIDR;
2076  sets = CCSIDR_SETS(ccsidr);
2077  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
2078  ways = CCSIDR_WAYS(ccsidr);
2079  wshift = __CLZ(ways) & 0x1f;
2080 
2081  __DSB();
2082 
2083  do { // clean & invalidate D-Cache
2084  int32_t tmpways = ways;
2085  do {
2086  sw = ((tmpways << wshift) | (sets << sshift));
2087  SCB->DCCISW = sw;
2088  } while(tmpways--);
2089  } while(sets--);
2090 
2091  __DSB();
2092  __ISB();
2093  #endif
2094 }
2095 
2096 
2101 /* ################################## SysTick function ############################################ */
2108 #if (__Vendor_SysTickConfig == 0)
2109 
2125 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2126 {
2127  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
2128 
2129  SysTick->LOAD = ticks - 1; /* set reload register */
2130  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
2131  SysTick->VAL = 0; /* Load the SysTick Counter Value */
2132  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2133  SysTick_CTRL_TICKINT_Msk |
2134  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2135  return (0); /* Function successful */
2136 }
2137 
2138 #endif
2139 
2144 /* ##################################### Debug In/Output function ########################################### */
2151 extern volatile int32_t ITM_RxBuffer;
2152 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
2165 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2166 {
2167  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
2168  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
2169  {
2170  while (ITM->PORT[0].u32 == 0);
2171  ITM->PORT[0].u8 = (uint8_t) ch;
2172  }
2173  return (ch);
2174 }
2175 
2176 
2184 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
2185  int32_t ch = -1; /* no character available */
2186 
2187  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
2188  ch = ITM_RxBuffer;
2189  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2190  }
2191 
2192  return (ch);
2193 }
2194 
2195 
2203 __STATIC_INLINE int32_t ITM_CheckChar (void) {
2204 
2205  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
2206  return (0); /* no character available */
2207  } else {
2208  return (1); /* character available */
2209  }
2210 }
2211 
2217 #ifdef __cplusplus
2218 }
2219 #endif
2220 
2221 #endif /* __CORE_CM7_H_DEPENDANT */
2222 
2223 #endif /* __CMSIS_GENERIC */
DWT_Type::FUNCTION3
__IO uint32_t FUNCTION3
Definition: core_cm7.h:1008
SysTick_IRQn
Definition: same70j19.h:73
DWT_Type::FUNCTION1
__IO uint32_t FUNCTION1
Definition: core_cm7.h:1000
xPSR_Type::Q
uint32_t Q
Definition: core_cm7.h:345
NVIC_Type::STIR
__O uint32_t STIR
Definition: core_cm7.h:394
APSR_Type::GE
uint32_t GE
Definition: core_cm7.h:303
DWT_Type::CPICNT
__IO uint32_t CPICNT
Definition: core_cm7.h:988
CoreDebug_Type::DCRDR
__IO uint32_t DCRDR
Definition: core_cm7.h:1491
IPSR_Type::w
uint32_t w
Definition: core_cm7.h:325
SCB_Type::MMFAR
__IO uint32_t MMFAR
Definition: core_cm7.h:425
DWT_Type::CYCCNT
__IO uint32_t CYCCNT
Definition: core_cm7.h:987
CoreDebug_Type::DHCSR
__IO uint32_t DHCSR
Definition: core_cm7.h:1489
SCB_Type::DCCIMVAC
__O uint32_t DCCIMVAC
Definition: core_cm7.h:454
ITM_Type::TPR
__IO uint32_t TPR
Definition: core_cm7.h:894
SCB_Type::DCISW
__O uint32_t DCISW
Definition: core_cm7.h:450
xPSR_Type::C
uint32_t C
Definition: core_cm7.h:347
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
ITM_Type::PID5
__I uint32_t PID5
Definition: core_cm7.h:906
ITM_Type::PID2
__I uint32_t PID2
Definition: core_cm7.h:911
SCB_Type::SHCSR
__IO uint32_t SHCSR
Definition: core_cm7.h:421
SCB_InvalidateICache
__STATIC_INLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: core_cm7.h:1919
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm7.h:2203
CoreDebug_Type::DCRSR
__O uint32_t DCRSR
Definition: core_cm7.h:1490
ITM_Type::PID3
__I uint32_t PID3
Definition: core_cm7.h:912
TPI_Type::TRIGGER
__I uint32_t TRIGGER
Definition: core_cm7.h:1145
xPSR_Type::IT
uint32_t IT
Definition: core_cm7.h:344
SCB_DisableDCache
__STATIC_INLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: core_cm7.h:1970
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm7.h:518
SCB_Type::ABFSR
__IO uint32_t ABFSR
Definition: core_cm7.h:463
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm7.h:380
SCB_Type::CACR
__IO uint32_t CACR
Definition: core_cm7.h:460
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:554
SCB_Type::CFSR
__IO uint32_t CFSR
Definition: core_cm7.h:422
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm7.h:846
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm7.h:412
ITM
#define ITM
Definition: core_cm7.h:1602
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm7.h:984
CONTROL_Type::w
uint32_t w
Definition: core_cm7.h:366
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
SCB_Type::MVFR2
__I uint32_t MVFR2
Definition: core_cm7.h:444
SysTick_Type::VAL
__IO uint32_t VAL
Definition: core_cm7.h:837
__IO
#define __IO
Definition: core_cm7.h:266
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm7.h:1808
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm7.h:2152
SCB_Type::DCCISW
__O uint32_t DCCISW
Definition: core_cm7.h:455
APSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm7.h:304
SCB_Type::ID_DFR
__I uint32_t ID_DFR
Definition: core_cm7.h:429
ITM_Type::PID7
__I uint32_t PID7
Definition: core_cm7.h:908
__O
#define __O
Definition: core_cm7.h:265
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm7.h:1766
CONTROL_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:364
SCB_Type::DCIMVAU
__O uint32_t DCIMVAU
Definition: core_cm7.h:449
DWT_Type::COMP3
__IO uint32_t COMP3
Definition: core_cm7.h:1006
DWT_Type::MASK2
__IO uint32_t MASK2
Definition: core_cm7.h:1003
IPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:323
SCB_Type::VTOR
__IO uint32_t VTOR
Definition: core_cm7.h:416
DWT_Type::SLEEPCNT
__IO uint32_t SLEEPCNT
Definition: core_cm7.h:990
ITM_Type::TER
__IO uint32_t TER
Definition: core_cm7.h:892
SysTick_Type::CALIB
__I uint32_t CALIB
Definition: core_cm7.h:838
SCB_EnableDCache
__STATIC_INLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: core_cm7.h:1935
SCB_Type::CSSELR
__IO uint32_t CSSELR
Definition: core_cm7.h:437
SCB_Type::ITCMCR
__IO uint32_t ITCMCR
Definition: core_cm7.h:457
xPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:339
SCB_DisableICache
__STATIC_INLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: core_cm7.h:1902
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
TPI_Type::CLAIMSET
__IO uint32_t CLAIMSET
Definition: core_cm7.h:1153
SCB_Type::AHBSCR
__IO uint32_t AHBSCR
Definition: core_cm7.h:461
SCB_Type::MVFR0
__I uint32_t MVFR0
Definition: core_cm7.h:442
DWT_Type::CTRL
__IO uint32_t CTRL
Definition: core_cm7.h:986
APSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:302
SCB_EnableICache
__STATIC_INLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: core_cm7.h:1885
TPI_Type::FSCR
__I uint32_t FSCR
Definition: core_cm7.h:1143
SCB_Type::ICSR
__IO uint32_t ICSR
Definition: core_cm7.h:415
SCB_Type::AIRCR
__IO uint32_t AIRCR
Definition: core_cm7.h:417
TPI_Type::FIFO1
__I uint32_t FIFO1
Definition: core_cm7.h:1150
SCB_Type::ID_AFR
__I uint32_t ID_AFR
Definition: core_cm7.h:430
DWT_Type::PCSR
__I uint32_t PCSR
Definition: core_cm7.h:993
SCB_Type::DFSR
__IO uint32_t DFSR
Definition: core_cm7.h:424
TPI_Type::FFSR
__I uint32_t FFSR
Definition: core_cm7.h:1141
SCB_Type::AFSR
__IO uint32_t AFSR
Definition: core_cm7.h:427
SCB_Type::ICIALLU
__O uint32_t ICIALLU
Definition: core_cm7.h:446
SCB_InvalidateDCache
__STATIC_INLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: core_cm7.h:2005
SCB_Type::DCCMVAU
__O uint32_t DCCMVAU
Definition: core_cm7.h:451
SCB_Type::STIR
__O uint32_t STIR
Definition: core_cm7.h:440
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm7.h:849
SCB
#define SCB
Definition: core_cm7.h:1599
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm7.h:1696
SCB_Type::HFSR
__IO uint32_t HFSR
Definition: core_cm7.h:423
xPSR_Type::ISR
uint32_t ISR
Definition: core_cm7.h:335
xPSR_Type::Z
uint32_t Z
Definition: core_cm7.h:348
ITM_Type::PID6
__I uint32_t PID6
Definition: core_cm7.h:907
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm7.h:833
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm7.h:1487
core_cmSimd.h
CMSIS Cortex-M SIMD Header File.
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm7.h:1854
ITM_Type::PID0
__I uint32_t PID0
Definition: core_cm7.h:909
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm7.h:295
SCB_Type::CLIDR
__I uint32_t CLIDR
Definition: core_cm7.h:434
APSR_Type::V
uint32_t V
Definition: core_cm7.h:307
ITM_Type::u8
__O uint8_t u8
Definition: core_cm7.h:887
SCB_Type::CTR
__I uint32_t CTR
Definition: core_cm7.h:435
SCB_Type::MVFR1
__I uint32_t MVFR1
Definition: core_cm7.h:443
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm7.h:1683
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm7.h:519
board_opt.h
CCSIDR_WAYS
#define CCSIDR_WAYS(x)
Definition: core_cm7.h:1876
xPSR_Type::N
uint32_t N
Definition: core_cm7.h:349
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: same70j19.h:293
CoreDebug_Type::DEMCR
__IO uint32_t DEMCR
Definition: core_cm7.h:1492
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm7.h:1712
xPSR_Type::V
uint32_t V
Definition: core_cm7.h:346
APSR_Type::C
uint32_t C
Definition: core_cm7.h:308
TPI_Type::ACPR
__IO uint32_t ACPR
Definition: core_cm7.h:1137
SCB_CleanInvalidateDCache
__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: core_cm7.h:2069
DWT_Type::EXCCNT
__IO uint32_t EXCCNT
Definition: core_cm7.h:989
TPI_Type::FFCR
__IO uint32_t FFCR
Definition: core_cm7.h:1142
DWT_Type::MASK0
__IO uint32_t MASK0
Definition: core_cm7.h:995
SysTick
#define SysTick
Definition: core_cm7.h:1600
APSR_Type::Z
uint32_t Z
Definition: core_cm7.h:309
DWT_Type::COMP2
__IO uint32_t COMP2
Definition: core_cm7.h:1002
CONTROL_Type::SPSEL
uint32_t SPSEL
Definition: core_cm7.h:362
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm7.h:528
xPSR_Type::GE
uint32_t GE
Definition: core_cm7.h:340
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm7.h:2125
DWT_Type::LSUCNT
__IO uint32_t LSUCNT
Definition: core_cm7.h:991
ITM_Type::IWR
__O uint32_t IWR
Definition: core_cm7.h:898
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm7.h:357
SCB_Type::CPUID
__I uint32_t CPUID
Definition: core_cm7.h:414
DWT_Type::FUNCTION0
__IO uint32_t FUNCTION0
Definition: core_cm7.h:996
SysTick_Type::CTRL
__IO uint32_t CTRL
Definition: core_cm7.h:835
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm7.h:1132
NVIC
#define NVIC
Definition: core_cm7.h:1601
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm7.h:856
TPI_Type::ITATBCTR0
__I uint32_t ITATBCTR0
Definition: core_cm7.h:1149
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Definition: core_cm7.h:1836
TPI_Type::CLAIMCLR
__IO uint32_t CLAIMCLR
Definition: core_cm7.h:1154
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm7.h:795
SCB_Type::SCR
__IO uint32_t SCR
Definition: core_cm7.h:418
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm7.h:1724
xPSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm7.h:341
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm7.h:1736
ITM_Type::TCR
__IO uint32_t TCR
Definition: core_cm7.h:896
DWT_Type::LSR
__I uint32_t LSR
Definition: core_cm7.h:1011
ITM_Type::IMCR
__IO uint32_t IMCR
Definition: core_cm7.h:900
ITM_Type::IRR
__I uint32_t IRR
Definition: core_cm7.h:899
SCnSCB_Type::ACTLR
__IO uint32_t ACTLR
Definition: core_cm7.h:799
ITM_Type::LAR
__O uint32_t LAR
Definition: core_cm7.h:902
DWT_Type::MASK1
__IO uint32_t MASK1
Definition: core_cm7.h:999
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm7.h:318
SCB_Type::AHBPCR
__IO uint32_t AHBPCR
Definition: core_cm7.h:459
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm7.h:2184
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm7.h:331
TPI_Type::DEVID
__I uint32_t DEVID
Definition: core_cm7.h:1156
TPI_Type::DEVTYPE
__I uint32_t DEVTYPE
Definition: core_cm7.h:1157
DWT_Type::MASK3
__IO uint32_t MASK3
Definition: core_cm7.h:1007
xPSR_Type::T
uint32_t T
Definition: core_cm7.h:343
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm7.h:1786
TPI_Type::ITCTRL
__IO uint32_t ITCTRL
Definition: core_cm7.h:1151
SysTick_Type::LOAD
__IO uint32_t LOAD
Definition: core_cm7.h:836
CONTROL_Type::FPCA
uint32_t FPCA
Definition: core_cm7.h:363
SCB_Type::ICIMVAU
__O uint32_t ICIMVAU
Definition: core_cm7.h:448
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm7.h:852
SCB_CleanDCache
__STATIC_INLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: core_cm7.h:2037
TPI_Type::SPPR
__IO uint32_t SPPR
Definition: core_cm7.h:1139
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:557
IRQn_Type
enum IRQn IRQn_Type
CONTROL_Type::nPRIV
uint32_t nPRIV
Definition: core_cm7.h:361
CCSIDR_LSSHIFT
#define CCSIDR_LSSHIFT(x)
Definition: core_cm7.h:1878
DWT_Type::COMP0
__IO uint32_t COMP0
Definition: core_cm7.h:994
APSR_Type::Q
uint32_t Q
Definition: core_cm7.h:306
DWT_Type::FOLDCNT
__IO uint32_t FOLDCNT
Definition: core_cm7.h:992
DWT_Type::COMP1
__IO uint32_t COMP1
Definition: core_cm7.h:998
ITM_Type::LSR
__I uint32_t LSR
Definition: core_cm7.h:903
TPI_Type::SSPSR
__IO uint32_t SSPSR
Definition: core_cm7.h:1134
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm7.h:1751
SCB_Type::CCSIDR
__I uint32_t CCSIDR
Definition: core_cm7.h:436
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm7.h:1651
SCB_Type::CCR
__IO uint32_t CCR
Definition: core_cm7.h:419
SCB_Type::DCCMVAC
__O uint32_t DCCMVAC
Definition: core_cm7.h:452
DWT_Type::FUNCTION2
__IO uint32_t FUNCTION2
Definition: core_cm7.h:1004
IRQn
IRQn
Definition: same70j19.h:62
CCSIDR_SETS
#define CCSIDR_SETS(x)
Definition: core_cm7.h:1877
xPSR_Type::w
uint32_t w
Definition: core_cm7.h:351
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm7.h:1671
ITM_Type::CID0
__I uint32_t CID0
Definition: core_cm7.h:913
TPI_Type::CSPSR
__IO uint32_t CSPSR
Definition: core_cm7.h:1135
ITM_Type::CID3
__I uint32_t CID3
Definition: core_cm7.h:916
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm7.h:949
SCB_Type::CPACR
__IO uint32_t CPACR
Definition: core_cm7.h:438
APSR_Type::N
uint32_t N
Definition: core_cm7.h:310
ITM_Type::CID2
__I uint32_t CID2
Definition: core_cm7.h:915
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm7.h:531
SCB_Type::DTCMCR
__IO uint32_t DTCMCR
Definition: core_cm7.h:458
ITM_Type::CID1
__I uint32_t CID1
Definition: core_cm7.h:914
ITM_Type::u32
__O uint32_t u32
Definition: core_cm7.h:889
APSR_Type::w
uint32_t w
Definition: core_cm7.h:312
ITM_Type::u16
__O uint16_t u16
Definition: core_cm7.h:888
TPI_Type::ITATBCTR2
__I uint32_t ITATBCTR2
Definition: core_cm7.h:1147
ITM_Type::PID1
__I uint32_t PID1
Definition: core_cm7.h:910
ITM_Type::PID4
__I uint32_t PID4
Definition: core_cm7.h:905
TPI_Type::FIFO0
__I uint32_t FIFO0
Definition: core_cm7.h:1146
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm7.h:883
SCB_Type::DCCSW
__O uint32_t DCCSW
Definition: core_cm7.h:453
__I
#define __I
Definition: core_cm7.h:263
SCB_Type::BFAR
__IO uint32_t BFAR
Definition: core_cm7.h:426
DWT_Type::LAR
__O uint32_t LAR
Definition: core_cm7.h:1010
SCnSCB_Type::ICTR
__I uint32_t ICTR
Definition: core_cm7.h:798
IPSR_Type::ISR
uint32_t ISR
Definition: core_cm7.h:322
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm7.h:527

inertial_sense_ros
Author(s):
autogenerated on Sun Feb 28 2021 03:17:57