Go to the documentation of this file. 35 #ifndef _SAME70_PWM0_INSTANCE_ 36 #define _SAME70_PWM0_INSTANCE_ 39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 #define REG_PWM0_CLK (0x40020000U) 41 #define REG_PWM0_ENA (0x40020004U) 42 #define REG_PWM0_DIS (0x40020008U) 43 #define REG_PWM0_SR (0x4002000CU) 44 #define REG_PWM0_IER1 (0x40020010U) 45 #define REG_PWM0_IDR1 (0x40020014U) 46 #define REG_PWM0_IMR1 (0x40020018U) 47 #define REG_PWM0_ISR1 (0x4002001CU) 48 #define REG_PWM0_SCM (0x40020020U) 49 #define REG_PWM0_DMAR (0x40020024U) 50 #define REG_PWM0_SCUC (0x40020028U) 51 #define REG_PWM0_SCUP (0x4002002CU) 52 #define REG_PWM0_SCUPUPD (0x40020030U) 53 #define REG_PWM0_IER2 (0x40020034U) 54 #define REG_PWM0_IDR2 (0x40020038U) 55 #define REG_PWM0_IMR2 (0x4002003CU) 56 #define REG_PWM0_ISR2 (0x40020040U) 57 #define REG_PWM0_OOV (0x40020044U) 58 #define REG_PWM0_OS (0x40020048U) 59 #define REG_PWM0_OSS (0x4002004CU) 60 #define REG_PWM0_OSC (0x40020050U) 61 #define REG_PWM0_OSSUPD (0x40020054U) 62 #define REG_PWM0_OSCUPD (0x40020058U) 63 #define REG_PWM0_FMR (0x4002005CU) 64 #define REG_PWM0_FSR (0x40020060U) 65 #define REG_PWM0_FCR (0x40020064U) 66 #define REG_PWM0_FPV1 (0x40020068U) 67 #define REG_PWM0_FPE (0x4002006CU) 68 #define REG_PWM0_ELMR (0x4002007CU) 69 #define REG_PWM0_SSPR (0x400200A0U) 70 #define REG_PWM0_SSPUP (0x400200A4U) 71 #define REG_PWM0_SMMR (0x400200B0U) 72 #define REG_PWM0_FPV2 (0x400200C0U) 73 #define REG_PWM0_WPCR (0x400200E4U) 74 #define REG_PWM0_WPSR (0x400200E8U) 75 #define REG_PWM0_VERSION (0x400200FCU) 76 #define REG_PWM0_CMPV0 (0x40020130U) 77 #define REG_PWM0_CMPVUPD0 (0x40020134U) 78 #define REG_PWM0_CMPM0 (0x40020138U) 79 #define REG_PWM0_CMPMUPD0 (0x4002013CU) 80 #define REG_PWM0_CMPV1 (0x40020140U) 81 #define REG_PWM0_CMPVUPD1 (0x40020144U) 82 #define REG_PWM0_CMPM1 (0x40020148U) 83 #define REG_PWM0_CMPMUPD1 (0x4002014CU) 84 #define REG_PWM0_CMPV2 (0x40020150U) 85 #define REG_PWM0_CMPVUPD2 (0x40020154U) 86 #define REG_PWM0_CMPM2 (0x40020158U) 87 #define REG_PWM0_CMPMUPD2 (0x4002015CU) 88 #define REG_PWM0_CMPV3 (0x40020160U) 89 #define REG_PWM0_CMPVUPD3 (0x40020164U) 90 #define REG_PWM0_CMPM3 (0x40020168U) 91 #define REG_PWM0_CMPMUPD3 (0x4002016CU) 92 #define REG_PWM0_CMPV4 (0x40020170U) 93 #define REG_PWM0_CMPVUPD4 (0x40020174U) 94 #define REG_PWM0_CMPM4 (0x40020178U) 95 #define REG_PWM0_CMPMUPD4 (0x4002017CU) 96 #define REG_PWM0_CMPV5 (0x40020180U) 97 #define REG_PWM0_CMPVUPD5 (0x40020184U) 98 #define REG_PWM0_CMPM5 (0x40020188U) 99 #define REG_PWM0_CMPMUPD5 (0x4002018CU) 100 #define REG_PWM0_CMPV6 (0x40020190U) 101 #define REG_PWM0_CMPVUPD6 (0x40020194U) 102 #define REG_PWM0_CMPM6 (0x40020198U) 103 #define REG_PWM0_CMPMUPD6 (0x4002019CU) 104 #define REG_PWM0_CMPV7 (0x400201A0U) 105 #define REG_PWM0_CMPVUPD7 (0x400201A4U) 106 #define REG_PWM0_CMPM7 (0x400201A8U) 107 #define REG_PWM0_CMPMUPD7 (0x400201ACU) 108 #define REG_PWM0_CMR0 (0x40020200U) 109 #define REG_PWM0_CDTY0 (0x40020204U) 110 #define REG_PWM0_CDTYUPD0 (0x40020208U) 111 #define REG_PWM0_CPRD0 (0x4002020CU) 112 #define REG_PWM0_CPRDUPD0 (0x40020210U) 113 #define REG_PWM0_CCNT0 (0x40020214U) 114 #define REG_PWM0_DT0 (0x40020218U) 115 #define REG_PWM0_DTUPD0 (0x4002021CU) 116 #define REG_PWM0_CMR1 (0x40020220U) 117 #define REG_PWM0_CDTY1 (0x40020224U) 118 #define REG_PWM0_CDTYUPD1 (0x40020228U) 119 #define REG_PWM0_CPRD1 (0x4002022CU) 120 #define REG_PWM0_CPRDUPD1 (0x40020230U) 121 #define REG_PWM0_CCNT1 (0x40020234U) 122 #define REG_PWM0_DT1 (0x40020238U) 123 #define REG_PWM0_DTUPD1 (0x4002023CU) 124 #define REG_PWM0_CMR2 (0x40020240U) 125 #define REG_PWM0_CDTY2 (0x40020244U) 126 #define REG_PWM0_CDTYUPD2 (0x40020248U) 127 #define REG_PWM0_CPRD2 (0x4002024CU) 128 #define REG_PWM0_CPRDUPD2 (0x40020250U) 129 #define REG_PWM0_CCNT2 (0x40020254U) 130 #define REG_PWM0_DT2 (0x40020258U) 131 #define REG_PWM0_DTUPD2 (0x4002025CU) 132 #define REG_PWM0_CMR3 (0x40020260U) 133 #define REG_PWM0_CDTY3 (0x40020264U) 134 #define REG_PWM0_CDTYUPD3 (0x40020268U) 135 #define REG_PWM0_CPRD3 (0x4002026CU) 136 #define REG_PWM0_CPRDUPD3 (0x40020270U) 137 #define REG_PWM0_CCNT3 (0x40020274U) 138 #define REG_PWM0_DT3 (0x40020278U) 139 #define REG_PWM0_DTUPD3 (0x4002027CU) 140 #define REG_PWM0_CMUPD0 (0x40020400U) 141 #define REG_PWM0_CMUPD1 (0x40020420U) 142 #define REG_PWM0_ETRG1 (0x4002042CU) 143 #define REG_PWM0_LEBR1 (0x40020430U) 144 #define REG_PWM0_CMUPD2 (0x40020440U) 145 #define REG_PWM0_ETRG2 (0x4002044CU) 146 #define REG_PWM0_LEBR2 (0x40020450U) 147 #define REG_PWM0_CMUPD3 (0x40020460U) 149 #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) 150 #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) 151 #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) 152 #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) 153 #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) 154 #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) 155 #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) 156 #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) 157 #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) 158 #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) 159 #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) 160 #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) 161 #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) 162 #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) 163 #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) 164 #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) 165 #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) 166 #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) 167 #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) 168 #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) 169 #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) 170 #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) 171 #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) 172 #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) 173 #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) 174 #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) 175 #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) 176 #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) 177 #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) 178 #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) 179 #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) 180 #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) 181 #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) 182 #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) 183 #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) 184 #define REG_PWM0_VERSION (*(__I uint32_t*)0x400200FCU) 185 #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) 186 #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) 187 #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) 188 #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) 189 #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) 190 #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) 191 #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) 192 #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) 193 #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) 194 #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) 195 #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) 196 #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) 197 #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) 198 #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) 199 #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) 200 #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) 201 #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) 202 #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) 203 #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) 204 #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) 205 #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) 206 #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) 207 #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) 208 #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) 209 #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) 210 #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) 211 #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) 212 #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) 213 #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) 214 #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) 215 #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) 216 #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) 217 #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) 218 #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) 219 #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) 220 #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) 221 #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) 222 #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) 223 #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) 224 #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) 225 #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) 226 #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) 227 #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) 228 #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) 229 #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) 230 #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) 231 #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) 232 #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) 233 #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) 234 #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) 235 #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) 236 #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) 237 #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) 238 #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) 239 #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) 240 #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) 241 #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) 242 #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) 243 #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) 244 #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) 245 #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) 246 #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) 247 #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) 248 #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) 249 #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) 250 #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) 251 #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) 252 #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) 253 #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) 254 #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) 255 #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) 256 #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U)