component/aes.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_AES_COMPONENT_
36 #define _SAME70_AES_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t AES_CR;
48  __IO uint32_t AES_MR;
49  __I uint32_t Reserved1[2];
50  __O uint32_t AES_IER;
51  __O uint32_t AES_IDR;
52  __I uint32_t AES_IMR;
53  __I uint32_t AES_ISR;
54  __O uint32_t AES_KEYWR[8];
55  __O uint32_t AES_IDATAR[4];
56  __I uint32_t AES_ODATAR[4];
57  __O uint32_t AES_IVR[4];
58  __IO uint32_t AES_AADLENR;
59  __IO uint32_t AES_CLENR;
60  __IO uint32_t AES_GHASHR[4];
61  __I uint32_t AES_TAGR[4];
62  __I uint32_t AES_CTRR;
63  __IO uint32_t AES_GCMHR[4];
64  __I uint32_t Reserved2[20];
65  __I uint32_t AES_VERSION;
66 } Aes;
67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
68 /* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */
69 #define AES_CR_START (0x1u << 0)
70 #define AES_CR_SWRST (0x1u << 8)
71 #define AES_CR_LOADSEED (0x1u << 16)
72 /* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */
73 #define AES_MR_CIPHER (0x1u << 0)
74 #define AES_MR_GTAGEN (0x1u << 1)
75 #define AES_MR_DUALBUFF (0x1u << 3)
76 #define AES_MR_DUALBUFF_INACTIVE (0x0u << 3)
77 #define AES_MR_DUALBUFF_ACTIVE (0x1u << 3)
78 #define AES_MR_PROCDLY_Pos 4
79 #define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos)
80 #define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
81 #define AES_MR_SMOD_Pos 8
82 #define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos)
83 #define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))
84 #define AES_MR_SMOD_MANUAL_START (0x0u << 8)
85 #define AES_MR_SMOD_AUTO_START (0x1u << 8)
86 #define AES_MR_SMOD_IDATAR0_START (0x2u << 8)
87 #define AES_MR_KEYSIZE_Pos 10
88 #define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos)
89 #define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))
90 #define AES_MR_KEYSIZE_AES128 (0x0u << 10)
91 #define AES_MR_KEYSIZE_AES192 (0x1u << 10)
92 #define AES_MR_KEYSIZE_AES256 (0x2u << 10)
93 #define AES_MR_OPMOD_Pos 12
94 #define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos)
95 #define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))
96 #define AES_MR_OPMOD_ECB (0x0u << 12)
97 #define AES_MR_OPMOD_CBC (0x1u << 12)
98 #define AES_MR_OPMOD_OFB (0x2u << 12)
99 #define AES_MR_OPMOD_CFB (0x3u << 12)
100 #define AES_MR_OPMOD_CTR (0x4u << 12)
101 #define AES_MR_OPMOD_GCM (0x5u << 12)
102 #define AES_MR_LOD (0x1u << 15)
103 #define AES_MR_CFBS_Pos 16
104 #define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos)
105 #define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))
106 #define AES_MR_CFBS_SIZE_128BIT (0x0u << 16)
107 #define AES_MR_CFBS_SIZE_64BIT (0x1u << 16)
108 #define AES_MR_CFBS_SIZE_32BIT (0x2u << 16)
109 #define AES_MR_CFBS_SIZE_16BIT (0x3u << 16)
110 #define AES_MR_CFBS_SIZE_8BIT (0x4u << 16)
111 #define AES_MR_CKEY_Pos 20
112 #define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos)
113 #define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
114 #define AES_MR_CKEY_PASSWD (0xEu << 20)
115 #define AES_MR_CMTYP1 (0x1u << 24)
116 #define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24)
117 #define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24)
118 #define AES_MR_CMTYP2 (0x1u << 25)
119 #define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25)
120 #define AES_MR_CMTYP2_PAUSE (0x1u << 25)
121 #define AES_MR_CMTYP3 (0x1u << 26)
122 #define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26)
123 #define AES_MR_CMTYP3_DUMMY (0x1u << 26)
124 #define AES_MR_CMTYP4 (0x1u << 27)
125 #define AES_MR_CMTYP4_NO_RESTART (0x0u << 27)
126 #define AES_MR_CMTYP4_RESTART (0x1u << 27)
127 #define AES_MR_CMTYP5 (0x1u << 28)
128 #define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28)
129 #define AES_MR_CMTYP5_ADDACCESS (0x1u << 28)
130 #define AES_MR_CMTYP6 (0x1u << 29)
131 #define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29)
132 #define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29)
133 /* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
134 #define AES_IER_DATRDY (0x1u << 0)
135 #define AES_IER_URAD (0x1u << 8)
136 #define AES_IER_TAGRDY (0x1u << 16)
137 /* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
138 #define AES_IDR_DATRDY (0x1u << 0)
139 #define AES_IDR_URAD (0x1u << 8)
140 #define AES_IDR_TAGRDY (0x1u << 16)
141 /* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
142 #define AES_IMR_DATRDY (0x1u << 0)
143 #define AES_IMR_URAD (0x1u << 8)
144 #define AES_IMR_TAGRDY (0x1u << 16)
145 /* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */
146 #define AES_ISR_DATRDY (0x1u << 0)
147 #define AES_ISR_URAD (0x1u << 8)
148 #define AES_ISR_URAT_Pos 12
149 #define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos)
150 #define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12)
151 #define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12)
152 #define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12)
153 #define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12)
154 #define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12)
155 #define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12)
156 #define AES_ISR_TAGRDY (0x1u << 16)
157 /* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */
158 #define AES_KEYWR_KEYW_Pos 0
159 #define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos)
160 #define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
161 /* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */
162 #define AES_IDATAR_IDATA_Pos 0
163 #define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos)
164 #define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
165 /* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */
166 #define AES_ODATAR_ODATA_Pos 0
167 #define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos)
168 /* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */
169 #define AES_IVR_IV_Pos 0
170 #define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos)
171 #define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
172 /* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */
173 #define AES_AADLENR_AADLEN_Pos 0
174 #define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos)
175 #define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
176 /* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */
177 #define AES_CLENR_CLEN_Pos 0
178 #define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos)
179 #define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
180 /* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */
181 #define AES_GHASHR_GHASH_Pos 0
182 #define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos)
183 #define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
184 /* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */
185 #define AES_TAGR_TAG_Pos 0
186 #define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos)
187 /* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */
188 #define AES_CTRR_CTR_Pos 0
189 #define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos)
190 /* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */
191 #define AES_GCMHR_H_Pos 0
192 #define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos)
193 #define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))
194 /* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */
195 #define AES_VERSION_VERSION_Pos 0
196 #define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos)
197 #define AES_VERSION_MFN_Pos 16
198 #define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos)
201 
202 
203 #endif /* _SAME70_AES_COMPONENT_ */
Aes::AES_CR
__O uint32_t AES_CR
(Aes Offset: 0x00) Control Register
Definition: component/aes.h:47
__IO
#define __IO
Definition: core_cm7.h:266
__O
#define __O
Definition: core_cm7.h:265
Aes::AES_IDR
__O uint32_t AES_IDR
(Aes Offset: 0x14) Interrupt Disable Register
Definition: component/aes.h:51
Aes::AES_CTRR
__I uint32_t AES_CTRR
(Aes Offset: 0x98) GCM Encryption Counter Value Register
Definition: component/aes.h:62
Aes
Aes hardware registers.
Definition: component/aes.h:46
Aes::AES_ISR
__I uint32_t AES_ISR
(Aes Offset: 0x1C) Interrupt Status Register
Definition: component/aes.h:53
Aes::AES_AADLENR
__IO uint32_t AES_AADLENR
(Aes Offset: 0x70) Additional Authenticated Data Length Register
Definition: component/aes.h:58
Aes::AES_IER
__O uint32_t AES_IER
(Aes Offset: 0x10) Interrupt Enable Register
Definition: component/aes.h:50
Aes::AES_MR
__IO uint32_t AES_MR
(Aes Offset: 0x04) Mode Register
Definition: component/aes.h:48
Aes::AES_CLENR
__IO uint32_t AES_CLENR
(Aes Offset: 0x74) Plaintext/Ciphertext Length Register
Definition: component/aes.h:59
Aes::AES_VERSION
__I uint32_t AES_VERSION
(Aes Offset: 0xFC) Version Register
Definition: component/aes.h:65
__I
#define __I
Definition: core_cm7.h:263
Aes::AES_IMR
__I uint32_t AES_IMR
(Aes Offset: 0x18) Interrupt Mask Register
Definition: component/aes.h:52

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autogenerated on Sun Feb 28 2021 03:17:08