Hsmci Struct Reference

Hsmci hardware registers. More...

#include <hsmci.h>

Public Attributes
__IO uint32_t	HSMCI_ARGR
	(Hsmci Offset: 0x10) Argument Register More...
__IO uint32_t	HSMCI_BLKR
	(Hsmci Offset: 0x18) Block Register More...
__IO uint32_t	HSMCI_CFG
	(Hsmci Offset: 0x54) Configuration Register More...
__O uint32_t	HSMCI_CMDR
	(Hsmci Offset: 0x14) Command Register More...
__O uint32_t	HSMCI_CR
	(Hsmci Offset: 0x00) Control Register More...
__IO uint32_t	HSMCI_CSTOR
	(Hsmci Offset: 0x1C) Completion Signal Timeout Register More...
__IO uint32_t	HSMCI_DMA
	(Hsmci Offset: 0x50) DMA Configuration Register More...
__IO uint32_t	HSMCI_DTOR
	(Hsmci Offset: 0x08) Data Timeout Register More...
__IO uint32_t	HSMCI_FIFO [256]
	(Hsmci Offset: 0x200) FIFO Memory Aperture0 More...
__O uint32_t	HSMCI_IDR
	(Hsmci Offset: 0x48) Interrupt Disable Register More...
__O uint32_t	HSMCI_IER
	(Hsmci Offset: 0x44) Interrupt Enable Register More...
__I uint32_t	HSMCI_IMR
	(Hsmci Offset: 0x4C) Interrupt Mask Register More...
__IO uint32_t	HSMCI_MR
	(Hsmci Offset: 0x04) Mode Register More...
__I uint32_t	HSMCI_RDR
	(Hsmci Offset: 0x30) Receive Data Register More...
__I uint32_t	HSMCI_RSPR [4]
	(Hsmci Offset: 0x20) Response Register More...
__IO uint32_t	HSMCI_SDCR
	(Hsmci Offset: 0x0C) SD/SDIO Card Register More...
__I uint32_t	HSMCI_SR
	(Hsmci Offset: 0x40) Status Register More...
__O uint32_t	HSMCI_TDR
	(Hsmci Offset: 0x34) Transmit Data Register More...
__I uint32_t	HSMCI_VERSION
	(Hsmci Offset: 0xFC) Version Register More...
__IO uint32_t	HSMCI_WPMR
	(Hsmci Offset: 0xE4) Write Protection Mode Register More...
__I uint32_t	HSMCI_WPSR
	(Hsmci Offset: 0xE8) Write Protection Status Register More...
__I uint32_t	Reserved1 [2]
__I uint32_t	Reserved2 [35]
__I uint32_t	Reserved3 [4]
__I uint32_t	Reserved4 [64]

Detailed Description

Hsmci hardware registers.

Definition at line 46 of file utils/cmsis/same70/include/component/hsmci.h.

Member Data Documentation

HSMCI_ARGR

__IO uint32_t Hsmci::HSMCI_ARGR

(Hsmci Offset: 0x10) Argument Register

Definition at line 51 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_BLKR

__IO uint32_t Hsmci::HSMCI_BLKR

(Hsmci Offset: 0x18) Block Register

Definition at line 53 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_CFG

__IO uint32_t Hsmci::HSMCI_CFG

(Hsmci Offset: 0x54) Configuration Register

Definition at line 64 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_CMDR

__O uint32_t Hsmci::HSMCI_CMDR

(Hsmci Offset: 0x14) Command Register

Definition at line 52 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_CR

__O uint32_t Hsmci::HSMCI_CR

(Hsmci Offset: 0x00) Control Register

Definition at line 47 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_CSTOR

__IO uint32_t Hsmci::HSMCI_CSTOR

(Hsmci Offset: 0x1C) Completion Signal Timeout Register

Definition at line 54 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_DMA

__IO uint32_t Hsmci::HSMCI_DMA

(Hsmci Offset: 0x50) DMA Configuration Register

Definition at line 63 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_DTOR

__IO uint32_t Hsmci::HSMCI_DTOR

(Hsmci Offset: 0x08) Data Timeout Register

Definition at line 49 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_FIFO

__IO uint32_t Hsmci::HSMCI_FIFO[256]

(Hsmci Offset: 0x200) FIFO Memory Aperture0

Definition at line 71 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_IDR

__O uint32_t Hsmci::HSMCI_IDR

(Hsmci Offset: 0x48) Interrupt Disable Register

Definition at line 61 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_IER

__O uint32_t Hsmci::HSMCI_IER

(Hsmci Offset: 0x44) Interrupt Enable Register

Definition at line 60 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_IMR

__I uint32_t Hsmci::HSMCI_IMR

(Hsmci Offset: 0x4C) Interrupt Mask Register

Definition at line 62 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_MR

__IO uint32_t Hsmci::HSMCI_MR

(Hsmci Offset: 0x04) Mode Register

Definition at line 48 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_RDR

__I uint32_t Hsmci::HSMCI_RDR

(Hsmci Offset: 0x30) Receive Data Register

Definition at line 56 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_RSPR

__I uint32_t Hsmci::HSMCI_RSPR[4]

(Hsmci Offset: 0x20) Response Register

Definition at line 55 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_SDCR

__IO uint32_t Hsmci::HSMCI_SDCR

(Hsmci Offset: 0x0C) SD/SDIO Card Register

Definition at line 50 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_SR

__I uint32_t Hsmci::HSMCI_SR

(Hsmci Offset: 0x40) Status Register

Definition at line 59 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_TDR

__O uint32_t Hsmci::HSMCI_TDR

(Hsmci Offset: 0x34) Transmit Data Register

Definition at line 57 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_VERSION

__I uint32_t Hsmci::HSMCI_VERSION

(Hsmci Offset: 0xFC) Version Register

Definition at line 69 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_WPMR

__IO uint32_t Hsmci::HSMCI_WPMR

(Hsmci Offset: 0xE4) Write Protection Mode Register

Definition at line 66 of file utils/cmsis/same70/include/component/hsmci.h.

HSMCI_WPSR

__I uint32_t Hsmci::HSMCI_WPSR

(Hsmci Offset: 0xE8) Write Protection Status Register

Definition at line 67 of file utils/cmsis/same70/include/component/hsmci.h.

Reserved1

__I uint32_t Hsmci::Reserved1[2]

Definition at line 58 of file utils/cmsis/same70/include/component/hsmci.h.

Reserved2

__I uint32_t Hsmci::Reserved2[35]

Definition at line 65 of file utils/cmsis/same70/include/component/hsmci.h.

Reserved3

__I uint32_t Hsmci::Reserved3[4]

Definition at line 68 of file utils/cmsis/same70/include/component/hsmci.h.

Reserved4

__I uint32_t Hsmci::Reserved4[64]

Definition at line 70 of file utils/cmsis/same70/include/component/hsmci.h.

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The documentation for this struct was generated from the following file:

• utils/cmsis/same70/include/component/hsmci.h