Pmc hardware registers. More...
#include <pmc.h>
Public Attributes | |
| __IO uint32_t | CKGR_MCFR |
| (Pmc Offset: 0x0024) Main Clock Frequency Register More... | |
| __IO uint32_t | CKGR_MOR |
| (Pmc Offset: 0x0020) Main Oscillator Register More... | |
| __IO uint32_t | CKGR_PLLAR |
| (Pmc Offset: 0x0028) PLLA Register More... | |
| __IO uint32_t | CKGR_UCKR |
| (Pmc Offset: 0x001C) UTMI Clock Register More... | |
| __IO uint32_t | PMC_APLLACR |
| (Pmc Offset: 0x0158) Audio PLL Analog Configuration Register More... | |
| __O uint32_t | PMC_FOCR |
| (Pmc Offset: 0x0078) Fault Output Clear Register More... | |
| __IO uint32_t | PMC_FSMR |
| (Pmc Offset: 0x0070) Fast Startup Mode Register More... | |
| __IO uint32_t | PMC_FSPR |
| (Pmc Offset: 0x0074) Fast Startup Polarity Register More... | |
| __O uint32_t | PMC_IDR |
| (Pmc Offset: 0x0064) Interrupt Disable Register More... | |
| __O uint32_t | PMC_IER |
| (Pmc Offset: 0x0060) Interrupt Enable Register More... | |
| __I uint32_t | PMC_IMR |
| (Pmc Offset: 0x006C) Interrupt Mask Register More... | |
| __IO uint32_t | PMC_MCKR |
| (Pmc Offset: 0x0030) Master Clock Register More... | |
| __IO uint32_t | PMC_OCR |
| (Pmc Offset: 0x0110) Oscillator Calibration Register More... | |
| __O uint32_t | PMC_PCDR0 |
| (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 More... | |
| __O uint32_t | PMC_PCDR1 |
| (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 More... | |
| __O uint32_t | PMC_PCER0 |
| (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 More... | |
| __O uint32_t | PMC_PCER1 |
| (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 More... | |
| __IO uint32_t | PMC_PCK [8] |
| (Pmc Offset: 0x40) Programmable Clock Register (chid = 0) More... | |
| __IO uint32_t | PMC_PCR |
| (Pmc Offset: 0x010C) Peripheral Control Register More... | |
| __I uint32_t | PMC_PCSR0 |
| (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 More... | |
| __I uint32_t | PMC_PCSR1 |
| (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 More... | |
| __IO uint32_t | PMC_PMMR |
| (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register More... | |
| __O uint32_t | PMC_SCDR |
| (Pmc Offset: 0x0004) System Clock Disable Register More... | |
| __O uint32_t | PMC_SCER |
| (Pmc Offset: 0x0000) System Clock Enable Register More... | |
| __I uint32_t | PMC_SCSR |
| (Pmc Offset: 0x0008) System Clock Status Register More... | |
| __I uint32_t | PMC_SLPWK_AIPR |
| (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register More... | |
| __I uint32_t | PMC_SLPWK_ASR0 |
| (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 More... | |
| __I uint32_t | PMC_SLPWK_ASR1 |
| (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 More... | |
| __O uint32_t | PMC_SLPWK_DR0 |
| (Pmc Offset: 0x0118) SleepWalking Disable Register 0 More... | |
| __O uint32_t | PMC_SLPWK_DR1 |
| (Pmc Offset: 0x0138) SleepWalking Disable Register 1 More... | |
| __O uint32_t | PMC_SLPWK_ER0 |
| (Pmc Offset: 0x0114) SleepWalking Enable Register 0 More... | |
| __O uint32_t | PMC_SLPWK_ER1 |
| (Pmc Offset: 0x0134) SleepWalking Enable Register 1 More... | |
| __I uint32_t | PMC_SLPWK_SR0 |
| (Pmc Offset: 0x011C) SleepWalking Status Register 0 More... | |
| __I uint32_t | PMC_SLPWK_SR1 |
| (Pmc Offset: 0x013C) SleepWalking Status Register 1 More... | |
| __I uint32_t | PMC_SR |
| (Pmc Offset: 0x0068) Status Register More... | |
| __IO uint32_t | PMC_USB |
| (Pmc Offset: 0x0038) USB Clock Register More... | |
| __I uint32_t | PMC_VERSION |
| (Pmc Offset: 0x00FC) Version Register More... | |
| __IO uint32_t | PMC_WMST |
| (Pmc Offset: 0x015C) Wait Mode Startup Time Register More... | |
| __IO uint32_t | PMC_WPMR |
| (Pmc Offset: 0x00E4) Write Protection Mode Register More... | |
| __I uint32_t | PMC_WPSR |
| (Pmc Offset: 0x00E8) Write Protection Status Register More... | |
| __I uint32_t | Reserved1 [1] |
| __I uint32_t | Reserved2 [1] |
| __I uint32_t | Reserved3 [1] |
| __I uint32_t | Reserved4 [1] |
| __I uint32_t | Reserved5 [26] |
| __I uint32_t | Reserved6 [4] |
| __I uint32_t | Reserved7 [3] |
| __I uint32_t | Reserved8 [4] |
Pmc hardware registers.
Definition at line 46 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::CKGR_MCFR |
(Pmc Offset: 0x0024) Main Clock Frequency Register
Definition at line 56 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::CKGR_MOR |
(Pmc Offset: 0x0020) Main Oscillator Register
Definition at line 55 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::CKGR_PLLAR |
(Pmc Offset: 0x0028) PLLA Register
Definition at line 57 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::CKGR_UCKR |
(Pmc Offset: 0x001C) UTMI Clock Register
Definition at line 54 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_APLLACR |
(Pmc Offset: 0x0158) Audio PLL Analog Configuration Register
Definition at line 93 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_FOCR |
(Pmc Offset: 0x0078) Fault Output Clear Register
Definition at line 70 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_FSMR |
(Pmc Offset: 0x0070) Fast Startup Mode Register
Definition at line 68 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_FSPR |
(Pmc Offset: 0x0074) Fast Startup Polarity Register
Definition at line 69 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_IDR |
(Pmc Offset: 0x0064) Interrupt Disable Register
Definition at line 65 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_IER |
(Pmc Offset: 0x0060) Interrupt Enable Register
Definition at line 64 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_IMR |
(Pmc Offset: 0x006C) Interrupt Mask Register
Definition at line 67 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_MCKR |
(Pmc Offset: 0x0030) Master Clock Register
Definition at line 59 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_OCR |
(Pmc Offset: 0x0110) Oscillator Calibration Register
Definition at line 80 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_PCDR0 |
(Pmc Offset: 0x0014) Peripheral Clock Disable Register 0
Definition at line 52 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_PCDR1 |
(Pmc Offset: 0x0104) Peripheral Clock Disable Register 1
Definition at line 77 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_PCER0 |
(Pmc Offset: 0x0010) Peripheral Clock Enable Register 0
Definition at line 51 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_PCER1 |
(Pmc Offset: 0x0100) Peripheral Clock Enable Register 1
Definition at line 76 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_PCK[8] |
(Pmc Offset: 0x40) Programmable Clock Register (chid = 0)
Definition at line 63 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_PCR |
(Pmc Offset: 0x010C) Peripheral Control Register
Definition at line 79 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_PCSR0 |
(Pmc Offset: 0x0018) Peripheral Clock Status Register 0
Definition at line 53 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_PCSR1 |
(Pmc Offset: 0x0108) Peripheral Clock Status Register 1
Definition at line 78 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_PMMR |
(Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register
Definition at line 86 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_SCDR |
(Pmc Offset: 0x0004) System Clock Disable Register
Definition at line 48 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_SCER |
(Pmc Offset: 0x0000) System Clock Enable Register
Definition at line 47 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_SCSR |
(Pmc Offset: 0x0008) System Clock Status Register
Definition at line 49 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_SLPWK_AIPR |
(Pmc Offset: 0x0144) SleepWalking Activity In Progress Register
Definition at line 91 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_SLPWK_ASR0 |
(Pmc Offset: 0x0120) SleepWalking Activity Status Register 0
Definition at line 84 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_SLPWK_ASR1 |
(Pmc Offset: 0x0140) SleepWalking Activity Status Register 1
Definition at line 90 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_SLPWK_DR0 |
(Pmc Offset: 0x0118) SleepWalking Disable Register 0
Definition at line 82 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_SLPWK_DR1 |
(Pmc Offset: 0x0138) SleepWalking Disable Register 1
Definition at line 88 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_SLPWK_ER0 |
(Pmc Offset: 0x0114) SleepWalking Enable Register 0
Definition at line 81 of file utils/cmsis/same70/include/component/pmc.h.
| __O uint32_t Pmc::PMC_SLPWK_ER1 |
(Pmc Offset: 0x0134) SleepWalking Enable Register 1
Definition at line 87 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_SLPWK_SR0 |
(Pmc Offset: 0x011C) SleepWalking Status Register 0
Definition at line 83 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_SLPWK_SR1 |
(Pmc Offset: 0x013C) SleepWalking Status Register 1
Definition at line 89 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_SR |
(Pmc Offset: 0x0068) Status Register
Definition at line 66 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_USB |
(Pmc Offset: 0x0038) USB Clock Register
Definition at line 61 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_VERSION |
(Pmc Offset: 0x00FC) Version Register
Definition at line 75 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_WMST |
(Pmc Offset: 0x015C) Wait Mode Startup Time Register
Definition at line 94 of file utils/cmsis/same70/include/component/pmc.h.
| __IO uint32_t Pmc::PMC_WPMR |
(Pmc Offset: 0x00E4) Write Protection Mode Register
Definition at line 72 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::PMC_WPSR |
(Pmc Offset: 0x00E8) Write Protection Status Register
Definition at line 73 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved1[1] |
Definition at line 50 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved2[1] |
Definition at line 58 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved3[1] |
Definition at line 60 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved4[1] |
Definition at line 62 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved5[26] |
Definition at line 71 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved6[4] |
Definition at line 74 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved7[3] |
Definition at line 85 of file utils/cmsis/same70/include/component/pmc.h.
| __I uint32_t Pmc::Reserved8[4] |
Definition at line 92 of file utils/cmsis/same70/include/component/pmc.h.