instance/dacc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_DACC_INSTANCE_
36 #define _SAME70_DACC_INSTANCE_
37 
38 /* ========== Register definition for DACC peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_DACC_CR (0x40040000U)
41  #define REG_DACC_MR (0x40040004U)
42  #define REG_DACC_TRIGR (0x40040008U)
43  #define REG_DACC_CHER (0x40040010U)
44  #define REG_DACC_CHDR (0x40040014U)
45  #define REG_DACC_CHSR (0x40040018U)
46  #define REG_DACC_CDR (0x4004001CU)
47  #define REG_DACC_IER (0x40040024U)
48  #define REG_DACC_IDR (0x40040028U)
49  #define REG_DACC_IMR (0x4004002CU)
50  #define REG_DACC_ISR (0x40040030U)
51  #define REG_DACC_ACR (0x40040094U)
52  #define REG_DACC_WPMR (0x400400E4U)
53  #define REG_DACC_WPSR (0x400400E8U)
54  #define REG_DACC_VERSION (0x400400FCU)
55 #else
56  #define REG_DACC_CR (*(__O uint32_t*)0x40040000U)
57  #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U)
58  #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U)
59  #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U)
60  #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U)
61  #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U)
62  #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU)
63  #define REG_DACC_IER (*(__O uint32_t*)0x40040024U)
64  #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U)
65  #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU)
66  #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U)
67  #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U)
68  #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U)
69  #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U)
70  #define REG_DACC_VERSION (*(__I uint32_t*)0x400400FCU)
71 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
72 
73 #endif /* _SAME70_DACC_INSTANCE_ */

inertial_sense_ros
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autogenerated on Sun Feb 28 2021 03:17:57