MIMXRT1052.h
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1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1052CVJ5B
4 ** MIMXRT1052CVL5B
5 ** MIMXRT1052DVJ6B
6 ** MIMXRT1052DVL6B
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2
15 ** Version: rev. 1.3, 2019-04-29
16 ** Build: b191115
17 **
18 ** Abstract:
19 ** CMSIS Peripheral Access Layer for MIMXRT1052
20 **
21 ** Copyright 1997-2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2019 NXP
23 ** All rights reserved.
24 **
25 ** SPDX-License-Identifier: BSD-3-Clause
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 0.1 (2017-01-10)
32 ** Initial version.
33 ** - rev. 1.0 (2018-09-21)
34 ** Update interrupt vector table and dma request source.
35 ** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
36 ** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
37 ** - rev. 1.1 (2018-11-16)
38 ** Update header files to align with IMXRT1050RM Rev.1.
39 ** - rev. 1.2 (2018-11-27)
40 ** Update header files to align with IMXRT1050RM Rev.2.1.
41 ** - rev. 1.3 (2019-04-29)
42 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
43 **
44 ** ###################################################################
45 */
46 
56 #ifndef _MIMXRT1052_H_
57 #define _MIMXRT1052_H_
61 #define MCU_MEM_MAP_VERSION 0x0100U
62 
63 #define MCU_MEM_MAP_VERSION_MINOR 0x0003U
64 
65 
66 /* ----------------------------------------------------------------------------
67  -- Interrupt vector numbers
68  ---------------------------------------------------------------------------- */
69 
76 #define NUMBER_OF_INT_VECTORS 168
78 typedef enum IRQn {
79  /* Auxiliary constants */
80  NotAvail_IRQn = -128,
82  /* Core interrupts */
83  NonMaskableInt_IRQn = -14,
84  HardFault_IRQn = -13,
85  MemoryManagement_IRQn = -12,
86  BusFault_IRQn = -11,
87  UsageFault_IRQn = -10,
88  SVCall_IRQn = -5,
89  DebugMonitor_IRQn = -4,
90  PendSV_IRQn = -2,
91  SysTick_IRQn = -1,
93  /* Device specific interrupts */
94  DMA0_DMA16_IRQn = 0,
95  DMA1_DMA17_IRQn = 1,
96  DMA2_DMA18_IRQn = 2,
97  DMA3_DMA19_IRQn = 3,
98  DMA4_DMA20_IRQn = 4,
99  DMA5_DMA21_IRQn = 5,
100  DMA6_DMA22_IRQn = 6,
101  DMA7_DMA23_IRQn = 7,
102  DMA8_DMA24_IRQn = 8,
103  DMA9_DMA25_IRQn = 9,
104  DMA10_DMA26_IRQn = 10,
105  DMA11_DMA27_IRQn = 11,
106  DMA12_DMA28_IRQn = 12,
107  DMA13_DMA29_IRQn = 13,
108  DMA14_DMA30_IRQn = 14,
109  DMA15_DMA31_IRQn = 15,
110  DMA_ERROR_IRQn = 16,
111  CTI0_ERROR_IRQn = 17,
112  CTI1_ERROR_IRQn = 18,
113  CORE_IRQn = 19,
114  LPUART1_IRQn = 20,
115  LPUART2_IRQn = 21,
116  LPUART3_IRQn = 22,
117  LPUART4_IRQn = 23,
118  LPUART5_IRQn = 24,
119  LPUART6_IRQn = 25,
120  LPUART7_IRQn = 26,
121  LPUART8_IRQn = 27,
122  LPI2C1_IRQn = 28,
123  LPI2C2_IRQn = 29,
124  LPI2C3_IRQn = 30,
125  LPI2C4_IRQn = 31,
126  LPSPI1_IRQn = 32,
127  LPSPI2_IRQn = 33,
128  LPSPI3_IRQn = 34,
129  LPSPI4_IRQn = 35,
130  CAN1_IRQn = 36,
131  CAN2_IRQn = 37,
132  FLEXRAM_IRQn = 38,
133  KPP_IRQn = 39,
134  TSC_DIG_IRQn = 40,
135  GPR_IRQ_IRQn = 41,
136  LCDIF_IRQn = 42,
137  CSI_IRQn = 43,
138  PXP_IRQn = 44,
139  WDOG2_IRQn = 45,
140  SNVS_HP_WRAPPER_IRQn = 46,
141  SNVS_HP_WRAPPER_TZ_IRQn = 47,
142  SNVS_LP_WRAPPER_IRQn = 48,
143  CSU_IRQn = 49,
144  DCP_IRQn = 50,
145  DCP_VMI_IRQn = 51,
146  Reserved68_IRQn = 52,
147  TRNG_IRQn = 53,
148  SJC_IRQn = 54,
149  BEE_IRQn = 55,
150  SAI1_IRQn = 56,
151  SAI2_IRQn = 57,
152  SAI3_RX_IRQn = 58,
153  SAI3_TX_IRQn = 59,
154  SPDIF_IRQn = 60,
155  PMU_EVENT_IRQn = 61,
156  Reserved78_IRQn = 62,
157  TEMP_LOW_HIGH_IRQn = 63,
158  TEMP_PANIC_IRQn = 64,
159  USB_PHY1_IRQn = 65,
160  USB_PHY2_IRQn = 66,
161  ADC1_IRQn = 67,
162  ADC2_IRQn = 68,
163  DCDC_IRQn = 69,
164  Reserved86_IRQn = 70,
165  Reserved87_IRQn = 71,
166  GPIO1_INT0_IRQn = 72,
167  GPIO1_INT1_IRQn = 73,
168  GPIO1_INT2_IRQn = 74,
169  GPIO1_INT3_IRQn = 75,
170  GPIO1_INT4_IRQn = 76,
171  GPIO1_INT5_IRQn = 77,
172  GPIO1_INT6_IRQn = 78,
173  GPIO1_INT7_IRQn = 79,
174  GPIO1_Combined_0_15_IRQn = 80,
175  GPIO1_Combined_16_31_IRQn = 81,
176  GPIO2_Combined_0_15_IRQn = 82,
177  GPIO2_Combined_16_31_IRQn = 83,
178  GPIO3_Combined_0_15_IRQn = 84,
179  GPIO3_Combined_16_31_IRQn = 85,
180  GPIO4_Combined_0_15_IRQn = 86,
181  GPIO4_Combined_16_31_IRQn = 87,
182  GPIO5_Combined_0_15_IRQn = 88,
183  GPIO5_Combined_16_31_IRQn = 89,
184  FLEXIO1_IRQn = 90,
185  FLEXIO2_IRQn = 91,
186  WDOG1_IRQn = 92,
187  RTWDOG_IRQn = 93,
188  EWM_IRQn = 94,
189  CCM_1_IRQn = 95,
190  CCM_2_IRQn = 96,
191  GPC_IRQn = 97,
192  SRC_IRQn = 98,
193  Reserved115_IRQn = 99,
194  GPT1_IRQn = 100,
195  GPT2_IRQn = 101,
196  PWM1_0_IRQn = 102,
197  PWM1_1_IRQn = 103,
198  PWM1_2_IRQn = 104,
199  PWM1_3_IRQn = 105,
200  PWM1_FAULT_IRQn = 106,
201  Reserved123_IRQn = 107,
202  FLEXSPI_IRQn = 108,
203  SEMC_IRQn = 109,
204  USDHC1_IRQn = 110,
205  USDHC2_IRQn = 111,
206  USB_OTG2_IRQn = 112,
207  USB_OTG1_IRQn = 113,
208  ENET_IRQn = 114,
209  ENET_1588_Timer_IRQn = 115,
210  XBAR1_IRQ_0_1_IRQn = 116,
211  XBAR1_IRQ_2_3_IRQn = 117,
212  ADC_ETC_IRQ0_IRQn = 118,
213  ADC_ETC_IRQ1_IRQn = 119,
214  ADC_ETC_IRQ2_IRQn = 120,
215  ADC_ETC_ERROR_IRQ_IRQn = 121,
216  PIT_IRQn = 122,
217  ACMP1_IRQn = 123,
218  ACMP2_IRQn = 124,
219  ACMP3_IRQn = 125,
220  ACMP4_IRQn = 126,
221  Reserved143_IRQn = 127,
222  Reserved144_IRQn = 128,
223  ENC1_IRQn = 129,
224  ENC2_IRQn = 130,
225  ENC3_IRQn = 131,
226  ENC4_IRQn = 132,
227  TMR1_IRQn = 133,
228  TMR2_IRQn = 134,
229  TMR3_IRQn = 135,
230  TMR4_IRQn = 136,
231  PWM2_0_IRQn = 137,
232  PWM2_1_IRQn = 138,
233  PWM2_2_IRQn = 139,
234  PWM2_3_IRQn = 140,
235  PWM2_FAULT_IRQn = 141,
236  PWM3_0_IRQn = 142,
237  PWM3_1_IRQn = 143,
238  PWM3_2_IRQn = 144,
239  PWM3_3_IRQn = 145,
240  PWM3_FAULT_IRQn = 146,
241  PWM4_0_IRQn = 147,
242  PWM4_1_IRQn = 148,
243  PWM4_2_IRQn = 149,
244  PWM4_3_IRQn = 150,
245  PWM4_FAULT_IRQn = 151
246 } IRQn_Type;
247  /* end of group Interrupt_vector_numbers */
251 
252 
253 /* ----------------------------------------------------------------------------
254  -- Cortex M7 Core Configuration
255  ---------------------------------------------------------------------------- */
256 
262 #define __MPU_PRESENT 1
263 #define __ICACHE_PRESENT 1
264 #define __DCACHE_PRESENT 1
265 #define __DTCM_PRESENT 1
266 #define __NVIC_PRIO_BITS 4
267 #define __Vendor_SysTickConfig 0
268 #define __FPU_PRESENT 1
270 #include "core_cm7.h" /* Core Peripheral Access Layer */
271 #include "system_MIMXRT1052.h" /* Device specific configuration file */
272  /* end of group Cortex_Core_Configuration */
276 
277 
278 /* ----------------------------------------------------------------------------
279  -- Mapping Information
280  ---------------------------------------------------------------------------- */
281 
293 /*******************************************************************************
294  * Definitions
295  ******************************************************************************/
296 
304 typedef enum _dma_request_source
305 {
306  kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U,
307  kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U,
308  kDmaRequestMuxLPUART1Tx = 2|0x100U,
309  kDmaRequestMuxLPUART1Rx = 3|0x100U,
310  kDmaRequestMuxLPUART3Tx = 4|0x100U,
311  kDmaRequestMuxLPUART3Rx = 5|0x100U,
312  kDmaRequestMuxLPUART5Tx = 6|0x100U,
313  kDmaRequestMuxLPUART5Rx = 7|0x100U,
314  kDmaRequestMuxLPUART7Tx = 8|0x100U,
315  kDmaRequestMuxLPUART7Rx = 9|0x100U,
316  kDmaRequestMuxCSI = 12|0x100U,
317  kDmaRequestMuxLPSPI1Rx = 13|0x100U,
318  kDmaRequestMuxLPSPI1Tx = 14|0x100U,
319  kDmaRequestMuxLPSPI3Rx = 15|0x100U,
320  kDmaRequestMuxLPSPI3Tx = 16|0x100U,
321  kDmaRequestMuxLPI2C1 = 17|0x100U,
322  kDmaRequestMuxLPI2C3 = 18|0x100U,
323  kDmaRequestMuxSai1Rx = 19|0x100U,
324  kDmaRequestMuxSai1Tx = 20|0x100U,
325  kDmaRequestMuxSai2Rx = 21|0x100U,
326  kDmaRequestMuxSai2Tx = 22|0x100U,
327  kDmaRequestMuxADC_ETC = 23|0x100U,
328  kDmaRequestMuxADC1 = 24|0x100U,
329  kDmaRequestMuxACMP1 = 25|0x100U,
330  kDmaRequestMuxACMP3 = 26|0x100U,
331  kDmaRequestMuxFlexSPIRx = 28|0x100U,
332  kDmaRequestMuxFlexSPITx = 29|0x100U,
333  kDmaRequestMuxXBAR1Request0 = 30|0x100U,
334  kDmaRequestMuxXBAR1Request1 = 31|0x100U,
335  kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U,
336  kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U,
337  kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U,
338  kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U,
339  kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U,
340  kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,
341  kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U,
342  kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U,
343  kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U,
344  kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U,
345  kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U,
346  kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U,
347  kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U,
348  kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,
349  kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U,
350  kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U,
351  kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,
352  kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,
353  kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,
354  kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,
355  kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U,
356  kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U,
357  kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U,
358  kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U,
359  kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U,
360  kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U,
361  kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U,
362  kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U,
363  kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U,
364  kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U,
365  kDmaRequestMuxLPUART2Tx = 66|0x100U,
366  kDmaRequestMuxLPUART2Rx = 67|0x100U,
367  kDmaRequestMuxLPUART4Tx = 68|0x100U,
368  kDmaRequestMuxLPUART4Rx = 69|0x100U,
369  kDmaRequestMuxLPUART6Tx = 70|0x100U,
370  kDmaRequestMuxLPUART6Rx = 71|0x100U,
371  kDmaRequestMuxLPUART8Tx = 72|0x100U,
372  kDmaRequestMuxLPUART8Rx = 73|0x100U,
373  kDmaRequestMuxPxp = 75|0x100U,
374  kDmaRequestMuxLCDIF = 76|0x100U,
375  kDmaRequestMuxLPSPI2Rx = 77|0x100U,
376  kDmaRequestMuxLPSPI2Tx = 78|0x100U,
377  kDmaRequestMuxLPSPI4Rx = 79|0x100U,
378  kDmaRequestMuxLPSPI4Tx = 80|0x100U,
379  kDmaRequestMuxLPI2C2 = 81|0x100U,
380  kDmaRequestMuxLPI2C4 = 82|0x100U,
381  kDmaRequestMuxSai3Rx = 83|0x100U,
382  kDmaRequestMuxSai3Tx = 84|0x100U,
383  kDmaRequestMuxSpdifRx = 85|0x100U,
384  kDmaRequestMuxSpdifTx = 86|0x100U,
385  kDmaRequestMuxADC2 = 88|0x100U,
386  kDmaRequestMuxACMP2 = 89|0x100U,
387  kDmaRequestMuxACMP4 = 90|0x100U,
388  kDmaRequestMuxEnetTimer0 = 92|0x100U,
389  kDmaRequestMuxEnetTimer1 = 93|0x100U,
390  kDmaRequestMuxXBAR1Request2 = 94|0x100U,
391  kDmaRequestMuxXBAR1Request3 = 95|0x100U,
392  kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U,
393  kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U,
394  kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U,
395  kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U,
396  kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U,
397  kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U,
398  kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,
399  kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U,
400  kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U,
401  kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U,
402  kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U,
403  kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U,
404  kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U,
405  kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U,
406  kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,
407  kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U,
408  kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,
409  kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,
410  kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,
411  kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,
412  kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U,
413  kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U,
414  kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U,
415  kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U,
416  kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U,
417  kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U,
418  kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U,
419  kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U,
420 } dma_request_source_t;
421 
422 /* @} */
423 
428 /*******************************************************************************
429  * Definitions
430 *******************************************************************************/
431 
437 typedef enum _iomuxc_sw_mux_ctl_pad
438 {
439  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U,
440  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U,
441  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U,
442  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,
443  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U,
444  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U,
445  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U,
446  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,
447  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U,
448  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U,
449  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U,
450  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,
451  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U,
452  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U,
453  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U,
454  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,
455  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U,
456  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U,
457  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U,
458  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,
459  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U,
460  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U,
461  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U,
462  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,
463  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U,
464  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U,
465  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U,
466  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,
467  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U,
468  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U,
469  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U,
470  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,
471  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U,
472  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U,
473  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U,
474  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,
475  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U,
476  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U,
477  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U,
478  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,
479  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U,
480  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U,
481  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U,
482  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,
483  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U,
484  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U,
485  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U,
486  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,
487  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U,
488  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U,
489  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U,
490  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,
491  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U,
492  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U,
493  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U,
494  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,
495  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U,
496  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U,
497  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U,
498  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,
499  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U,
500  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U,
501  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U,
502  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,
503  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U,
504  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U,
505  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U,
506  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,
507  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U,
508  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U,
509  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U,
510  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,
511  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U,
512  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U,
513  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U,
514  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U,
515  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U,
516  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U,
517  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U,
518  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U,
519  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U,
520  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U,
521  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U,
522  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U,
523  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U,
524  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U,
525  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U,
526  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U,
527  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U,
528  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U,
529  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U,
530  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U,
531  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U,
532  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U,
533  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U,
534  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U,
535  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U,
536  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U,
537  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U,
538  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U,
539  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U,
540  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U,
541  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U,
542  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U,
543  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U,
544  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U,
545  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U,
546  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U,
547  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U,
548  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U,
549  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U,
550  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U,
551  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U,
552  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U,
553  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U,
554  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U,
555  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U,
556  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U,
557  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U,
558  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U,
559  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U,
560  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U,
561  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U,
562  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U,
563 } iomuxc_sw_mux_ctl_pad_t;
564 
565 /* @} */
566 
571 /*******************************************************************************
572  * Definitions
573 *******************************************************************************/
574 
580 typedef enum _iomuxc_sw_pad_ctl_pad
581 {
582  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U,
583  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U,
584  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U,
585  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,
586  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U,
587  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U,
588  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U,
589  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,
590  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U,
591  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U,
592  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U,
593  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,
594  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U,
595  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U,
596  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U,
597  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,
598  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U,
599  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U,
600  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U,
601  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,
602  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U,
603  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U,
604  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U,
605  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,
606  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U,
607  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U,
608  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U,
609  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,
610  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U,
611  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U,
612  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U,
613  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,
614  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U,
615  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U,
616  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U,
617  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,
618  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U,
619  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U,
620  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U,
621  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,
622  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U,
623  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U,
624  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U,
625  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,
626  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U,
627  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U,
628  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U,
629  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,
630  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U,
631  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U,
632  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U,
633  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,
634  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U,
635  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U,
636  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U,
637  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,
638  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U,
639  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U,
640  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U,
641  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,
642  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U,
643  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U,
644  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U,
645  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,
646  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U,
647  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U,
648  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U,
649  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,
650  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U,
651  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U,
652  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U,
653  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,
654  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U,
655  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U,
656  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U,
657  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U,
658  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U,
659  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U,
660  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U,
661  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U,
662  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U,
663  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U,
664  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U,
665  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U,
666  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U,
667  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U,
668  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U,
669  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U,
670  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U,
671  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U,
672  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U,
673  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U,
674  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U,
675  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U,
676  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U,
677  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U,
678  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U,
679  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U,
680  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U,
681  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U,
682  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U,
683  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U,
684  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U,
685  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U,
686  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U,
687  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U,
688  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U,
689  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U,
690  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U,
691  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U,
692  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U,
693  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U,
694  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U,
695  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U,
696  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U,
697  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U,
698  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U,
699  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U,
700  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U,
701  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U,
702  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U,
703  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U,
704  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U,
705  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U,
706 } iomuxc_sw_pad_ctl_pad_t;
707 
708 /* @} */
709 
715 typedef enum _iomuxc_select_input
716 {
717  kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U,
718  kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U,
719  kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U,
720  kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U,
721  kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U,
722  kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U,
723  kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U,
724  kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U,
725  kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U,
726  kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U,
727  kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U,
728  kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U,
729  kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U,
730  kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U,
731  kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U,
732  kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U,
733  kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U,
734  kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U,
735  kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U,
736  kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U,
737  kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U,
738  kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U,
739  kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U,
740  kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U,
741  kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U,
742  kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U,
743  kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U,
744  kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U,
745  kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U,
746  kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U,
747  kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U,
748  kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U,
749  kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U,
750  kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U,
751  kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U,
752  kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U,
753  kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U,
754  kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U,
755  kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U,
756  kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U,
757  kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U,
758  kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U,
759  kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U,
760  kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U,
761  kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U,
762  kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U,
763  kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U,
764  kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U,
765  kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U,
766  kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U,
767  kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U,
768  kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U,
769  kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U,
770  kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U,
771  kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U,
772  kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U,
773  kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U,
774  kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U,
775  kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U,
776  kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U,
777  kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U,
778  kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U,
779  kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U,
780  kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U,
781  kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U,
782  kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U,
783  kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U,
784  kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U,
785  kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U,
786  kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U,
787  kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U,
788  kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U,
789  kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U,
790  kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U,
791  kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U,
792  kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U,
793  kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U,
794  kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U,
795  kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U,
796  kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U,
797  kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U,
798  kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U,
799  kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U,
800  kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U,
801  kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U,
802  kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U,
803  kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U,
804  kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U,
805  kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U,
806  kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U,
807  kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U,
808  kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U,
809  kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U,
810  kIOMUXC_NMI_SELECT_INPUT = 93U,
811  kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U,
812  kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U,
813  kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U,
814  kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U,
815  kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U,
816  kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U,
817  kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U,
818  kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U,
819  kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U,
820  kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U,
821  kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U,
822  kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U,
823  kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U,
824  kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U,
825  kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U,
826  kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U,
827  kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U,
828  kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U,
829  kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U,
830  kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U,
831  kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U,
832  kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U,
833  kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U,
834  kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U,
835  kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U,
836  kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U,
837  kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U,
838  kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U,
839  kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U,
840  kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U,
841  kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U,
842  kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U,
843  kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U,
844  kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U,
845  kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U,
846  kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U,
847  kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U,
848  kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U,
849  kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U,
850  kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U,
851  kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U,
852  kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U,
853  kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U,
854  kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U,
855  kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U,
856  kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U,
857  kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U,
858  kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U,
859  kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U,
860  kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U,
861  kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U,
862  kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U,
863  kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U,
864  kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U,
865  kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U,
866  kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U,
867  kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U,
868  kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U,
869  kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U,
870  kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U,
871 } iomuxc_select_input_t;
872 
873 typedef enum _xbar_input_signal
874 {
875  kXBARA1_InputLogicLow = 0|0x100U,
876  kXBARA1_InputLogicHigh = 1|0x100U,
877  kXBARA1_InputIomuxXbarIn02 = 2|0x100U,
878  kXBARA1_InputIomuxXbarIn03 = 3|0x100U,
879  kXBARA1_InputIomuxXbarInout04 = 4|0x100U,
880  kXBARA1_InputIomuxXbarInout05 = 5|0x100U,
881  kXBARA1_InputIomuxXbarInout06 = 6|0x100U,
882  kXBARA1_InputIomuxXbarInout07 = 7|0x100U,
883  kXBARA1_InputIomuxXbarInout08 = 8|0x100U,
884  kXBARA1_InputIomuxXbarInout09 = 9|0x100U,
885  kXBARA1_InputIomuxXbarInout10 = 10|0x100U,
886  kXBARA1_InputIomuxXbarInout11 = 11|0x100U,
887  kXBARA1_InputIomuxXbarInout12 = 12|0x100U,
888  kXBARA1_InputIomuxXbarInout13 = 13|0x100U,
889  kXBARA1_InputIomuxXbarInout14 = 14|0x100U,
890  kXBARA1_InputIomuxXbarInout15 = 15|0x100U,
891  kXBARA1_InputIomuxXbarInout16 = 16|0x100U,
892  kXBARA1_InputIomuxXbarInout17 = 17|0x100U,
893  kXBARA1_InputIomuxXbarInout18 = 18|0x100U,
894  kXBARA1_InputIomuxXbarInout19 = 19|0x100U,
895  kXBARA1_InputIomuxXbarIn20 = 20|0x100U,
896  kXBARA1_InputIomuxXbarIn21 = 21|0x100U,
897  kXBARA1_InputIomuxXbarIn22 = 22|0x100U,
898  kXBARA1_InputIomuxXbarIn23 = 23|0x100U,
899  kXBARA1_InputIomuxXbarIn24 = 24|0x100U,
900  kXBARA1_InputIomuxXbarIn25 = 25|0x100U,
901  kXBARA1_InputAcmp1Out = 26|0x100U,
902  kXBARA1_InputAcmp2Out = 27|0x100U,
903  kXBARA1_InputAcmp3Out = 28|0x100U,
904  kXBARA1_InputAcmp4Out = 29|0x100U,
905  kXBARA1_InputRESERVED30 = 30|0x100U,
906  kXBARA1_InputRESERVED31 = 31|0x100U,
907  kXBARA1_InputQtimer3Tmr0Output = 32|0x100U,
908  kXBARA1_InputQtimer3Tmr1Output = 33|0x100U,
909  kXBARA1_InputQtimer3Tmr2Output = 34|0x100U,
910  kXBARA1_InputQtimer3Tmr3Output = 35|0x100U,
911  kXBARA1_InputQtimer4Tmr0Output = 36|0x100U,
912  kXBARA1_InputQtimer4Tmr1Output = 37|0x100U,
913  kXBARA1_InputQtimer4Tmr2Output = 38|0x100U,
914  kXBARA1_InputQtimer4Tmr3Output = 39|0x100U,
915  kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U,
916  kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U,
917  kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U,
918  kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U,
919  kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U,
920  kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U,
921  kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U,
922  kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U,
923  kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U,
924  kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U,
925  kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U,
926  kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U,
927  kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U,
928  kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U,
929  kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U,
930  kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U,
931  kXBARA1_InputPitTrigger0 = 56|0x100U,
932  kXBARA1_InputPitTrigger1 = 57|0x100U,
933  kXBARA1_InputPitTrigger2 = 58|0x100U,
934  kXBARA1_InputPitTrigger3 = 59|0x100U,
935  kXBARA1_InputEnc1PosMatch = 60|0x100U,
936  kXBARA1_InputEnc2PosMatch = 61|0x100U,
937  kXBARA1_InputEnc3PosMatch = 62|0x100U,
938  kXBARA1_InputEnc4PosMatch = 63|0x100U,
939  kXBARA1_InputDmaDone0 = 64|0x100U,
940  kXBARA1_InputDmaDone1 = 65|0x100U,
941  kXBARA1_InputDmaDone2 = 66|0x100U,
942  kXBARA1_InputDmaDone3 = 67|0x100U,
943  kXBARA1_InputDmaDone4 = 68|0x100U,
944  kXBARA1_InputDmaDone5 = 69|0x100U,
945  kXBARA1_InputDmaDone6 = 70|0x100U,
946  kXBARA1_InputDmaDone7 = 71|0x100U,
947  kXBARA1_InputAoi1Out0 = 72|0x100U,
948  kXBARA1_InputAoi1Out1 = 73|0x100U,
949  kXBARA1_InputAoi1Out2 = 74|0x100U,
950  kXBARA1_InputAoi1Out3 = 75|0x100U,
951  kXBARA1_InputAoi2Out0 = 76|0x100U,
952  kXBARA1_InputAoi2Out1 = 77|0x100U,
953  kXBARA1_InputAoi2Out2 = 78|0x100U,
954  kXBARA1_InputAoi2Out3 = 79|0x100U,
955  kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U,
956  kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U,
957  kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U,
958  kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U,
959  kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U,
960  kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U,
961  kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U,
962  kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U,
963  kXBARB2_InputLogicLow = 0|0x200U,
964  kXBARB2_InputLogicHigh = 1|0x200U,
965  kXBARB2_InputRESERVED2 = 2|0x200U,
966  kXBARB2_InputRESERVED3 = 3|0x200U,
967  kXBARB2_InputRESERVED4 = 4|0x200U,
968  kXBARB2_InputRESERVED5 = 5|0x200U,
969  kXBARB2_InputAcmp1Out = 6|0x200U,
970  kXBARB2_InputAcmp2Out = 7|0x200U,
971  kXBARB2_InputAcmp3Out = 8|0x200U,
972  kXBARB2_InputAcmp4Out = 9|0x200U,
973  kXBARB2_InputRESERVED10 = 10|0x200U,
974  kXBARB2_InputRESERVED11 = 11|0x200U,
975  kXBARB2_InputQtimer3Tmr0Output = 12|0x200U,
976  kXBARB2_InputQtimer3Tmr1Output = 13|0x200U,
977  kXBARB2_InputQtimer3Tmr2Output = 14|0x200U,
978  kXBARB2_InputQtimer3Tmr3Output = 15|0x200U,
979  kXBARB2_InputQtimer4Tmr0Output = 16|0x200U,
980  kXBARB2_InputQtimer4Tmr1Output = 17|0x200U,
981  kXBARB2_InputQtimer4Tmr2Output = 18|0x200U,
982  kXBARB2_InputQtimer4Tmr3Output = 19|0x200U,
983  kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U,
984  kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U,
985  kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U,
986  kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U,
987  kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U,
988  kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U,
989  kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U,
990  kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U,
991  kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U,
992  kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U,
993  kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U,
994  kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U,
995  kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U,
996  kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U,
997  kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U,
998  kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U,
999  kXBARB2_InputPitTrigger0 = 36|0x200U,
1000  kXBARB2_InputPitTrigger1 = 37|0x200U,
1001  kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U,
1002  kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U,
1003  kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U,
1004  kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U,
1005  kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U,
1006  kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U,
1007  kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U,
1008  kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U,
1009  kXBARB2_InputEnc1PosMatch = 46|0x200U,
1010  kXBARB2_InputEnc2PosMatch = 47|0x200U,
1011  kXBARB2_InputEnc3PosMatch = 48|0x200U,
1012  kXBARB2_InputEnc4PosMatch = 49|0x200U,
1013  kXBARB2_InputDmaDone0 = 50|0x200U,
1014  kXBARB2_InputDmaDone1 = 51|0x200U,
1015  kXBARB2_InputDmaDone2 = 52|0x200U,
1016  kXBARB2_InputDmaDone3 = 53|0x200U,
1017  kXBARB2_InputDmaDone4 = 54|0x200U,
1018  kXBARB2_InputDmaDone5 = 55|0x200U,
1019  kXBARB2_InputDmaDone6 = 56|0x200U,
1020  kXBARB2_InputDmaDone7 = 57|0x200U,
1021  kXBARB3_InputLogicLow = 0|0x300U,
1022  kXBARB3_InputLogicHigh = 1|0x300U,
1023  kXBARB3_InputRESERVED2 = 2|0x300U,
1024  kXBARB3_InputRESERVED3 = 3|0x300U,
1025  kXBARB3_InputRESERVED4 = 4|0x300U,
1026  kXBARB3_InputRESERVED5 = 5|0x300U,
1027  kXBARB3_InputAcmp1Out = 6|0x300U,
1028  kXBARB3_InputAcmp2Out = 7|0x300U,
1029  kXBARB3_InputAcmp3Out = 8|0x300U,
1030  kXBARB3_InputAcmp4Out = 9|0x300U,
1031  kXBARB3_InputRESERVED10 = 10|0x300U,
1032  kXBARB3_InputRESERVED11 = 11|0x300U,
1033  kXBARB3_InputQtimer3Tmr0Output = 12|0x300U,
1034  kXBARB3_InputQtimer3Tmr1Output = 13|0x300U,
1035  kXBARB3_InputQtimer3Tmr2Output = 14|0x300U,
1036  kXBARB3_InputQtimer3Tmr3Output = 15|0x300U,
1037  kXBARB3_InputQtimer4Tmr0Output = 16|0x300U,
1038  kXBARB3_InputQtimer4Tmr1Output = 17|0x300U,
1039  kXBARB3_InputQtimer4Tmr2Output = 18|0x300U,
1040  kXBARB3_InputQtimer4Tmr3Output = 19|0x300U,
1041  kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U,
1042  kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U,
1043  kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U,
1044  kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U,
1045  kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U,
1046  kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U,
1047  kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U,
1048  kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U,
1049  kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U,
1050  kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U,
1051  kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U,
1052  kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U,
1053  kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U,
1054  kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U,
1055  kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U,
1056  kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U,
1057  kXBARB3_InputPitTrigger0 = 36|0x300U,
1058  kXBARB3_InputPitTrigger1 = 37|0x300U,
1059  kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U,
1060  kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U,
1061  kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U,
1062  kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U,
1063  kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U,
1064  kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U,
1065  kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U,
1066  kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U,
1067  kXBARB3_InputEnc1PosMatch = 46|0x300U,
1068  kXBARB3_InputEnc2PosMatch = 47|0x300U,
1069  kXBARB3_InputEnc3PosMatch = 48|0x300U,
1070  kXBARB3_InputEnc4PosMatch = 49|0x300U,
1071  kXBARB3_InputDmaDone0 = 50|0x300U,
1072  kXBARB3_InputDmaDone1 = 51|0x300U,
1073  kXBARB3_InputDmaDone2 = 52|0x300U,
1074  kXBARB3_InputDmaDone3 = 53|0x300U,
1075  kXBARB3_InputDmaDone4 = 54|0x300U,
1076  kXBARB3_InputDmaDone5 = 55|0x300U,
1077  kXBARB3_InputDmaDone6 = 56|0x300U,
1078  kXBARB3_InputDmaDone7 = 57|0x300U,
1079 } xbar_input_signal_t;
1080 
1081 typedef enum _xbar_output_signal
1082 {
1083  kXBARA1_OutputDmaChMuxReq30 = 0|0x100U,
1084  kXBARA1_OutputDmaChMuxReq31 = 1|0x100U,
1085  kXBARA1_OutputDmaChMuxReq94 = 2|0x100U,
1086  kXBARA1_OutputDmaChMuxReq95 = 3|0x100U,
1087  kXBARA1_OutputIomuxXbarInout04 = 4|0x100U,
1088  kXBARA1_OutputIomuxXbarInout05 = 5|0x100U,
1089  kXBARA1_OutputIomuxXbarInout06 = 6|0x100U,
1090  kXBARA1_OutputIomuxXbarInout07 = 7|0x100U,
1091  kXBARA1_OutputIomuxXbarInout08 = 8|0x100U,
1092  kXBARA1_OutputIomuxXbarInout09 = 9|0x100U,
1093  kXBARA1_OutputIomuxXbarInout10 = 10|0x100U,
1094  kXBARA1_OutputIomuxXbarInout11 = 11|0x100U,
1095  kXBARA1_OutputIomuxXbarInout12 = 12|0x100U,
1096  kXBARA1_OutputIomuxXbarInout13 = 13|0x100U,
1097  kXBARA1_OutputIomuxXbarInout14 = 14|0x100U,
1098  kXBARA1_OutputIomuxXbarInout15 = 15|0x100U,
1099  kXBARA1_OutputIomuxXbarInout16 = 16|0x100U,
1100  kXBARA1_OutputIomuxXbarInout17 = 17|0x100U,
1101  kXBARA1_OutputIomuxXbarInout18 = 18|0x100U,
1102  kXBARA1_OutputIomuxXbarInout19 = 19|0x100U,
1103  kXBARA1_OutputAcmp1Sample = 20|0x100U,
1104  kXBARA1_OutputAcmp2Sample = 21|0x100U,
1105  kXBARA1_OutputAcmp3Sample = 22|0x100U,
1106  kXBARA1_OutputAcmp4Sample = 23|0x100U,
1107  kXBARA1_OutputRESERVED24 = 24|0x100U,
1108  kXBARA1_OutputRESERVED25 = 25|0x100U,
1109  kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U,
1110  kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U,
1111  kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U,
1112  kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U,
1113  kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U,
1114  kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U,
1115  kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U,
1116  kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U,
1117  kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U,
1118  kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U,
1119  kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U,
1120  kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U,
1121  kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U,
1122  kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U,
1123  kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U,
1124  kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U,
1125  kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U,
1126  kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U,
1127  kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U,
1128  kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U,
1129  kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U,
1130  kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U,
1131  kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U,
1132  kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U,
1133  kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U,
1134  kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U,
1135  kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U,
1136  kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U,
1137  kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U,
1138  kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U,
1139  kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U,
1140  kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U,
1141  kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U,
1142  kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U,
1143  kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U,
1144  kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U,
1145  kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U,
1146  kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U,
1147  kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U,
1148  kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U,
1149  kXBARA1_OutputEnc1PhaseAInput = 66|0x100U,
1150  kXBARA1_OutputEnc1PhaseBInput = 67|0x100U,
1151  kXBARA1_OutputEnc1Index = 68|0x100U,
1152  kXBARA1_OutputEnc1Home = 69|0x100U,
1153  kXBARA1_OutputEnc1Trigger = 70|0x100U,
1154  kXBARA1_OutputEnc2PhaseAInput = 71|0x100U,
1155  kXBARA1_OutputEnc2PhaseBInput = 72|0x100U,
1156  kXBARA1_OutputEnc2Index = 73|0x100U,
1157  kXBARA1_OutputEnc2Home = 74|0x100U,
1158  kXBARA1_OutputEnc2Trigger = 75|0x100U,
1159  kXBARA1_OutputEnc3PhaseAInput = 76|0x100U,
1160  kXBARA1_OutputEnc3PhaseBInput = 77|0x100U,
1161  kXBARA1_OutputEnc3Index = 78|0x100U,
1162  kXBARA1_OutputEnc3Home = 79|0x100U,
1163  kXBARA1_OutputEnc3Trigger = 80|0x100U,
1164  kXBARA1_OutputEnc4PhaseAInput = 81|0x100U,
1165  kXBARA1_OutputEnc4PhaseBInput = 82|0x100U,
1166  kXBARA1_OutputEnc4Index = 83|0x100U,
1167  kXBARA1_OutputEnc4Home = 84|0x100U,
1168  kXBARA1_OutputEnc4Trigger = 85|0x100U,
1169  kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U,
1170  kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U,
1171  kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U,
1172  kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U,
1173  kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U,
1174  kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U,
1175  kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U,
1176  kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U,
1177  kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U,
1178  kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U,
1179  kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U,
1180  kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U,
1181  kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U,
1182  kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U,
1183  kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U,
1184  kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U,
1185  kXBARA1_OutputEwmEwmIn = 102|0x100U,
1186  kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U,
1187  kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U,
1188  kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U,
1189  kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U,
1190  kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U,
1191  kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U,
1192  kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U,
1193  kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U,
1194  kXBARA1_OutputLpi2c1TrgInput = 111|0x100U,
1195  kXBARA1_OutputLpi2c2TrgInput = 112|0x100U,
1196  kXBARA1_OutputLpi2c3TrgInput = 113|0x100U,
1197  kXBARA1_OutputLpi2c4TrgInput = 114|0x100U,
1198  kXBARA1_OutputLpspi1TrgInput = 115|0x100U,
1199  kXBARA1_OutputLpspi2TrgInput = 116|0x100U,
1200  kXBARA1_OutputLpspi3TrgInput = 117|0x100U,
1201  kXBARA1_OutputLpspi4TrgInput = 118|0x100U,
1202  kXBARA1_OutputLpuart1TrgInput = 119|0x100U,
1203  kXBARA1_OutputLpuart2TrgInput = 120|0x100U,
1204  kXBARA1_OutputLpuart3TrgInput = 121|0x100U,
1205  kXBARA1_OutputLpuart4TrgInput = 122|0x100U,
1206  kXBARA1_OutputLpuart5TrgInput = 123|0x100U,
1207  kXBARA1_OutputLpuart6TrgInput = 124|0x100U,
1208  kXBARA1_OutputLpuart7TrgInput = 125|0x100U,
1209  kXBARA1_OutputLpuart8TrgInput = 126|0x100U,
1210  kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,
1211  kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U,
1212  kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U,
1213  kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U,
1214  kXBARB2_OutputAoi1In00 = 0|0x200U,
1215  kXBARB2_OutputAoi1In01 = 1|0x200U,
1216  kXBARB2_OutputAoi1In02 = 2|0x200U,
1217  kXBARB2_OutputAoi1In03 = 3|0x200U,
1218  kXBARB2_OutputAoi1In04 = 4|0x200U,
1219  kXBARB2_OutputAoi1In05 = 5|0x200U,
1220  kXBARB2_OutputAoi1In06 = 6|0x200U,
1221  kXBARB2_OutputAoi1In07 = 7|0x200U,
1222  kXBARB2_OutputAoi1In08 = 8|0x200U,
1223  kXBARB2_OutputAoi1In09 = 9|0x200U,
1224  kXBARB2_OutputAoi1In10 = 10|0x200U,
1225  kXBARB2_OutputAoi1In11 = 11|0x200U,
1226  kXBARB2_OutputAoi1In12 = 12|0x200U,
1227  kXBARB2_OutputAoi1In13 = 13|0x200U,
1228  kXBARB2_OutputAoi1In14 = 14|0x200U,
1229  kXBARB2_OutputAoi1In15 = 15|0x200U,
1230  kXBARB3_OutputAoi2In00 = 0|0x300U,
1231  kXBARB3_OutputAoi2In01 = 1|0x300U,
1232  kXBARB3_OutputAoi2In02 = 2|0x300U,
1233  kXBARB3_OutputAoi2In03 = 3|0x300U,
1234  kXBARB3_OutputAoi2In04 = 4|0x300U,
1235  kXBARB3_OutputAoi2In05 = 5|0x300U,
1236  kXBARB3_OutputAoi2In06 = 6|0x300U,
1237  kXBARB3_OutputAoi2In07 = 7|0x300U,
1238  kXBARB3_OutputAoi2In08 = 8|0x300U,
1239  kXBARB3_OutputAoi2In09 = 9|0x300U,
1240  kXBARB3_OutputAoi2In10 = 10|0x300U,
1241  kXBARB3_OutputAoi2In11 = 11|0x300U,
1242  kXBARB3_OutputAoi2In12 = 12|0x300U,
1243  kXBARB3_OutputAoi2In13 = 13|0x300U,
1244  kXBARB3_OutputAoi2In14 = 14|0x300U,
1245  kXBARB3_OutputAoi2In15 = 15|0x300U,
1246 } xbar_output_signal_t;
1247 
1248  /* end of group Mapping_Information */
1252 
1253 
1254 /* ----------------------------------------------------------------------------
1255  -- Device Peripheral Access Layer
1256  ---------------------------------------------------------------------------- */
1257 
1264 /*
1265 ** Start of section using anonymous unions
1266 */
1267 
1268 #if defined(__ARMCC_VERSION)
1269  #if (__ARMCC_VERSION >= 6010050)
1270  #pragma clang diagnostic push
1271  #else
1272  #pragma push
1273  #pragma anon_unions
1274  #endif
1275 #elif defined(__CWCC__)
1276  #pragma push
1277  #pragma cpp_extensions on
1278 #elif defined(__GNUC__)
1279  /* anonymous unions are enabled by default */
1280 #elif defined(__IAR_SYSTEMS_ICC__)
1281  #pragma language=extended
1282 #else
1283  #error Not supported compiler type
1284 #endif
1285 
1286 /* ----------------------------------------------------------------------------
1287  -- ADC Peripheral Access Layer
1288  ---------------------------------------------------------------------------- */
1289 
1296 typedef struct {
1297  __IO uint32_t HC[8];
1298  __I uint32_t HS;
1299  __I uint32_t R[8];
1300  __IO uint32_t CFG;
1301  __IO uint32_t GC;
1302  __IO uint32_t GS;
1303  __IO uint32_t CV;
1304  __IO uint32_t OFS;
1305  __IO uint32_t CAL;
1306 } ADC_Type;
1307 
1308 /* ----------------------------------------------------------------------------
1309  -- ADC Register Masks
1310  ---------------------------------------------------------------------------- */
1311 
1319 #define ADC_HC_ADCH_MASK (0x1FU)
1320 #define ADC_HC_ADCH_SHIFT (0U)
1321 
1329 #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1330 #define ADC_HC_AIEN_MASK (0x80U)
1331 #define ADC_HC_AIEN_SHIFT (7U)
1332 
1336 #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1337 
1339 /* The count of ADC_HC */
1340 #define ADC_HC_COUNT (8U)
1341 
1344 #define ADC_HS_COCO0_MASK (0x1U)
1345 #define ADC_HS_COCO0_SHIFT (0U)
1346 
1348 #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1349 
1353 #define ADC_R_CDATA_MASK (0xFFFU)
1354 #define ADC_R_CDATA_SHIFT (0U)
1355 
1357 #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1358 
1360 /* The count of ADC_R */
1361 #define ADC_R_COUNT (8U)
1362 
1365 #define ADC_CFG_ADICLK_MASK (0x3U)
1366 #define ADC_CFG_ADICLK_SHIFT (0U)
1367 
1373 #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1374 #define ADC_CFG_MODE_MASK (0xCU)
1375 #define ADC_CFG_MODE_SHIFT (2U)
1376 
1382 #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1383 #define ADC_CFG_ADLSMP_MASK (0x10U)
1384 #define ADC_CFG_ADLSMP_SHIFT (4U)
1385 
1389 #define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1390 #define ADC_CFG_ADIV_MASK (0x60U)
1391 #define ADC_CFG_ADIV_SHIFT (5U)
1392 
1398 #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1399 #define ADC_CFG_ADLPC_MASK (0x80U)
1400 #define ADC_CFG_ADLPC_SHIFT (7U)
1401 
1405 #define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1406 #define ADC_CFG_ADSTS_MASK (0x300U)
1407 #define ADC_CFG_ADSTS_SHIFT (8U)
1408 
1414 #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1415 #define ADC_CFG_ADHSC_MASK (0x400U)
1416 #define ADC_CFG_ADHSC_SHIFT (10U)
1417 
1421 #define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1422 #define ADC_CFG_REFSEL_MASK (0x1800U)
1423 #define ADC_CFG_REFSEL_SHIFT (11U)
1424 
1430 #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1431 #define ADC_CFG_ADTRG_MASK (0x2000U)
1432 #define ADC_CFG_ADTRG_SHIFT (13U)
1433 
1437 #define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1438 #define ADC_CFG_AVGS_MASK (0xC000U)
1439 #define ADC_CFG_AVGS_SHIFT (14U)
1440 
1446 #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1447 #define ADC_CFG_OVWREN_MASK (0x10000U)
1448 #define ADC_CFG_OVWREN_SHIFT (16U)
1449 
1453 #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1454 
1458 #define ADC_GC_ADACKEN_MASK (0x1U)
1459 #define ADC_GC_ADACKEN_SHIFT (0U)
1460 
1464 #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1465 #define ADC_GC_DMAEN_MASK (0x2U)
1466 #define ADC_GC_DMAEN_SHIFT (1U)
1467 
1471 #define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1472 #define ADC_GC_ACREN_MASK (0x4U)
1473 #define ADC_GC_ACREN_SHIFT (2U)
1474 
1478 #define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1479 #define ADC_GC_ACFGT_MASK (0x8U)
1480 #define ADC_GC_ACFGT_SHIFT (3U)
1481 
1487 #define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1488 #define ADC_GC_ACFE_MASK (0x10U)
1489 #define ADC_GC_ACFE_SHIFT (4U)
1490 
1494 #define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1495 #define ADC_GC_AVGE_MASK (0x20U)
1496 #define ADC_GC_AVGE_SHIFT (5U)
1497 
1501 #define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1502 #define ADC_GC_ADCO_MASK (0x40U)
1503 #define ADC_GC_ADCO_SHIFT (6U)
1504 
1508 #define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1509 #define ADC_GC_CAL_MASK (0x80U)
1510 #define ADC_GC_CAL_SHIFT (7U)
1511 
1513 #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1514 
1518 #define ADC_GS_ADACT_MASK (0x1U)
1519 #define ADC_GS_ADACT_SHIFT (0U)
1520 
1524 #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1525 #define ADC_GS_CALF_MASK (0x2U)
1526 #define ADC_GS_CALF_SHIFT (1U)
1527 
1531 #define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1532 #define ADC_GS_AWKST_MASK (0x4U)
1533 #define ADC_GS_AWKST_SHIFT (2U)
1534 
1538 #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1539 
1543 #define ADC_CV_CV1_MASK (0xFFFU)
1544 #define ADC_CV_CV1_SHIFT (0U)
1545 
1547 #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1548 #define ADC_CV_CV2_MASK (0xFFF0000U)
1549 #define ADC_CV_CV2_SHIFT (16U)
1550 
1552 #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1553 
1557 #define ADC_OFS_OFS_MASK (0xFFFU)
1558 #define ADC_OFS_OFS_SHIFT (0U)
1559 
1561 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1562 #define ADC_OFS_SIGN_MASK (0x1000U)
1563 #define ADC_OFS_SIGN_SHIFT (12U)
1564 
1568 #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1569 
1573 #define ADC_CAL_CAL_CODE_MASK (0xFU)
1574 #define ADC_CAL_CAL_CODE_SHIFT (0U)
1575 
1577 #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1578  /* end of group ADC_Register_Masks */
1584 
1585 
1586 /* ADC - Peripheral instance base addresses */
1588 #define ADC1_BASE (0x400C4000u)
1589 
1590 #define ADC1 ((ADC_Type *)ADC1_BASE)
1591 
1592 #define ADC2_BASE (0x400C8000u)
1593 
1594 #define ADC2 ((ADC_Type *)ADC2_BASE)
1595 
1596 #define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1597 
1598 #define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1599 
1600 #define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1601  /* end of group ADC_Peripheral_Access_Layer */
1605 
1606 
1607 /* ----------------------------------------------------------------------------
1608  -- ADC_ETC Peripheral Access Layer
1609  ---------------------------------------------------------------------------- */
1610 
1617 typedef struct {
1618  __IO uint32_t CTRL;
1619  __IO uint32_t DONE0_1_IRQ;
1620  __IO uint32_t DONE2_ERR_IRQ;
1621  __IO uint32_t DMA_CTRL;
1622  struct { /* offset: 0x10, array step: 0x28 */
1623  __IO uint32_t TRIGn_CTRL;
1624  __IO uint32_t TRIGn_COUNTER;
1625  __IO uint32_t TRIGn_CHAIN_1_0;
1626  __IO uint32_t TRIGn_CHAIN_3_2;
1627  __IO uint32_t TRIGn_CHAIN_5_4;
1628  __IO uint32_t TRIGn_CHAIN_7_6;
1629  __I uint32_t TRIGn_RESULT_1_0;
1630  __I uint32_t TRIGn_RESULT_3_2;
1631  __I uint32_t TRIGn_RESULT_5_4;
1632  __I uint32_t TRIGn_RESULT_7_6;
1633  } TRIG[8];
1634 } ADC_ETC_Type;
1635 
1636 /* ----------------------------------------------------------------------------
1637  -- ADC_ETC Register Masks
1638  ---------------------------------------------------------------------------- */
1639 
1647 #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1648 #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1649 #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1650 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1651 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1652 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1653 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1654 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1655 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1656 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1657 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1658 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1659 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1660 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1661 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1662 #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1663 #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1664 #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1665 #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1666 #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1667 #define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1668 #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1669 #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1670 #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1671 #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1672 #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1673 #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1674 
1678 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1679 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1680 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1681 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1682 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1683 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1684 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1685 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1686 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1687 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1688 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1689 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1690 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1691 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1692 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1693 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1694 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1695 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1696 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1697 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1698 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1699 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1700 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1701 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1702 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1703 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1704 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1705 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1706 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1707 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1708 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1709 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1710 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1711 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1712 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1713 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1714 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1715 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1716 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1717 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1718 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1719 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1720 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1721 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1722 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1723 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1724 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1725 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1726 
1730 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1731 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1732 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1733 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1734 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1735 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1736 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1737 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1738 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1739 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1740 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1741 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1742 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1743 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1744 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1745 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1746 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1747 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1748 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1749 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1750 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1751 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1752 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1753 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1754 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1755 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1756 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1757 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1758 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1759 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1760 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1761 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1762 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1763 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1764 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1765 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1766 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1767 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1768 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1769 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1770 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1771 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1772 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1773 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1774 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1775 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1776 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1777 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1778 
1782 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1783 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1784 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1785 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1786 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1787 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1788 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1789 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1790 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1791 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1792 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1793 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1794 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1795 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1796 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1797 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1798 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1799 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1800 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1801 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1802 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1803 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1804 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1805 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1806 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1807 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1808 #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1809 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1810 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1811 #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1812 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1813 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1814 #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1815 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1816 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1817 #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1818 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1819 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1820 #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1821 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1822 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1823 #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1824 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1825 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1826 #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1827 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1828 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1829 #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1830 
1834 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1835 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1836 #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1837 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1838 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1839 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1840 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1841 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1842 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1843 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1844 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1845 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1846 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1847 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1848 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1849 
1851 /* The count of ADC_ETC_TRIGn_CTRL */
1852 #define ADC_ETC_TRIGn_CTRL_COUNT (8U)
1853 
1856 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1857 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1858 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1859 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1860 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1861 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1862 
1864 /* The count of ADC_ETC_TRIGn_COUNTER */
1865 #define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
1866 
1869 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
1870 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
1871 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
1872 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
1873 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
1874 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
1875 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
1876 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
1877 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
1878 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
1879 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
1880 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
1881 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
1882 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
1883 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
1884 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
1885 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
1886 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
1887 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
1888 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
1889 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
1890 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
1891 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
1892 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
1893 
1895 /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
1896 #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
1897 
1900 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
1901 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
1902 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
1903 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
1904 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
1905 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
1906 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
1907 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
1908 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
1909 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
1910 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
1911 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
1912 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
1913 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
1914 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
1915 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
1916 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
1917 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
1918 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
1919 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
1920 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
1921 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
1922 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
1923 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
1924 
1926 /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
1927 #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
1928 
1931 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
1932 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
1933 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
1934 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
1935 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
1936 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
1937 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
1938 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
1939 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
1940 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
1941 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
1942 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
1943 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
1944 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
1945 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
1946 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
1947 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
1948 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
1949 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
1950 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
1951 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
1952 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
1953 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
1954 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
1955 
1957 /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
1958 #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
1959 
1962 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
1963 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
1964 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
1965 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
1966 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
1967 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
1968 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
1969 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
1970 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
1971 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
1972 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
1973 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
1974 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
1975 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
1976 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
1977 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
1978 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
1979 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
1980 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
1981 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
1982 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
1983 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
1984 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
1985 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
1986 
1988 /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
1989 #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
1990 
1993 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
1994 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
1995 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
1996 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
1997 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
1998 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
1999 
2001 /* The count of ADC_ETC_TRIGn_RESULT_1_0 */
2002 #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
2003 
2006 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
2007 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
2008 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
2009 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
2010 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
2011 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
2012 
2014 /* The count of ADC_ETC_TRIGn_RESULT_3_2 */
2015 #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
2016 
2019 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
2020 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
2021 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
2022 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
2023 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
2024 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
2025 
2027 /* The count of ADC_ETC_TRIGn_RESULT_5_4 */
2028 #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
2029 
2032 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
2033 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
2034 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
2035 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
2036 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
2037 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
2038 
2040 /* The count of ADC_ETC_TRIGn_RESULT_7_6 */
2041 #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
2042 
2043  /* end of group ADC_ETC_Register_Masks */
2047 
2048 
2049 /* ADC_ETC - Peripheral instance base addresses */
2051 #define ADC_ETC_BASE (0x403B0000u)
2052 
2053 #define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
2054 
2055 #define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
2056 
2057 #define ADC_ETC_BASE_PTRS { ADC_ETC }
2058 
2059 #define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
2060 #define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
2061  /* end of group ADC_ETC_Peripheral_Access_Layer */
2065 
2066 
2067 /* ----------------------------------------------------------------------------
2068  -- AIPSTZ Peripheral Access Layer
2069  ---------------------------------------------------------------------------- */
2070 
2077 typedef struct {
2078  __IO uint32_t MPR;
2079  uint8_t RESERVED_0[60];
2080  __IO uint32_t OPACR;
2081  __IO uint32_t OPACR1;
2082  __IO uint32_t OPACR2;
2083  __IO uint32_t OPACR3;
2084  __IO uint32_t OPACR4;
2085 } AIPSTZ_Type;
2086 
2087 /* ----------------------------------------------------------------------------
2088  -- AIPSTZ Register Masks
2089  ---------------------------------------------------------------------------- */
2090 
2098 #define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
2099 #define AIPSTZ_MPR_MPROT5_SHIFT (8U)
2100 
2109 #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
2110 #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
2111 #define AIPSTZ_MPR_MPROT3_SHIFT (16U)
2112 
2121 #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
2122 #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
2123 #define AIPSTZ_MPR_MPROT2_SHIFT (20U)
2124 
2133 #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
2134 #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
2135 #define AIPSTZ_MPR_MPROT1_SHIFT (24U)
2136 
2145 #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
2146 #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
2147 #define AIPSTZ_MPR_MPROT0_SHIFT (28U)
2148 
2157 #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
2158 
2162 #define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
2163 #define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
2164 
2178 #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
2179 #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
2180 #define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
2181 
2195 #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
2196 #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
2197 #define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
2198 
2212 #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2213 #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2214 #define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2215 
2229 #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2230 #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2231 #define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2232 
2246 #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2247 #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2248 #define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2249 
2263 #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2264 #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2265 #define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
2266 
2280 #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
2281 #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
2282 #define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
2283 
2297 #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
2298 
2302 #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
2303 #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
2304 
2318 #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
2319 #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
2320 #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
2321 
2335 #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
2336 #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
2337 #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
2338 
2352 #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
2353 #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
2354 #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
2355 
2369 #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
2370 #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
2371 #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
2372 
2386 #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2387 #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2388 #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2389 
2403 #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2404 #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2405 #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2406 
2420 #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2421 #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2422 #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2423 
2437 #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2438 
2442 #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2443 #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2444 
2458 #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2459 #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2460 #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2461 
2475 #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2476 #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2477 #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2478 
2492 #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2493 #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2494 #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2495 
2509 #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2510 #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2511 #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2512 
2526 #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2527 #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2528 #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2529 
2543 #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2544 #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2545 #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2546 
2560 #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2561 #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2562 #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2563 
2577 #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2578 
2582 #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2583 #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2584 
2598 #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2599 #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2600 #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2601 
2615 #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2616 #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2617 #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2618 
2632 #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2633 #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2634 #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2635 
2649 #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2650 #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2651 #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2652 
2666 #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2667 #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2668 #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2669 
2683 #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2684 #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2685 #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2686 
2700 #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2701 #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2702 #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2703 
2717 #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2718 
2722 #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2723 #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2724 
2738 #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2739 #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2740 #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2741 
2755 #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2756  /* end of group AIPSTZ_Register_Masks */
2762 
2763 
2764 /* AIPSTZ - Peripheral instance base addresses */
2766 #define AIPSTZ1_BASE (0x4007C000u)
2767 
2768 #define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2769 
2770 #define AIPSTZ2_BASE (0x4017C000u)
2771 
2772 #define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2773 
2774 #define AIPSTZ3_BASE (0x4027C000u)
2775 
2776 #define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2777 
2778 #define AIPSTZ4_BASE (0x4037C000u)
2779 
2780 #define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2781 
2782 #define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2783 
2784 #define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2785  /* end of group AIPSTZ_Peripheral_Access_Layer */
2789 
2790 
2791 /* ----------------------------------------------------------------------------
2792  -- AOI Peripheral Access Layer
2793  ---------------------------------------------------------------------------- */
2794 
2801 typedef struct {
2802  struct { /* offset: 0x0, array step: 0x4 */
2803  __IO uint16_t BFCRT01;
2804  __IO uint16_t BFCRT23;
2805  } BFCRT[4];
2806 } AOI_Type;
2807 
2808 /* ----------------------------------------------------------------------------
2809  -- AOI Register Masks
2810  ---------------------------------------------------------------------------- */
2811 
2819 #define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2820 #define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2821 
2827 #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2828 #define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2829 #define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2830 
2836 #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2837 #define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2838 #define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2839 
2845 #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2846 #define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2847 #define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2848 
2854 #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2855 #define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2856 #define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2857 
2863 #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2864 #define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2865 #define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2866 
2872 #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
2873 #define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
2874 #define AOI_BFCRT01_PT0_BC_SHIFT (12U)
2875 
2881 #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
2882 #define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
2883 #define AOI_BFCRT01_PT0_AC_SHIFT (14U)
2884 
2890 #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
2891 
2893 /* The count of AOI_BFCRT01 */
2894 #define AOI_BFCRT01_COUNT (4U)
2895 
2898 #define AOI_BFCRT23_PT3_DC_MASK (0x3U)
2899 #define AOI_BFCRT23_PT3_DC_SHIFT (0U)
2900 
2906 #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
2907 #define AOI_BFCRT23_PT3_CC_MASK (0xCU)
2908 #define AOI_BFCRT23_PT3_CC_SHIFT (2U)
2909 
2915 #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
2916 #define AOI_BFCRT23_PT3_BC_MASK (0x30U)
2917 #define AOI_BFCRT23_PT3_BC_SHIFT (4U)
2918 
2924 #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
2925 #define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
2926 #define AOI_BFCRT23_PT3_AC_SHIFT (6U)
2927 
2933 #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
2934 #define AOI_BFCRT23_PT2_DC_MASK (0x300U)
2935 #define AOI_BFCRT23_PT2_DC_SHIFT (8U)
2936 
2942 #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
2943 #define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
2944 #define AOI_BFCRT23_PT2_CC_SHIFT (10U)
2945 
2951 #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
2952 #define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
2953 #define AOI_BFCRT23_PT2_BC_SHIFT (12U)
2954 
2960 #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
2961 #define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
2962 #define AOI_BFCRT23_PT2_AC_SHIFT (14U)
2963 
2969 #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
2970 
2972 /* The count of AOI_BFCRT23 */
2973 #define AOI_BFCRT23_COUNT (4U)
2974 
2975  /* end of group AOI_Register_Masks */
2979 
2980 
2981 /* AOI - Peripheral instance base addresses */
2983 #define AOI1_BASE (0x403B4000u)
2984 
2985 #define AOI1 ((AOI_Type *)AOI1_BASE)
2986 
2987 #define AOI2_BASE (0x403B8000u)
2988 
2989 #define AOI2 ((AOI_Type *)AOI2_BASE)
2990 
2991 #define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
2992 
2993 #define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
2994  /* end of group AOI_Peripheral_Access_Layer */
2998 
2999 
3000 /* ----------------------------------------------------------------------------
3001  -- BEE Peripheral Access Layer
3002  ---------------------------------------------------------------------------- */
3003 
3010 typedef struct {
3011  __IO uint32_t CTRL;
3012  __IO uint32_t ADDR_OFFSET0;
3013  __IO uint32_t ADDR_OFFSET1;
3014  __IO uint32_t AES_KEY0_W0;
3015  __IO uint32_t AES_KEY0_W1;
3016  __IO uint32_t AES_KEY0_W2;
3017  __IO uint32_t AES_KEY0_W3;
3018  __IO uint32_t STATUS;
3019  __O uint32_t CTR_NONCE0_W0;
3020  __O uint32_t CTR_NONCE0_W1;
3021  __O uint32_t CTR_NONCE0_W2;
3022  __O uint32_t CTR_NONCE0_W3;
3023  __O uint32_t CTR_NONCE1_W0;
3024  __O uint32_t CTR_NONCE1_W1;
3025  __O uint32_t CTR_NONCE1_W2;
3026  __O uint32_t CTR_NONCE1_W3;
3027  __IO uint32_t REGION1_TOP;
3028  __IO uint32_t REGION1_BOT;
3029 } BEE_Type;
3030 
3031 /* ----------------------------------------------------------------------------
3032  -- BEE Register Masks
3033  ---------------------------------------------------------------------------- */
3034 
3042 #define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
3043 #define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
3044 
3048 #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
3049 #define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
3050 #define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
3051 #define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
3052 #define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
3053 #define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
3054 #define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
3055 #define BEE_CTRL_KEY_VALID_MASK (0x10U)
3056 #define BEE_CTRL_KEY_VALID_SHIFT (4U)
3057 #define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
3058 #define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
3059 #define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
3060 
3064 #define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
3065 #define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
3066 #define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
3067 #define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
3068 #define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
3069 #define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
3070 
3076 #define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
3077 #define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
3078 #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
3079 #define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
3080 #define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
3081 #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
3082 
3086 #define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
3087 #define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
3088 #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
3089 #define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
3090 #define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
3091 #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
3092 
3096 #define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
3097 #define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
3098 #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
3099 #define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
3100 #define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
3101 #define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
3102 #define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
3103 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
3104 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
3105 #define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
3106 #define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
3107 #define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
3108 #define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
3109 #define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
3110 #define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
3111 #define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
3112 #define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
3113 #define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
3114 #define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
3115 #define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
3116 #define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
3117 #define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
3118 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
3119 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
3120 #define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
3121 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
3122 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
3123 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
3124 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
3125 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
3126 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
3127 #define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
3128 #define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
3129 #define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
3130 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
3131 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
3132 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
3133 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
3134 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
3135 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
3136 #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
3137 #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
3138 #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
3139 
3143 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
3144 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
3145 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
3146 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
3147 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
3148 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
3149 
3153 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
3154 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
3155 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
3156 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
3157 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
3158 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
3159 
3163 #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
3164 #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
3165 
3167 #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
3168 
3172 #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
3173 #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
3174 
3176 #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
3177 
3181 #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
3182 #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
3183 
3185 #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
3186 
3190 #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
3191 #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
3192 
3194 #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
3195 
3199 #define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
3200 #define BEE_STATUS_IRQ_VEC_SHIFT (0U)
3201 #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
3202 #define BEE_STATUS_BEE_IDLE_MASK (0x100U)
3203 #define BEE_STATUS_BEE_IDLE_SHIFT (8U)
3204 #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
3205 
3209 #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
3210 #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
3211 #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
3212 
3216 #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
3217 #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
3218 #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
3219 
3223 #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
3224 #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
3225 #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
3226 
3230 #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
3231 #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
3232 #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
3233 
3237 #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
3238 #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
3239 #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
3240 
3244 #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
3245 #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
3246 #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
3247 
3251 #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
3252 #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
3253 #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
3254 
3258 #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
3259 #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
3260 #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
3261 
3265 #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
3266 #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
3267 
3269 #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
3270 
3274 #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
3275 #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
3276 
3278 #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
3279  /* end of group BEE_Register_Masks */
3285 
3286 
3287 /* BEE - Peripheral instance base addresses */
3289 #define BEE_BASE (0x403EC000u)
3290 
3291 #define BEE ((BEE_Type *)BEE_BASE)
3292 
3293 #define BEE_BASE_ADDRS { BEE_BASE }
3294 
3295 #define BEE_BASE_PTRS { BEE }
3296  /* end of group BEE_Peripheral_Access_Layer */
3300 
3301 
3302 /* ----------------------------------------------------------------------------
3303  -- CAN Peripheral Access Layer
3304  ---------------------------------------------------------------------------- */
3305 
3312 typedef struct {
3313  __IO uint32_t MCR;
3314  __IO uint32_t CTRL1;
3315  __IO uint32_t TIMER;
3316  uint8_t RESERVED_0[4];
3317  __IO uint32_t RXMGMASK;
3318  __IO uint32_t RX14MASK;
3319  __IO uint32_t RX15MASK;
3320  __IO uint32_t ECR;
3321  __IO uint32_t ESR1;
3322  __IO uint32_t IMASK2;
3323  __IO uint32_t IMASK1;
3324  __IO uint32_t IFLAG2;
3325  __IO uint32_t IFLAG1;
3326  __IO uint32_t CTRL2;
3327  __I uint32_t ESR2;
3328  uint8_t RESERVED_1[8];
3329  __I uint32_t CRCR;
3330  __IO uint32_t RXFGMASK;
3331  __I uint32_t RXFIR;
3332  uint8_t RESERVED_2[8];
3333  __I uint32_t DBG1;
3334  __I uint32_t DBG2;
3335  uint8_t RESERVED_3[32];
3336  struct { /* offset: 0x80, array step: 0x10 */
3337  __IO uint32_t CS;
3338  __IO uint32_t ID;
3339  __IO uint32_t WORD0;
3340  __IO uint32_t WORD1;
3341  } MB[64];
3342  uint8_t RESERVED_4[1024];
3343  __IO uint32_t RXIMR[64];
3344  uint8_t RESERVED_5[96];
3345  __IO uint32_t GFWR;
3346 } CAN_Type;
3347 
3348 /* ----------------------------------------------------------------------------
3349  -- CAN Register Masks
3350  ---------------------------------------------------------------------------- */
3351 
3359 #define CAN_MCR_MAXMB_MASK (0x7FU)
3360 #define CAN_MCR_MAXMB_SHIFT (0U)
3361 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
3362 #define CAN_MCR_IDAM_MASK (0x300U)
3363 #define CAN_MCR_IDAM_SHIFT (8U)
3364 
3370 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
3371 #define CAN_MCR_AEN_MASK (0x1000U)
3372 #define CAN_MCR_AEN_SHIFT (12U)
3373 
3377 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
3378 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
3379 #define CAN_MCR_LPRIOEN_SHIFT (13U)
3380 
3384 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
3385 #define CAN_MCR_IRMQ_MASK (0x10000U)
3386 #define CAN_MCR_IRMQ_SHIFT (16U)
3387 
3391 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
3392 #define CAN_MCR_SRXDIS_MASK (0x20000U)
3393 #define CAN_MCR_SRXDIS_SHIFT (17U)
3394 
3398 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
3399 #define CAN_MCR_WAKSRC_MASK (0x80000U)
3400 #define CAN_MCR_WAKSRC_SHIFT (19U)
3401 
3405 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
3406 #define CAN_MCR_LPMACK_MASK (0x100000U)
3407 #define CAN_MCR_LPMACK_SHIFT (20U)
3408 
3412 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
3413 #define CAN_MCR_WRNEN_MASK (0x200000U)
3414 #define CAN_MCR_WRNEN_SHIFT (21U)
3415 
3419 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
3420 #define CAN_MCR_SLFWAK_MASK (0x400000U)
3421 #define CAN_MCR_SLFWAK_SHIFT (22U)
3422 
3426 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
3427 #define CAN_MCR_SUPV_MASK (0x800000U)
3428 #define CAN_MCR_SUPV_SHIFT (23U)
3429 
3434 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
3435 #define CAN_MCR_FRZACK_MASK (0x1000000U)
3436 #define CAN_MCR_FRZACK_SHIFT (24U)
3437 
3441 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
3442 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
3443 #define CAN_MCR_SOFTRST_SHIFT (25U)
3444 
3448 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
3449 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
3450 #define CAN_MCR_WAKMSK_SHIFT (26U)
3451 
3455 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
3456 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
3457 #define CAN_MCR_NOTRDY_SHIFT (27U)
3458 
3462 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
3463 #define CAN_MCR_HALT_MASK (0x10000000U)
3464 #define CAN_MCR_HALT_SHIFT (28U)
3465 
3469 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
3470 #define CAN_MCR_RFEN_MASK (0x20000000U)
3471 #define CAN_MCR_RFEN_SHIFT (29U)
3472 
3476 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
3477 #define CAN_MCR_FRZ_MASK (0x40000000U)
3478 #define CAN_MCR_FRZ_SHIFT (30U)
3479 
3483 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
3484 #define CAN_MCR_MDIS_MASK (0x80000000U)
3485 #define CAN_MCR_MDIS_SHIFT (31U)
3486 
3490 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
3491 
3495 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
3496 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
3497 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
3498 #define CAN_CTRL1_LOM_MASK (0x8U)
3499 #define CAN_CTRL1_LOM_SHIFT (3U)
3500 
3504 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
3505 #define CAN_CTRL1_LBUF_MASK (0x10U)
3506 #define CAN_CTRL1_LBUF_SHIFT (4U)
3507 
3511 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
3512 #define CAN_CTRL1_TSYN_MASK (0x20U)
3513 #define CAN_CTRL1_TSYN_SHIFT (5U)
3514 
3518 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
3519 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
3520 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
3521 
3525 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
3526 #define CAN_CTRL1_SMP_MASK (0x80U)
3527 #define CAN_CTRL1_SMP_SHIFT (7U)
3528 
3533 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
3534 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
3535 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
3536 
3540 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
3541 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
3542 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
3543 
3547 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
3548 #define CAN_CTRL1_LPB_MASK (0x1000U)
3549 #define CAN_CTRL1_LPB_SHIFT (12U)
3550 
3554 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
3555 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
3556 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
3557 
3561 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
3562 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
3563 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
3564 
3568 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
3569 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
3570 #define CAN_CTRL1_PSEG2_SHIFT (16U)
3571 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
3572 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
3573 #define CAN_CTRL1_PSEG1_SHIFT (19U)
3574 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
3575 #define CAN_CTRL1_RJW_MASK (0xC00000U)
3576 #define CAN_CTRL1_RJW_SHIFT (22U)
3577 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
3578 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
3579 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
3580 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
3581 
3585 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
3586 #define CAN_TIMER_TIMER_SHIFT (0U)
3587 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
3588 
3592 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
3593 #define CAN_RXMGMASK_MG_SHIFT (0U)
3594 
3598 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
3599 
3603 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
3604 #define CAN_RX14MASK_RX14M_SHIFT (0U)
3605 
3609 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
3610 
3614 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
3615 #define CAN_RX15MASK_RX15M_SHIFT (0U)
3616 
3620 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
3621 
3625 #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
3626 #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
3627 #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
3628 #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
3629 #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
3630 #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
3631 
3635 #define CAN_ESR1_WAKINT_MASK (0x1U)
3636 #define CAN_ESR1_WAKINT_SHIFT (0U)
3637 
3641 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
3642 #define CAN_ESR1_ERRINT_MASK (0x2U)
3643 #define CAN_ESR1_ERRINT_SHIFT (1U)
3644 
3648 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
3649 #define CAN_ESR1_BOFFINT_MASK (0x4U)
3650 #define CAN_ESR1_BOFFINT_SHIFT (2U)
3651 
3655 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
3656 #define CAN_ESR1_RX_MASK (0x8U)
3657 #define CAN_ESR1_RX_SHIFT (3U)
3658 
3662 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
3663 #define CAN_ESR1_FLTCONF_MASK (0x30U)
3664 #define CAN_ESR1_FLTCONF_SHIFT (4U)
3665 
3670 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
3671 #define CAN_ESR1_TX_MASK (0x40U)
3672 #define CAN_ESR1_TX_SHIFT (6U)
3673 
3677 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
3678 #define CAN_ESR1_IDLE_MASK (0x80U)
3679 #define CAN_ESR1_IDLE_SHIFT (7U)
3680 
3684 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
3685 #define CAN_ESR1_RXWRN_MASK (0x100U)
3686 #define CAN_ESR1_RXWRN_SHIFT (8U)
3687 
3691 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
3692 #define CAN_ESR1_TXWRN_MASK (0x200U)
3693 #define CAN_ESR1_TXWRN_SHIFT (9U)
3694 
3698 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
3699 #define CAN_ESR1_STFERR_MASK (0x400U)
3700 #define CAN_ESR1_STFERR_SHIFT (10U)
3701 
3705 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
3706 #define CAN_ESR1_FRMERR_MASK (0x800U)
3707 #define CAN_ESR1_FRMERR_SHIFT (11U)
3708 
3712 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
3713 #define CAN_ESR1_CRCERR_MASK (0x1000U)
3714 #define CAN_ESR1_CRCERR_SHIFT (12U)
3715 
3719 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
3720 #define CAN_ESR1_ACKERR_MASK (0x2000U)
3721 #define CAN_ESR1_ACKERR_SHIFT (13U)
3722 
3726 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
3727 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
3728 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
3729 
3733 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
3734 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
3735 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
3736 
3740 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
3741 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
3742 #define CAN_ESR1_RWRNINT_SHIFT (16U)
3743 
3747 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
3748 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
3749 #define CAN_ESR1_TWRNINT_SHIFT (17U)
3750 
3754 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
3755 #define CAN_ESR1_SYNCH_MASK (0x40000U)
3756 #define CAN_ESR1_SYNCH_SHIFT (18U)
3757 
3761 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
3762 
3766 #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
3767 #define CAN_IMASK2_BUFHM_SHIFT (0U)
3768 
3772 #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
3773 
3777 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
3778 #define CAN_IMASK1_BUFLM_SHIFT (0U)
3779 
3783 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
3784 
3788 #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
3789 #define CAN_IFLAG2_BUFHI_SHIFT (0U)
3790 
3794 #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
3795 
3799 #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
3800 #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
3801 
3805 #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
3806 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
3807 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
3808 
3812 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
3813 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
3814 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
3815 
3819 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
3820 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
3821 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
3822 
3826 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
3827 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
3828 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
3829 
3833 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
3834 
3838 #define CAN_CTRL2_EACEN_MASK (0x10000U)
3839 #define CAN_CTRL2_EACEN_SHIFT (16U)
3840 
3845 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
3846 #define CAN_CTRL2_RRS_MASK (0x20000U)
3847 #define CAN_CTRL2_RRS_SHIFT (17U)
3848 
3852 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
3853 #define CAN_CTRL2_MRP_MASK (0x40000U)
3854 #define CAN_CTRL2_MRP_SHIFT (18U)
3855 
3859 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
3860 #define CAN_CTRL2_TASD_MASK (0xF80000U)
3861 #define CAN_CTRL2_TASD_SHIFT (19U)
3862 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
3863 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
3864 #define CAN_CTRL2_RFFN_SHIFT (24U)
3865 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
3866 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
3867 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
3868 
3872 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
3873 
3877 #define CAN_ESR2_IMB_MASK (0x2000U)
3878 #define CAN_ESR2_IMB_SHIFT (13U)
3879 
3883 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
3884 #define CAN_ESR2_VPS_MASK (0x4000U)
3885 #define CAN_ESR2_VPS_SHIFT (14U)
3886 
3890 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
3891 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
3892 #define CAN_ESR2_LPTM_SHIFT (16U)
3893 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
3894 
3898 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
3899 #define CAN_CRCR_TXCRC_SHIFT (0U)
3900 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
3901 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
3902 #define CAN_CRCR_MBCRC_SHIFT (16U)
3903 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
3904 
3908 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
3909 #define CAN_RXFGMASK_FGM_SHIFT (0U)
3910 
3914 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
3915 
3919 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
3920 #define CAN_RXFIR_IDHIT_SHIFT (0U)
3921 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
3922 
3926 #define CAN_DBG1_CFSM_MASK (0x3FU)
3927 #define CAN_DBG1_CFSM_SHIFT (0U)
3928 
3930 #define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
3931 #define CAN_DBG1_CBN_MASK (0x1F000000U)
3932 #define CAN_DBG1_CBN_SHIFT (24U)
3933 
3935 #define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
3936 
3940 #define CAN_DBG2_RMP_MASK (0x7FU)
3941 #define CAN_DBG2_RMP_SHIFT (0U)
3942 
3944 #define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
3945 #define CAN_DBG2_MPP_MASK (0x80U)
3946 #define CAN_DBG2_MPP_SHIFT (7U)
3947 
3951 #define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
3952 #define CAN_DBG2_TAP_MASK (0x7F00U)
3953 #define CAN_DBG2_TAP_SHIFT (8U)
3954 
3956 #define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
3957 #define CAN_DBG2_APP_MASK (0x8000U)
3958 #define CAN_DBG2_APP_SHIFT (15U)
3959 
3963 #define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
3964 
3968 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
3969 #define CAN_CS_TIME_STAMP_SHIFT (0U)
3970 
3974 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
3975 #define CAN_CS_DLC_MASK (0xF0000U)
3976 #define CAN_CS_DLC_SHIFT (16U)
3977 
3979 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
3980 #define CAN_CS_RTR_MASK (0x100000U)
3981 #define CAN_CS_RTR_SHIFT (20U)
3982 
3984 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
3985 #define CAN_CS_IDE_MASK (0x200000U)
3986 #define CAN_CS_IDE_SHIFT (21U)
3987 
3989 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
3990 #define CAN_CS_SRR_MASK (0x400000U)
3991 #define CAN_CS_SRR_SHIFT (22U)
3992 
3994 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
3995 #define CAN_CS_CODE_MASK (0xF000000U)
3996 #define CAN_CS_CODE_SHIFT (24U)
3997 
3999 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4000 
4002 /* The count of CAN_CS */
4003 #define CAN_CS_COUNT (64U)
4004 
4007 #define CAN_ID_EXT_MASK (0x3FFFFU)
4008 #define CAN_ID_EXT_SHIFT (0U)
4009 
4011 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4012 #define CAN_ID_STD_MASK (0x1FFC0000U)
4013 #define CAN_ID_STD_SHIFT (18U)
4014 
4016 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4017 #define CAN_ID_PRIO_MASK (0xE0000000U)
4018 #define CAN_ID_PRIO_SHIFT (29U)
4019 
4023 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4024 
4026 /* The count of CAN_ID */
4027 #define CAN_ID_COUNT (64U)
4028 
4031 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4032 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4033 
4035 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4036 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4037 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4038 
4040 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4041 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4042 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4043 
4045 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4046 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4047 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4048 
4050 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4051 
4053 /* The count of CAN_WORD0 */
4054 #define CAN_WORD0_COUNT (64U)
4055 
4058 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4059 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4060 
4062 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4063 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4064 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4065 
4067 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4068 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4069 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4070 
4072 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4073 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4074 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4075 
4077 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4078 
4080 /* The count of CAN_WORD1 */
4081 #define CAN_WORD1_COUNT (64U)
4082 
4085 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4086 #define CAN_RXIMR_MI_SHIFT (0U)
4087 
4091 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4092 
4094 /* The count of CAN_RXIMR */
4095 #define CAN_RXIMR_COUNT (64U)
4096 
4099 #define CAN_GFWR_GFWR_MASK (0xFFU)
4100 #define CAN_GFWR_GFWR_SHIFT (0U)
4101 #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
4102  /* end of group CAN_Register_Masks */
4108 
4109 
4110 /* CAN - Peripheral instance base addresses */
4112 #define CAN1_BASE (0x401D0000u)
4113 
4114 #define CAN1 ((CAN_Type *)CAN1_BASE)
4115 
4116 #define CAN2_BASE (0x401D4000u)
4117 
4118 #define CAN2 ((CAN_Type *)CAN2_BASE)
4119 
4120 #define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }
4121 
4122 #define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }
4123 
4124 #define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
4125 #define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
4126 #define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
4127 #define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
4128 #define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
4129 #define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
4130 /* Backward compatibility */
4131 #define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK
4132 #define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT
4133 #define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)
4134 #define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK
4135 #define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT
4136 #define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)
4137 
4138  /* end of group CAN_Peripheral_Access_Layer */
4142 
4143 
4144 /* ----------------------------------------------------------------------------
4145  -- CCM Peripheral Access Layer
4146  ---------------------------------------------------------------------------- */
4147 
4154 typedef struct {
4155  __IO uint32_t CCR;
4156  uint8_t RESERVED_0[4];
4157  __I uint32_t CSR;
4158  __IO uint32_t CCSR;
4159  __IO uint32_t CACRR;
4160  __IO uint32_t CBCDR;
4161  __IO uint32_t CBCMR;
4162  __IO uint32_t CSCMR1;
4163  __IO uint32_t CSCMR2;
4164  __IO uint32_t CSCDR1;
4165  __IO uint32_t CS1CDR;
4166  __IO uint32_t CS2CDR;
4167  __IO uint32_t CDCDR;
4168  uint8_t RESERVED_1[4];
4169  __IO uint32_t CSCDR2;
4170  __IO uint32_t CSCDR3;
4171  uint8_t RESERVED_2[8];
4172  __I uint32_t CDHIPR;
4173  uint8_t RESERVED_3[8];
4174  __IO uint32_t CLPCR;
4175  __IO uint32_t CISR;
4176  __IO uint32_t CIMR;
4177  __IO uint32_t CCOSR;
4178  __IO uint32_t CGPR;
4179  __IO uint32_t CCGR0;
4180  __IO uint32_t CCGR1;
4181  __IO uint32_t CCGR2;
4182  __IO uint32_t CCGR3;
4183  __IO uint32_t CCGR4;
4184  __IO uint32_t CCGR5;
4185  __IO uint32_t CCGR6;
4186  uint8_t RESERVED_4[4];
4187  __IO uint32_t CMEOR;
4188 } CCM_Type;
4189 
4190 /* ----------------------------------------------------------------------------
4191  -- CCM Register Masks
4192  ---------------------------------------------------------------------------- */
4193 
4201 #define CCM_CCR_OSCNT_MASK (0xFFU)
4202 #define CCM_CCR_OSCNT_SHIFT (0U)
4203 
4209 #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
4210 #define CCM_CCR_COSC_EN_MASK (0x1000U)
4211 #define CCM_CCR_COSC_EN_SHIFT (12U)
4212 
4216 #define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
4217 #define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
4218 #define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
4219 
4224 #define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
4225 #define CCM_CCR_RBC_EN_MASK (0x8000000U)
4226 #define CCM_CCR_RBC_EN_SHIFT (27U)
4227 
4231 #define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
4232 
4236 #define CCM_CSR_REF_EN_B_MASK (0x1U)
4237 #define CCM_CSR_REF_EN_B_SHIFT (0U)
4238 
4242 #define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
4243 #define CCM_CSR_CAMP2_READY_MASK (0x8U)
4244 #define CCM_CSR_CAMP2_READY_SHIFT (3U)
4245 
4249 #define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
4250 #define CCM_CSR_COSC_READY_MASK (0x20U)
4251 #define CCM_CSR_COSC_READY_SHIFT (5U)
4252 
4256 #define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
4257 
4261 #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
4262 #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
4263 
4267 #define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
4268 
4272 #define CCM_CACRR_ARM_PODF_MASK (0x7U)
4273 #define CCM_CACRR_ARM_PODF_SHIFT (0U)
4274 
4284 #define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
4285 
4289 #define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
4290 #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
4291 
4295 #define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
4296 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
4297 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
4298 
4302 #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
4303 #define CCM_CBCDR_IPG_PODF_MASK (0x300U)
4304 #define CCM_CBCDR_IPG_PODF_SHIFT (8U)
4305 
4311 #define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
4312 #define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
4313 #define CCM_CBCDR_AHB_PODF_SHIFT (10U)
4314 
4324 #define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
4325 #define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
4326 #define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
4327 
4337 #define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
4338 #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
4339 #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
4340 
4344 #define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
4345 #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
4346 #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
4347 
4357 #define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
4358 
4362 #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
4363 #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
4364 
4370 #define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
4371 #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
4372 #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
4373 
4379 #define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
4380 #define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
4381 #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
4382 
4388 #define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
4389 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
4390 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
4391 
4397 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
4398 #define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
4399 #define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
4400 
4410 #define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
4411 #define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
4412 #define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
4413 
4423 #define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
4424 
4428 #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
4429 #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
4430 
4496 #define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
4497 #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
4498 #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
4499 
4503 #define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
4504 #define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
4505 #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
4506 
4512 #define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
4513 #define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
4514 #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
4515 
4521 #define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
4522 #define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
4523 #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
4524 
4530 #define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
4531 #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
4532 #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
4533 
4537 #define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
4538 #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
4539 #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
4540 
4544 #define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
4545 #define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
4546 #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
4547 
4557 #define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
4558 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
4559 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
4560 
4566 #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
4567 
4571 #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
4572 #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
4573 
4639 #define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
4640 #define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
4641 #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
4642 
4648 #define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
4649 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
4650 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
4651 
4657 #define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
4658 
4662 #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
4663 #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
4664 
4730 #define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
4731 #define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
4732 #define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
4733 
4737 #define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
4738 #define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
4739 #define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
4740 
4750 #define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
4751 #define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
4752 #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
4753 
4763 #define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
4764 #define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
4765 #define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
4766 
4772 #define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
4773 
4777 #define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
4778 #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
4779 
4846 #define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
4847 #define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
4848 #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
4849 
4859 #define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
4860 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
4861 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
4862 
4872 #define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
4873 #define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
4874 #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
4875 
4942 #define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
4943 #define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
4944 #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
4945 
4955 #define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
4956 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
4957 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
4958 
4968 #define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
4969 
4973 #define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
4974 #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
4975 
5042 #define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
5043 #define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
5044 #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
5045 
5055 #define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
5056 
5060 #define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
5061 #define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
5062 
5068 #define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
5069 #define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
5070 #define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
5071 
5081 #define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
5082 #define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
5083 #define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
5084 
5094 #define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
5095 #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
5096 #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
5097 
5103 #define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
5104 #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
5105 #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
5106 
5116 #define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
5117 #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
5118 #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
5119 
5129 #define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
5130 
5134 #define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
5135 #define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
5136 
5146 #define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
5147 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
5148 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
5149 
5157 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
5158 #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
5159 #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
5160 
5164 #define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
5165 #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
5166 #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
5167 
5235 #define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
5236 
5240 #define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
5241 #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
5242 
5248 #define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
5249 #define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
5250 #define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
5251 
5261 #define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
5262 
5266 #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
5267 #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
5268 
5273 #define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
5274 #define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
5275 #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
5276 
5281 #define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
5282 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
5283 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
5284 
5289 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
5290 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
5291 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
5292 
5297 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
5298 #define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
5299 #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
5300 
5305 #define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
5306 
5310 #define CCM_CLPCR_LPM_MASK (0x3U)
5311 #define CCM_CLPCR_LPM_SHIFT (0U)
5312 
5318 #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
5319 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
5320 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
5321 
5325 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
5326 #define CCM_CLPCR_SBYOS_MASK (0x40U)
5327 #define CCM_CLPCR_SBYOS_SHIFT (6U)
5328 
5336 #define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
5337 #define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
5338 #define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
5339 
5343 #define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
5344 #define CCM_CLPCR_VSTBY_MASK (0x100U)
5345 #define CCM_CLPCR_VSTBY_SHIFT (8U)
5346 
5350 #define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
5351 #define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
5352 #define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
5353 
5359 #define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
5360 #define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
5361 #define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
5362 
5366 #define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
5367 #define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
5368 #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
5369 #define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
5370 #define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
5371 #define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
5372 #define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
5373 #define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
5374 #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
5375 
5379 #define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
5380 #define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
5381 #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
5382 
5386 #define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
5387 #define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
5388 #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
5389 
5393 #define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
5394 
5398 #define CCM_CISR_LRF_PLL_MASK (0x1U)
5399 #define CCM_CISR_LRF_PLL_SHIFT (0U)
5400 
5404 #define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
5405 #define CCM_CISR_COSC_READY_MASK (0x40U)
5406 #define CCM_CISR_COSC_READY_SHIFT (6U)
5407 
5411 #define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
5412 #define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
5413 #define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
5414 
5418 #define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
5419 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
5420 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
5421 
5425 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
5426 #define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
5427 #define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
5428 
5432 #define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
5433 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
5434 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
5435 
5439 #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
5440 #define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
5441 #define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
5442 
5446 #define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
5447 
5451 #define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
5452 #define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
5453 
5457 #define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
5458 #define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
5459 #define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
5460 
5464 #define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
5465 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
5466 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
5467 
5471 #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
5472 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
5473 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
5474 
5478 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
5479 #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
5480 #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
5481 
5485 #define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
5486 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
5487 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
5488 
5492 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
5493 #define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
5494 #define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
5495 
5499 #define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
5500 
5504 #define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
5505 #define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
5506 
5519 #define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
5520 #define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
5521 #define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
5522 
5532 #define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
5533 #define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
5534 #define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
5535 
5539 #define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
5540 #define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
5541 #define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
5542 
5546 #define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
5547 #define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
5548 #define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
5549 
5565 #define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
5566 #define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
5567 #define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
5568 
5578 #define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
5579 #define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
5580 #define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
5581 
5585 #define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
5586 
5590 #define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
5591 #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
5592 
5596 #define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
5597 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
5598 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
5599 
5603 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
5604 #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
5605 #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
5606 
5611 #define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
5612 #define CCM_CGPR_FPL_MASK (0x10000U)
5613 #define CCM_CGPR_FPL_SHIFT (16U)
5614 
5618 #define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
5619 #define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
5620 #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
5621 
5626 #define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
5627 
5631 #define CCM_CCGR0_CG0_MASK (0x3U)
5632 #define CCM_CCGR0_CG0_SHIFT (0U)
5633 #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
5634 #define CCM_CCGR0_CG1_MASK (0xCU)
5635 #define CCM_CCGR0_CG1_SHIFT (2U)
5636 #define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
5637 #define CCM_CCGR0_CG2_MASK (0x30U)
5638 #define CCM_CCGR0_CG2_SHIFT (4U)
5639 #define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
5640 #define CCM_CCGR0_CG3_MASK (0xC0U)
5641 #define CCM_CCGR0_CG3_SHIFT (6U)
5642 #define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
5643 #define CCM_CCGR0_CG4_MASK (0x300U)
5644 #define CCM_CCGR0_CG4_SHIFT (8U)
5645 #define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
5646 #define CCM_CCGR0_CG5_MASK (0xC00U)
5647 #define CCM_CCGR0_CG5_SHIFT (10U)
5648 #define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
5649 #define CCM_CCGR0_CG6_MASK (0x3000U)
5650 #define CCM_CCGR0_CG6_SHIFT (12U)
5651 #define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
5652 #define CCM_CCGR0_CG7_MASK (0xC000U)
5653 #define CCM_CCGR0_CG7_SHIFT (14U)
5654 #define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
5655 #define CCM_CCGR0_CG8_MASK (0x30000U)
5656 #define CCM_CCGR0_CG8_SHIFT (16U)
5657 #define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
5658 #define CCM_CCGR0_CG9_MASK (0xC0000U)
5659 #define CCM_CCGR0_CG9_SHIFT (18U)
5660 #define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
5661 #define CCM_CCGR0_CG10_MASK (0x300000U)
5662 #define CCM_CCGR0_CG10_SHIFT (20U)
5663 #define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
5664 #define CCM_CCGR0_CG11_MASK (0xC00000U)
5665 #define CCM_CCGR0_CG11_SHIFT (22U)
5666 #define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
5667 #define CCM_CCGR0_CG12_MASK (0x3000000U)
5668 #define CCM_CCGR0_CG12_SHIFT (24U)
5669 #define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
5670 #define CCM_CCGR0_CG13_MASK (0xC000000U)
5671 #define CCM_CCGR0_CG13_SHIFT (26U)
5672 #define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
5673 #define CCM_CCGR0_CG14_MASK (0x30000000U)
5674 #define CCM_CCGR0_CG14_SHIFT (28U)
5675 #define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
5676 #define CCM_CCGR0_CG15_MASK (0xC0000000U)
5677 #define CCM_CCGR0_CG15_SHIFT (30U)
5678 #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
5679 
5683 #define CCM_CCGR1_CG0_MASK (0x3U)
5684 #define CCM_CCGR1_CG0_SHIFT (0U)
5685 #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
5686 #define CCM_CCGR1_CG1_MASK (0xCU)
5687 #define CCM_CCGR1_CG1_SHIFT (2U)
5688 #define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
5689 #define CCM_CCGR1_CG2_MASK (0x30U)
5690 #define CCM_CCGR1_CG2_SHIFT (4U)
5691 #define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
5692 #define CCM_CCGR1_CG3_MASK (0xC0U)
5693 #define CCM_CCGR1_CG3_SHIFT (6U)
5694 #define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
5695 #define CCM_CCGR1_CG4_MASK (0x300U)
5696 #define CCM_CCGR1_CG4_SHIFT (8U)
5697 #define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
5698 #define CCM_CCGR1_CG5_MASK (0xC00U)
5699 #define CCM_CCGR1_CG5_SHIFT (10U)
5700 #define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
5701 #define CCM_CCGR1_CG6_MASK (0x3000U)
5702 #define CCM_CCGR1_CG6_SHIFT (12U)
5703 #define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
5704 #define CCM_CCGR1_CG7_MASK (0xC000U)
5705 #define CCM_CCGR1_CG7_SHIFT (14U)
5706 #define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
5707 #define CCM_CCGR1_CG8_MASK (0x30000U)
5708 #define CCM_CCGR1_CG8_SHIFT (16U)
5709 #define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
5710 #define CCM_CCGR1_CG9_MASK (0xC0000U)
5711 #define CCM_CCGR1_CG9_SHIFT (18U)
5712 #define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
5713 #define CCM_CCGR1_CG10_MASK (0x300000U)
5714 #define CCM_CCGR1_CG10_SHIFT (20U)
5715 #define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
5716 #define CCM_CCGR1_CG11_MASK (0xC00000U)
5717 #define CCM_CCGR1_CG11_SHIFT (22U)
5718 #define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
5719 #define CCM_CCGR1_CG12_MASK (0x3000000U)
5720 #define CCM_CCGR1_CG12_SHIFT (24U)
5721 #define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
5722 #define CCM_CCGR1_CG13_MASK (0xC000000U)
5723 #define CCM_CCGR1_CG13_SHIFT (26U)
5724 #define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
5725 #define CCM_CCGR1_CG14_MASK (0x30000000U)
5726 #define CCM_CCGR1_CG14_SHIFT (28U)
5727 #define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
5728 #define CCM_CCGR1_CG15_MASK (0xC0000000U)
5729 #define CCM_CCGR1_CG15_SHIFT (30U)
5730 #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
5731 
5735 #define CCM_CCGR2_CG0_MASK (0x3U)
5736 #define CCM_CCGR2_CG0_SHIFT (0U)
5737 #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
5738 #define CCM_CCGR2_CG1_MASK (0xCU)
5739 #define CCM_CCGR2_CG1_SHIFT (2U)
5740 #define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
5741 #define CCM_CCGR2_CG2_MASK (0x30U)
5742 #define CCM_CCGR2_CG2_SHIFT (4U)
5743 #define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
5744 #define CCM_CCGR2_CG3_MASK (0xC0U)
5745 #define CCM_CCGR2_CG3_SHIFT (6U)
5746 #define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
5747 #define CCM_CCGR2_CG4_MASK (0x300U)
5748 #define CCM_CCGR2_CG4_SHIFT (8U)
5749 #define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
5750 #define CCM_CCGR2_CG5_MASK (0xC00U)
5751 #define CCM_CCGR2_CG5_SHIFT (10U)
5752 #define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
5753 #define CCM_CCGR2_CG6_MASK (0x3000U)
5754 #define CCM_CCGR2_CG6_SHIFT (12U)
5755 #define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
5756 #define CCM_CCGR2_CG7_MASK (0xC000U)
5757 #define CCM_CCGR2_CG7_SHIFT (14U)
5758 #define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
5759 #define CCM_CCGR2_CG8_MASK (0x30000U)
5760 #define CCM_CCGR2_CG8_SHIFT (16U)
5761 #define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
5762 #define CCM_CCGR2_CG9_MASK (0xC0000U)
5763 #define CCM_CCGR2_CG9_SHIFT (18U)
5764 #define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
5765 #define CCM_CCGR2_CG10_MASK (0x300000U)
5766 #define CCM_CCGR2_CG10_SHIFT (20U)
5767 #define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
5768 #define CCM_CCGR2_CG11_MASK (0xC00000U)
5769 #define CCM_CCGR2_CG11_SHIFT (22U)
5770 #define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
5771 #define CCM_CCGR2_CG12_MASK (0x3000000U)
5772 #define CCM_CCGR2_CG12_SHIFT (24U)
5773 #define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
5774 #define CCM_CCGR2_CG13_MASK (0xC000000U)
5775 #define CCM_CCGR2_CG13_SHIFT (26U)
5776 #define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
5777 #define CCM_CCGR2_CG14_MASK (0x30000000U)
5778 #define CCM_CCGR2_CG14_SHIFT (28U)
5779 #define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
5780 #define CCM_CCGR2_CG15_MASK (0xC0000000U)
5781 #define CCM_CCGR2_CG15_SHIFT (30U)
5782 #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
5783 
5787 #define CCM_CCGR3_CG0_MASK (0x3U)
5788 #define CCM_CCGR3_CG0_SHIFT (0U)
5789 #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
5790 #define CCM_CCGR3_CG1_MASK (0xCU)
5791 #define CCM_CCGR3_CG1_SHIFT (2U)
5792 #define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
5793 #define CCM_CCGR3_CG2_MASK (0x30U)
5794 #define CCM_CCGR3_CG2_SHIFT (4U)
5795 #define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
5796 #define CCM_CCGR3_CG3_MASK (0xC0U)
5797 #define CCM_CCGR3_CG3_SHIFT (6U)
5798 #define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
5799 #define CCM_CCGR3_CG4_MASK (0x300U)
5800 #define CCM_CCGR3_CG4_SHIFT (8U)
5801 #define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
5802 #define CCM_CCGR3_CG5_MASK (0xC00U)
5803 #define CCM_CCGR3_CG5_SHIFT (10U)
5804 #define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
5805 #define CCM_CCGR3_CG6_MASK (0x3000U)
5806 #define CCM_CCGR3_CG6_SHIFT (12U)
5807 #define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
5808 #define CCM_CCGR3_CG7_MASK (0xC000U)
5809 #define CCM_CCGR3_CG7_SHIFT (14U)
5810 #define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
5811 #define CCM_CCGR3_CG8_MASK (0x30000U)
5812 #define CCM_CCGR3_CG8_SHIFT (16U)
5813 #define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
5814 #define CCM_CCGR3_CG9_MASK (0xC0000U)
5815 #define CCM_CCGR3_CG9_SHIFT (18U)
5816 #define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
5817 #define CCM_CCGR3_CG10_MASK (0x300000U)
5818 #define CCM_CCGR3_CG10_SHIFT (20U)
5819 #define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
5820 #define CCM_CCGR3_CG11_MASK (0xC00000U)
5821 #define CCM_CCGR3_CG11_SHIFT (22U)
5822 #define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
5823 #define CCM_CCGR3_CG12_MASK (0x3000000U)
5824 #define CCM_CCGR3_CG12_SHIFT (24U)
5825 #define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
5826 #define CCM_CCGR3_CG13_MASK (0xC000000U)
5827 #define CCM_CCGR3_CG13_SHIFT (26U)
5828 #define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
5829 #define CCM_CCGR3_CG14_MASK (0x30000000U)
5830 #define CCM_CCGR3_CG14_SHIFT (28U)
5831 #define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
5832 #define CCM_CCGR3_CG15_MASK (0xC0000000U)
5833 #define CCM_CCGR3_CG15_SHIFT (30U)
5834 #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
5835 
5839 #define CCM_CCGR4_CG0_MASK (0x3U)
5840 #define CCM_CCGR4_CG0_SHIFT (0U)
5841 #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
5842 #define CCM_CCGR4_CG1_MASK (0xCU)
5843 #define CCM_CCGR4_CG1_SHIFT (2U)
5844 #define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
5845 #define CCM_CCGR4_CG2_MASK (0x30U)
5846 #define CCM_CCGR4_CG2_SHIFT (4U)
5847 #define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
5848 #define CCM_CCGR4_CG3_MASK (0xC0U)
5849 #define CCM_CCGR4_CG3_SHIFT (6U)
5850 #define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
5851 #define CCM_CCGR4_CG4_MASK (0x300U)
5852 #define CCM_CCGR4_CG4_SHIFT (8U)
5853 #define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
5854 #define CCM_CCGR4_CG5_MASK (0xC00U)
5855 #define CCM_CCGR4_CG5_SHIFT (10U)
5856 #define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
5857 #define CCM_CCGR4_CG6_MASK (0x3000U)
5858 #define CCM_CCGR4_CG6_SHIFT (12U)
5859 #define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
5860 #define CCM_CCGR4_CG7_MASK (0xC000U)
5861 #define CCM_CCGR4_CG7_SHIFT (14U)
5862 #define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
5863 #define CCM_CCGR4_CG8_MASK (0x30000U)
5864 #define CCM_CCGR4_CG8_SHIFT (16U)
5865 #define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
5866 #define CCM_CCGR4_CG9_MASK (0xC0000U)
5867 #define CCM_CCGR4_CG9_SHIFT (18U)
5868 #define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
5869 #define CCM_CCGR4_CG10_MASK (0x300000U)
5870 #define CCM_CCGR4_CG10_SHIFT (20U)
5871 #define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
5872 #define CCM_CCGR4_CG11_MASK (0xC00000U)
5873 #define CCM_CCGR4_CG11_SHIFT (22U)
5874 #define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
5875 #define CCM_CCGR4_CG12_MASK (0x3000000U)
5876 #define CCM_CCGR4_CG12_SHIFT (24U)
5877 #define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
5878 #define CCM_CCGR4_CG13_MASK (0xC000000U)
5879 #define CCM_CCGR4_CG13_SHIFT (26U)
5880 #define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
5881 #define CCM_CCGR4_CG14_MASK (0x30000000U)
5882 #define CCM_CCGR4_CG14_SHIFT (28U)
5883 #define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
5884 #define CCM_CCGR4_CG15_MASK (0xC0000000U)
5885 #define CCM_CCGR4_CG15_SHIFT (30U)
5886 #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
5887 
5891 #define CCM_CCGR5_CG0_MASK (0x3U)
5892 #define CCM_CCGR5_CG0_SHIFT (0U)
5893 #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
5894 #define CCM_CCGR5_CG1_MASK (0xCU)
5895 #define CCM_CCGR5_CG1_SHIFT (2U)
5896 #define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
5897 #define CCM_CCGR5_CG2_MASK (0x30U)
5898 #define CCM_CCGR5_CG2_SHIFT (4U)
5899 #define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
5900 #define CCM_CCGR5_CG3_MASK (0xC0U)
5901 #define CCM_CCGR5_CG3_SHIFT (6U)
5902 #define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
5903 #define CCM_CCGR5_CG4_MASK (0x300U)
5904 #define CCM_CCGR5_CG4_SHIFT (8U)
5905 #define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
5906 #define CCM_CCGR5_CG5_MASK (0xC00U)
5907 #define CCM_CCGR5_CG5_SHIFT (10U)
5908 #define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
5909 #define CCM_CCGR5_CG6_MASK (0x3000U)
5910 #define CCM_CCGR5_CG6_SHIFT (12U)
5911 #define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
5912 #define CCM_CCGR5_CG7_MASK (0xC000U)
5913 #define CCM_CCGR5_CG7_SHIFT (14U)
5914 #define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
5915 #define CCM_CCGR5_CG8_MASK (0x30000U)
5916 #define CCM_CCGR5_CG8_SHIFT (16U)
5917 #define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
5918 #define CCM_CCGR5_CG9_MASK (0xC0000U)
5919 #define CCM_CCGR5_CG9_SHIFT (18U)
5920 #define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
5921 #define CCM_CCGR5_CG10_MASK (0x300000U)
5922 #define CCM_CCGR5_CG10_SHIFT (20U)
5923 #define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
5924 #define CCM_CCGR5_CG11_MASK (0xC00000U)
5925 #define CCM_CCGR5_CG11_SHIFT (22U)
5926 #define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
5927 #define CCM_CCGR5_CG12_MASK (0x3000000U)
5928 #define CCM_CCGR5_CG12_SHIFT (24U)
5929 #define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
5930 #define CCM_CCGR5_CG13_MASK (0xC000000U)
5931 #define CCM_CCGR5_CG13_SHIFT (26U)
5932 #define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
5933 #define CCM_CCGR5_CG14_MASK (0x30000000U)
5934 #define CCM_CCGR5_CG14_SHIFT (28U)
5935 #define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
5936 #define CCM_CCGR5_CG15_MASK (0xC0000000U)
5937 #define CCM_CCGR5_CG15_SHIFT (30U)
5938 #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
5939 
5943 #define CCM_CCGR6_CG0_MASK (0x3U)
5944 #define CCM_CCGR6_CG0_SHIFT (0U)
5945 #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
5946 #define CCM_CCGR6_CG1_MASK (0xCU)
5947 #define CCM_CCGR6_CG1_SHIFT (2U)
5948 #define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
5949 #define CCM_CCGR6_CG2_MASK (0x30U)
5950 #define CCM_CCGR6_CG2_SHIFT (4U)
5951 #define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
5952 #define CCM_CCGR6_CG3_MASK (0xC0U)
5953 #define CCM_CCGR6_CG3_SHIFT (6U)
5954 #define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
5955 #define CCM_CCGR6_CG4_MASK (0x300U)
5956 #define CCM_CCGR6_CG4_SHIFT (8U)
5957 #define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
5958 #define CCM_CCGR6_CG5_MASK (0xC00U)
5959 #define CCM_CCGR6_CG5_SHIFT (10U)
5960 #define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
5961 #define CCM_CCGR6_CG6_MASK (0x3000U)
5962 #define CCM_CCGR6_CG6_SHIFT (12U)
5963 #define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
5964 #define CCM_CCGR6_CG7_MASK (0xC000U)
5965 #define CCM_CCGR6_CG7_SHIFT (14U)
5966 #define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
5967 #define CCM_CCGR6_CG8_MASK (0x30000U)
5968 #define CCM_CCGR6_CG8_SHIFT (16U)
5969 #define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
5970 #define CCM_CCGR6_CG9_MASK (0xC0000U)
5971 #define CCM_CCGR6_CG9_SHIFT (18U)
5972 #define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
5973 #define CCM_CCGR6_CG10_MASK (0x300000U)
5974 #define CCM_CCGR6_CG10_SHIFT (20U)
5975 #define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
5976 #define CCM_CCGR6_CG11_MASK (0xC00000U)
5977 #define CCM_CCGR6_CG11_SHIFT (22U)
5978 #define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
5979 #define CCM_CCGR6_CG12_MASK (0x3000000U)
5980 #define CCM_CCGR6_CG12_SHIFT (24U)
5981 #define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
5982 #define CCM_CCGR6_CG13_MASK (0xC000000U)
5983 #define CCM_CCGR6_CG13_SHIFT (26U)
5984 #define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
5985 #define CCM_CCGR6_CG14_MASK (0x30000000U)
5986 #define CCM_CCGR6_CG14_SHIFT (28U)
5987 #define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
5988 #define CCM_CCGR6_CG15_MASK (0xC0000000U)
5989 #define CCM_CCGR6_CG15_SHIFT (30U)
5990 #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
5991 
5995 #define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
5996 #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
5997 
6001 #define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
6002 #define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
6003 #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
6004 
6008 #define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
6009 #define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
6010 #define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
6011 
6015 #define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
6016 #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
6017 #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
6018 
6022 #define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
6023 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
6024 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
6025 
6029 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
6030 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
6031 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
6032 
6036 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
6037  /* end of group CCM_Register_Masks */
6043 
6044 
6045 /* CCM - Peripheral instance base addresses */
6047 #define CCM_BASE (0x400FC000u)
6048 
6049 #define CCM ((CCM_Type *)CCM_BASE)
6050 
6051 #define CCM_BASE_ADDRS { CCM_BASE }
6052 
6053 #define CCM_BASE_PTRS { CCM }
6054 
6055 #define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
6056  /* end of group CCM_Peripheral_Access_Layer */
6060 
6061 
6062 /* ----------------------------------------------------------------------------
6063  -- CCM_ANALOG Peripheral Access Layer
6064  ---------------------------------------------------------------------------- */
6065 
6072 typedef struct {
6073  __IO uint32_t PLL_ARM;
6074  __IO uint32_t PLL_ARM_SET;
6075  __IO uint32_t PLL_ARM_CLR;
6076  __IO uint32_t PLL_ARM_TOG;
6077  __IO uint32_t PLL_USB1;
6078  __IO uint32_t PLL_USB1_SET;
6079  __IO uint32_t PLL_USB1_CLR;
6080  __IO uint32_t PLL_USB1_TOG;
6081  __IO uint32_t PLL_USB2;
6082  __IO uint32_t PLL_USB2_SET;
6083  __IO uint32_t PLL_USB2_CLR;
6084  __IO uint32_t PLL_USB2_TOG;
6085  __IO uint32_t PLL_SYS;
6086  __IO uint32_t PLL_SYS_SET;
6087  __IO uint32_t PLL_SYS_CLR;
6088  __IO uint32_t PLL_SYS_TOG;
6089  __IO uint32_t PLL_SYS_SS;
6090  uint8_t RESERVED_0[12];
6091  __IO uint32_t PLL_SYS_NUM;
6092  uint8_t RESERVED_1[12];
6093  __IO uint32_t PLL_SYS_DENOM;
6094  uint8_t RESERVED_2[12];
6095  __IO uint32_t PLL_AUDIO;
6096  __IO uint32_t PLL_AUDIO_SET;
6097  __IO uint32_t PLL_AUDIO_CLR;
6098  __IO uint32_t PLL_AUDIO_TOG;
6099  __IO uint32_t PLL_AUDIO_NUM;
6100  uint8_t RESERVED_3[12];
6101  __IO uint32_t PLL_AUDIO_DENOM;
6102  uint8_t RESERVED_4[12];
6103  __IO uint32_t PLL_VIDEO;
6104  __IO uint32_t PLL_VIDEO_SET;
6105  __IO uint32_t PLL_VIDEO_CLR;
6106  __IO uint32_t PLL_VIDEO_TOG;
6107  __IO uint32_t PLL_VIDEO_NUM;
6108  uint8_t RESERVED_5[12];
6109  __IO uint32_t PLL_VIDEO_DENOM;
6110  uint8_t RESERVED_6[28];
6111  __IO uint32_t PLL_ENET;
6112  __IO uint32_t PLL_ENET_SET;
6113  __IO uint32_t PLL_ENET_CLR;
6114  __IO uint32_t PLL_ENET_TOG;
6115  __IO uint32_t PFD_480;
6116  __IO uint32_t PFD_480_SET;
6117  __IO uint32_t PFD_480_CLR;
6118  __IO uint32_t PFD_480_TOG;
6119  __IO uint32_t PFD_528;
6120  __IO uint32_t PFD_528_SET;
6121  __IO uint32_t PFD_528_CLR;
6122  __IO uint32_t PFD_528_TOG;
6123  uint8_t RESERVED_7[64];
6124  __IO uint32_t MISC0;
6125  __IO uint32_t MISC0_SET;
6126  __IO uint32_t MISC0_CLR;
6127  __IO uint32_t MISC0_TOG;
6128  __IO uint32_t MISC1;
6129  __IO uint32_t MISC1_SET;
6130  __IO uint32_t MISC1_CLR;
6131  __IO uint32_t MISC1_TOG;
6132  __IO uint32_t MISC2;
6133  __IO uint32_t MISC2_SET;
6134  __IO uint32_t MISC2_CLR;
6135  __IO uint32_t MISC2_TOG;
6136 } CCM_ANALOG_Type;
6137 
6138 /* ----------------------------------------------------------------------------
6139  -- CCM_ANALOG Register Masks
6140  ---------------------------------------------------------------------------- */
6141 
6149 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
6150 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
6151 #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
6152 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
6153 #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
6154 #define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
6155 #define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
6156 #define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
6157 #define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
6158 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
6159 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
6160 
6166 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
6167 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
6168 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
6169 #define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
6170 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
6171 #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
6172 #define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
6173 #define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
6174 #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
6175 #define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
6176 
6180 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
6181 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
6182 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
6183 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
6184 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
6185 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
6186 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
6187 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
6188 #define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
6189 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6190 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
6191 
6197 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
6198 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
6199 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
6200 #define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
6201 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
6202 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
6203 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
6204 #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
6205 #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
6206 #define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
6207 
6211 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
6212 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
6213 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
6214 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
6215 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
6216 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
6217 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
6218 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
6219 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
6220 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6221 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6222 
6228 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
6229 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
6230 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
6231 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
6232 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
6233 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
6234 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
6235 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
6236 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
6237 #define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
6238 
6242 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
6243 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
6244 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
6245 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
6246 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
6247 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
6248 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
6249 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
6250 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
6251 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6252 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6253 
6259 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
6260 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
6261 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
6262 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
6263 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
6264 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
6265 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
6266 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
6267 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
6268 #define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
6269 
6273 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
6274 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
6275 #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
6276 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
6277 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
6278 
6282 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
6283 #define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
6284 #define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
6285 #define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
6286 #define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
6287 #define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
6288 #define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
6289 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
6290 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
6291 
6295 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
6296 #define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
6297 #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
6298 #define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
6299 #define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
6300 #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
6301 #define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
6302 
6306 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
6307 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
6308 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
6309 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
6310 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
6311 
6315 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
6316 #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
6317 #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
6318 #define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
6319 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
6320 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
6321 #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
6322 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6323 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
6324 
6328 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
6329 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
6330 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
6331 #define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
6332 #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
6333 #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
6334 #define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
6335 
6339 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
6340 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
6341 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
6342 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
6343 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
6344 
6348 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
6349 #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
6350 #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
6351 #define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
6352 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
6353 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
6354 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
6355 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6356 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6357 
6361 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
6362 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
6363 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
6364 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
6365 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
6366 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
6367 #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
6368 
6372 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
6373 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
6374 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
6375 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
6376 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
6377 
6381 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
6382 #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
6383 #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
6384 #define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
6385 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
6386 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
6387 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
6388 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6389 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6390 
6394 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
6395 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
6396 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
6397 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
6398 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
6399 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
6400 #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
6401 
6405 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
6406 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
6407 #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
6408 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
6409 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
6410 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
6411 #define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
6412 #define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
6413 #define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
6414 #define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
6415 #define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
6416 #define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
6417 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
6418 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
6419 
6425 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
6426 #define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
6427 #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
6428 #define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
6429 #define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
6430 #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
6431 #define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
6432 
6436 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
6437 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
6438 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
6439 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
6440 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
6441 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
6442 #define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
6443 #define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
6444 #define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
6445 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
6446 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
6447 #define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
6448 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6449 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
6450 
6456 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
6457 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
6458 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
6459 #define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
6460 #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
6461 #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
6462 #define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
6463 
6467 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
6468 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
6469 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
6470 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
6471 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
6472 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
6473 #define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
6474 #define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
6475 #define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
6476 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
6477 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
6478 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
6479 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6480 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6481 
6487 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
6488 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
6489 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
6490 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
6491 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
6492 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
6493 #define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
6494 
6498 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
6499 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
6500 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
6501 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
6502 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
6503 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
6504 #define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
6505 #define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
6506 #define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
6507 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
6508 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
6509 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
6510 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6511 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6512 
6518 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
6519 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
6520 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
6521 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
6522 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
6523 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
6524 #define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
6525 
6529 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
6530 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
6531 #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
6532 #define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
6533 #define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
6534 #define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
6535 #define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
6536 #define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
6537 #define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
6538 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
6539 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
6540 
6544 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
6545 #define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
6546 #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
6547 #define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
6548 #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)
6549 #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)
6550 #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)
6551 #define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
6552 #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
6553 #define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
6554 
6558 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
6559 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
6560 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
6561 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
6562 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
6563 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
6564 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
6565 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
6566 #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
6567 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6568 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
6569 
6573 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
6574 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
6575 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
6576 #define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
6577 #define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)
6578 #define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)
6579 #define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)
6580 #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
6581 #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
6582 #define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
6583 
6587 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
6588 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
6589 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
6590 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
6591 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
6592 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
6593 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
6594 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
6595 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
6596 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6597 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6598 
6602 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
6603 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
6604 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
6605 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
6606 #define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U)
6607 #define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U)
6608 #define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK)
6609 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
6610 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
6611 #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
6612 
6616 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
6617 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
6618 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
6619 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
6620 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
6621 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
6622 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
6623 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
6624 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
6625 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6626 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6627 
6631 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
6632 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
6633 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
6634 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
6635 #define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U)
6636 #define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U)
6637 #define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK)
6638 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
6639 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
6640 #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
6641 
6645 #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
6646 #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
6647 #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
6648 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
6649 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
6650 
6654 #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
6655 #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
6656 #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
6657 #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
6658 
6662 #define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
6663 #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
6664 #define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
6665 
6669 #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
6670 #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
6671 #define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
6672 
6676 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
6677 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
6678 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
6679 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
6680 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
6681 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
6682 #define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
6683 #define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
6684 #define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
6685 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
6686 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
6687 
6693 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
6694 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
6695 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
6696 #define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
6697 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U)
6698 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U)
6699 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK)
6700 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
6701 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
6702 
6708 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
6709 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
6710 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
6711 #define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
6712 
6716 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
6717 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
6718 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
6719 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
6720 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
6721 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
6722 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
6723 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
6724 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
6725 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6726 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
6727 
6733 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
6734 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
6735 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
6736 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
6737 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U)
6738 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U)
6739 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK)
6740 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
6741 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
6742 
6748 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
6749 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
6750 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
6751 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
6752 
6756 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
6757 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
6758 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
6759 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
6760 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
6761 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
6762 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
6763 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
6764 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
6765 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6766 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6767 
6773 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
6774 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
6775 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
6776 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
6777 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
6778 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)
6779 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)
6780 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
6781 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
6782 
6788 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
6789 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
6790 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
6791 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
6792 
6796 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
6797 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
6798 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
6799 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
6800 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
6801 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
6802 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
6803 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
6804 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
6805 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6806 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6807 
6813 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
6814 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
6815 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
6816 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
6817 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
6818 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)
6819 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)
6820 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
6821 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
6822 
6828 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
6829 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
6830 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
6831 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
6832 
6836 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
6837 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
6838 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
6839 
6843 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
6844 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
6845 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
6846 
6850 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
6851 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
6852 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
6853 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
6854 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
6855 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
6856 #define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
6857 #define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
6858 #define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
6859 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
6860 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
6861 
6867 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
6868 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
6869 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
6870 #define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
6871 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U)
6872 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U)
6873 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK)
6874 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
6875 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
6876 
6882 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
6883 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
6884 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
6885 #define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
6886 
6890 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
6891 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
6892 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
6893 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
6894 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
6895 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
6896 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
6897 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
6898 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
6899 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6900 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
6901 
6907 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
6908 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
6909 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
6910 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
6911 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U)
6912 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U)
6913 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK)
6914 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
6915 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
6916 
6922 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
6923 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
6924 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
6925 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
6926 
6930 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
6931 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
6932 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
6933 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
6934 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
6935 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
6936 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
6937 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
6938 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
6939 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6940 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6941 
6947 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
6948 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
6949 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
6950 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
6951 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
6952 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U)
6953 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK)
6954 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
6955 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
6956 
6962 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
6963 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
6964 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
6965 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
6966 
6970 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
6971 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
6972 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
6973 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
6974 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
6975 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
6976 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
6977 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
6978 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
6979 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6980 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6981 
6987 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
6988 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
6989 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
6990 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
6991 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
6992 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U)
6993 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK)
6994 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
6995 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
6996 
7002 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
7003 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
7004 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
7005 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
7006 
7010 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
7011 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
7012 #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
7013 
7017 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
7018 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
7019 #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
7020 
7024 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
7025 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
7026 #define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
7027 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
7028 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
7029 #define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
7030 #define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
7031 #define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
7032 #define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
7033 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
7034 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
7035 
7041 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
7042 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
7043 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
7044 #define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
7045 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)
7046 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)
7047 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)
7048 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
7049 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
7050 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
7051 #define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
7052 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
7053 #define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
7054 
7058 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
7059 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
7060 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
7061 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
7062 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
7063 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
7064 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
7065 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
7066 #define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
7067 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7068 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
7069 
7075 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
7076 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
7077 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
7078 #define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
7079 #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)
7080 #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)
7081 #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)
7082 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
7083 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
7084 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
7085 #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
7086 #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
7087 #define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
7088 
7092 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
7093 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
7094 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
7095 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
7096 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
7097 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
7098 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
7099 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
7100 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
7101 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7102 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7103 
7109 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
7110 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
7111 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
7112 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
7113 #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)
7114 #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)
7115 #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)
7116 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
7117 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
7118 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
7119 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
7120 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
7121 #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
7122 
7126 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
7127 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
7128 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
7129 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
7130 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
7131 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
7132 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
7133 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
7134 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
7135 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7136 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7137 
7143 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
7144 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
7145 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
7146 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
7147 #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)
7148 #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)
7149 #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)
7150 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
7151 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
7152 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
7153 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
7154 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
7155 #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
7156 
7160 #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
7161 #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
7162 #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
7163 #define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
7164 #define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
7165 #define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
7166 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
7167 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
7168 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
7169 #define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
7170 #define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
7171 #define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
7172 #define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
7173 #define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
7174 #define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
7175 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
7176 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
7177 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
7178 #define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
7179 #define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
7180 #define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
7181 #define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
7182 #define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
7183 #define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
7184 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
7185 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
7186 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
7187 #define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
7188 #define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
7189 #define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
7190 #define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
7191 #define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
7192 #define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
7193 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
7194 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
7195 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
7196 
7200 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
7201 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
7202 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
7203 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
7204 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
7205 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
7206 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
7207 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
7208 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
7209 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
7210 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
7211 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
7212 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
7213 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
7214 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
7215 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
7216 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
7217 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
7218 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
7219 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
7220 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
7221 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
7222 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
7223 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
7224 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
7225 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
7226 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
7227 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
7228 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
7229 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
7230 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
7231 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
7232 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
7233 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
7234 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
7235 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
7236 
7240 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
7241 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
7242 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
7243 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
7244 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
7245 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
7246 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
7247 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
7248 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
7249 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
7250 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
7251 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
7252 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
7253 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
7254 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
7255 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
7256 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
7257 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
7258 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
7259 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
7260 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
7261 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
7262 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
7263 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
7264 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
7265 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
7266 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
7267 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
7268 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
7269 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
7270 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
7271 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
7272 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
7273 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
7274 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
7275 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
7276 
7280 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
7281 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
7282 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
7283 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
7284 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
7285 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
7286 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
7287 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
7288 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
7289 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
7290 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
7291 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
7292 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
7293 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
7294 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
7295 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
7296 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
7297 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
7298 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
7299 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
7300 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
7301 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
7302 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
7303 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
7304 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
7305 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
7306 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
7307 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
7308 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
7309 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
7310 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
7311 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
7312 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
7313 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
7314 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
7315 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
7316 
7320 #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
7321 #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
7322 #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
7323 #define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
7324 #define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
7325 #define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
7326 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
7327 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
7328 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
7329 #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
7330 #define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
7331 #define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
7332 #define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
7333 #define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
7334 #define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
7335 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
7336 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
7337 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
7338 #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
7339 #define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
7340 #define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
7341 #define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
7342 #define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
7343 #define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
7344 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
7345 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
7346 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
7347 #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
7348 #define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
7349 #define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
7350 #define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
7351 #define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
7352 #define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
7353 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
7354 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
7355 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
7356 
7360 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
7361 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
7362 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
7363 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
7364 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
7365 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
7366 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
7367 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
7368 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
7369 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
7370 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
7371 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
7372 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
7373 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
7374 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
7375 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
7376 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
7377 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
7378 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
7379 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
7380 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
7381 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
7382 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
7383 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
7384 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
7385 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
7386 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
7387 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
7388 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
7389 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
7390 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
7391 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
7392 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
7393 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
7394 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
7395 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
7396 
7400 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
7401 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
7402 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
7403 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
7404 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
7405 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
7406 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
7407 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
7408 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
7409 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
7410 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
7411 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
7412 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
7413 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
7414 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
7415 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
7416 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
7417 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
7418 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
7419 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
7420 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
7421 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
7422 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
7423 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
7424 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
7425 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
7426 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
7427 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
7428 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
7429 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
7430 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
7431 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
7432 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
7433 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
7434 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
7435 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
7436 
7440 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
7441 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
7442 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
7443 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
7444 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
7445 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
7446 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
7447 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
7448 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
7449 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
7450 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
7451 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
7452 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
7453 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
7454 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
7455 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
7456 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
7457 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
7458 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
7459 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
7460 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
7461 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
7462 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
7463 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
7464 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
7465 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
7466 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
7467 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
7468 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
7469 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
7470 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
7471 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
7472 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
7473 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
7474 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
7475 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
7476 
7480 #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
7481 #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
7482 #define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
7483 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
7484 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
7485 
7489 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
7490 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
7491 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
7492 
7502 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
7503 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
7504 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
7505 #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
7506 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
7507 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
7508 
7514 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
7515 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
7516 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
7517 
7521 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
7522 #define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
7523 #define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
7524 
7530 #define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
7531 #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
7532 #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
7533 #define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
7534 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
7535 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
7536 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
7537 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
7538 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
7539 
7543 #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
7544 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
7545 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
7546 
7556 #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
7557 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
7558 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
7559 
7563 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
7564 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
7565 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
7566 #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
7567 
7571 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
7572 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
7573 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
7574 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
7575 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
7576 
7580 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
7581 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
7582 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
7583 
7593 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
7594 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
7595 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
7596 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
7597 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
7598 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
7599 
7605 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
7606 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
7607 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
7608 
7612 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
7613 #define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
7614 #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
7615 
7621 #define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
7622 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
7623 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
7624 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
7625 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
7626 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
7627 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
7628 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
7629 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
7630 
7634 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
7635 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
7636 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
7637 
7647 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
7648 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
7649 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
7650 
7654 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
7655 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
7656 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
7657 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
7658 
7662 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
7663 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
7664 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
7665 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
7666 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
7667 
7671 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
7672 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
7673 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
7674 
7684 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
7685 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
7686 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
7687 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
7688 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
7689 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
7690 
7696 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
7697 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
7698 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
7699 
7703 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
7704 #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
7705 #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
7706 
7712 #define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
7713 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
7714 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
7715 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
7716 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
7717 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
7718 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
7719 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
7720 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
7721 
7725 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
7726 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
7727 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
7728 
7738 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
7739 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
7740 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
7741 
7745 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
7746 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
7747 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
7748 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
7749 
7753 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
7754 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
7755 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
7756 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
7757 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
7758 
7762 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
7763 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
7764 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
7765 
7775 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
7776 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
7777 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
7778 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
7779 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
7780 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
7781 
7787 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
7788 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
7789 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
7790 
7794 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
7795 #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
7796 #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
7797 
7803 #define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
7804 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
7805 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
7806 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
7807 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
7808 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
7809 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
7810 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
7811 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
7812 
7816 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
7817 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
7818 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
7819 
7829 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
7830 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
7831 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
7832 
7836 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
7837 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
7838 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
7839 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
7840 
7844 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
7845 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
7846 
7864 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
7865 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
7866 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
7867 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
7868 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
7869 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
7870 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
7871 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7872 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
7873 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
7874 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7875 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
7876 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
7877 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
7878 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
7879 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
7880 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
7881 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
7882 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
7883 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
7884 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
7885 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
7886 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
7887 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
7888 #define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
7889 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
7890 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
7891 #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
7892 
7896 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
7897 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
7898 
7916 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
7917 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
7918 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
7919 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
7920 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
7921 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
7922 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
7923 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7924 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
7925 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
7926 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7927 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
7928 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
7929 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
7930 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
7931 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
7932 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
7933 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
7934 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
7935 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
7936 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
7937 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
7938 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
7939 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
7940 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
7941 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
7942 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
7943 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
7944 
7948 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
7949 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
7950 
7968 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
7969 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
7970 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
7971 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
7972 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
7973 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
7974 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
7975 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7976 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
7977 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
7978 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7979 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
7980 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
7981 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
7982 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
7983 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
7984 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
7985 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
7986 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
7987 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
7988 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
7989 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
7990 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
7991 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
7992 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
7993 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
7994 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
7995 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
7996 
8000 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
8001 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
8002 
8020 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
8021 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
8022 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
8023 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
8024 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
8025 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
8026 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
8027 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
8028 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
8029 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
8030 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
8031 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
8032 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
8033 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
8034 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
8035 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
8036 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
8037 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
8038 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
8039 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
8040 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
8041 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
8042 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
8043 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
8044 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
8045 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
8046 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
8047 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
8048 
8052 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
8053 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
8054 
8058 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
8059 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
8060 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
8061 
8064 #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
8065 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
8066 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
8067 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
8068 #define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
8069 #define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
8070 #define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
8071 #define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)
8072 #define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)
8073 
8077 #define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)
8078 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
8079 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
8080 
8084 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
8085 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
8086 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
8087 
8090 #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
8091 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
8092 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
8093 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
8094 #define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
8095 #define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
8096 #define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
8097 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
8098 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
8099 
8103 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
8104 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
8105 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
8106 
8110 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
8111 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
8112 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
8113 #define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
8114 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
8115 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
8116 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
8117 #define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
8118 #define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
8119 #define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
8120 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
8121 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
8122 
8126 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
8127 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
8128 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
8129 
8135 #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
8136 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
8137 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
8138 
8144 #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
8145 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
8146 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
8147 
8153 #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
8154 #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
8155 #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
8156 
8162 #define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
8163 
8167 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
8168 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
8169 
8173 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
8174 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
8175 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
8176 
8179 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
8180 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
8181 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
8182 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
8183 #define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
8184 #define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
8185 #define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
8186 #define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)
8187 #define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)
8188 
8192 #define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)
8193 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
8194 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
8195 
8199 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
8200 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
8201 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
8202 
8205 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
8206 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
8207 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
8208 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
8209 #define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
8210 #define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
8211 #define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
8212 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
8213 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
8214 
8218 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
8219 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
8220 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
8221 
8225 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
8226 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
8227 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
8228 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
8229 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
8230 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
8231 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
8232 #define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
8233 #define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
8234 #define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
8235 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
8236 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
8237 
8241 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
8242 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
8243 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
8244 
8250 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
8251 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
8252 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
8253 
8259 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
8260 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
8261 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
8262 
8268 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
8269 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
8270 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
8271 
8277 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
8278 
8282 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
8283 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
8284 
8288 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
8289 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
8290 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
8291 
8294 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
8295 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
8296 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
8297 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
8298 #define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
8299 #define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
8300 #define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
8301 #define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U)
8302 #define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U)
8303 
8307 #define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK)
8308 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
8309 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
8310 
8314 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
8315 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
8316 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
8317 
8320 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
8321 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
8322 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
8323 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
8324 #define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
8325 #define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
8326 #define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
8327 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
8328 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
8329 
8333 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
8334 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
8335 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
8336 
8340 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
8341 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
8342 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
8343 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
8344 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
8345 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
8346 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
8347 #define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
8348 #define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
8349 #define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
8350 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
8351 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
8352 
8356 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
8357 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
8358 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
8359 
8365 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
8366 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
8367 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
8368 
8374 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
8375 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
8376 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
8377 
8383 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
8384 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
8385 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
8386 
8392 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
8393 
8397 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
8398 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
8399 
8403 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
8404 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
8405 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
8406 
8409 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
8410 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
8411 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
8412 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
8413 #define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
8414 #define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
8415 #define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
8416 #define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U)
8417 #define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U)
8418 
8422 #define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK)
8423 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
8424 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
8425 
8429 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
8430 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
8431 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
8432 
8435 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
8436 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
8437 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
8438 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
8439 #define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
8440 #define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
8441 #define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
8442 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
8443 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
8444 
8448 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
8449 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
8450 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
8451 
8455 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
8456 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
8457 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
8458 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
8459 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
8460 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
8461 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
8462 #define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
8463 #define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
8464 #define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
8465 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
8466 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
8467 
8471 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
8472 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
8473 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
8474 
8480 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
8481 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
8482 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
8483 
8489 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
8490 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
8491 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
8492 
8498 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
8499 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
8500 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
8501 
8507 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
8508  /* end of group CCM_ANALOG_Register_Masks */
8514 
8515 
8516 /* CCM_ANALOG - Peripheral instance base addresses */
8518 #define CCM_ANALOG_BASE (0x400D8000u)
8519 
8520 #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
8521 
8522 #define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
8523 
8524 #define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
8525  /* end of group CCM_ANALOG_Peripheral_Access_Layer */
8529 
8530 
8531 /* ----------------------------------------------------------------------------
8532  -- CMP Peripheral Access Layer
8533  ---------------------------------------------------------------------------- */
8534 
8541 typedef struct {
8542  __IO uint8_t CR0;
8543  __IO uint8_t CR1;
8544  __IO uint8_t FPR;
8545  __IO uint8_t SCR;
8546  __IO uint8_t DACCR;
8547  __IO uint8_t MUXCR;
8548 } CMP_Type;
8549 
8550 /* ----------------------------------------------------------------------------
8551  -- CMP Register Masks
8552  ---------------------------------------------------------------------------- */
8553 
8561 #define CMP_CR0_HYSTCTR_MASK (0x3U)
8562 #define CMP_CR0_HYSTCTR_SHIFT (0U)
8563 
8569 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
8570 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
8571 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
8572 
8582 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
8583 
8587 #define CMP_CR1_EN_MASK (0x1U)
8588 #define CMP_CR1_EN_SHIFT (0U)
8589 
8593 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
8594 #define CMP_CR1_OPE_MASK (0x2U)
8595 #define CMP_CR1_OPE_SHIFT (1U)
8596 
8602 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
8603 #define CMP_CR1_COS_MASK (0x4U)
8604 #define CMP_CR1_COS_SHIFT (2U)
8605 
8609 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
8610 #define CMP_CR1_INV_MASK (0x8U)
8611 #define CMP_CR1_INV_SHIFT (3U)
8612 
8616 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
8617 #define CMP_CR1_PMODE_MASK (0x10U)
8618 #define CMP_CR1_PMODE_SHIFT (4U)
8619 
8623 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
8624 #define CMP_CR1_WE_MASK (0x40U)
8625 #define CMP_CR1_WE_SHIFT (6U)
8626 
8630 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
8631 #define CMP_CR1_SE_MASK (0x80U)
8632 #define CMP_CR1_SE_SHIFT (7U)
8633 
8637 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
8638 
8642 #define CMP_FPR_FILT_PER_MASK (0xFFU)
8643 #define CMP_FPR_FILT_PER_SHIFT (0U)
8644 
8646 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
8647 
8651 #define CMP_SCR_COUT_MASK (0x1U)
8652 #define CMP_SCR_COUT_SHIFT (0U)
8653 
8655 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
8656 #define CMP_SCR_CFF_MASK (0x2U)
8657 #define CMP_SCR_CFF_SHIFT (1U)
8658 
8662 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
8663 #define CMP_SCR_CFR_MASK (0x4U)
8664 #define CMP_SCR_CFR_SHIFT (2U)
8665 
8669 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
8670 #define CMP_SCR_IEF_MASK (0x8U)
8671 #define CMP_SCR_IEF_SHIFT (3U)
8672 
8676 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
8677 #define CMP_SCR_IER_MASK (0x10U)
8678 #define CMP_SCR_IER_SHIFT (4U)
8679 
8683 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
8684 #define CMP_SCR_DMAEN_MASK (0x40U)
8685 #define CMP_SCR_DMAEN_SHIFT (6U)
8686 
8690 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
8691 
8695 #define CMP_DACCR_VOSEL_MASK (0x3FU)
8696 #define CMP_DACCR_VOSEL_SHIFT (0U)
8697 
8699 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
8700 #define CMP_DACCR_VRSEL_MASK (0x40U)
8701 #define CMP_DACCR_VRSEL_SHIFT (6U)
8702 
8706 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
8707 #define CMP_DACCR_DACEN_MASK (0x80U)
8708 #define CMP_DACCR_DACEN_SHIFT (7U)
8709 
8713 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
8714 
8718 #define CMP_MUXCR_MSEL_MASK (0x7U)
8719 #define CMP_MUXCR_MSEL_SHIFT (0U)
8720 
8730 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
8731 #define CMP_MUXCR_PSEL_MASK (0x38U)
8732 #define CMP_MUXCR_PSEL_SHIFT (3U)
8733 
8743 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
8744  /* end of group CMP_Register_Masks */
8750 
8751 
8752 /* CMP - Peripheral instance base addresses */
8754 #define CMP1_BASE (0x40094000u)
8755 
8756 #define CMP1 ((CMP_Type *)CMP1_BASE)
8757 
8758 #define CMP2_BASE (0x40094008u)
8759 
8760 #define CMP2 ((CMP_Type *)CMP2_BASE)
8761 
8762 #define CMP3_BASE (0x40094010u)
8763 
8764 #define CMP3 ((CMP_Type *)CMP3_BASE)
8765 
8766 #define CMP4_BASE (0x40094018u)
8767 
8768 #define CMP4 ((CMP_Type *)CMP4_BASE)
8769 
8770 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
8771 
8772 #define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
8773 
8774 #define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
8775  /* end of group CMP_Peripheral_Access_Layer */
8779 
8780 
8781 /* ----------------------------------------------------------------------------
8782  -- CSI Peripheral Access Layer
8783  ---------------------------------------------------------------------------- */
8784 
8791 typedef struct {
8792  __IO uint32_t CSICR1;
8793  __IO uint32_t CSICR2;
8794  __IO uint32_t CSICR3;
8795  __I uint32_t CSISTATFIFO;
8796  __I uint32_t CSIRFIFO;
8797  __IO uint32_t CSIRXCNT;
8798  __IO uint32_t CSISR;
8799  uint8_t RESERVED_0[4];
8800  __IO uint32_t CSIDMASA_STATFIFO;
8801  __IO uint32_t CSIDMATS_STATFIFO;
8802  __IO uint32_t CSIDMASA_FB1;
8803  __IO uint32_t CSIDMASA_FB2;
8804  __IO uint32_t CSIFBUF_PARA;
8805  __IO uint32_t CSIIMAG_PARA;
8806  uint8_t RESERVED_1[16];
8807  __IO uint32_t CSICR18;
8808  __IO uint32_t CSICR19;
8809 } CSI_Type;
8810 
8811 /* ----------------------------------------------------------------------------
8812  -- CSI Register Masks
8813  ---------------------------------------------------------------------------- */
8814 
8822 #define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
8823 #define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
8824 
8828 #define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
8829 #define CSI_CSICR1_REDGE_MASK (0x2U)
8830 #define CSI_CSICR1_REDGE_SHIFT (1U)
8831 
8835 #define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
8836 #define CSI_CSICR1_INV_PCLK_MASK (0x4U)
8837 #define CSI_CSICR1_INV_PCLK_SHIFT (2U)
8838 
8842 #define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
8843 #define CSI_CSICR1_INV_DATA_MASK (0x8U)
8844 #define CSI_CSICR1_INV_DATA_SHIFT (3U)
8845 
8849 #define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
8850 #define CSI_CSICR1_GCLK_MODE_MASK (0x10U)
8851 #define CSI_CSICR1_GCLK_MODE_SHIFT (4U)
8852 
8856 #define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
8857 #define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
8858 #define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
8859 #define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
8860 #define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
8861 #define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
8862 #define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
8863 #define CSI_CSICR1_PACK_DIR_MASK (0x80U)
8864 #define CSI_CSICR1_PACK_DIR_SHIFT (7U)
8865 
8871 #define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
8872 #define CSI_CSICR1_FCC_MASK (0x100U)
8873 #define CSI_CSICR1_FCC_SHIFT (8U)
8874 
8878 #define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
8879 #define CSI_CSICR1_CCIR_EN_MASK (0x400U)
8880 #define CSI_CSICR1_CCIR_EN_SHIFT (10U)
8881 
8885 #define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
8886 #define CSI_CSICR1_HSYNC_POL_MASK (0x800U)
8887 #define CSI_CSICR1_HSYNC_POL_SHIFT (11U)
8888 
8892 #define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
8893 #define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
8894 #define CSI_CSICR1_SOF_INTEN_SHIFT (16U)
8895 
8899 #define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
8900 #define CSI_CSICR1_SOF_POL_MASK (0x20000U)
8901 #define CSI_CSICR1_SOF_POL_SHIFT (17U)
8902 
8906 #define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
8907 #define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
8908 #define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
8909 
8913 #define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
8914 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
8915 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
8916 
8920 #define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
8921 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
8922 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
8923 
8927 #define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
8928 #define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
8929 #define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
8930 
8934 #define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
8935 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
8936 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
8937 
8941 #define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
8942 #define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
8943 #define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
8944 
8948 #define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
8949 #define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
8950 #define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
8951 
8955 #define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
8956 #define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
8957 #define CSI_CSICR1_COF_INT_EN_SHIFT (26U)
8958 
8962 #define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
8963 #define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
8964 #define CSI_CSICR1_CCIR_MODE_SHIFT (27U)
8965 
8969 #define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
8970 #define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
8971 #define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
8972 
8976 #define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
8977 #define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
8978 #define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
8979 
8983 #define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
8984 #define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
8985 #define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
8986 
8990 #define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
8991 #define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
8992 #define CSI_CSICR1_SWAP16_EN_SHIFT (31U)
8993 
8997 #define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
8998 
9002 #define CSI_CSICR2_HSC_MASK (0xFFU)
9003 #define CSI_CSICR2_HSC_SHIFT (0U)
9004 #define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
9005 #define CSI_CSICR2_VSC_MASK (0xFF00U)
9006 #define CSI_CSICR2_VSC_SHIFT (8U)
9007 #define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
9008 #define CSI_CSICR2_LVRM_MASK (0x70000U)
9009 #define CSI_CSICR2_LVRM_SHIFT (16U)
9010 
9019 #define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
9020 #define CSI_CSICR2_BTS_MASK (0x180000U)
9021 #define CSI_CSICR2_BTS_SHIFT (19U)
9022 
9028 #define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
9029 #define CSI_CSICR2_SCE_MASK (0x800000U)
9030 #define CSI_CSICR2_SCE_SHIFT (23U)
9031 
9035 #define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
9036 #define CSI_CSICR2_AFS_MASK (0x3000000U)
9037 #define CSI_CSICR2_AFS_SHIFT (24U)
9038 
9043 #define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
9044 #define CSI_CSICR2_DRM_MASK (0x4000000U)
9045 #define CSI_CSICR2_DRM_SHIFT (26U)
9046 
9050 #define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
9051 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
9052 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
9053 
9058 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
9059 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
9060 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
9061 
9066 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
9067 
9071 #define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
9072 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
9073 
9077 #define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
9078 #define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
9079 #define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
9080 
9084 #define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
9085 #define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
9086 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
9087 
9091 #define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
9092 #define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
9093 #define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
9094 
9098 #define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
9099 #define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
9100 #define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
9101 
9111 #define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
9112 #define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
9113 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
9114 
9118 #define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
9119 #define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
9120 #define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
9121 
9131 #define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
9132 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
9133 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
9134 
9138 #define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
9139 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
9140 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
9141 
9145 #define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
9146 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
9147 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
9148 
9152 #define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
9153 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
9154 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
9155 
9159 #define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
9160 #define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
9161 #define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
9162 
9166 #define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
9167 #define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
9168 #define CSI_CSICR3_FRMCNT_SHIFT (16U)
9169 #define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
9170 
9174 #define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
9175 #define CSI_CSISTATFIFO_STAT_SHIFT (0U)
9176 #define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
9177 
9181 #define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
9182 #define CSI_CSIRFIFO_IMAGE_SHIFT (0U)
9183 #define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
9184 
9188 #define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
9189 #define CSI_CSIRXCNT_RXCNT_SHIFT (0U)
9190 #define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
9191 
9195 #define CSI_CSISR_DRDY_MASK (0x1U)
9196 #define CSI_CSISR_DRDY_SHIFT (0U)
9197 
9201 #define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
9202 #define CSI_CSISR_ECC_INT_MASK (0x2U)
9203 #define CSI_CSISR_ECC_INT_SHIFT (1U)
9204 
9208 #define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
9209 #define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
9210 #define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
9211 
9215 #define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
9216 #define CSI_CSISR_COF_INT_MASK (0x2000U)
9217 #define CSI_CSISR_COF_INT_SHIFT (13U)
9218 
9222 #define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
9223 #define CSI_CSISR_F1_INT_MASK (0x4000U)
9224 #define CSI_CSISR_F1_INT_SHIFT (14U)
9225 
9229 #define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
9230 #define CSI_CSISR_F2_INT_MASK (0x8000U)
9231 #define CSI_CSISR_F2_INT_SHIFT (15U)
9232 
9236 #define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
9237 #define CSI_CSISR_SOF_INT_MASK (0x10000U)
9238 #define CSI_CSISR_SOF_INT_SHIFT (16U)
9239 
9243 #define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
9244 #define CSI_CSISR_EOF_INT_MASK (0x20000U)
9245 #define CSI_CSISR_EOF_INT_SHIFT (17U)
9246 
9250 #define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
9251 #define CSI_CSISR_RxFF_INT_MASK (0x40000U)
9252 #define CSI_CSISR_RxFF_INT_SHIFT (18U)
9253 
9257 #define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
9258 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
9259 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
9260 
9264 #define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
9265 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
9266 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
9267 
9271 #define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
9272 #define CSI_CSISR_STATFF_INT_MASK (0x200000U)
9273 #define CSI_CSISR_STATFF_INT_SHIFT (21U)
9274 
9278 #define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
9279 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
9280 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
9281 
9285 #define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
9286 #define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
9287 #define CSI_CSISR_RF_OR_INT_SHIFT (24U)
9288 
9292 #define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
9293 #define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
9294 #define CSI_CSISR_SF_OR_INT_SHIFT (25U)
9295 
9299 #define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
9300 #define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
9301 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
9302 #define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
9303 #define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
9304 #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
9305 #define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
9306 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
9307 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
9308 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
9309 
9313 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
9314 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
9315 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
9316 
9320 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
9321 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
9322 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
9323 
9327 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
9328 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
9329 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
9330 
9334 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
9335 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
9336 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
9337 
9341 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
9342 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
9343 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
9344 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
9345 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
9346 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
9347 
9351 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
9352 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
9353 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
9354 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
9355 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
9356 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
9357 
9361 #define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
9362 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
9363 
9367 #define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
9368 #define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
9369 #define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
9370 #define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
9371 #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
9372 #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
9373 #define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
9374 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
9375 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
9376 
9380 #define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
9381 #define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
9382 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
9383 
9387 #define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
9388 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
9389 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
9390 
9394 #define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
9395 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
9396 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
9397 
9401 #define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
9402 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
9403 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
9404 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
9405 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
9406 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
9407 
9411 #define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
9412 #define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
9413 #define CSI_CSICR18_AHB_HPROT_SHIFT (12U)
9414 #define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
9415 #define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
9416 #define CSI_CSICR18_MASK_OPTION_SHIFT (18U)
9417 
9423 #define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
9424 #define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
9425 #define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
9426 #define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
9427 
9431 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
9432 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
9433 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
9434  /* end of group CSI_Register_Masks */
9440 
9441 
9442 /* CSI - Peripheral instance base addresses */
9444 #define CSI_BASE (0x402BC000u)
9445 
9446 #define CSI ((CSI_Type *)CSI_BASE)
9447 
9448 #define CSI_BASE_ADDRS { CSI_BASE }
9449 
9450 #define CSI_BASE_PTRS { CSI }
9451 
9452 #define CSI_IRQS { CSI_IRQn }
9453  /* end of group CSI_Peripheral_Access_Layer */
9457 
9458 
9459 /* ----------------------------------------------------------------------------
9460  -- CSU Peripheral Access Layer
9461  ---------------------------------------------------------------------------- */
9462 
9469 typedef struct {
9470  __IO uint32_t CSL[32];
9471  uint8_t RESERVED_0[384];
9472  __IO uint32_t HP0;
9473  uint8_t RESERVED_1[20];
9474  __IO uint32_t SA;
9475  uint8_t RESERVED_2[316];
9476  __IO uint32_t HPCONTROL0;
9477 } CSU_Type;
9478 
9479 /* ----------------------------------------------------------------------------
9480  -- CSU Register Masks
9481  ---------------------------------------------------------------------------- */
9482 
9490 #define CSU_CSL_SUR_S2_MASK (0x1U)
9491 #define CSU_CSL_SUR_S2_SHIFT (0U)
9492 
9496 #define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
9497 #define CSU_CSL_SSR_S2_MASK (0x2U)
9498 #define CSU_CSL_SSR_S2_SHIFT (1U)
9499 
9503 #define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
9504 #define CSU_CSL_NUR_S2_MASK (0x4U)
9505 #define CSU_CSL_NUR_S2_SHIFT (2U)
9506 
9510 #define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
9511 #define CSU_CSL_NSR_S2_MASK (0x8U)
9512 #define CSU_CSL_NSR_S2_SHIFT (3U)
9513 
9517 #define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
9518 #define CSU_CSL_SUW_S2_MASK (0x10U)
9519 #define CSU_CSL_SUW_S2_SHIFT (4U)
9520 
9524 #define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
9525 #define CSU_CSL_SSW_S2_MASK (0x20U)
9526 #define CSU_CSL_SSW_S2_SHIFT (5U)
9527 
9531 #define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
9532 #define CSU_CSL_NUW_S2_MASK (0x40U)
9533 #define CSU_CSL_NUW_S2_SHIFT (6U)
9534 
9538 #define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
9539 #define CSU_CSL_NSW_S2_MASK (0x80U)
9540 #define CSU_CSL_NSW_S2_SHIFT (7U)
9541 
9545 #define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
9546 #define CSU_CSL_LOCK_S2_MASK (0x100U)
9547 #define CSU_CSL_LOCK_S2_SHIFT (8U)
9548 
9552 #define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
9553 #define CSU_CSL_SUR_S1_MASK (0x10000U)
9554 #define CSU_CSL_SUR_S1_SHIFT (16U)
9555 
9559 #define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
9560 #define CSU_CSL_SSR_S1_MASK (0x20000U)
9561 #define CSU_CSL_SSR_S1_SHIFT (17U)
9562 
9566 #define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
9567 #define CSU_CSL_NUR_S1_MASK (0x40000U)
9568 #define CSU_CSL_NUR_S1_SHIFT (18U)
9569 
9573 #define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
9574 #define CSU_CSL_NSR_S1_MASK (0x80000U)
9575 #define CSU_CSL_NSR_S1_SHIFT (19U)
9576 
9580 #define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
9581 #define CSU_CSL_SUW_S1_MASK (0x100000U)
9582 #define CSU_CSL_SUW_S1_SHIFT (20U)
9583 
9587 #define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
9588 #define CSU_CSL_SSW_S1_MASK (0x200000U)
9589 #define CSU_CSL_SSW_S1_SHIFT (21U)
9590 
9594 #define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
9595 #define CSU_CSL_NUW_S1_MASK (0x400000U)
9596 #define CSU_CSL_NUW_S1_SHIFT (22U)
9597 
9601 #define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
9602 #define CSU_CSL_NSW_S1_MASK (0x800000U)
9603 #define CSU_CSL_NSW_S1_SHIFT (23U)
9604 
9608 #define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
9609 #define CSU_CSL_LOCK_S1_MASK (0x1000000U)
9610 #define CSU_CSL_LOCK_S1_SHIFT (24U)
9611 
9615 #define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
9616 
9618 /* The count of CSU_CSL */
9619 #define CSU_CSL_COUNT (32U)
9620 
9623 #define CSU_HP0_HP_DMA_MASK (0x4U)
9624 #define CSU_HP0_HP_DMA_SHIFT (2U)
9625 
9629 #define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
9630 #define CSU_HP0_L_DMA_MASK (0x8U)
9631 #define CSU_HP0_L_DMA_SHIFT (3U)
9632 
9636 #define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
9637 #define CSU_HP0_HP_LCDIF_MASK (0x10U)
9638 #define CSU_HP0_HP_LCDIF_SHIFT (4U)
9639 
9643 #define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
9644 #define CSU_HP0_L_LCDIF_MASK (0x20U)
9645 #define CSU_HP0_L_LCDIF_SHIFT (5U)
9646 
9650 #define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
9651 #define CSU_HP0_HP_CSI_MASK (0x40U)
9652 #define CSU_HP0_HP_CSI_SHIFT (6U)
9653 
9657 #define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
9658 #define CSU_HP0_L_CSI_MASK (0x80U)
9659 #define CSU_HP0_L_CSI_SHIFT (7U)
9660 
9664 #define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
9665 #define CSU_HP0_HP_PXP_MASK (0x100U)
9666 #define CSU_HP0_HP_PXP_SHIFT (8U)
9667 
9671 #define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
9672 #define CSU_HP0_L_PXP_MASK (0x200U)
9673 #define CSU_HP0_L_PXP_SHIFT (9U)
9674 
9678 #define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
9679 #define CSU_HP0_HP_DCP_MASK (0x400U)
9680 #define CSU_HP0_HP_DCP_SHIFT (10U)
9681 
9685 #define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
9686 #define CSU_HP0_L_DCP_MASK (0x800U)
9687 #define CSU_HP0_L_DCP_SHIFT (11U)
9688 
9692 #define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
9693 #define CSU_HP0_HP_ENET_MASK (0x4000U)
9694 #define CSU_HP0_HP_ENET_SHIFT (14U)
9695 
9699 #define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
9700 #define CSU_HP0_L_ENET_MASK (0x8000U)
9701 #define CSU_HP0_L_ENET_SHIFT (15U)
9702 
9706 #define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
9707 #define CSU_HP0_HP_USDHC1_MASK (0x10000U)
9708 #define CSU_HP0_HP_USDHC1_SHIFT (16U)
9709 
9713 #define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
9714 #define CSU_HP0_L_USDHC1_MASK (0x20000U)
9715 #define CSU_HP0_L_USDHC1_SHIFT (17U)
9716 
9720 #define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
9721 #define CSU_HP0_HP_USDHC2_MASK (0x40000U)
9722 #define CSU_HP0_HP_USDHC2_SHIFT (18U)
9723 
9727 #define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
9728 #define CSU_HP0_L_USDHC2_MASK (0x80000U)
9729 #define CSU_HP0_L_USDHC2_SHIFT (19U)
9730 
9734 #define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
9735 #define CSU_HP0_HP_TPSMP_MASK (0x100000U)
9736 #define CSU_HP0_HP_TPSMP_SHIFT (20U)
9737 
9741 #define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
9742 #define CSU_HP0_L_TPSMP_MASK (0x200000U)
9743 #define CSU_HP0_L_TPSMP_SHIFT (21U)
9744 
9748 #define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
9749 #define CSU_HP0_HP_USB_MASK (0x400000U)
9750 #define CSU_HP0_HP_USB_SHIFT (22U)
9751 
9755 #define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
9756 #define CSU_HP0_L_USB_MASK (0x800000U)
9757 #define CSU_HP0_L_USB_SHIFT (23U)
9758 
9762 #define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
9763 
9767 #define CSU_SA_NSA_DMA_MASK (0x4U)
9768 #define CSU_SA_NSA_DMA_SHIFT (2U)
9769 
9773 #define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
9774 #define CSU_SA_L_DMA_MASK (0x8U)
9775 #define CSU_SA_L_DMA_SHIFT (3U)
9776 
9780 #define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
9781 #define CSU_SA_NSA_LCDIF_MASK (0x10U)
9782 #define CSU_SA_NSA_LCDIF_SHIFT (4U)
9783 
9787 #define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
9788 #define CSU_SA_L_LCDIF_MASK (0x20U)
9789 #define CSU_SA_L_LCDIF_SHIFT (5U)
9790 
9794 #define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
9795 #define CSU_SA_NSA_CSI_MASK (0x40U)
9796 #define CSU_SA_NSA_CSI_SHIFT (6U)
9797 
9801 #define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
9802 #define CSU_SA_L_CSI_MASK (0x80U)
9803 #define CSU_SA_L_CSI_SHIFT (7U)
9804 
9808 #define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
9809 #define CSU_SA_NSA_PXP_MASK (0x100U)
9810 #define CSU_SA_NSA_PXP_SHIFT (8U)
9811 
9815 #define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
9816 #define CSU_SA_L_PXP_MASK (0x200U)
9817 #define CSU_SA_L_PXP_SHIFT (9U)
9818 
9822 #define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
9823 #define CSU_SA_NSA_DCP_MASK (0x400U)
9824 #define CSU_SA_NSA_DCP_SHIFT (10U)
9825 
9829 #define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
9830 #define CSU_SA_L_DCP_MASK (0x800U)
9831 #define CSU_SA_L_DCP_SHIFT (11U)
9832 
9836 #define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
9837 #define CSU_SA_NSA_ENET_MASK (0x4000U)
9838 #define CSU_SA_NSA_ENET_SHIFT (14U)
9839 
9843 #define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
9844 #define CSU_SA_L_ENET_MASK (0x8000U)
9845 #define CSU_SA_L_ENET_SHIFT (15U)
9846 
9850 #define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
9851 #define CSU_SA_NSA_USDHC1_MASK (0x10000U)
9852 #define CSU_SA_NSA_USDHC1_SHIFT (16U)
9853 
9857 #define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
9858 #define CSU_SA_L_USDHC1_MASK (0x20000U)
9859 #define CSU_SA_L_USDHC1_SHIFT (17U)
9860 
9864 #define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
9865 #define CSU_SA_NSA_USDHC2_MASK (0x40000U)
9866 #define CSU_SA_NSA_USDHC2_SHIFT (18U)
9867 
9871 #define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
9872 #define CSU_SA_L_USDHC2_MASK (0x80000U)
9873 #define CSU_SA_L_USDHC2_SHIFT (19U)
9874 
9878 #define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
9879 #define CSU_SA_NSA_TPSMP_MASK (0x100000U)
9880 #define CSU_SA_NSA_TPSMP_SHIFT (20U)
9881 
9885 #define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
9886 #define CSU_SA_L_TPSMP_MASK (0x200000U)
9887 #define CSU_SA_L_TPSMP_SHIFT (21U)
9888 
9892 #define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
9893 #define CSU_SA_NSA_USB_MASK (0x400000U)
9894 #define CSU_SA_NSA_USB_SHIFT (22U)
9895 
9899 #define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
9900 #define CSU_SA_L_USB_MASK (0x800000U)
9901 #define CSU_SA_L_USB_SHIFT (23U)
9902 
9906 #define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
9907 
9911 #define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
9912 #define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
9913 
9917 #define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
9918 #define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
9919 #define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
9920 
9924 #define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
9925 #define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
9926 #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
9927 
9931 #define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
9932 #define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
9933 #define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
9934 
9938 #define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
9939 #define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
9940 #define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
9941 
9945 #define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
9946 #define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
9947 #define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
9948 
9952 #define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
9953 #define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
9954 #define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
9955 
9959 #define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
9960 #define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
9961 #define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
9962 
9966 #define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
9967 #define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
9968 #define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
9969 
9973 #define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
9974 #define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
9975 #define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
9976 
9980 #define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
9981 #define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
9982 #define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
9983 
9987 #define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
9988 #define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
9989 #define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
9990 
9994 #define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
9995 #define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
9996 #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
9997 
10001 #define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
10002 #define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
10003 #define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
10004 
10008 #define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
10009 #define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
10010 #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
10011 
10015 #define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
10016 #define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
10017 #define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
10018 
10022 #define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
10023 #define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
10024 #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
10025 
10029 #define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
10030 #define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
10031 #define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
10032 
10036 #define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
10037 #define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
10038 #define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
10039 
10043 #define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
10044 #define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
10045 #define CSU_HPCONTROL0_L_USB_SHIFT (23U)
10046 
10050 #define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
10051  /* end of group CSU_Register_Masks */
10057 
10058 
10059 /* CSU - Peripheral instance base addresses */
10061 #define CSU_BASE (0x400DC000u)
10062 
10063 #define CSU ((CSU_Type *)CSU_BASE)
10064 
10065 #define CSU_BASE_ADDRS { CSU_BASE }
10066 
10067 #define CSU_BASE_PTRS { CSU }
10068  /* end of group CSU_Peripheral_Access_Layer */
10072 
10073 
10074 /* ----------------------------------------------------------------------------
10075  -- DCDC Peripheral Access Layer
10076  ---------------------------------------------------------------------------- */
10077 
10084 typedef struct {
10085  __IO uint32_t REG0;
10086  __IO uint32_t REG1;
10087  __IO uint32_t REG2;
10088  __IO uint32_t REG3;
10089 } DCDC_Type;
10090 
10091 /* ----------------------------------------------------------------------------
10092  -- DCDC Register Masks
10093  ---------------------------------------------------------------------------- */
10094 
10102 #define DCDC_REG0_PWD_ZCD_MASK (0x1U)
10103 #define DCDC_REG0_PWD_ZCD_SHIFT (0U)
10104 #define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
10105 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
10106 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
10107 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
10108 #define DCDC_REG0_SEL_CLK_MASK (0x4U)
10109 #define DCDC_REG0_SEL_CLK_SHIFT (2U)
10110 #define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
10111 #define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
10112 #define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
10113 #define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
10114 #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
10115 #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
10116 #define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
10117 #define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
10118 #define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
10119 #define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
10120 #define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
10121 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
10122 #define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
10123 #define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
10124 #define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
10125 #define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
10126 #define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
10127 #define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
10128 #define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
10129 #define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
10130 #define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
10131 #define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
10132 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
10133 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
10134 #define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
10135 #define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
10136 #define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
10137 #define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
10138 #define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
10139 #define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
10140 #define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
10141 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
10142 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
10143 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
10144 #define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
10145 #define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
10146 #define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
10147 #define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
10148 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
10149 #define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
10150 #define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
10151 #define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
10152 #define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
10153 #define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
10154 #define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
10155 #define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
10156 #define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
10157 #define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
10158 #define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
10159 #define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
10160 #define DCDC_REG0_STS_DC_OK_SHIFT (31U)
10161 #define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
10162 
10166 #define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
10167 #define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
10168 #define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
10169 #define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
10170 #define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
10171 #define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
10172 #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
10173 #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
10174 #define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
10175 #define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
10176 #define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
10177 #define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
10178 #define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
10179 #define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
10180 #define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
10181 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
10182 #define DCDC_REG1_VBG_TRIM_SHIFT (24U)
10183 #define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
10184 
10188 #define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
10189 #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
10190 #define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
10191 #define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
10192 #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
10193 #define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
10194 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
10195 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
10196 #define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
10197 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
10198 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
10199 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
10200 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
10201 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
10202 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
10203 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
10204 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
10205 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
10206 #define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
10207 #define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
10208 #define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
10209 #define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
10210 #define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
10211 #define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
10212 
10216 #define DCDC_REG3_TRG_MASK (0x1FU)
10217 #define DCDC_REG3_TRG_SHIFT (0U)
10218 #define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
10219 #define DCDC_REG3_TARGET_LP_MASK (0x700U)
10220 #define DCDC_REG3_TARGET_LP_SHIFT (8U)
10221 #define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
10222 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
10223 #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
10224 #define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
10225 #define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
10226 #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
10227 #define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
10228 #define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
10229 #define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
10230 #define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
10231 #define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
10232 #define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
10233 #define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
10234  /* end of group DCDC_Register_Masks */
10240 
10241 
10242 /* DCDC - Peripheral instance base addresses */
10244 #define DCDC_BASE (0x40080000u)
10245 
10246 #define DCDC ((DCDC_Type *)DCDC_BASE)
10247 
10248 #define DCDC_BASE_ADDRS { DCDC_BASE }
10249 
10250 #define DCDC_BASE_PTRS { DCDC }
10251 
10252 #define DCDC_IRQS { DCDC_IRQn }
10253  /* end of group DCDC_Peripheral_Access_Layer */
10257 
10258 
10259 /* ----------------------------------------------------------------------------
10260  -- DCP Peripheral Access Layer
10261  ---------------------------------------------------------------------------- */
10262 
10269 typedef struct {
10270  __IO uint32_t CTRL;
10271  __IO uint32_t CTRL_SET;
10272  __IO uint32_t CTRL_CLR;
10273  __IO uint32_t CTRL_TOG;
10274  __IO uint32_t STAT;
10275  __IO uint32_t STAT_SET;
10276  __IO uint32_t STAT_CLR;
10277  __IO uint32_t STAT_TOG;
10278  __IO uint32_t CHANNELCTRL;
10279  __IO uint32_t CHANNELCTRL_SET;
10280  __IO uint32_t CHANNELCTRL_CLR;
10281  __IO uint32_t CHANNELCTRL_TOG;
10282  __IO uint32_t CAPABILITY0;
10283  uint8_t RESERVED_0[12];
10284  __I uint32_t CAPABILITY1;
10285  uint8_t RESERVED_1[12];
10286  __IO uint32_t CONTEXT;
10287  uint8_t RESERVED_2[12];
10288  __IO uint32_t KEY;
10289  uint8_t RESERVED_3[12];
10290  __IO uint32_t KEYDATA;
10291  uint8_t RESERVED_4[12];
10292  __I uint32_t PACKET0;
10293  uint8_t RESERVED_5[12];
10294  __I uint32_t PACKET1;
10295  uint8_t RESERVED_6[12];
10296  __I uint32_t PACKET2;
10297  uint8_t RESERVED_7[12];
10298  __I uint32_t PACKET3;
10299  uint8_t RESERVED_8[12];
10300  __I uint32_t PACKET4;
10301  uint8_t RESERVED_9[12];
10302  __I uint32_t PACKET5;
10303  uint8_t RESERVED_10[12];
10304  __I uint32_t PACKET6;
10305  uint8_t RESERVED_11[28];
10306  __IO uint32_t CH0CMDPTR;
10307  uint8_t RESERVED_12[12];
10308  __IO uint32_t CH0SEMA;
10309  uint8_t RESERVED_13[12];
10310  __IO uint32_t CH0STAT;
10311  __IO uint32_t CH0STAT_SET;
10312  __IO uint32_t CH0STAT_CLR;
10313  __IO uint32_t CH0STAT_TOG;
10314  __IO uint32_t CH0OPTS;
10315  __IO uint32_t CH0OPTS_SET;
10316  __IO uint32_t CH0OPTS_CLR;
10317  __IO uint32_t CH0OPTS_TOG;
10318  __IO uint32_t CH1CMDPTR;
10319  uint8_t RESERVED_14[12];
10320  __IO uint32_t CH1SEMA;
10321  uint8_t RESERVED_15[12];
10322  __IO uint32_t CH1STAT;
10323  __IO uint32_t CH1STAT_SET;
10324  __IO uint32_t CH1STAT_CLR;
10325  __IO uint32_t CH1STAT_TOG;
10326  __IO uint32_t CH1OPTS;
10327  __IO uint32_t CH1OPTS_SET;
10328  __IO uint32_t CH1OPTS_CLR;
10329  __IO uint32_t CH1OPTS_TOG;
10330  __IO uint32_t CH2CMDPTR;
10331  uint8_t RESERVED_16[12];
10332  __IO uint32_t CH2SEMA;
10333  uint8_t RESERVED_17[12];
10334  __IO uint32_t CH2STAT;
10335  __IO uint32_t CH2STAT_SET;
10336  __IO uint32_t CH2STAT_CLR;
10337  __IO uint32_t CH2STAT_TOG;
10338  __IO uint32_t CH2OPTS;
10339  __IO uint32_t CH2OPTS_SET;
10340  __IO uint32_t CH2OPTS_CLR;
10341  __IO uint32_t CH2OPTS_TOG;
10342  __IO uint32_t CH3CMDPTR;
10343  uint8_t RESERVED_18[12];
10344  __IO uint32_t CH3SEMA;
10345  uint8_t RESERVED_19[12];
10346  __IO uint32_t CH3STAT;
10347  __IO uint32_t CH3STAT_SET;
10348  __IO uint32_t CH3STAT_CLR;
10349  __IO uint32_t CH3STAT_TOG;
10350  __IO uint32_t CH3OPTS;
10351  __IO uint32_t CH3OPTS_SET;
10352  __IO uint32_t CH3OPTS_CLR;
10353  __IO uint32_t CH3OPTS_TOG;
10354  uint8_t RESERVED_20[512];
10355  __IO uint32_t DBGSELECT;
10356  uint8_t RESERVED_21[12];
10357  __I uint32_t DBGDATA;
10358  uint8_t RESERVED_22[12];
10359  __IO uint32_t PAGETABLE;
10360  uint8_t RESERVED_23[12];
10361  __I uint32_t VERSION;
10362 } DCP_Type;
10363 
10364 /* ----------------------------------------------------------------------------
10365  -- DCP Register Masks
10366  ---------------------------------------------------------------------------- */
10367 
10375 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10376 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10377 
10383 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
10384 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10385 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10386 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10387 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10388 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10389 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
10390 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10391 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10392 #define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
10393 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10394 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10395 #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
10396 #define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
10397 #define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
10398 
10402 #define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
10403 #define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
10404 #define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
10405 
10409 #define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
10410 #define DCP_CTRL_CLKGATE_MASK (0x40000000U)
10411 #define DCP_CTRL_CLKGATE_SHIFT (30U)
10412 #define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
10413 #define DCP_CTRL_SFTRST_MASK (0x80000000U)
10414 #define DCP_CTRL_SFTRST_SHIFT (31U)
10415 #define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
10416 
10420 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10421 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10422 
10428 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
10429 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10430 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10431 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10432 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10433 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10434 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
10435 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10436 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10437 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
10438 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10439 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10440 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
10441 #define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)
10442 #define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)
10443 
10447 #define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
10448 #define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)
10449 #define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)
10450 
10454 #define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
10455 #define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)
10456 #define DCP_CTRL_SET_CLKGATE_SHIFT (30U)
10457 #define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
10458 #define DCP_CTRL_SET_SFTRST_MASK (0x80000000U)
10459 #define DCP_CTRL_SET_SFTRST_SHIFT (31U)
10460 #define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
10461 
10465 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10466 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10467 
10473 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
10474 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10475 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10476 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10477 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10478 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10479 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
10480 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10481 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10482 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
10483 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10484 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10485 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
10486 #define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)
10487 #define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)
10488 
10492 #define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
10493 #define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)
10494 #define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)
10495 
10499 #define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
10500 #define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
10501 #define DCP_CTRL_CLR_CLKGATE_SHIFT (30U)
10502 #define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
10503 #define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U)
10504 #define DCP_CTRL_CLR_SFTRST_SHIFT (31U)
10505 #define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
10506 
10510 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10511 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10512 
10518 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
10519 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10520 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10521 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10522 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10523 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10524 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
10525 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10526 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10527 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
10528 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10529 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10530 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
10531 #define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U)
10532 #define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U)
10533 
10537 #define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
10538 #define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U)
10539 #define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U)
10540 
10544 #define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
10545 #define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
10546 #define DCP_CTRL_TOG_CLKGATE_SHIFT (30U)
10547 #define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
10548 #define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U)
10549 #define DCP_CTRL_TOG_SFTRST_SHIFT (31U)
10550 #define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
10551 
10555 #define DCP_STAT_IRQ_MASK (0xFU)
10556 #define DCP_STAT_IRQ_SHIFT (0U)
10557 #define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
10558 #define DCP_STAT_RSVD_IRQ_MASK (0x100U)
10559 #define DCP_STAT_RSVD_IRQ_SHIFT (8U)
10560 #define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
10561 #define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
10562 #define DCP_STAT_READY_CHANNELS_SHIFT (16U)
10563 
10569 #define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
10570 #define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
10571 #define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
10572 
10579 #define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
10580 #define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
10581 #define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
10582 #define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
10583 
10587 #define DCP_STAT_SET_IRQ_MASK (0xFU)
10588 #define DCP_STAT_SET_IRQ_SHIFT (0U)
10589 #define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
10590 #define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U)
10591 #define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U)
10592 #define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
10593 #define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U)
10594 #define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U)
10595 
10601 #define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
10602 #define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U)
10603 #define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U)
10604 
10611 #define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
10612 #define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U)
10613 #define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U)
10614 #define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
10615 
10619 #define DCP_STAT_CLR_IRQ_MASK (0xFU)
10620 #define DCP_STAT_CLR_IRQ_SHIFT (0U)
10621 #define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
10622 #define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U)
10623 #define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U)
10624 #define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
10625 #define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U)
10626 #define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U)
10627 
10633 #define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
10634 #define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U)
10635 #define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U)
10636 
10643 #define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
10644 #define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U)
10645 #define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U)
10646 #define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
10647 
10651 #define DCP_STAT_TOG_IRQ_MASK (0xFU)
10652 #define DCP_STAT_TOG_IRQ_SHIFT (0U)
10653 #define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
10654 #define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U)
10655 #define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U)
10656 #define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
10657 #define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U)
10658 #define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U)
10659 
10665 #define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
10666 #define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U)
10667 #define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U)
10668 
10675 #define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
10676 #define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U)
10677 #define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U)
10678 #define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
10679 
10683 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
10684 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
10685 
10691 #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
10692 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10693 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10694 
10700 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
10701 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
10702 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
10703 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
10704 #define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
10705 #define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
10706 #define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
10707 
10711 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU)
10712 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
10713 
10719 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
10720 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10721 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10722 
10728 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
10729 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U)
10730 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
10731 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
10732 #define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U)
10733 #define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U)
10734 #define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
10735 
10739 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU)
10740 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
10741 
10747 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
10748 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10749 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10750 
10756 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
10757 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U)
10758 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
10759 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
10760 #define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U)
10761 #define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U)
10762 #define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
10763 
10767 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU)
10768 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
10769 
10775 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
10776 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10777 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10778 
10784 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
10785 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U)
10786 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
10787 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
10788 #define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U)
10789 #define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U)
10790 #define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
10791 
10795 #define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
10796 #define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
10797 #define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
10798 #define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
10799 #define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
10800 #define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
10801 #define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
10802 #define DCP_CAPABILITY0_RSVD_SHIFT (12U)
10803 #define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
10804 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
10805 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
10806 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
10807 #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
10808 #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
10809 #define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
10810 
10814 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
10815 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
10816 
10819 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
10820 #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
10821 #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
10822 
10827 #define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
10828 
10832 #define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
10833 #define DCP_CONTEXT_ADDR_SHIFT (0U)
10834 #define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
10835 
10839 #define DCP_KEY_SUBWORD_MASK (0x3U)
10840 #define DCP_KEY_SUBWORD_SHIFT (0U)
10841 #define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
10842 #define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
10843 #define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
10844 #define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
10845 #define DCP_KEY_INDEX_MASK (0x30U)
10846 #define DCP_KEY_INDEX_SHIFT (4U)
10847 #define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
10848 #define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
10849 #define DCP_KEY_RSVD_INDEX_SHIFT (6U)
10850 #define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
10851 #define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
10852 #define DCP_KEY_RSVD_SHIFT (8U)
10853 #define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
10854 
10858 #define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
10859 #define DCP_KEYDATA_DATA_SHIFT (0U)
10860 #define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
10861 
10865 #define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
10866 #define DCP_PACKET0_ADDR_SHIFT (0U)
10867 #define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
10868 
10872 #define DCP_PACKET1_INTERRUPT_MASK (0x1U)
10873 #define DCP_PACKET1_INTERRUPT_SHIFT (0U)
10874 #define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
10875 #define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
10876 #define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
10877 #define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
10878 #define DCP_PACKET1_CHAIN_MASK (0x4U)
10879 #define DCP_PACKET1_CHAIN_SHIFT (2U)
10880 #define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
10881 #define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
10882 #define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
10883 #define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
10884 #define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
10885 #define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
10886 #define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
10887 #define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
10888 #define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
10889 #define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
10890 #define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
10891 #define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
10892 #define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
10893 #define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
10894 #define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
10895 #define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
10896 #define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
10897 #define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
10898 
10902 #define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
10903 #define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
10904 #define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
10905 #define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
10906 #define DCP_PACKET1_OTP_KEY_MASK (0x400U)
10907 #define DCP_PACKET1_OTP_KEY_SHIFT (10U)
10908 #define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
10909 #define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
10910 #define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
10911 #define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
10912 #define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
10913 #define DCP_PACKET1_HASH_INIT_SHIFT (12U)
10914 #define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
10915 #define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
10916 #define DCP_PACKET1_HASH_TERM_SHIFT (13U)
10917 #define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
10918 #define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
10919 #define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
10920 #define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
10921 #define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
10922 #define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
10923 
10927 #define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
10928 #define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
10929 #define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
10930 #define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
10931 #define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
10932 #define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
10933 #define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
10934 #define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
10935 #define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
10936 #define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
10937 #define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
10938 #define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
10939 #define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
10940 #define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
10941 #define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
10942 #define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
10943 #define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
10944 #define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
10945 #define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
10946 #define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
10947 #define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
10948 #define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
10949 #define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
10950 #define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
10951 #define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
10952 #define DCP_PACKET1_TAG_MASK (0xFF000000U)
10953 #define DCP_PACKET1_TAG_SHIFT (24U)
10954 #define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
10955 
10959 #define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
10960 #define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
10961 
10964 #define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
10965 #define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
10966 #define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
10967 
10971 #define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
10972 #define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
10973 #define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
10974 
10982 #define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
10983 #define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
10984 #define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
10985 
10990 #define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
10991 #define DCP_PACKET2_RSVD_MASK (0xF00000U)
10992 #define DCP_PACKET2_RSVD_SHIFT (20U)
10993 #define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
10994 #define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
10995 #define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
10996 #define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
10997 
11001 #define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
11002 #define DCP_PACKET3_ADDR_SHIFT (0U)
11003 #define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
11004 
11008 #define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
11009 #define DCP_PACKET4_ADDR_SHIFT (0U)
11010 #define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
11011 
11015 #define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
11016 #define DCP_PACKET5_COUNT_SHIFT (0U)
11017 #define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
11018 
11022 #define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
11023 #define DCP_PACKET6_ADDR_SHIFT (0U)
11024 #define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
11025 
11029 #define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11030 #define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
11031 #define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
11032 
11036 #define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
11037 #define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
11038 #define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
11039 #define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
11040 #define DCP_CH0SEMA_VALUE_SHIFT (16U)
11041 #define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
11042 
11046 #define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
11047 #define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
11048 #define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
11049 #define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
11050 #define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
11051 #define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
11052 #define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
11053 #define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
11054 #define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
11055 #define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
11056 #define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
11057 #define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
11058 #define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
11059 #define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
11060 #define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
11061 #define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
11062 #define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
11063 #define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
11064 #define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
11065 #define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
11066 #define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
11067 #define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
11068 #define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
11069 
11076 #define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
11077 #define DCP_CH0STAT_TAG_MASK (0xFF000000U)
11078 #define DCP_CH0STAT_TAG_SHIFT (24U)
11079 #define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
11080 
11084 #define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11085 #define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11086 #define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
11087 #define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)
11088 #define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)
11089 #define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
11090 #define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)
11091 #define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)
11092 #define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
11093 #define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)
11094 #define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)
11095 #define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
11096 #define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)
11097 #define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)
11098 #define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
11099 #define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)
11100 #define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)
11101 #define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
11102 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11103 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11104 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
11105 #define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11106 #define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)
11107 
11114 #define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
11115 #define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)
11116 #define DCP_CH0STAT_SET_TAG_SHIFT (24U)
11117 #define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
11118 
11122 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11123 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11124 #define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
11125 #define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11126 #define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11127 #define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
11128 #define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)
11129 #define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)
11130 #define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
11131 #define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)
11132 #define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)
11133 #define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
11134 #define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)
11135 #define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)
11136 #define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
11137 #define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)
11138 #define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)
11139 #define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
11140 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11141 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11142 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
11143 #define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11144 #define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)
11145 
11152 #define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
11153 #define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)
11154 #define DCP_CH0STAT_CLR_TAG_SHIFT (24U)
11155 #define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
11156 
11160 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11161 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11162 #define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
11163 #define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11164 #define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11165 #define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
11166 #define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)
11167 #define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)
11168 #define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
11169 #define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)
11170 #define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)
11171 #define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
11172 #define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)
11173 #define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)
11174 #define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
11175 #define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)
11176 #define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)
11177 #define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
11178 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11179 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11180 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
11181 #define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11182 #define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)
11183 
11190 #define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
11191 #define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)
11192 #define DCP_CH0STAT_TOG_TAG_SHIFT (24U)
11193 #define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
11194 
11198 #define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11199 #define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
11200 #define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
11201 #define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
11202 #define DCP_CH0OPTS_RSVD_SHIFT (16U)
11203 #define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
11204 
11208 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11209 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11210 #define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
11211 #define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)
11212 #define DCP_CH0OPTS_SET_RSVD_SHIFT (16U)
11213 #define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
11214 
11218 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11219 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11220 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
11221 #define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11222 #define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)
11223 #define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
11224 
11228 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11229 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11230 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
11231 #define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11232 #define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)
11233 #define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
11234 
11238 #define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11239 #define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
11240 #define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
11241 
11245 #define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
11246 #define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
11247 #define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
11248 #define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
11249 #define DCP_CH1SEMA_VALUE_SHIFT (16U)
11250 #define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
11251 
11255 #define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
11256 #define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
11257 #define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
11258 #define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
11259 #define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
11260 #define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
11261 #define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
11262 #define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
11263 #define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
11264 #define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
11265 #define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
11266 #define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
11267 #define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
11268 #define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
11269 #define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
11270 #define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
11271 #define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
11272 #define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
11273 #define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
11274 #define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
11275 #define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
11276 #define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
11277 #define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
11278 
11285 #define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
11286 #define DCP_CH1STAT_TAG_MASK (0xFF000000U)
11287 #define DCP_CH1STAT_TAG_SHIFT (24U)
11288 #define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
11289 
11293 #define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11294 #define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11295 #define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
11296 #define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)
11297 #define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)
11298 #define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
11299 #define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)
11300 #define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)
11301 #define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
11302 #define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)
11303 #define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)
11304 #define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
11305 #define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)
11306 #define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)
11307 #define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
11308 #define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)
11309 #define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)
11310 #define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
11311 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11312 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11313 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
11314 #define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11315 #define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)
11316 
11323 #define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
11324 #define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)
11325 #define DCP_CH1STAT_SET_TAG_SHIFT (24U)
11326 #define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
11327 
11331 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11332 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11333 #define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
11334 #define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11335 #define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11336 #define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
11337 #define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)
11338 #define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)
11339 #define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
11340 #define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)
11341 #define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)
11342 #define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
11343 #define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)
11344 #define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)
11345 #define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
11346 #define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)
11347 #define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)
11348 #define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
11349 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11350 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11351 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
11352 #define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11353 #define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)
11354 
11361 #define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
11362 #define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)
11363 #define DCP_CH1STAT_CLR_TAG_SHIFT (24U)
11364 #define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
11365 
11369 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11370 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11371 #define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
11372 #define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11373 #define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11374 #define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
11375 #define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)
11376 #define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)
11377 #define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
11378 #define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)
11379 #define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)
11380 #define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
11381 #define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)
11382 #define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)
11383 #define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
11384 #define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)
11385 #define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)
11386 #define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
11387 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11388 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11389 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
11390 #define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11391 #define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)
11392 
11399 #define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
11400 #define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)
11401 #define DCP_CH1STAT_TOG_TAG_SHIFT (24U)
11402 #define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
11403 
11407 #define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11408 #define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
11409 #define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
11410 #define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
11411 #define DCP_CH1OPTS_RSVD_SHIFT (16U)
11412 #define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
11413 
11417 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11418 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11419 #define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
11420 #define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)
11421 #define DCP_CH1OPTS_SET_RSVD_SHIFT (16U)
11422 #define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
11423 
11427 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11428 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11429 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
11430 #define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11431 #define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U)
11432 #define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
11433 
11437 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11438 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11439 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
11440 #define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11441 #define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U)
11442 #define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
11443 
11447 #define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11448 #define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
11449 #define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
11450 
11454 #define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
11455 #define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
11456 #define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
11457 #define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
11458 #define DCP_CH2SEMA_VALUE_SHIFT (16U)
11459 #define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
11460 
11464 #define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
11465 #define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
11466 #define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
11467 #define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
11468 #define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
11469 #define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
11470 #define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
11471 #define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
11472 #define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
11473 #define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
11474 #define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
11475 #define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
11476 #define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
11477 #define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
11478 #define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
11479 #define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
11480 #define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
11481 #define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
11482 #define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
11483 #define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
11484 #define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
11485 #define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
11486 #define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
11487 
11494 #define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
11495 #define DCP_CH2STAT_TAG_MASK (0xFF000000U)
11496 #define DCP_CH2STAT_TAG_SHIFT (24U)
11497 #define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
11498 
11502 #define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11503 #define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11504 #define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
11505 #define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)
11506 #define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)
11507 #define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
11508 #define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)
11509 #define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)
11510 #define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
11511 #define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)
11512 #define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)
11513 #define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
11514 #define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)
11515 #define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)
11516 #define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
11517 #define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)
11518 #define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)
11519 #define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
11520 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11521 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11522 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
11523 #define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11524 #define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)
11525 
11532 #define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
11533 #define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U)
11534 #define DCP_CH2STAT_SET_TAG_SHIFT (24U)
11535 #define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
11536 
11540 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11541 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11542 #define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
11543 #define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11544 #define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11545 #define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
11546 #define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)
11547 #define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)
11548 #define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
11549 #define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)
11550 #define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)
11551 #define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
11552 #define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)
11553 #define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)
11554 #define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
11555 #define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)
11556 #define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)
11557 #define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
11558 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11559 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11560 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
11561 #define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11562 #define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)
11563 
11570 #define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
11571 #define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)
11572 #define DCP_CH2STAT_CLR_TAG_SHIFT (24U)
11573 #define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
11574 
11578 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11579 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11580 #define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
11581 #define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11582 #define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11583 #define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
11584 #define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)
11585 #define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)
11586 #define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
11587 #define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)
11588 #define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)
11589 #define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
11590 #define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)
11591 #define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)
11592 #define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
11593 #define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)
11594 #define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)
11595 #define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
11596 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11597 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11598 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
11599 #define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11600 #define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)
11601 
11608 #define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
11609 #define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)
11610 #define DCP_CH2STAT_TOG_TAG_SHIFT (24U)
11611 #define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
11612 
11616 #define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11617 #define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
11618 #define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
11619 #define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
11620 #define DCP_CH2OPTS_RSVD_SHIFT (16U)
11621 #define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
11622 
11626 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11627 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11628 #define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
11629 #define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)
11630 #define DCP_CH2OPTS_SET_RSVD_SHIFT (16U)
11631 #define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
11632 
11636 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11637 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11638 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
11639 #define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11640 #define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U)
11641 #define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
11642 
11646 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11647 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11648 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
11649 #define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11650 #define DCP_CH2OPTS_TOG_RSVD_SHIFT (16U)
11651 #define DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
11652 
11656 #define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11657 #define DCP_CH3CMDPTR_ADDR_SHIFT (0U)
11658 #define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
11659 
11663 #define DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
11664 #define DCP_CH3SEMA_INCREMENT_SHIFT (0U)
11665 #define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
11666 #define DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
11667 #define DCP_CH3SEMA_VALUE_SHIFT (16U)
11668 #define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
11669 
11673 #define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
11674 #define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
11675 #define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
11676 #define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
11677 #define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
11678 #define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
11679 #define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
11680 #define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
11681 #define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
11682 #define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
11683 #define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
11684 #define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
11685 #define DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
11686 #define DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
11687 #define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
11688 #define DCP_CH3STAT_ERROR_DST_MASK (0x20U)
11689 #define DCP_CH3STAT_ERROR_DST_SHIFT (5U)
11690 #define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
11691 #define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
11692 #define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
11693 #define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
11694 #define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
11695 #define DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
11696 
11703 #define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
11704 #define DCP_CH3STAT_TAG_MASK (0xFF000000U)
11705 #define DCP_CH3STAT_TAG_SHIFT (24U)
11706 #define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
11707 
11711 #define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11712 #define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11713 #define DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
11714 #define DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U)
11715 #define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U)
11716 #define DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
11717 #define DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U)
11718 #define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U)
11719 #define DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
11720 #define DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U)
11721 #define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U)
11722 #define DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
11723 #define DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U)
11724 #define DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U)
11725 #define DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
11726 #define DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U)
11727 #define DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U)
11728 #define DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
11729 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11730 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11731 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
11732 #define DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11733 #define DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U)
11734 
11741 #define DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
11742 #define DCP_CH3STAT_SET_TAG_MASK (0xFF000000U)
11743 #define DCP_CH3STAT_SET_TAG_SHIFT (24U)
11744 #define DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
11745 
11749 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11750 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11751 #define DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
11752 #define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11753 #define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11754 #define DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
11755 #define DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U)
11756 #define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U)
11757 #define DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
11758 #define DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U)
11759 #define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U)
11760 #define DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
11761 #define DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U)
11762 #define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U)
11763 #define DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
11764 #define DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U)
11765 #define DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U)
11766 #define DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
11767 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11768 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11769 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
11770 #define DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11771 #define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U)
11772 
11779 #define DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
11780 #define DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U)
11781 #define DCP_CH3STAT_CLR_TAG_SHIFT (24U)
11782 #define DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
11783 
11787 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11788 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11789 #define DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
11790 #define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11791 #define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11792 #define DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
11793 #define DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U)
11794 #define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U)
11795 #define DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
11796 #define DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U)
11797 #define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U)
11798 #define DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
11799 #define DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U)
11800 #define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U)
11801 #define DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
11802 #define DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U)
11803 #define DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U)
11804 #define DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
11805 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11806 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11807 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
11808 #define DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11809 #define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U)
11810 
11817 #define DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
11818 #define DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U)
11819 #define DCP_CH3STAT_TOG_TAG_SHIFT (24U)
11820 #define DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
11821 
11825 #define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11826 #define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
11827 #define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
11828 #define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
11829 #define DCP_CH3OPTS_RSVD_SHIFT (16U)
11830 #define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
11831 
11835 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11836 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11837 #define DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
11838 #define DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U)
11839 #define DCP_CH3OPTS_SET_RSVD_SHIFT (16U)
11840 #define DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
11841 
11845 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11846 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11847 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
11848 #define DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11849 #define DCP_CH3OPTS_CLR_RSVD_SHIFT (16U)
11850 #define DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
11851 
11855 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11856 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11857 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
11858 #define DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11859 #define DCP_CH3OPTS_TOG_RSVD_SHIFT (16U)
11860 #define DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
11861 
11865 #define DCP_DBGSELECT_INDEX_MASK (0xFFU)
11866 #define DCP_DBGSELECT_INDEX_SHIFT (0U)
11867 
11874 #define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
11875 #define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
11876 #define DCP_DBGSELECT_RSVD_SHIFT (8U)
11877 #define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
11878 
11882 #define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
11883 #define DCP_DBGDATA_DATA_SHIFT (0U)
11884 #define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
11885 
11889 #define DCP_PAGETABLE_ENABLE_MASK (0x1U)
11890 #define DCP_PAGETABLE_ENABLE_SHIFT (0U)
11891 #define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
11892 #define DCP_PAGETABLE_FLUSH_MASK (0x2U)
11893 #define DCP_PAGETABLE_FLUSH_SHIFT (1U)
11894 #define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
11895 #define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
11896 #define DCP_PAGETABLE_BASE_SHIFT (2U)
11897 #define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
11898 
11902 #define DCP_VERSION_STEP_MASK (0xFFFFU)
11903 #define DCP_VERSION_STEP_SHIFT (0U)
11904 #define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
11905 #define DCP_VERSION_MINOR_MASK (0xFF0000U)
11906 #define DCP_VERSION_MINOR_SHIFT (16U)
11907 #define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
11908 #define DCP_VERSION_MAJOR_MASK (0xFF000000U)
11909 #define DCP_VERSION_MAJOR_SHIFT (24U)
11910 #define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)
11911  /* end of group DCP_Register_Masks */
11917 
11918 
11919 /* DCP - Peripheral instance base addresses */
11921 #define DCP_BASE (0x402FC000u)
11922 
11923 #define DCP ((DCP_Type *)DCP_BASE)
11924 
11925 #define DCP_BASE_ADDRS { DCP_BASE }
11926 
11927 #define DCP_BASE_PTRS { DCP }
11928 
11929 #define DCP_IRQS { DCP_IRQn }
11930 #define DCP_VMI_IRQS { DCP_VMI_IRQn }
11931  /* end of group DCP_Peripheral_Access_Layer */
11935 
11936 
11937 /* ----------------------------------------------------------------------------
11938  -- DMA Peripheral Access Layer
11939  ---------------------------------------------------------------------------- */
11940 
11947 typedef struct {
11948  __IO uint32_t CR;
11949  __I uint32_t ES;
11950  uint8_t RESERVED_0[4];
11951  __IO uint32_t ERQ;
11952  uint8_t RESERVED_1[4];
11953  __IO uint32_t EEI;
11954  __O uint8_t CEEI;
11955  __O uint8_t SEEI;
11956  __O uint8_t CERQ;
11957  __O uint8_t SERQ;
11958  __O uint8_t CDNE;
11959  __O uint8_t SSRT;
11960  __O uint8_t CERR;
11961  __O uint8_t CINT;
11962  uint8_t RESERVED_2[4];
11963  __IO uint32_t INT;
11964  uint8_t RESERVED_3[4];
11965  __IO uint32_t ERR;
11966  uint8_t RESERVED_4[4];
11967  __I uint32_t HRS;
11968  uint8_t RESERVED_5[12];
11969  __IO uint32_t EARS;
11970  uint8_t RESERVED_6[184];
11971  __IO uint8_t DCHPRI3;
11972  __IO uint8_t DCHPRI2;
11973  __IO uint8_t DCHPRI1;
11974  __IO uint8_t DCHPRI0;
11975  __IO uint8_t DCHPRI7;
11976  __IO uint8_t DCHPRI6;
11977  __IO uint8_t DCHPRI5;
11978  __IO uint8_t DCHPRI4;
11979  __IO uint8_t DCHPRI11;
11980  __IO uint8_t DCHPRI10;
11981  __IO uint8_t DCHPRI9;
11982  __IO uint8_t DCHPRI8;
11983  __IO uint8_t DCHPRI15;
11984  __IO uint8_t DCHPRI14;
11985  __IO uint8_t DCHPRI13;
11986  __IO uint8_t DCHPRI12;
11987  __IO uint8_t DCHPRI19;
11988  __IO uint8_t DCHPRI18;
11989  __IO uint8_t DCHPRI17;
11990  __IO uint8_t DCHPRI16;
11991  __IO uint8_t DCHPRI23;
11992  __IO uint8_t DCHPRI22;
11993  __IO uint8_t DCHPRI21;
11994  __IO uint8_t DCHPRI20;
11995  __IO uint8_t DCHPRI27;
11996  __IO uint8_t DCHPRI26;
11997  __IO uint8_t DCHPRI25;
11998  __IO uint8_t DCHPRI24;
11999  __IO uint8_t DCHPRI31;
12000  __IO uint8_t DCHPRI30;
12001  __IO uint8_t DCHPRI29;
12002  __IO uint8_t DCHPRI28;
12003  uint8_t RESERVED_7[3808];
12004  struct { /* offset: 0x1000, array step: 0x20 */
12005  __IO uint32_t SADDR;
12006  __IO uint16_t SOFF;
12007  __IO uint16_t ATTR;
12008  union { /* offset: 0x1008, array step: 0x20 */
12009  __IO uint32_t NBYTES_MLNO;
12010  __IO uint32_t NBYTES_MLOFFNO;
12011  __IO uint32_t NBYTES_MLOFFYES;
12012  };
12013  __IO uint32_t SLAST;
12014  __IO uint32_t DADDR;
12015  __IO uint16_t DOFF;
12016  union { /* offset: 0x1016, array step: 0x20 */
12017  __IO uint16_t CITER_ELINKNO;
12018  __IO uint16_t CITER_ELINKYES;
12019  };
12020  __IO uint32_t DLAST_SGA;
12021  __IO uint16_t CSR;
12022  union { /* offset: 0x101E, array step: 0x20 */
12023  __IO uint16_t BITER_ELINKNO;
12024  __IO uint16_t BITER_ELINKYES;
12025  };
12026  } TCD[32];
12027 } DMA_Type;
12028 
12029 /* ----------------------------------------------------------------------------
12030  -- DMA Register Masks
12031  ---------------------------------------------------------------------------- */
12032 
12040 #define DMA_CR_EDBG_MASK (0x2U)
12041 #define DMA_CR_EDBG_SHIFT (1U)
12042 
12047 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
12048 #define DMA_CR_ERCA_MASK (0x4U)
12049 #define DMA_CR_ERCA_SHIFT (2U)
12050 
12054 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
12055 #define DMA_CR_ERGA_MASK (0x8U)
12056 #define DMA_CR_ERGA_SHIFT (3U)
12057 
12061 #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
12062 #define DMA_CR_HOE_MASK (0x10U)
12063 #define DMA_CR_HOE_SHIFT (4U)
12064 
12068 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
12069 #define DMA_CR_HALT_MASK (0x20U)
12070 #define DMA_CR_HALT_SHIFT (5U)
12071 
12075 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
12076 #define DMA_CR_CLM_MASK (0x40U)
12077 #define DMA_CR_CLM_SHIFT (6U)
12078 
12085 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
12086 #define DMA_CR_EMLM_MASK (0x80U)
12087 #define DMA_CR_EMLM_SHIFT (7U)
12088 
12094 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
12095 #define DMA_CR_GRP0PRI_MASK (0x100U)
12096 #define DMA_CR_GRP0PRI_SHIFT (8U)
12097 
12099 #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
12100 #define DMA_CR_GRP1PRI_MASK (0x400U)
12101 #define DMA_CR_GRP1PRI_SHIFT (10U)
12102 
12104 #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
12105 #define DMA_CR_ECX_MASK (0x10000U)
12106 #define DMA_CR_ECX_SHIFT (16U)
12107 
12115 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
12116 #define DMA_CR_CX_MASK (0x20000U)
12117 #define DMA_CR_CX_SHIFT (17U)
12118 
12124 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
12125 #define DMA_CR_ACTIVE_MASK (0x80000000U)
12126 #define DMA_CR_ACTIVE_SHIFT (31U)
12127 
12131 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
12132 
12136 #define DMA_ES_DBE_MASK (0x1U)
12137 #define DMA_ES_DBE_SHIFT (0U)
12138 
12142 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
12143 #define DMA_ES_SBE_MASK (0x2U)
12144 #define DMA_ES_SBE_SHIFT (1U)
12145 
12149 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
12150 #define DMA_ES_SGE_MASK (0x4U)
12151 #define DMA_ES_SGE_SHIFT (2U)
12152 
12158 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
12159 #define DMA_ES_NCE_MASK (0x8U)
12160 #define DMA_ES_NCE_SHIFT (3U)
12161 
12167 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
12168 #define DMA_ES_DOE_MASK (0x10U)
12169 #define DMA_ES_DOE_SHIFT (4U)
12170 
12174 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
12175 #define DMA_ES_DAE_MASK (0x20U)
12176 #define DMA_ES_DAE_SHIFT (5U)
12177 
12181 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
12182 #define DMA_ES_SOE_MASK (0x40U)
12183 #define DMA_ES_SOE_SHIFT (6U)
12184 
12188 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
12189 #define DMA_ES_SAE_MASK (0x80U)
12190 #define DMA_ES_SAE_SHIFT (7U)
12191 
12195 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
12196 #define DMA_ES_ERRCHN_MASK (0x1F00U)
12197 #define DMA_ES_ERRCHN_SHIFT (8U)
12198 
12200 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
12201 #define DMA_ES_CPE_MASK (0x4000U)
12202 #define DMA_ES_CPE_SHIFT (14U)
12203 
12208 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
12209 #define DMA_ES_GPE_MASK (0x8000U)
12210 #define DMA_ES_GPE_SHIFT (15U)
12211 
12215 #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
12216 #define DMA_ES_ECX_MASK (0x10000U)
12217 #define DMA_ES_ECX_SHIFT (16U)
12218 
12222 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
12223 #define DMA_ES_VLD_MASK (0x80000000U)
12224 #define DMA_ES_VLD_SHIFT (31U)
12225 
12229 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
12230 
12234 #define DMA_ERQ_ERQ0_MASK (0x1U)
12235 #define DMA_ERQ_ERQ0_SHIFT (0U)
12236 
12240 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
12241 #define DMA_ERQ_ERQ1_MASK (0x2U)
12242 #define DMA_ERQ_ERQ1_SHIFT (1U)
12243 
12247 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
12248 #define DMA_ERQ_ERQ2_MASK (0x4U)
12249 #define DMA_ERQ_ERQ2_SHIFT (2U)
12250 
12254 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
12255 #define DMA_ERQ_ERQ3_MASK (0x8U)
12256 #define DMA_ERQ_ERQ3_SHIFT (3U)
12257 
12261 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
12262 #define DMA_ERQ_ERQ4_MASK (0x10U)
12263 #define DMA_ERQ_ERQ4_SHIFT (4U)
12264 
12268 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
12269 #define DMA_ERQ_ERQ5_MASK (0x20U)
12270 #define DMA_ERQ_ERQ5_SHIFT (5U)
12271 
12275 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
12276 #define DMA_ERQ_ERQ6_MASK (0x40U)
12277 #define DMA_ERQ_ERQ6_SHIFT (6U)
12278 
12282 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
12283 #define DMA_ERQ_ERQ7_MASK (0x80U)
12284 #define DMA_ERQ_ERQ7_SHIFT (7U)
12285 
12289 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
12290 #define DMA_ERQ_ERQ8_MASK (0x100U)
12291 #define DMA_ERQ_ERQ8_SHIFT (8U)
12292 
12296 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
12297 #define DMA_ERQ_ERQ9_MASK (0x200U)
12298 #define DMA_ERQ_ERQ9_SHIFT (9U)
12299 
12303 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
12304 #define DMA_ERQ_ERQ10_MASK (0x400U)
12305 #define DMA_ERQ_ERQ10_SHIFT (10U)
12306 
12310 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
12311 #define DMA_ERQ_ERQ11_MASK (0x800U)
12312 #define DMA_ERQ_ERQ11_SHIFT (11U)
12313 
12317 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
12318 #define DMA_ERQ_ERQ12_MASK (0x1000U)
12319 #define DMA_ERQ_ERQ12_SHIFT (12U)
12320 
12324 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
12325 #define DMA_ERQ_ERQ13_MASK (0x2000U)
12326 #define DMA_ERQ_ERQ13_SHIFT (13U)
12327 
12331 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
12332 #define DMA_ERQ_ERQ14_MASK (0x4000U)
12333 #define DMA_ERQ_ERQ14_SHIFT (14U)
12334 
12338 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
12339 #define DMA_ERQ_ERQ15_MASK (0x8000U)
12340 #define DMA_ERQ_ERQ15_SHIFT (15U)
12341 
12345 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
12346 #define DMA_ERQ_ERQ16_MASK (0x10000U)
12347 #define DMA_ERQ_ERQ16_SHIFT (16U)
12348 
12352 #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
12353 #define DMA_ERQ_ERQ17_MASK (0x20000U)
12354 #define DMA_ERQ_ERQ17_SHIFT (17U)
12355 
12359 #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
12360 #define DMA_ERQ_ERQ18_MASK (0x40000U)
12361 #define DMA_ERQ_ERQ18_SHIFT (18U)
12362 
12366 #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
12367 #define DMA_ERQ_ERQ19_MASK (0x80000U)
12368 #define DMA_ERQ_ERQ19_SHIFT (19U)
12369 
12373 #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
12374 #define DMA_ERQ_ERQ20_MASK (0x100000U)
12375 #define DMA_ERQ_ERQ20_SHIFT (20U)
12376 
12380 #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
12381 #define DMA_ERQ_ERQ21_MASK (0x200000U)
12382 #define DMA_ERQ_ERQ21_SHIFT (21U)
12383 
12387 #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
12388 #define DMA_ERQ_ERQ22_MASK (0x400000U)
12389 #define DMA_ERQ_ERQ22_SHIFT (22U)
12390 
12394 #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
12395 #define DMA_ERQ_ERQ23_MASK (0x800000U)
12396 #define DMA_ERQ_ERQ23_SHIFT (23U)
12397 
12401 #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
12402 #define DMA_ERQ_ERQ24_MASK (0x1000000U)
12403 #define DMA_ERQ_ERQ24_SHIFT (24U)
12404 
12408 #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
12409 #define DMA_ERQ_ERQ25_MASK (0x2000000U)
12410 #define DMA_ERQ_ERQ25_SHIFT (25U)
12411 
12415 #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
12416 #define DMA_ERQ_ERQ26_MASK (0x4000000U)
12417 #define DMA_ERQ_ERQ26_SHIFT (26U)
12418 
12422 #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
12423 #define DMA_ERQ_ERQ27_MASK (0x8000000U)
12424 #define DMA_ERQ_ERQ27_SHIFT (27U)
12425 
12429 #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
12430 #define DMA_ERQ_ERQ28_MASK (0x10000000U)
12431 #define DMA_ERQ_ERQ28_SHIFT (28U)
12432 
12436 #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
12437 #define DMA_ERQ_ERQ29_MASK (0x20000000U)
12438 #define DMA_ERQ_ERQ29_SHIFT (29U)
12439 
12443 #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
12444 #define DMA_ERQ_ERQ30_MASK (0x40000000U)
12445 #define DMA_ERQ_ERQ30_SHIFT (30U)
12446 
12450 #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
12451 #define DMA_ERQ_ERQ31_MASK (0x80000000U)
12452 #define DMA_ERQ_ERQ31_SHIFT (31U)
12453 
12457 #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
12458 
12462 #define DMA_EEI_EEI0_MASK (0x1U)
12463 #define DMA_EEI_EEI0_SHIFT (0U)
12464 
12468 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
12469 #define DMA_EEI_EEI1_MASK (0x2U)
12470 #define DMA_EEI_EEI1_SHIFT (1U)
12471 
12475 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
12476 #define DMA_EEI_EEI2_MASK (0x4U)
12477 #define DMA_EEI_EEI2_SHIFT (2U)
12478 
12482 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
12483 #define DMA_EEI_EEI3_MASK (0x8U)
12484 #define DMA_EEI_EEI3_SHIFT (3U)
12485 
12489 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
12490 #define DMA_EEI_EEI4_MASK (0x10U)
12491 #define DMA_EEI_EEI4_SHIFT (4U)
12492 
12496 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
12497 #define DMA_EEI_EEI5_MASK (0x20U)
12498 #define DMA_EEI_EEI5_SHIFT (5U)
12499 
12503 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
12504 #define DMA_EEI_EEI6_MASK (0x40U)
12505 #define DMA_EEI_EEI6_SHIFT (6U)
12506 
12510 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
12511 #define DMA_EEI_EEI7_MASK (0x80U)
12512 #define DMA_EEI_EEI7_SHIFT (7U)
12513 
12517 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
12518 #define DMA_EEI_EEI8_MASK (0x100U)
12519 #define DMA_EEI_EEI8_SHIFT (8U)
12520 
12524 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
12525 #define DMA_EEI_EEI9_MASK (0x200U)
12526 #define DMA_EEI_EEI9_SHIFT (9U)
12527 
12531 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
12532 #define DMA_EEI_EEI10_MASK (0x400U)
12533 #define DMA_EEI_EEI10_SHIFT (10U)
12534 
12538 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
12539 #define DMA_EEI_EEI11_MASK (0x800U)
12540 #define DMA_EEI_EEI11_SHIFT (11U)
12541 
12545 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
12546 #define DMA_EEI_EEI12_MASK (0x1000U)
12547 #define DMA_EEI_EEI12_SHIFT (12U)
12548 
12552 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
12553 #define DMA_EEI_EEI13_MASK (0x2000U)
12554 #define DMA_EEI_EEI13_SHIFT (13U)
12555 
12559 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
12560 #define DMA_EEI_EEI14_MASK (0x4000U)
12561 #define DMA_EEI_EEI14_SHIFT (14U)
12562 
12566 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
12567 #define DMA_EEI_EEI15_MASK (0x8000U)
12568 #define DMA_EEI_EEI15_SHIFT (15U)
12569 
12573 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
12574 #define DMA_EEI_EEI16_MASK (0x10000U)
12575 #define DMA_EEI_EEI16_SHIFT (16U)
12576 
12580 #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
12581 #define DMA_EEI_EEI17_MASK (0x20000U)
12582 #define DMA_EEI_EEI17_SHIFT (17U)
12583 
12587 #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
12588 #define DMA_EEI_EEI18_MASK (0x40000U)
12589 #define DMA_EEI_EEI18_SHIFT (18U)
12590 
12594 #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
12595 #define DMA_EEI_EEI19_MASK (0x80000U)
12596 #define DMA_EEI_EEI19_SHIFT (19U)
12597 
12601 #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
12602 #define DMA_EEI_EEI20_MASK (0x100000U)
12603 #define DMA_EEI_EEI20_SHIFT (20U)
12604 
12608 #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
12609 #define DMA_EEI_EEI21_MASK (0x200000U)
12610 #define DMA_EEI_EEI21_SHIFT (21U)
12611 
12615 #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
12616 #define DMA_EEI_EEI22_MASK (0x400000U)
12617 #define DMA_EEI_EEI22_SHIFT (22U)
12618 
12622 #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
12623 #define DMA_EEI_EEI23_MASK (0x800000U)
12624 #define DMA_EEI_EEI23_SHIFT (23U)
12625 
12629 #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
12630 #define DMA_EEI_EEI24_MASK (0x1000000U)
12631 #define DMA_EEI_EEI24_SHIFT (24U)
12632 
12636 #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
12637 #define DMA_EEI_EEI25_MASK (0x2000000U)
12638 #define DMA_EEI_EEI25_SHIFT (25U)
12639 
12643 #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
12644 #define DMA_EEI_EEI26_MASK (0x4000000U)
12645 #define DMA_EEI_EEI26_SHIFT (26U)
12646 
12650 #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
12651 #define DMA_EEI_EEI27_MASK (0x8000000U)
12652 #define DMA_EEI_EEI27_SHIFT (27U)
12653 
12657 #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
12658 #define DMA_EEI_EEI28_MASK (0x10000000U)
12659 #define DMA_EEI_EEI28_SHIFT (28U)
12660 
12664 #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
12665 #define DMA_EEI_EEI29_MASK (0x20000000U)
12666 #define DMA_EEI_EEI29_SHIFT (29U)
12667 
12671 #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
12672 #define DMA_EEI_EEI30_MASK (0x40000000U)
12673 #define DMA_EEI_EEI30_SHIFT (30U)
12674 
12678 #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
12679 #define DMA_EEI_EEI31_MASK (0x80000000U)
12680 #define DMA_EEI_EEI31_SHIFT (31U)
12681 
12685 #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
12686 
12690 #define DMA_CEEI_CEEI_MASK (0x1FU)
12691 #define DMA_CEEI_CEEI_SHIFT (0U)
12692 
12694 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
12695 #define DMA_CEEI_CAEE_MASK (0x40U)
12696 #define DMA_CEEI_CAEE_SHIFT (6U)
12697 
12701 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
12702 #define DMA_CEEI_NOP_MASK (0x80U)
12703 #define DMA_CEEI_NOP_SHIFT (7U)
12704 
12708 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
12709 
12713 #define DMA_SEEI_SEEI_MASK (0x1FU)
12714 #define DMA_SEEI_SEEI_SHIFT (0U)
12715 
12717 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
12718 #define DMA_SEEI_SAEE_MASK (0x40U)
12719 #define DMA_SEEI_SAEE_SHIFT (6U)
12720 
12724 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
12725 #define DMA_SEEI_NOP_MASK (0x80U)
12726 #define DMA_SEEI_NOP_SHIFT (7U)
12727 
12731 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
12732 
12736 #define DMA_CERQ_CERQ_MASK (0x1FU)
12737 #define DMA_CERQ_CERQ_SHIFT (0U)
12738 
12740 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
12741 #define DMA_CERQ_CAER_MASK (0x40U)
12742 #define DMA_CERQ_CAER_SHIFT (6U)
12743 
12747 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
12748 #define DMA_CERQ_NOP_MASK (0x80U)
12749 #define DMA_CERQ_NOP_SHIFT (7U)
12750 
12754 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
12755 
12759 #define DMA_SERQ_SERQ_MASK (0x1FU)
12760 #define DMA_SERQ_SERQ_SHIFT (0U)
12761 
12763 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
12764 #define DMA_SERQ_SAER_MASK (0x40U)
12765 #define DMA_SERQ_SAER_SHIFT (6U)
12766 
12770 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
12771 #define DMA_SERQ_NOP_MASK (0x80U)
12772 #define DMA_SERQ_NOP_SHIFT (7U)
12773 
12777 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
12778 
12782 #define DMA_CDNE_CDNE_MASK (0x1FU)
12783 #define DMA_CDNE_CDNE_SHIFT (0U)
12784 
12786 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
12787 #define DMA_CDNE_CADN_MASK (0x40U)
12788 #define DMA_CDNE_CADN_SHIFT (6U)
12789 
12793 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
12794 #define DMA_CDNE_NOP_MASK (0x80U)
12795 #define DMA_CDNE_NOP_SHIFT (7U)
12796 
12800 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
12801 
12805 #define DMA_SSRT_SSRT_MASK (0x1FU)
12806 #define DMA_SSRT_SSRT_SHIFT (0U)
12807 
12809 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
12810 #define DMA_SSRT_SAST_MASK (0x40U)
12811 #define DMA_SSRT_SAST_SHIFT (6U)
12812 
12816 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
12817 #define DMA_SSRT_NOP_MASK (0x80U)
12818 #define DMA_SSRT_NOP_SHIFT (7U)
12819 
12823 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
12824 
12828 #define DMA_CERR_CERR_MASK (0x1FU)
12829 #define DMA_CERR_CERR_SHIFT (0U)
12830 
12832 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
12833 #define DMA_CERR_CAEI_MASK (0x40U)
12834 #define DMA_CERR_CAEI_SHIFT (6U)
12835 
12839 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
12840 #define DMA_CERR_NOP_MASK (0x80U)
12841 #define DMA_CERR_NOP_SHIFT (7U)
12842 
12846 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
12847 
12851 #define DMA_CINT_CINT_MASK (0x1FU)
12852 #define DMA_CINT_CINT_SHIFT (0U)
12853 
12855 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
12856 #define DMA_CINT_CAIR_MASK (0x40U)
12857 #define DMA_CINT_CAIR_SHIFT (6U)
12858 
12862 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
12863 #define DMA_CINT_NOP_MASK (0x80U)
12864 #define DMA_CINT_NOP_SHIFT (7U)
12865 
12869 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
12870 
12874 #define DMA_INT_INT0_MASK (0x1U)
12875 #define DMA_INT_INT0_SHIFT (0U)
12876 
12880 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
12881 #define DMA_INT_INT1_MASK (0x2U)
12882 #define DMA_INT_INT1_SHIFT (1U)
12883 
12887 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
12888 #define DMA_INT_INT2_MASK (0x4U)
12889 #define DMA_INT_INT2_SHIFT (2U)
12890 
12894 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
12895 #define DMA_INT_INT3_MASK (0x8U)
12896 #define DMA_INT_INT3_SHIFT (3U)
12897 
12901 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
12902 #define DMA_INT_INT4_MASK (0x10U)
12903 #define DMA_INT_INT4_SHIFT (4U)
12904 
12908 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
12909 #define DMA_INT_INT5_MASK (0x20U)
12910 #define DMA_INT_INT5_SHIFT (5U)
12911 
12915 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
12916 #define DMA_INT_INT6_MASK (0x40U)
12917 #define DMA_INT_INT6_SHIFT (6U)
12918 
12922 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
12923 #define DMA_INT_INT7_MASK (0x80U)
12924 #define DMA_INT_INT7_SHIFT (7U)
12925 
12929 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
12930 #define DMA_INT_INT8_MASK (0x100U)
12931 #define DMA_INT_INT8_SHIFT (8U)
12932 
12936 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
12937 #define DMA_INT_INT9_MASK (0x200U)
12938 #define DMA_INT_INT9_SHIFT (9U)
12939 
12943 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
12944 #define DMA_INT_INT10_MASK (0x400U)
12945 #define DMA_INT_INT10_SHIFT (10U)
12946 
12950 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
12951 #define DMA_INT_INT11_MASK (0x800U)
12952 #define DMA_INT_INT11_SHIFT (11U)
12953 
12957 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
12958 #define DMA_INT_INT12_MASK (0x1000U)
12959 #define DMA_INT_INT12_SHIFT (12U)
12960 
12964 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
12965 #define DMA_INT_INT13_MASK (0x2000U)
12966 #define DMA_INT_INT13_SHIFT (13U)
12967 
12971 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
12972 #define DMA_INT_INT14_MASK (0x4000U)
12973 #define DMA_INT_INT14_SHIFT (14U)
12974 
12978 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
12979 #define DMA_INT_INT15_MASK (0x8000U)
12980 #define DMA_INT_INT15_SHIFT (15U)
12981 
12985 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
12986 #define DMA_INT_INT16_MASK (0x10000U)
12987 #define DMA_INT_INT16_SHIFT (16U)
12988 
12992 #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
12993 #define DMA_INT_INT17_MASK (0x20000U)
12994 #define DMA_INT_INT17_SHIFT (17U)
12995 
12999 #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
13000 #define DMA_INT_INT18_MASK (0x40000U)
13001 #define DMA_INT_INT18_SHIFT (18U)
13002 
13006 #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
13007 #define DMA_INT_INT19_MASK (0x80000U)
13008 #define DMA_INT_INT19_SHIFT (19U)
13009 
13013 #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
13014 #define DMA_INT_INT20_MASK (0x100000U)
13015 #define DMA_INT_INT20_SHIFT (20U)
13016 
13020 #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
13021 #define DMA_INT_INT21_MASK (0x200000U)
13022 #define DMA_INT_INT21_SHIFT (21U)
13023 
13027 #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
13028 #define DMA_INT_INT22_MASK (0x400000U)
13029 #define DMA_INT_INT22_SHIFT (22U)
13030 
13034 #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
13035 #define DMA_INT_INT23_MASK (0x800000U)
13036 #define DMA_INT_INT23_SHIFT (23U)
13037 
13041 #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
13042 #define DMA_INT_INT24_MASK (0x1000000U)
13043 #define DMA_INT_INT24_SHIFT (24U)
13044 
13048 #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
13049 #define DMA_INT_INT25_MASK (0x2000000U)
13050 #define DMA_INT_INT25_SHIFT (25U)
13051 
13055 #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
13056 #define DMA_INT_INT26_MASK (0x4000000U)
13057 #define DMA_INT_INT26_SHIFT (26U)
13058 
13062 #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
13063 #define DMA_INT_INT27_MASK (0x8000000U)
13064 #define DMA_INT_INT27_SHIFT (27U)
13065 
13069 #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
13070 #define DMA_INT_INT28_MASK (0x10000000U)
13071 #define DMA_INT_INT28_SHIFT (28U)
13072 
13076 #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
13077 #define DMA_INT_INT29_MASK (0x20000000U)
13078 #define DMA_INT_INT29_SHIFT (29U)
13079 
13083 #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
13084 #define DMA_INT_INT30_MASK (0x40000000U)
13085 #define DMA_INT_INT30_SHIFT (30U)
13086 
13090 #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
13091 #define DMA_INT_INT31_MASK (0x80000000U)
13092 #define DMA_INT_INT31_SHIFT (31U)
13093 
13097 #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
13098 
13102 #define DMA_ERR_ERR0_MASK (0x1U)
13103 #define DMA_ERR_ERR0_SHIFT (0U)
13104 
13108 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
13109 #define DMA_ERR_ERR1_MASK (0x2U)
13110 #define DMA_ERR_ERR1_SHIFT (1U)
13111 
13115 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
13116 #define DMA_ERR_ERR2_MASK (0x4U)
13117 #define DMA_ERR_ERR2_SHIFT (2U)
13118 
13122 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
13123 #define DMA_ERR_ERR3_MASK (0x8U)
13124 #define DMA_ERR_ERR3_SHIFT (3U)
13125 
13129 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
13130 #define DMA_ERR_ERR4_MASK (0x10U)
13131 #define DMA_ERR_ERR4_SHIFT (4U)
13132 
13136 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
13137 #define DMA_ERR_ERR5_MASK (0x20U)
13138 #define DMA_ERR_ERR5_SHIFT (5U)
13139 
13143 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
13144 #define DMA_ERR_ERR6_MASK (0x40U)
13145 #define DMA_ERR_ERR6_SHIFT (6U)
13146 
13150 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
13151 #define DMA_ERR_ERR7_MASK (0x80U)
13152 #define DMA_ERR_ERR7_SHIFT (7U)
13153 
13157 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
13158 #define DMA_ERR_ERR8_MASK (0x100U)
13159 #define DMA_ERR_ERR8_SHIFT (8U)
13160 
13164 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
13165 #define DMA_ERR_ERR9_MASK (0x200U)
13166 #define DMA_ERR_ERR9_SHIFT (9U)
13167 
13171 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
13172 #define DMA_ERR_ERR10_MASK (0x400U)
13173 #define DMA_ERR_ERR10_SHIFT (10U)
13174 
13178 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
13179 #define DMA_ERR_ERR11_MASK (0x800U)
13180 #define DMA_ERR_ERR11_SHIFT (11U)
13181 
13185 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
13186 #define DMA_ERR_ERR12_MASK (0x1000U)
13187 #define DMA_ERR_ERR12_SHIFT (12U)
13188 
13192 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
13193 #define DMA_ERR_ERR13_MASK (0x2000U)
13194 #define DMA_ERR_ERR13_SHIFT (13U)
13195 
13199 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
13200 #define DMA_ERR_ERR14_MASK (0x4000U)
13201 #define DMA_ERR_ERR14_SHIFT (14U)
13202 
13206 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
13207 #define DMA_ERR_ERR15_MASK (0x8000U)
13208 #define DMA_ERR_ERR15_SHIFT (15U)
13209 
13213 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
13214 #define DMA_ERR_ERR16_MASK (0x10000U)
13215 #define DMA_ERR_ERR16_SHIFT (16U)
13216 
13220 #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
13221 #define DMA_ERR_ERR17_MASK (0x20000U)
13222 #define DMA_ERR_ERR17_SHIFT (17U)
13223 
13227 #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
13228 #define DMA_ERR_ERR18_MASK (0x40000U)
13229 #define DMA_ERR_ERR18_SHIFT (18U)
13230 
13234 #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
13235 #define DMA_ERR_ERR19_MASK (0x80000U)
13236 #define DMA_ERR_ERR19_SHIFT (19U)
13237 
13241 #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
13242 #define DMA_ERR_ERR20_MASK (0x100000U)
13243 #define DMA_ERR_ERR20_SHIFT (20U)
13244 
13248 #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
13249 #define DMA_ERR_ERR21_MASK (0x200000U)
13250 #define DMA_ERR_ERR21_SHIFT (21U)
13251 
13255 #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
13256 #define DMA_ERR_ERR22_MASK (0x400000U)
13257 #define DMA_ERR_ERR22_SHIFT (22U)
13258 
13262 #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
13263 #define DMA_ERR_ERR23_MASK (0x800000U)
13264 #define DMA_ERR_ERR23_SHIFT (23U)
13265 
13269 #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
13270 #define DMA_ERR_ERR24_MASK (0x1000000U)
13271 #define DMA_ERR_ERR24_SHIFT (24U)
13272 
13276 #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
13277 #define DMA_ERR_ERR25_MASK (0x2000000U)
13278 #define DMA_ERR_ERR25_SHIFT (25U)
13279 
13283 #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
13284 #define DMA_ERR_ERR26_MASK (0x4000000U)
13285 #define DMA_ERR_ERR26_SHIFT (26U)
13286 
13290 #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
13291 #define DMA_ERR_ERR27_MASK (0x8000000U)
13292 #define DMA_ERR_ERR27_SHIFT (27U)
13293 
13297 #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
13298 #define DMA_ERR_ERR28_MASK (0x10000000U)
13299 #define DMA_ERR_ERR28_SHIFT (28U)
13300 
13304 #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
13305 #define DMA_ERR_ERR29_MASK (0x20000000U)
13306 #define DMA_ERR_ERR29_SHIFT (29U)
13307 
13311 #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
13312 #define DMA_ERR_ERR30_MASK (0x40000000U)
13313 #define DMA_ERR_ERR30_SHIFT (30U)
13314 
13318 #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
13319 #define DMA_ERR_ERR31_MASK (0x80000000U)
13320 #define DMA_ERR_ERR31_SHIFT (31U)
13321 
13325 #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
13326 
13330 #define DMA_HRS_HRS0_MASK (0x1U)
13331 #define DMA_HRS_HRS0_SHIFT (0U)
13332 
13336 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
13337 #define DMA_HRS_HRS1_MASK (0x2U)
13338 #define DMA_HRS_HRS1_SHIFT (1U)
13339 
13343 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
13344 #define DMA_HRS_HRS2_MASK (0x4U)
13345 #define DMA_HRS_HRS2_SHIFT (2U)
13346 
13350 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
13351 #define DMA_HRS_HRS3_MASK (0x8U)
13352 #define DMA_HRS_HRS3_SHIFT (3U)
13353 
13357 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
13358 #define DMA_HRS_HRS4_MASK (0x10U)
13359 #define DMA_HRS_HRS4_SHIFT (4U)
13360 
13364 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
13365 #define DMA_HRS_HRS5_MASK (0x20U)
13366 #define DMA_HRS_HRS5_SHIFT (5U)
13367 
13371 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
13372 #define DMA_HRS_HRS6_MASK (0x40U)
13373 #define DMA_HRS_HRS6_SHIFT (6U)
13374 
13378 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
13379 #define DMA_HRS_HRS7_MASK (0x80U)
13380 #define DMA_HRS_HRS7_SHIFT (7U)
13381 
13385 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
13386 #define DMA_HRS_HRS8_MASK (0x100U)
13387 #define DMA_HRS_HRS8_SHIFT (8U)
13388 
13392 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
13393 #define DMA_HRS_HRS9_MASK (0x200U)
13394 #define DMA_HRS_HRS9_SHIFT (9U)
13395 
13399 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
13400 #define DMA_HRS_HRS10_MASK (0x400U)
13401 #define DMA_HRS_HRS10_SHIFT (10U)
13402 
13406 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
13407 #define DMA_HRS_HRS11_MASK (0x800U)
13408 #define DMA_HRS_HRS11_SHIFT (11U)
13409 
13413 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
13414 #define DMA_HRS_HRS12_MASK (0x1000U)
13415 #define DMA_HRS_HRS12_SHIFT (12U)
13416 
13420 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
13421 #define DMA_HRS_HRS13_MASK (0x2000U)
13422 #define DMA_HRS_HRS13_SHIFT (13U)
13423 
13427 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
13428 #define DMA_HRS_HRS14_MASK (0x4000U)
13429 #define DMA_HRS_HRS14_SHIFT (14U)
13430 
13434 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
13435 #define DMA_HRS_HRS15_MASK (0x8000U)
13436 #define DMA_HRS_HRS15_SHIFT (15U)
13437 
13441 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
13442 #define DMA_HRS_HRS16_MASK (0x10000U)
13443 #define DMA_HRS_HRS16_SHIFT (16U)
13444 
13448 #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
13449 #define DMA_HRS_HRS17_MASK (0x20000U)
13450 #define DMA_HRS_HRS17_SHIFT (17U)
13451 
13455 #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
13456 #define DMA_HRS_HRS18_MASK (0x40000U)
13457 #define DMA_HRS_HRS18_SHIFT (18U)
13458 
13462 #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
13463 #define DMA_HRS_HRS19_MASK (0x80000U)
13464 #define DMA_HRS_HRS19_SHIFT (19U)
13465 
13469 #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
13470 #define DMA_HRS_HRS20_MASK (0x100000U)
13471 #define DMA_HRS_HRS20_SHIFT (20U)
13472 
13476 #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
13477 #define DMA_HRS_HRS21_MASK (0x200000U)
13478 #define DMA_HRS_HRS21_SHIFT (21U)
13479 
13483 #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
13484 #define DMA_HRS_HRS22_MASK (0x400000U)
13485 #define DMA_HRS_HRS22_SHIFT (22U)
13486 
13490 #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
13491 #define DMA_HRS_HRS23_MASK (0x800000U)
13492 #define DMA_HRS_HRS23_SHIFT (23U)
13493 
13497 #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
13498 #define DMA_HRS_HRS24_MASK (0x1000000U)
13499 #define DMA_HRS_HRS24_SHIFT (24U)
13500 
13504 #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
13505 #define DMA_HRS_HRS25_MASK (0x2000000U)
13506 #define DMA_HRS_HRS25_SHIFT (25U)
13507 
13511 #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
13512 #define DMA_HRS_HRS26_MASK (0x4000000U)
13513 #define DMA_HRS_HRS26_SHIFT (26U)
13514 
13518 #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
13519 #define DMA_HRS_HRS27_MASK (0x8000000U)
13520 #define DMA_HRS_HRS27_SHIFT (27U)
13521 
13525 #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
13526 #define DMA_HRS_HRS28_MASK (0x10000000U)
13527 #define DMA_HRS_HRS28_SHIFT (28U)
13528 
13532 #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
13533 #define DMA_HRS_HRS29_MASK (0x20000000U)
13534 #define DMA_HRS_HRS29_SHIFT (29U)
13535 
13539 #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
13540 #define DMA_HRS_HRS30_MASK (0x40000000U)
13541 #define DMA_HRS_HRS30_SHIFT (30U)
13542 
13546 #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
13547 #define DMA_HRS_HRS31_MASK (0x80000000U)
13548 #define DMA_HRS_HRS31_SHIFT (31U)
13549 
13553 #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
13554 
13558 #define DMA_EARS_EDREQ_0_MASK (0x1U)
13559 #define DMA_EARS_EDREQ_0_SHIFT (0U)
13560 
13564 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
13565 #define DMA_EARS_EDREQ_1_MASK (0x2U)
13566 #define DMA_EARS_EDREQ_1_SHIFT (1U)
13567 
13571 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
13572 #define DMA_EARS_EDREQ_2_MASK (0x4U)
13573 #define DMA_EARS_EDREQ_2_SHIFT (2U)
13574 
13578 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
13579 #define DMA_EARS_EDREQ_3_MASK (0x8U)
13580 #define DMA_EARS_EDREQ_3_SHIFT (3U)
13581 
13585 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
13586 #define DMA_EARS_EDREQ_4_MASK (0x10U)
13587 #define DMA_EARS_EDREQ_4_SHIFT (4U)
13588 
13592 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
13593 #define DMA_EARS_EDREQ_5_MASK (0x20U)
13594 #define DMA_EARS_EDREQ_5_SHIFT (5U)
13595 
13599 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
13600 #define DMA_EARS_EDREQ_6_MASK (0x40U)
13601 #define DMA_EARS_EDREQ_6_SHIFT (6U)
13602 
13606 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
13607 #define DMA_EARS_EDREQ_7_MASK (0x80U)
13608 #define DMA_EARS_EDREQ_7_SHIFT (7U)
13609 
13613 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
13614 #define DMA_EARS_EDREQ_8_MASK (0x100U)
13615 #define DMA_EARS_EDREQ_8_SHIFT (8U)
13616 
13620 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
13621 #define DMA_EARS_EDREQ_9_MASK (0x200U)
13622 #define DMA_EARS_EDREQ_9_SHIFT (9U)
13623 
13627 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
13628 #define DMA_EARS_EDREQ_10_MASK (0x400U)
13629 #define DMA_EARS_EDREQ_10_SHIFT (10U)
13630 
13634 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
13635 #define DMA_EARS_EDREQ_11_MASK (0x800U)
13636 #define DMA_EARS_EDREQ_11_SHIFT (11U)
13637 
13641 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
13642 #define DMA_EARS_EDREQ_12_MASK (0x1000U)
13643 #define DMA_EARS_EDREQ_12_SHIFT (12U)
13644 
13648 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
13649 #define DMA_EARS_EDREQ_13_MASK (0x2000U)
13650 #define DMA_EARS_EDREQ_13_SHIFT (13U)
13651 
13655 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
13656 #define DMA_EARS_EDREQ_14_MASK (0x4000U)
13657 #define DMA_EARS_EDREQ_14_SHIFT (14U)
13658 
13662 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
13663 #define DMA_EARS_EDREQ_15_MASK (0x8000U)
13664 #define DMA_EARS_EDREQ_15_SHIFT (15U)
13665 
13669 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
13670 #define DMA_EARS_EDREQ_16_MASK (0x10000U)
13671 #define DMA_EARS_EDREQ_16_SHIFT (16U)
13672 
13676 #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
13677 #define DMA_EARS_EDREQ_17_MASK (0x20000U)
13678 #define DMA_EARS_EDREQ_17_SHIFT (17U)
13679 
13683 #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
13684 #define DMA_EARS_EDREQ_18_MASK (0x40000U)
13685 #define DMA_EARS_EDREQ_18_SHIFT (18U)
13686 
13690 #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
13691 #define DMA_EARS_EDREQ_19_MASK (0x80000U)
13692 #define DMA_EARS_EDREQ_19_SHIFT (19U)
13693 
13697 #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
13698 #define DMA_EARS_EDREQ_20_MASK (0x100000U)
13699 #define DMA_EARS_EDREQ_20_SHIFT (20U)
13700 
13704 #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
13705 #define DMA_EARS_EDREQ_21_MASK (0x200000U)
13706 #define DMA_EARS_EDREQ_21_SHIFT (21U)
13707 
13711 #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
13712 #define DMA_EARS_EDREQ_22_MASK (0x400000U)
13713 #define DMA_EARS_EDREQ_22_SHIFT (22U)
13714 
13718 #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
13719 #define DMA_EARS_EDREQ_23_MASK (0x800000U)
13720 #define DMA_EARS_EDREQ_23_SHIFT (23U)
13721 
13725 #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
13726 #define DMA_EARS_EDREQ_24_MASK (0x1000000U)
13727 #define DMA_EARS_EDREQ_24_SHIFT (24U)
13728 
13732 #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
13733 #define DMA_EARS_EDREQ_25_MASK (0x2000000U)
13734 #define DMA_EARS_EDREQ_25_SHIFT (25U)
13735 
13739 #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
13740 #define DMA_EARS_EDREQ_26_MASK (0x4000000U)
13741 #define DMA_EARS_EDREQ_26_SHIFT (26U)
13742 
13746 #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
13747 #define DMA_EARS_EDREQ_27_MASK (0x8000000U)
13748 #define DMA_EARS_EDREQ_27_SHIFT (27U)
13749 
13753 #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
13754 #define DMA_EARS_EDREQ_28_MASK (0x10000000U)
13755 #define DMA_EARS_EDREQ_28_SHIFT (28U)
13756 
13760 #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
13761 #define DMA_EARS_EDREQ_29_MASK (0x20000000U)
13762 #define DMA_EARS_EDREQ_29_SHIFT (29U)
13763 
13767 #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
13768 #define DMA_EARS_EDREQ_30_MASK (0x40000000U)
13769 #define DMA_EARS_EDREQ_30_SHIFT (30U)
13770 
13774 #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
13775 #define DMA_EARS_EDREQ_31_MASK (0x80000000U)
13776 #define DMA_EARS_EDREQ_31_SHIFT (31U)
13777 
13781 #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
13782 
13786 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
13787 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
13788 
13790 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
13791 #define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
13792 #define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
13793 
13795 #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
13796 #define DMA_DCHPRI3_DPA_MASK (0x40U)
13797 #define DMA_DCHPRI3_DPA_SHIFT (6U)
13798 
13802 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
13803 #define DMA_DCHPRI3_ECP_MASK (0x80U)
13804 #define DMA_DCHPRI3_ECP_SHIFT (7U)
13805 
13809 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
13810 
13814 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
13815 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
13816 
13818 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
13819 #define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
13820 #define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
13821 
13823 #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
13824 #define DMA_DCHPRI2_DPA_MASK (0x40U)
13825 #define DMA_DCHPRI2_DPA_SHIFT (6U)
13826 
13830 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
13831 #define DMA_DCHPRI2_ECP_MASK (0x80U)
13832 #define DMA_DCHPRI2_ECP_SHIFT (7U)
13833 
13837 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
13838 
13842 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
13843 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
13844 
13846 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
13847 #define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
13848 #define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
13849 
13851 #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
13852 #define DMA_DCHPRI1_DPA_MASK (0x40U)
13853 #define DMA_DCHPRI1_DPA_SHIFT (6U)
13854 
13858 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
13859 #define DMA_DCHPRI1_ECP_MASK (0x80U)
13860 #define DMA_DCHPRI1_ECP_SHIFT (7U)
13861 
13865 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
13866 
13870 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
13871 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
13872 
13874 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
13875 #define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
13876 #define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
13877 
13879 #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
13880 #define DMA_DCHPRI0_DPA_MASK (0x40U)
13881 #define DMA_DCHPRI0_DPA_SHIFT (6U)
13882 
13886 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
13887 #define DMA_DCHPRI0_ECP_MASK (0x80U)
13888 #define DMA_DCHPRI0_ECP_SHIFT (7U)
13889 
13893 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
13894 
13898 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
13899 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
13900 
13902 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
13903 #define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
13904 #define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
13905 
13907 #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
13908 #define DMA_DCHPRI7_DPA_MASK (0x40U)
13909 #define DMA_DCHPRI7_DPA_SHIFT (6U)
13910 
13914 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
13915 #define DMA_DCHPRI7_ECP_MASK (0x80U)
13916 #define DMA_DCHPRI7_ECP_SHIFT (7U)
13917 
13921 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
13922 
13926 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
13927 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
13928 
13930 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
13931 #define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
13932 #define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
13933 
13935 #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
13936 #define DMA_DCHPRI6_DPA_MASK (0x40U)
13937 #define DMA_DCHPRI6_DPA_SHIFT (6U)
13938 
13942 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
13943 #define DMA_DCHPRI6_ECP_MASK (0x80U)
13944 #define DMA_DCHPRI6_ECP_SHIFT (7U)
13945 
13949 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
13950 
13954 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
13955 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
13956 
13958 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
13959 #define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
13960 #define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
13961 
13963 #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
13964 #define DMA_DCHPRI5_DPA_MASK (0x40U)
13965 #define DMA_DCHPRI5_DPA_SHIFT (6U)
13966 
13970 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
13971 #define DMA_DCHPRI5_ECP_MASK (0x80U)
13972 #define DMA_DCHPRI5_ECP_SHIFT (7U)
13973 
13977 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
13978 
13982 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
13983 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
13984 
13986 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
13987 #define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
13988 #define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
13989 
13991 #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
13992 #define DMA_DCHPRI4_DPA_MASK (0x40U)
13993 #define DMA_DCHPRI4_DPA_SHIFT (6U)
13994 
13998 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
13999 #define DMA_DCHPRI4_ECP_MASK (0x80U)
14000 #define DMA_DCHPRI4_ECP_SHIFT (7U)
14001 
14005 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
14006 
14010 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
14011 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
14012 
14014 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
14015 #define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
14016 #define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
14017 
14019 #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
14020 #define DMA_DCHPRI11_DPA_MASK (0x40U)
14021 #define DMA_DCHPRI11_DPA_SHIFT (6U)
14022 
14026 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
14027 #define DMA_DCHPRI11_ECP_MASK (0x80U)
14028 #define DMA_DCHPRI11_ECP_SHIFT (7U)
14029 
14033 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
14034 
14038 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
14039 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
14040 
14042 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
14043 #define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
14044 #define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
14045 
14047 #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
14048 #define DMA_DCHPRI10_DPA_MASK (0x40U)
14049 #define DMA_DCHPRI10_DPA_SHIFT (6U)
14050 
14054 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
14055 #define DMA_DCHPRI10_ECP_MASK (0x80U)
14056 #define DMA_DCHPRI10_ECP_SHIFT (7U)
14057 
14061 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
14062 
14066 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
14067 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
14068 
14070 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
14071 #define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
14072 #define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
14073 
14075 #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
14076 #define DMA_DCHPRI9_DPA_MASK (0x40U)
14077 #define DMA_DCHPRI9_DPA_SHIFT (6U)
14078 
14082 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
14083 #define DMA_DCHPRI9_ECP_MASK (0x80U)
14084 #define DMA_DCHPRI9_ECP_SHIFT (7U)
14085 
14089 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
14090 
14094 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
14095 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
14096 
14098 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
14099 #define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
14100 #define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
14101 
14103 #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
14104 #define DMA_DCHPRI8_DPA_MASK (0x40U)
14105 #define DMA_DCHPRI8_DPA_SHIFT (6U)
14106 
14110 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
14111 #define DMA_DCHPRI8_ECP_MASK (0x80U)
14112 #define DMA_DCHPRI8_ECP_SHIFT (7U)
14113 
14117 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
14118 
14122 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
14123 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
14124 
14126 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
14127 #define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
14128 #define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
14129 
14131 #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
14132 #define DMA_DCHPRI15_DPA_MASK (0x40U)
14133 #define DMA_DCHPRI15_DPA_SHIFT (6U)
14134 
14138 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
14139 #define DMA_DCHPRI15_ECP_MASK (0x80U)
14140 #define DMA_DCHPRI15_ECP_SHIFT (7U)
14141 
14145 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
14146 
14150 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
14151 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
14152 
14154 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
14155 #define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
14156 #define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
14157 
14159 #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
14160 #define DMA_DCHPRI14_DPA_MASK (0x40U)
14161 #define DMA_DCHPRI14_DPA_SHIFT (6U)
14162 
14166 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
14167 #define DMA_DCHPRI14_ECP_MASK (0x80U)
14168 #define DMA_DCHPRI14_ECP_SHIFT (7U)
14169 
14173 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
14174 
14178 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
14179 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
14180 
14182 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
14183 #define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
14184 #define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
14185 
14187 #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
14188 #define DMA_DCHPRI13_DPA_MASK (0x40U)
14189 #define DMA_DCHPRI13_DPA_SHIFT (6U)
14190 
14194 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
14195 #define DMA_DCHPRI13_ECP_MASK (0x80U)
14196 #define DMA_DCHPRI13_ECP_SHIFT (7U)
14197 
14201 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
14202 
14206 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
14207 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
14208 
14210 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
14211 #define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
14212 #define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
14213 
14215 #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
14216 #define DMA_DCHPRI12_DPA_MASK (0x40U)
14217 #define DMA_DCHPRI12_DPA_SHIFT (6U)
14218 
14222 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
14223 #define DMA_DCHPRI12_ECP_MASK (0x80U)
14224 #define DMA_DCHPRI12_ECP_SHIFT (7U)
14225 
14229 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
14230 
14234 #define DMA_DCHPRI19_CHPRI_MASK (0xFU)
14235 #define DMA_DCHPRI19_CHPRI_SHIFT (0U)
14236 
14238 #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
14239 #define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
14240 #define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
14241 
14243 #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
14244 #define DMA_DCHPRI19_DPA_MASK (0x40U)
14245 #define DMA_DCHPRI19_DPA_SHIFT (6U)
14246 
14250 #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
14251 #define DMA_DCHPRI19_ECP_MASK (0x80U)
14252 #define DMA_DCHPRI19_ECP_SHIFT (7U)
14253 
14257 #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
14258 
14262 #define DMA_DCHPRI18_CHPRI_MASK (0xFU)
14263 #define DMA_DCHPRI18_CHPRI_SHIFT (0U)
14264 
14266 #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
14267 #define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
14268 #define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
14269 
14271 #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
14272 #define DMA_DCHPRI18_DPA_MASK (0x40U)
14273 #define DMA_DCHPRI18_DPA_SHIFT (6U)
14274 
14278 #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
14279 #define DMA_DCHPRI18_ECP_MASK (0x80U)
14280 #define DMA_DCHPRI18_ECP_SHIFT (7U)
14281 
14285 #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
14286 
14290 #define DMA_DCHPRI17_CHPRI_MASK (0xFU)
14291 #define DMA_DCHPRI17_CHPRI_SHIFT (0U)
14292 
14294 #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
14295 #define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
14296 #define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
14297 
14299 #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
14300 #define DMA_DCHPRI17_DPA_MASK (0x40U)
14301 #define DMA_DCHPRI17_DPA_SHIFT (6U)
14302 
14306 #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
14307 #define DMA_DCHPRI17_ECP_MASK (0x80U)
14308 #define DMA_DCHPRI17_ECP_SHIFT (7U)
14309 
14313 #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
14314 
14318 #define DMA_DCHPRI16_CHPRI_MASK (0xFU)
14319 #define DMA_DCHPRI16_CHPRI_SHIFT (0U)
14320 
14322 #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
14323 #define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
14324 #define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
14325 
14327 #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
14328 #define DMA_DCHPRI16_DPA_MASK (0x40U)
14329 #define DMA_DCHPRI16_DPA_SHIFT (6U)
14330 
14334 #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
14335 #define DMA_DCHPRI16_ECP_MASK (0x80U)
14336 #define DMA_DCHPRI16_ECP_SHIFT (7U)
14337 
14341 #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
14342 
14346 #define DMA_DCHPRI23_CHPRI_MASK (0xFU)
14347 #define DMA_DCHPRI23_CHPRI_SHIFT (0U)
14348 
14350 #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
14351 #define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
14352 #define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
14353 
14355 #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
14356 #define DMA_DCHPRI23_DPA_MASK (0x40U)
14357 #define DMA_DCHPRI23_DPA_SHIFT (6U)
14358 
14362 #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
14363 #define DMA_DCHPRI23_ECP_MASK (0x80U)
14364 #define DMA_DCHPRI23_ECP_SHIFT (7U)
14365 
14369 #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
14370 
14374 #define DMA_DCHPRI22_CHPRI_MASK (0xFU)
14375 #define DMA_DCHPRI22_CHPRI_SHIFT (0U)
14376 
14378 #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
14379 #define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
14380 #define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
14381 
14383 #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
14384 #define DMA_DCHPRI22_DPA_MASK (0x40U)
14385 #define DMA_DCHPRI22_DPA_SHIFT (6U)
14386 
14390 #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
14391 #define DMA_DCHPRI22_ECP_MASK (0x80U)
14392 #define DMA_DCHPRI22_ECP_SHIFT (7U)
14393 
14397 #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
14398 
14402 #define DMA_DCHPRI21_CHPRI_MASK (0xFU)
14403 #define DMA_DCHPRI21_CHPRI_SHIFT (0U)
14404 
14406 #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
14407 #define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
14408 #define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
14409 
14411 #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
14412 #define DMA_DCHPRI21_DPA_MASK (0x40U)
14413 #define DMA_DCHPRI21_DPA_SHIFT (6U)
14414 
14418 #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
14419 #define DMA_DCHPRI21_ECP_MASK (0x80U)
14420 #define DMA_DCHPRI21_ECP_SHIFT (7U)
14421 
14425 #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
14426 
14430 #define DMA_DCHPRI20_CHPRI_MASK (0xFU)
14431 #define DMA_DCHPRI20_CHPRI_SHIFT (0U)
14432 
14434 #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
14435 #define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
14436 #define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
14437 
14439 #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
14440 #define DMA_DCHPRI20_DPA_MASK (0x40U)
14441 #define DMA_DCHPRI20_DPA_SHIFT (6U)
14442 
14446 #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
14447 #define DMA_DCHPRI20_ECP_MASK (0x80U)
14448 #define DMA_DCHPRI20_ECP_SHIFT (7U)
14449 
14453 #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
14454 
14458 #define DMA_DCHPRI27_CHPRI_MASK (0xFU)
14459 #define DMA_DCHPRI27_CHPRI_SHIFT (0U)
14460 
14462 #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
14463 #define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
14464 #define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
14465 
14467 #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
14468 #define DMA_DCHPRI27_DPA_MASK (0x40U)
14469 #define DMA_DCHPRI27_DPA_SHIFT (6U)
14470 
14474 #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
14475 #define DMA_DCHPRI27_ECP_MASK (0x80U)
14476 #define DMA_DCHPRI27_ECP_SHIFT (7U)
14477 
14481 #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
14482 
14486 #define DMA_DCHPRI26_CHPRI_MASK (0xFU)
14487 #define DMA_DCHPRI26_CHPRI_SHIFT (0U)
14488 
14490 #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
14491 #define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
14492 #define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
14493 
14495 #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
14496 #define DMA_DCHPRI26_DPA_MASK (0x40U)
14497 #define DMA_DCHPRI26_DPA_SHIFT (6U)
14498 
14502 #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
14503 #define DMA_DCHPRI26_ECP_MASK (0x80U)
14504 #define DMA_DCHPRI26_ECP_SHIFT (7U)
14505 
14509 #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
14510 
14514 #define DMA_DCHPRI25_CHPRI_MASK (0xFU)
14515 #define DMA_DCHPRI25_CHPRI_SHIFT (0U)
14516 
14518 #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
14519 #define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
14520 #define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
14521 
14523 #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
14524 #define DMA_DCHPRI25_DPA_MASK (0x40U)
14525 #define DMA_DCHPRI25_DPA_SHIFT (6U)
14526 
14530 #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
14531 #define DMA_DCHPRI25_ECP_MASK (0x80U)
14532 #define DMA_DCHPRI25_ECP_SHIFT (7U)
14533 
14537 #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
14538 
14542 #define DMA_DCHPRI24_CHPRI_MASK (0xFU)
14543 #define DMA_DCHPRI24_CHPRI_SHIFT (0U)
14544 
14546 #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
14547 #define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
14548 #define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
14549 
14551 #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
14552 #define DMA_DCHPRI24_DPA_MASK (0x40U)
14553 #define DMA_DCHPRI24_DPA_SHIFT (6U)
14554 
14558 #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
14559 #define DMA_DCHPRI24_ECP_MASK (0x80U)
14560 #define DMA_DCHPRI24_ECP_SHIFT (7U)
14561 
14565 #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
14566 
14570 #define DMA_DCHPRI31_CHPRI_MASK (0xFU)
14571 #define DMA_DCHPRI31_CHPRI_SHIFT (0U)
14572 
14574 #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
14575 #define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
14576 #define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
14577 
14579 #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
14580 #define DMA_DCHPRI31_DPA_MASK (0x40U)
14581 #define DMA_DCHPRI31_DPA_SHIFT (6U)
14582 
14586 #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
14587 #define DMA_DCHPRI31_ECP_MASK (0x80U)
14588 #define DMA_DCHPRI31_ECP_SHIFT (7U)
14589 
14593 #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
14594 
14598 #define DMA_DCHPRI30_CHPRI_MASK (0xFU)
14599 #define DMA_DCHPRI30_CHPRI_SHIFT (0U)
14600 
14602 #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
14603 #define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
14604 #define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
14605 
14607 #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
14608 #define DMA_DCHPRI30_DPA_MASK (0x40U)
14609 #define DMA_DCHPRI30_DPA_SHIFT (6U)
14610 
14614 #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
14615 #define DMA_DCHPRI30_ECP_MASK (0x80U)
14616 #define DMA_DCHPRI30_ECP_SHIFT (7U)
14617 
14621 #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
14622 
14626 #define DMA_DCHPRI29_CHPRI_MASK (0xFU)
14627 #define DMA_DCHPRI29_CHPRI_SHIFT (0U)
14628 
14630 #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
14631 #define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
14632 #define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
14633 
14635 #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
14636 #define DMA_DCHPRI29_DPA_MASK (0x40U)
14637 #define DMA_DCHPRI29_DPA_SHIFT (6U)
14638 
14642 #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
14643 #define DMA_DCHPRI29_ECP_MASK (0x80U)
14644 #define DMA_DCHPRI29_ECP_SHIFT (7U)
14645 
14649 #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
14650 
14654 #define DMA_DCHPRI28_CHPRI_MASK (0xFU)
14655 #define DMA_DCHPRI28_CHPRI_SHIFT (0U)
14656 
14658 #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
14659 #define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
14660 #define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
14661 
14663 #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
14664 #define DMA_DCHPRI28_DPA_MASK (0x40U)
14665 #define DMA_DCHPRI28_DPA_SHIFT (6U)
14666 
14670 #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
14671 #define DMA_DCHPRI28_ECP_MASK (0x80U)
14672 #define DMA_DCHPRI28_ECP_SHIFT (7U)
14673 
14677 #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
14678 
14682 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
14683 #define DMA_SADDR_SADDR_SHIFT (0U)
14684 
14686 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
14687 
14689 /* The count of DMA_SADDR */
14690 #define DMA_SADDR_COUNT (32U)
14691 
14694 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
14695 #define DMA_SOFF_SOFF_SHIFT (0U)
14696 
14698 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
14699 
14701 /* The count of DMA_SOFF */
14702 #define DMA_SOFF_COUNT (32U)
14703 
14706 #define DMA_ATTR_DSIZE_MASK (0x7U)
14707 #define DMA_ATTR_DSIZE_SHIFT (0U)
14708 
14710 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
14711 #define DMA_ATTR_DMOD_MASK (0xF8U)
14712 #define DMA_ATTR_DMOD_SHIFT (3U)
14713 
14715 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
14716 #define DMA_ATTR_SSIZE_MASK (0x700U)
14717 #define DMA_ATTR_SSIZE_SHIFT (8U)
14718 
14728 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
14729 #define DMA_ATTR_SMOD_MASK (0xF800U)
14730 #define DMA_ATTR_SMOD_SHIFT (11U)
14731 
14742 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
14743 
14745 /* The count of DMA_ATTR */
14746 #define DMA_ATTR_COUNT (32U)
14747 
14750 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
14751 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
14752 
14754 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
14755 
14757 /* The count of DMA_NBYTES_MLNO */
14758 #define DMA_NBYTES_MLNO_COUNT (32U)
14759 
14762 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
14763 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
14764 
14766 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
14767 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
14768 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
14769 
14773 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
14774 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
14775 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
14776 
14780 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
14781 
14783 /* The count of DMA_NBYTES_MLOFFNO */
14784 #define DMA_NBYTES_MLOFFNO_COUNT (32U)
14785 
14788 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
14789 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
14790 
14792 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
14793 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
14794 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
14795 
14798 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
14799 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
14800 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
14801 
14805 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
14806 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
14807 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
14808 
14812 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
14813 
14815 /* The count of DMA_NBYTES_MLOFFYES */
14816 #define DMA_NBYTES_MLOFFYES_COUNT (32U)
14817 
14820 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
14821 #define DMA_SLAST_SLAST_SHIFT (0U)
14822 
14824 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
14825 
14827 /* The count of DMA_SLAST */
14828 #define DMA_SLAST_COUNT (32U)
14829 
14832 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
14833 #define DMA_DADDR_DADDR_SHIFT (0U)
14834 
14836 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
14837 
14839 /* The count of DMA_DADDR */
14840 #define DMA_DADDR_COUNT (32U)
14841 
14844 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
14845 #define DMA_DOFF_DOFF_SHIFT (0U)
14846 
14848 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
14849 
14851 /* The count of DMA_DOFF */
14852 #define DMA_DOFF_COUNT (32U)
14853 
14856 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
14857 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
14858 
14860 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
14861 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
14862 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
14863 
14867 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
14868 
14870 /* The count of DMA_CITER_ELINKNO */
14871 #define DMA_CITER_ELINKNO_COUNT (32U)
14872 
14875 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
14876 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
14877 
14879 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
14880 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
14881 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
14882 
14884 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
14885 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
14886 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
14887 
14891 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
14892 
14894 /* The count of DMA_CITER_ELINKYES */
14895 #define DMA_CITER_ELINKYES_COUNT (32U)
14896 
14899 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
14900 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
14901 
14903 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
14904 
14906 /* The count of DMA_DLAST_SGA */
14907 #define DMA_DLAST_SGA_COUNT (32U)
14908 
14911 #define DMA_CSR_START_MASK (0x1U)
14912 #define DMA_CSR_START_SHIFT (0U)
14913 
14917 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
14918 #define DMA_CSR_INTMAJOR_MASK (0x2U)
14919 #define DMA_CSR_INTMAJOR_SHIFT (1U)
14920 
14924 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
14925 #define DMA_CSR_INTHALF_MASK (0x4U)
14926 #define DMA_CSR_INTHALF_SHIFT (2U)
14927 
14931 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
14932 #define DMA_CSR_DREQ_MASK (0x8U)
14933 #define DMA_CSR_DREQ_SHIFT (3U)
14934 
14938 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
14939 #define DMA_CSR_ESG_MASK (0x10U)
14940 #define DMA_CSR_ESG_SHIFT (4U)
14941 
14946 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
14947 #define DMA_CSR_MAJORELINK_MASK (0x20U)
14948 #define DMA_CSR_MAJORELINK_SHIFT (5U)
14949 
14953 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
14954 #define DMA_CSR_ACTIVE_MASK (0x40U)
14955 #define DMA_CSR_ACTIVE_SHIFT (6U)
14956 
14958 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
14959 #define DMA_CSR_DONE_MASK (0x80U)
14960 #define DMA_CSR_DONE_SHIFT (7U)
14961 
14963 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
14964 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
14965 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
14966 
14968 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
14969 #define DMA_CSR_BWC_MASK (0xC000U)
14970 #define DMA_CSR_BWC_SHIFT (14U)
14971 
14977 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
14978 
14980 /* The count of DMA_CSR */
14981 #define DMA_CSR_COUNT (32U)
14982 
14985 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
14986 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
14987 
14989 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
14990 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
14991 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
14992 
14996 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
14997 
14999 /* The count of DMA_BITER_ELINKNO */
15000 #define DMA_BITER_ELINKNO_COUNT (32U)
15001 
15004 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
15005 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
15006 
15008 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
15009 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
15010 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
15011 
15013 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
15014 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
15015 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
15016 
15020 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
15021 
15023 /* The count of DMA_BITER_ELINKYES */
15024 #define DMA_BITER_ELINKYES_COUNT (32U)
15025 
15026  /* end of group DMA_Register_Masks */
15030 
15031 
15032 /* DMA - Peripheral instance base addresses */
15034 #define DMA0_BASE (0x400E8000u)
15035 
15036 #define DMA0 ((DMA_Type *)DMA0_BASE)
15037 
15038 #define DMA_BASE_ADDRS { DMA0_BASE }
15039 
15040 #define DMA_BASE_PTRS { DMA0 }
15041 
15042 #define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
15043 #define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
15044  /* end of group DMA_Peripheral_Access_Layer */
15048 
15049 
15050 /* ----------------------------------------------------------------------------
15051  -- DMAMUX Peripheral Access Layer
15052  ---------------------------------------------------------------------------- */
15053 
15060 typedef struct {
15061  __IO uint32_t CHCFG[32];
15062 } DMAMUX_Type;
15063 
15064 /* ----------------------------------------------------------------------------
15065  -- DMAMUX Register Masks
15066  ---------------------------------------------------------------------------- */
15067 
15075 #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
15076 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
15077 
15079 #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
15080 #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
15081 #define DMAMUX_CHCFG_A_ON_SHIFT (29U)
15082 
15086 #define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
15087 #define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
15088 #define DMAMUX_CHCFG_TRIG_SHIFT (30U)
15089 
15094 #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
15095 #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
15096 #define DMAMUX_CHCFG_ENBL_SHIFT (31U)
15097 
15101 #define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
15102 
15104 /* The count of DMAMUX_CHCFG */
15105 #define DMAMUX_CHCFG_COUNT (32U)
15106 
15107  /* end of group DMAMUX_Register_Masks */
15111 
15112 
15113 /* DMAMUX - Peripheral instance base addresses */
15115 #define DMAMUX_BASE (0x400EC000u)
15116 
15117 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
15118 
15119 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
15120 
15121 #define DMAMUX_BASE_PTRS { DMAMUX }
15122  /* end of group DMAMUX_Peripheral_Access_Layer */
15126 
15127 
15128 /* ----------------------------------------------------------------------------
15129  -- ENC Peripheral Access Layer
15130  ---------------------------------------------------------------------------- */
15131 
15138 typedef struct {
15139  __IO uint16_t CTRL;
15140  __IO uint16_t FILT;
15141  __IO uint16_t WTR;
15142  __IO uint16_t POSD;
15143  __I uint16_t POSDH;
15144  __IO uint16_t REV;
15145  __I uint16_t REVH;
15146  __IO uint16_t UPOS;
15147  __IO uint16_t LPOS;
15148  __I uint16_t UPOSH;
15149  __I uint16_t LPOSH;
15150  __IO uint16_t UINIT;
15151  __IO uint16_t LINIT;
15152  __I uint16_t IMR;
15153  __IO uint16_t TST;
15154  __IO uint16_t CTRL2;
15155  __IO uint16_t UMOD;
15156  __IO uint16_t LMOD;
15157  __IO uint16_t UCOMP;
15158  __IO uint16_t LCOMP;
15159 } ENC_Type;
15160 
15161 /* ----------------------------------------------------------------------------
15162  -- ENC Register Masks
15163  ---------------------------------------------------------------------------- */
15164 
15172 #define ENC_CTRL_CMPIE_MASK (0x1U)
15173 #define ENC_CTRL_CMPIE_SHIFT (0U)
15174 
15178 #define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
15179 #define ENC_CTRL_CMPIRQ_MASK (0x2U)
15180 #define ENC_CTRL_CMPIRQ_SHIFT (1U)
15181 
15185 #define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
15186 #define ENC_CTRL_WDE_MASK (0x4U)
15187 #define ENC_CTRL_WDE_SHIFT (2U)
15188 
15192 #define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
15193 #define ENC_CTRL_DIE_MASK (0x8U)
15194 #define ENC_CTRL_DIE_SHIFT (3U)
15195 
15199 #define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
15200 #define ENC_CTRL_DIRQ_MASK (0x10U)
15201 #define ENC_CTRL_DIRQ_SHIFT (4U)
15202 
15206 #define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
15207 #define ENC_CTRL_XNE_MASK (0x20U)
15208 #define ENC_CTRL_XNE_SHIFT (5U)
15209 
15213 #define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
15214 #define ENC_CTRL_XIP_MASK (0x40U)
15215 #define ENC_CTRL_XIP_SHIFT (6U)
15216 
15220 #define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
15221 #define ENC_CTRL_XIE_MASK (0x80U)
15222 #define ENC_CTRL_XIE_SHIFT (7U)
15223 
15227 #define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
15228 #define ENC_CTRL_XIRQ_MASK (0x100U)
15229 #define ENC_CTRL_XIRQ_SHIFT (8U)
15230 
15234 #define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
15235 #define ENC_CTRL_PH1_MASK (0x200U)
15236 #define ENC_CTRL_PH1_SHIFT (9U)
15237 
15244 #define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
15245 #define ENC_CTRL_REV_MASK (0x400U)
15246 #define ENC_CTRL_REV_SHIFT (10U)
15247 
15251 #define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
15252 #define ENC_CTRL_SWIP_MASK (0x800U)
15253 #define ENC_CTRL_SWIP_SHIFT (11U)
15254 
15258 #define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
15259 #define ENC_CTRL_HNE_MASK (0x1000U)
15260 #define ENC_CTRL_HNE_SHIFT (12U)
15261 
15265 #define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
15266 #define ENC_CTRL_HIP_MASK (0x2000U)
15267 #define ENC_CTRL_HIP_SHIFT (13U)
15268 
15272 #define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
15273 #define ENC_CTRL_HIE_MASK (0x4000U)
15274 #define ENC_CTRL_HIE_SHIFT (14U)
15275 
15279 #define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
15280 #define ENC_CTRL_HIRQ_MASK (0x8000U)
15281 #define ENC_CTRL_HIRQ_SHIFT (15U)
15282 
15286 #define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
15287 
15291 #define ENC_FILT_FILT_PER_MASK (0xFFU)
15292 #define ENC_FILT_FILT_PER_SHIFT (0U)
15293 
15295 #define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
15296 #define ENC_FILT_FILT_CNT_MASK (0x700U)
15297 #define ENC_FILT_FILT_CNT_SHIFT (8U)
15298 
15300 #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
15301 
15305 #define ENC_WTR_WDOG_MASK (0xFFFFU)
15306 #define ENC_WTR_WDOG_SHIFT (0U)
15307 #define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
15308 
15312 #define ENC_POSD_POSD_MASK (0xFFFFU)
15313 #define ENC_POSD_POSD_SHIFT (0U)
15314 #define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
15315 
15319 #define ENC_POSDH_POSDH_MASK (0xFFFFU)
15320 #define ENC_POSDH_POSDH_SHIFT (0U)
15321 #define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
15322 
15326 #define ENC_REV_REV_MASK (0xFFFFU)
15327 #define ENC_REV_REV_SHIFT (0U)
15328 #define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
15329 
15333 #define ENC_REVH_REVH_MASK (0xFFFFU)
15334 #define ENC_REVH_REVH_SHIFT (0U)
15335 #define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
15336 
15340 #define ENC_UPOS_POS_MASK (0xFFFFU)
15341 #define ENC_UPOS_POS_SHIFT (0U)
15342 #define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
15343 
15347 #define ENC_LPOS_POS_MASK (0xFFFFU)
15348 #define ENC_LPOS_POS_SHIFT (0U)
15349 #define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
15350 
15354 #define ENC_UPOSH_POSH_MASK (0xFFFFU)
15355 #define ENC_UPOSH_POSH_SHIFT (0U)
15356 #define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
15357 
15361 #define ENC_LPOSH_POSH_MASK (0xFFFFU)
15362 #define ENC_LPOSH_POSH_SHIFT (0U)
15363 #define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
15364 
15368 #define ENC_UINIT_INIT_MASK (0xFFFFU)
15369 #define ENC_UINIT_INIT_SHIFT (0U)
15370 #define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
15371 
15375 #define ENC_LINIT_INIT_MASK (0xFFFFU)
15376 #define ENC_LINIT_INIT_SHIFT (0U)
15377 #define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
15378 
15382 #define ENC_IMR_HOME_MASK (0x1U)
15383 #define ENC_IMR_HOME_SHIFT (0U)
15384 #define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
15385 #define ENC_IMR_INDEX_MASK (0x2U)
15386 #define ENC_IMR_INDEX_SHIFT (1U)
15387 #define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
15388 #define ENC_IMR_PHB_MASK (0x4U)
15389 #define ENC_IMR_PHB_SHIFT (2U)
15390 #define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
15391 #define ENC_IMR_PHA_MASK (0x8U)
15392 #define ENC_IMR_PHA_SHIFT (3U)
15393 #define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
15394 #define ENC_IMR_FHOM_MASK (0x10U)
15395 #define ENC_IMR_FHOM_SHIFT (4U)
15396 #define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
15397 #define ENC_IMR_FIND_MASK (0x20U)
15398 #define ENC_IMR_FIND_SHIFT (5U)
15399 #define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
15400 #define ENC_IMR_FPHB_MASK (0x40U)
15401 #define ENC_IMR_FPHB_SHIFT (6U)
15402 #define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
15403 #define ENC_IMR_FPHA_MASK (0x80U)
15404 #define ENC_IMR_FPHA_SHIFT (7U)
15405 #define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
15406 
15410 #define ENC_TST_TEST_COUNT_MASK (0xFFU)
15411 #define ENC_TST_TEST_COUNT_SHIFT (0U)
15412 #define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
15413 #define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
15414 #define ENC_TST_TEST_PERIOD_SHIFT (8U)
15415 #define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
15416 #define ENC_TST_QDN_MASK (0x2000U)
15417 #define ENC_TST_QDN_SHIFT (13U)
15418 
15422 #define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
15423 #define ENC_TST_TCE_MASK (0x4000U)
15424 #define ENC_TST_TCE_SHIFT (14U)
15425 
15429 #define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
15430 #define ENC_TST_TEN_MASK (0x8000U)
15431 #define ENC_TST_TEN_SHIFT (15U)
15432 
15436 #define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
15437 
15441 #define ENC_CTRL2_UPDHLD_MASK (0x1U)
15442 #define ENC_CTRL2_UPDHLD_SHIFT (0U)
15443 
15447 #define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
15448 #define ENC_CTRL2_UPDPOS_MASK (0x2U)
15449 #define ENC_CTRL2_UPDPOS_SHIFT (1U)
15450 
15454 #define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
15455 #define ENC_CTRL2_MOD_MASK (0x4U)
15456 #define ENC_CTRL2_MOD_SHIFT (2U)
15457 
15461 #define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
15462 #define ENC_CTRL2_DIR_MASK (0x8U)
15463 #define ENC_CTRL2_DIR_SHIFT (3U)
15464 
15468 #define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
15469 #define ENC_CTRL2_RUIE_MASK (0x10U)
15470 #define ENC_CTRL2_RUIE_SHIFT (4U)
15471 
15475 #define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
15476 #define ENC_CTRL2_RUIRQ_MASK (0x20U)
15477 #define ENC_CTRL2_RUIRQ_SHIFT (5U)
15478 
15482 #define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
15483 #define ENC_CTRL2_ROIE_MASK (0x40U)
15484 #define ENC_CTRL2_ROIE_SHIFT (6U)
15485 
15489 #define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
15490 #define ENC_CTRL2_ROIRQ_MASK (0x80U)
15491 #define ENC_CTRL2_ROIRQ_SHIFT (7U)
15492 
15496 #define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
15497 #define ENC_CTRL2_REVMOD_MASK (0x100U)
15498 #define ENC_CTRL2_REVMOD_SHIFT (8U)
15499 
15503 #define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
15504 #define ENC_CTRL2_OUTCTL_MASK (0x200U)
15505 #define ENC_CTRL2_OUTCTL_SHIFT (9U)
15506 
15510 #define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
15511 #define ENC_CTRL2_SABIE_MASK (0x400U)
15512 #define ENC_CTRL2_SABIE_SHIFT (10U)
15513 
15517 #define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
15518 #define ENC_CTRL2_SABIRQ_MASK (0x800U)
15519 #define ENC_CTRL2_SABIRQ_SHIFT (11U)
15520 
15524 #define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
15525 
15529 #define ENC_UMOD_MOD_MASK (0xFFFFU)
15530 #define ENC_UMOD_MOD_SHIFT (0U)
15531 #define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
15532 
15536 #define ENC_LMOD_MOD_MASK (0xFFFFU)
15537 #define ENC_LMOD_MOD_SHIFT (0U)
15538 #define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
15539 
15543 #define ENC_UCOMP_COMP_MASK (0xFFFFU)
15544 #define ENC_UCOMP_COMP_SHIFT (0U)
15545 #define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
15546 
15550 #define ENC_LCOMP_COMP_MASK (0xFFFFU)
15551 #define ENC_LCOMP_COMP_SHIFT (0U)
15552 #define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
15553  /* end of group ENC_Register_Masks */
15559 
15560 
15561 /* ENC - Peripheral instance base addresses */
15563 #define ENC1_BASE (0x403C8000u)
15564 
15565 #define ENC1 ((ENC_Type *)ENC1_BASE)
15566 
15567 #define ENC2_BASE (0x403CC000u)
15568 
15569 #define ENC2 ((ENC_Type *)ENC2_BASE)
15570 
15571 #define ENC3_BASE (0x403D0000u)
15572 
15573 #define ENC3 ((ENC_Type *)ENC3_BASE)
15574 
15575 #define ENC4_BASE (0x403D4000u)
15576 
15577 #define ENC4 ((ENC_Type *)ENC4_BASE)
15578 
15579 #define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
15580 
15581 #define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
15582 
15583 #define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
15584 #define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
15585 #define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
15586 #define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
15587 #define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
15588  /* end of group ENC_Peripheral_Access_Layer */
15592 
15593 
15594 /* ----------------------------------------------------------------------------
15595  -- ENET Peripheral Access Layer
15596  ---------------------------------------------------------------------------- */
15597 
15604 typedef struct {
15605  uint8_t RESERVED_0[4];
15606  __IO uint32_t EIR;
15607  __IO uint32_t EIMR;
15608  uint8_t RESERVED_1[4];
15609  __IO uint32_t RDAR;
15610  __IO uint32_t TDAR;
15611  uint8_t RESERVED_2[12];
15612  __IO uint32_t ECR;
15613  uint8_t RESERVED_3[24];
15614  __IO uint32_t MMFR;
15615  __IO uint32_t MSCR;
15616  uint8_t RESERVED_4[28];
15617  __IO uint32_t MIBC;
15618  uint8_t RESERVED_5[28];
15619  __IO uint32_t RCR;
15620  uint8_t RESERVED_6[60];
15621  __IO uint32_t TCR;
15622  uint8_t RESERVED_7[28];
15623  __IO uint32_t PALR;
15624  __IO uint32_t PAUR;
15625  __IO uint32_t OPD;
15626  __IO uint32_t TXIC;
15627  uint8_t RESERVED_8[12];
15628  __IO uint32_t RXIC;
15629  uint8_t RESERVED_9[20];
15630  __IO uint32_t IAUR;
15631  __IO uint32_t IALR;
15632  __IO uint32_t GAUR;
15633  __IO uint32_t GALR;
15634  uint8_t RESERVED_10[28];
15635  __IO uint32_t TFWR;
15636  uint8_t RESERVED_11[56];
15637  __IO uint32_t RDSR;
15638  __IO uint32_t TDSR;
15639  __IO uint32_t MRBR;
15640  uint8_t RESERVED_12[4];
15641  __IO uint32_t RSFL;
15642  __IO uint32_t RSEM;
15643  __IO uint32_t RAEM;
15644  __IO uint32_t RAFL;
15645  __IO uint32_t TSEM;
15646  __IO uint32_t TAEM;
15647  __IO uint32_t TAFL;
15648  __IO uint32_t TIPG;
15649  __IO uint32_t FTRL;
15650  uint8_t RESERVED_13[12];
15651  __IO uint32_t TACC;
15652  __IO uint32_t RACC;
15653  uint8_t RESERVED_14[56];
15654  uint32_t RMON_T_DROP;
15655  __I uint32_t RMON_T_PACKETS;
15656  __I uint32_t RMON_T_BC_PKT;
15657  __I uint32_t RMON_T_MC_PKT;
15658  __I uint32_t RMON_T_CRC_ALIGN;
15659  __I uint32_t RMON_T_UNDERSIZE;
15660  __I uint32_t RMON_T_OVERSIZE;
15661  __I uint32_t RMON_T_FRAG;
15662  __I uint32_t RMON_T_JAB;
15663  __I uint32_t RMON_T_COL;
15664  __I uint32_t RMON_T_P64;
15665  __I uint32_t RMON_T_P65TO127;
15666  __I uint32_t RMON_T_P128TO255;
15667  __I uint32_t RMON_T_P256TO511;
15668  __I uint32_t RMON_T_P512TO1023;
15669  __I uint32_t RMON_T_P1024TO2047;
15670  __I uint32_t RMON_T_P_GTE2048;
15671  __I uint32_t RMON_T_OCTETS;
15672  uint32_t IEEE_T_DROP;
15673  __I uint32_t IEEE_T_FRAME_OK;
15674  __I uint32_t IEEE_T_1COL;
15675  __I uint32_t IEEE_T_MCOL;
15676  __I uint32_t IEEE_T_DEF;
15677  __I uint32_t IEEE_T_LCOL;
15678  __I uint32_t IEEE_T_EXCOL;
15679  __I uint32_t IEEE_T_MACERR;
15680  __I uint32_t IEEE_T_CSERR;
15681  __I uint32_t IEEE_T_SQE;
15682  __I uint32_t IEEE_T_FDXFC;
15683  __I uint32_t IEEE_T_OCTETS_OK;
15684  uint8_t RESERVED_15[12];
15685  __I uint32_t RMON_R_PACKETS;
15686  __I uint32_t RMON_R_BC_PKT;
15687  __I uint32_t RMON_R_MC_PKT;
15688  __I uint32_t RMON_R_CRC_ALIGN;
15689  __I uint32_t RMON_R_UNDERSIZE;
15690  __I uint32_t RMON_R_OVERSIZE;
15691  __I uint32_t RMON_R_FRAG;
15692  __I uint32_t RMON_R_JAB;
15693  uint32_t RMON_R_RESVD_0;
15694  __I uint32_t RMON_R_P64;
15695  __I uint32_t RMON_R_P65TO127;
15696  __I uint32_t RMON_R_P128TO255;
15697  __I uint32_t RMON_R_P256TO511;
15698  __I uint32_t RMON_R_P512TO1023;
15699  __I uint32_t RMON_R_P1024TO2047;
15700  __I uint32_t RMON_R_P_GTE2048;
15701  __I uint32_t RMON_R_OCTETS;
15702  __I uint32_t IEEE_R_DROP;
15703  __I uint32_t IEEE_R_FRAME_OK;
15704  __I uint32_t IEEE_R_CRC;
15705  __I uint32_t IEEE_R_ALIGN;
15706  __I uint32_t IEEE_R_MACERR;
15707  __I uint32_t IEEE_R_FDXFC;
15708  __I uint32_t IEEE_R_OCTETS_OK;
15709  uint8_t RESERVED_16[284];
15710  __IO uint32_t ATCR;
15711  __IO uint32_t ATVR;
15712  __IO uint32_t ATOFF;
15713  __IO uint32_t ATPER;
15714  __IO uint32_t ATCOR;
15715  __IO uint32_t ATINC;
15716  __I uint32_t ATSTMP;
15717  uint8_t RESERVED_17[488];
15718  __IO uint32_t TGSR;
15719  struct { /* offset: 0x608, array step: 0x8 */
15720  __IO uint32_t TCSR;
15721  __IO uint32_t TCCR;
15722  } CHANNEL[4];
15723 } ENET_Type;
15724 
15725 /* ----------------------------------------------------------------------------
15726  -- ENET Register Masks
15727  ---------------------------------------------------------------------------- */
15728 
15736 #define ENET_EIR_TS_TIMER_MASK (0x8000U)
15737 #define ENET_EIR_TS_TIMER_SHIFT (15U)
15738 
15740 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
15741 #define ENET_EIR_TS_AVAIL_MASK (0x10000U)
15742 #define ENET_EIR_TS_AVAIL_SHIFT (16U)
15743 
15745 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
15746 #define ENET_EIR_WAKEUP_MASK (0x20000U)
15747 #define ENET_EIR_WAKEUP_SHIFT (17U)
15748 
15750 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
15751 #define ENET_EIR_PLR_MASK (0x40000U)
15752 #define ENET_EIR_PLR_SHIFT (18U)
15753 
15755 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
15756 #define ENET_EIR_UN_MASK (0x80000U)
15757 #define ENET_EIR_UN_SHIFT (19U)
15758 
15760 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
15761 #define ENET_EIR_RL_MASK (0x100000U)
15762 #define ENET_EIR_RL_SHIFT (20U)
15763 
15765 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
15766 #define ENET_EIR_LC_MASK (0x200000U)
15767 #define ENET_EIR_LC_SHIFT (21U)
15768 
15770 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
15771 #define ENET_EIR_EBERR_MASK (0x400000U)
15772 #define ENET_EIR_EBERR_SHIFT (22U)
15773 
15775 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
15776 #define ENET_EIR_MII_MASK (0x800000U)
15777 #define ENET_EIR_MII_SHIFT (23U)
15778 
15780 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
15781 #define ENET_EIR_RXB_MASK (0x1000000U)
15782 #define ENET_EIR_RXB_SHIFT (24U)
15783 
15785 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
15786 #define ENET_EIR_RXF_MASK (0x2000000U)
15787 #define ENET_EIR_RXF_SHIFT (25U)
15788 
15790 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
15791 #define ENET_EIR_TXB_MASK (0x4000000U)
15792 #define ENET_EIR_TXB_SHIFT (26U)
15793 
15795 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
15796 #define ENET_EIR_TXF_MASK (0x8000000U)
15797 #define ENET_EIR_TXF_SHIFT (27U)
15798 
15800 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
15801 #define ENET_EIR_GRA_MASK (0x10000000U)
15802 #define ENET_EIR_GRA_SHIFT (28U)
15803 
15805 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
15806 #define ENET_EIR_BABT_MASK (0x20000000U)
15807 #define ENET_EIR_BABT_SHIFT (29U)
15808 
15810 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
15811 #define ENET_EIR_BABR_MASK (0x40000000U)
15812 #define ENET_EIR_BABR_SHIFT (30U)
15813 
15815 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
15816 
15820 #define ENET_EIMR_TS_TIMER_MASK (0x8000U)
15821 #define ENET_EIMR_TS_TIMER_SHIFT (15U)
15822 
15824 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
15825 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
15826 #define ENET_EIMR_TS_AVAIL_SHIFT (16U)
15827 
15829 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
15830 #define ENET_EIMR_WAKEUP_MASK (0x20000U)
15831 #define ENET_EIMR_WAKEUP_SHIFT (17U)
15832 
15834 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
15835 #define ENET_EIMR_PLR_MASK (0x40000U)
15836 #define ENET_EIMR_PLR_SHIFT (18U)
15837 
15839 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
15840 #define ENET_EIMR_UN_MASK (0x80000U)
15841 #define ENET_EIMR_UN_SHIFT (19U)
15842 
15844 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
15845 #define ENET_EIMR_RL_MASK (0x100000U)
15846 #define ENET_EIMR_RL_SHIFT (20U)
15847 
15849 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
15850 #define ENET_EIMR_LC_MASK (0x200000U)
15851 #define ENET_EIMR_LC_SHIFT (21U)
15852 
15854 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
15855 #define ENET_EIMR_EBERR_MASK (0x400000U)
15856 #define ENET_EIMR_EBERR_SHIFT (22U)
15857 
15859 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
15860 #define ENET_EIMR_MII_MASK (0x800000U)
15861 #define ENET_EIMR_MII_SHIFT (23U)
15862 
15864 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
15865 #define ENET_EIMR_RXB_MASK (0x1000000U)
15866 #define ENET_EIMR_RXB_SHIFT (24U)
15867 
15869 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
15870 #define ENET_EIMR_RXF_MASK (0x2000000U)
15871 #define ENET_EIMR_RXF_SHIFT (25U)
15872 
15874 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
15875 #define ENET_EIMR_TXB_MASK (0x4000000U)
15876 #define ENET_EIMR_TXB_SHIFT (26U)
15877 
15881 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
15882 #define ENET_EIMR_TXF_MASK (0x8000000U)
15883 #define ENET_EIMR_TXF_SHIFT (27U)
15884 
15888 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
15889 #define ENET_EIMR_GRA_MASK (0x10000000U)
15890 #define ENET_EIMR_GRA_SHIFT (28U)
15891 
15895 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
15896 #define ENET_EIMR_BABT_MASK (0x20000000U)
15897 #define ENET_EIMR_BABT_SHIFT (29U)
15898 
15902 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
15903 #define ENET_EIMR_BABR_MASK (0x40000000U)
15904 #define ENET_EIMR_BABR_SHIFT (30U)
15905 
15909 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
15910 
15914 #define ENET_RDAR_RDAR_MASK (0x1000000U)
15915 #define ENET_RDAR_RDAR_SHIFT (24U)
15916 
15918 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
15919 
15923 #define ENET_TDAR_TDAR_MASK (0x1000000U)
15924 #define ENET_TDAR_TDAR_SHIFT (24U)
15925 
15927 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
15928 
15932 #define ENET_ECR_RESET_MASK (0x1U)
15933 #define ENET_ECR_RESET_SHIFT (0U)
15934 
15936 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
15937 #define ENET_ECR_ETHEREN_MASK (0x2U)
15938 #define ENET_ECR_ETHEREN_SHIFT (1U)
15939 
15943 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
15944 #define ENET_ECR_MAGICEN_MASK (0x4U)
15945 #define ENET_ECR_MAGICEN_SHIFT (2U)
15946 
15950 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
15951 #define ENET_ECR_SLEEP_MASK (0x8U)
15952 #define ENET_ECR_SLEEP_SHIFT (3U)
15953 
15957 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
15958 #define ENET_ECR_EN1588_MASK (0x10U)
15959 #define ENET_ECR_EN1588_SHIFT (4U)
15960 
15964 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
15965 #define ENET_ECR_DBGEN_MASK (0x40U)
15966 #define ENET_ECR_DBGEN_SHIFT (6U)
15967 
15971 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
15972 #define ENET_ECR_DBSWP_MASK (0x100U)
15973 #define ENET_ECR_DBSWP_SHIFT (8U)
15974 
15978 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
15979 
15983 #define ENET_MMFR_DATA_MASK (0xFFFFU)
15984 #define ENET_MMFR_DATA_SHIFT (0U)
15985 
15987 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
15988 #define ENET_MMFR_TA_MASK (0x30000U)
15989 #define ENET_MMFR_TA_SHIFT (16U)
15990 
15992 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
15993 #define ENET_MMFR_RA_MASK (0x7C0000U)
15994 #define ENET_MMFR_RA_SHIFT (18U)
15995 
15997 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
15998 #define ENET_MMFR_PA_MASK (0xF800000U)
15999 #define ENET_MMFR_PA_SHIFT (23U)
16000 
16002 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
16003 #define ENET_MMFR_OP_MASK (0x30000000U)
16004 #define ENET_MMFR_OP_SHIFT (28U)
16005 
16007 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
16008 #define ENET_MMFR_ST_MASK (0xC0000000U)
16009 #define ENET_MMFR_ST_SHIFT (30U)
16010 
16012 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
16013 
16017 #define ENET_MSCR_MII_SPEED_MASK (0x7EU)
16018 #define ENET_MSCR_MII_SPEED_SHIFT (1U)
16019 
16021 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
16022 #define ENET_MSCR_DIS_PRE_MASK (0x80U)
16023 #define ENET_MSCR_DIS_PRE_SHIFT (7U)
16024 
16028 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
16029 #define ENET_MSCR_HOLDTIME_MASK (0x700U)
16030 #define ENET_MSCR_HOLDTIME_SHIFT (8U)
16031 
16037 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
16038 
16042 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
16043 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
16044 
16048 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
16049 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
16050 #define ENET_MIBC_MIB_IDLE_SHIFT (30U)
16051 
16055 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
16056 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
16057 #define ENET_MIBC_MIB_DIS_SHIFT (31U)
16058 
16062 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
16063 
16067 #define ENET_RCR_LOOP_MASK (0x1U)
16068 #define ENET_RCR_LOOP_SHIFT (0U)
16069 
16073 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
16074 #define ENET_RCR_DRT_MASK (0x2U)
16075 #define ENET_RCR_DRT_SHIFT (1U)
16076 
16080 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
16081 #define ENET_RCR_MII_MODE_MASK (0x4U)
16082 #define ENET_RCR_MII_MODE_SHIFT (2U)
16083 
16087 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
16088 #define ENET_RCR_PROM_MASK (0x8U)
16089 #define ENET_RCR_PROM_SHIFT (3U)
16090 
16094 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
16095 #define ENET_RCR_BC_REJ_MASK (0x10U)
16096 #define ENET_RCR_BC_REJ_SHIFT (4U)
16097 
16099 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
16100 #define ENET_RCR_FCE_MASK (0x20U)
16101 #define ENET_RCR_FCE_SHIFT (5U)
16102 
16104 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
16105 #define ENET_RCR_RMII_MODE_MASK (0x100U)
16106 #define ENET_RCR_RMII_MODE_SHIFT (8U)
16107 
16111 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
16112 #define ENET_RCR_RMII_10T_MASK (0x200U)
16113 #define ENET_RCR_RMII_10T_SHIFT (9U)
16114 
16118 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
16119 #define ENET_RCR_PADEN_MASK (0x1000U)
16120 #define ENET_RCR_PADEN_SHIFT (12U)
16121 
16125 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
16126 #define ENET_RCR_PAUFWD_MASK (0x2000U)
16127 #define ENET_RCR_PAUFWD_SHIFT (13U)
16128 
16132 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
16133 #define ENET_RCR_CRCFWD_MASK (0x4000U)
16134 #define ENET_RCR_CRCFWD_SHIFT (14U)
16135 
16139 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
16140 #define ENET_RCR_CFEN_MASK (0x8000U)
16141 #define ENET_RCR_CFEN_SHIFT (15U)
16142 
16146 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
16147 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
16148 #define ENET_RCR_MAX_FL_SHIFT (16U)
16149 
16151 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
16152 #define ENET_RCR_NLC_MASK (0x40000000U)
16153 #define ENET_RCR_NLC_SHIFT (30U)
16154 
16158 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
16159 #define ENET_RCR_GRS_MASK (0x80000000U)
16160 #define ENET_RCR_GRS_SHIFT (31U)
16161 
16163 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
16164 
16168 #define ENET_TCR_GTS_MASK (0x1U)
16169 #define ENET_TCR_GTS_SHIFT (0U)
16170 
16172 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
16173 #define ENET_TCR_FDEN_MASK (0x4U)
16174 #define ENET_TCR_FDEN_SHIFT (2U)
16175 
16177 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
16178 #define ENET_TCR_TFC_PAUSE_MASK (0x8U)
16179 #define ENET_TCR_TFC_PAUSE_SHIFT (3U)
16180 
16184 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
16185 #define ENET_TCR_RFC_PAUSE_MASK (0x10U)
16186 #define ENET_TCR_RFC_PAUSE_SHIFT (4U)
16187 
16189 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
16190 #define ENET_TCR_ADDSEL_MASK (0xE0U)
16191 #define ENET_TCR_ADDSEL_SHIFT (5U)
16192 
16198 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
16199 #define ENET_TCR_ADDINS_MASK (0x100U)
16200 #define ENET_TCR_ADDINS_SHIFT (8U)
16201 
16205 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
16206 #define ENET_TCR_CRCFWD_MASK (0x200U)
16207 #define ENET_TCR_CRCFWD_SHIFT (9U)
16208 
16212 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
16213 
16217 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
16218 #define ENET_PALR_PADDR1_SHIFT (0U)
16219 
16221 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
16222 
16226 #define ENET_PAUR_TYPE_MASK (0xFFFFU)
16227 #define ENET_PAUR_TYPE_SHIFT (0U)
16228 
16230 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
16231 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
16232 #define ENET_PAUR_PADDR2_SHIFT (16U)
16233 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
16234 
16238 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
16239 #define ENET_OPD_PAUSE_DUR_SHIFT (0U)
16240 
16242 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
16243 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
16244 #define ENET_OPD_OPCODE_SHIFT (16U)
16245 
16247 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
16248 
16252 #define ENET_TXIC_ICTT_MASK (0xFFFFU)
16253 #define ENET_TXIC_ICTT_SHIFT (0U)
16254 
16256 #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
16257 #define ENET_TXIC_ICFT_MASK (0xFF00000U)
16258 #define ENET_TXIC_ICFT_SHIFT (20U)
16259 
16261 #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
16262 #define ENET_TXIC_ICCS_MASK (0x40000000U)
16263 #define ENET_TXIC_ICCS_SHIFT (30U)
16264 
16268 #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
16269 #define ENET_TXIC_ICEN_MASK (0x80000000U)
16270 #define ENET_TXIC_ICEN_SHIFT (31U)
16271 
16275 #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
16276 
16280 #define ENET_RXIC_ICTT_MASK (0xFFFFU)
16281 #define ENET_RXIC_ICTT_SHIFT (0U)
16282 
16284 #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
16285 #define ENET_RXIC_ICFT_MASK (0xFF00000U)
16286 #define ENET_RXIC_ICFT_SHIFT (20U)
16287 
16289 #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
16290 #define ENET_RXIC_ICCS_MASK (0x40000000U)
16291 #define ENET_RXIC_ICCS_SHIFT (30U)
16292 
16296 #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
16297 #define ENET_RXIC_ICEN_MASK (0x80000000U)
16298 #define ENET_RXIC_ICEN_SHIFT (31U)
16299 
16303 #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
16304 
16308 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
16309 #define ENET_IAUR_IADDR1_SHIFT (0U)
16310 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
16311 
16315 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
16316 #define ENET_IALR_IADDR2_SHIFT (0U)
16317 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
16318 
16322 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
16323 #define ENET_GAUR_GADDR1_SHIFT (0U)
16324 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
16325 
16329 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
16330 #define ENET_GALR_GADDR2_SHIFT (0U)
16331 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
16332 
16336 #define ENET_TFWR_TFWR_MASK (0x3FU)
16337 #define ENET_TFWR_TFWR_SHIFT (0U)
16338 
16345 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
16346 #define ENET_TFWR_STRFWD_MASK (0x100U)
16347 #define ENET_TFWR_STRFWD_SHIFT (8U)
16348 
16352 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
16353 
16357 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
16358 #define ENET_RDSR_R_DES_START_SHIFT (3U)
16359 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
16360 
16364 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
16365 #define ENET_TDSR_X_DES_START_SHIFT (3U)
16366 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
16367 
16371 #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
16372 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
16373 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
16374 
16378 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
16379 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
16380 
16382 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
16383 
16387 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
16388 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
16389 
16391 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
16392 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
16393 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
16394 
16396 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
16397 
16401 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
16402 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
16403 
16405 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
16406 
16410 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
16411 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
16412 
16414 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
16415 
16419 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
16420 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
16421 
16423 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
16424 
16428 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
16429 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
16430 
16432 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
16433 
16437 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
16438 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
16439 
16441 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
16442 
16446 #define ENET_TIPG_IPG_MASK (0x1FU)
16447 #define ENET_TIPG_IPG_SHIFT (0U)
16448 
16450 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
16451 
16455 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
16456 #define ENET_FTRL_TRUNC_FL_SHIFT (0U)
16457 
16459 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
16460 
16464 #define ENET_TACC_SHIFT16_MASK (0x1U)
16465 #define ENET_TACC_SHIFT16_SHIFT (0U)
16466 
16473 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
16474 #define ENET_TACC_IPCHK_MASK (0x8U)
16475 #define ENET_TACC_IPCHK_SHIFT (3U)
16476 
16481 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
16482 #define ENET_TACC_PROCHK_MASK (0x10U)
16483 #define ENET_TACC_PROCHK_SHIFT (4U)
16484 
16489 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
16490 
16494 #define ENET_RACC_PADREM_MASK (0x1U)
16495 #define ENET_RACC_PADREM_SHIFT (0U)
16496 
16500 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
16501 #define ENET_RACC_IPDIS_MASK (0x2U)
16502 #define ENET_RACC_IPDIS_SHIFT (1U)
16503 
16509 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
16510 #define ENET_RACC_PRODIS_MASK (0x4U)
16511 #define ENET_RACC_PRODIS_SHIFT (2U)
16512 
16518 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
16519 #define ENET_RACC_LINEDIS_MASK (0x40U)
16520 #define ENET_RACC_LINEDIS_SHIFT (6U)
16521 
16525 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
16526 #define ENET_RACC_SHIFT16_MASK (0x80U)
16527 #define ENET_RACC_SHIFT16_SHIFT (7U)
16528 
16532 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
16533 
16537 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
16538 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
16539 
16541 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
16542 
16546 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
16547 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
16548 
16550 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
16551 
16555 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
16556 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
16557 
16559 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
16560 
16564 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
16565 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
16566 
16568 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
16569 
16573 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
16574 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
16575 
16577 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
16578 
16582 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
16583 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
16584 
16586 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
16587 
16591 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
16592 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
16593 
16595 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
16596 
16600 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
16601 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
16602 
16604 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
16605 
16609 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
16610 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
16611 
16613 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
16614 
16618 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
16619 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
16620 
16622 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
16623 
16627 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
16628 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
16629 
16631 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
16632 
16636 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
16637 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
16638 
16640 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
16641 
16645 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
16646 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
16647 
16649 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
16650 
16654 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
16655 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
16656 
16658 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
16659 
16663 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
16664 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
16665 
16667 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
16668 
16672 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
16673 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
16674 
16676 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
16677 
16681 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
16682 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
16683 
16685 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
16686 
16690 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
16691 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
16692 
16694 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
16695 
16699 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
16700 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
16701 
16703 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
16704 
16708 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
16709 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
16710 
16712 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
16713 
16717 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
16718 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
16719 
16721 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
16722 
16726 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
16727 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
16728 
16730 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
16731 
16735 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
16736 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
16737 
16739 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
16740 
16744 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
16745 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
16746 
16748 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
16749 
16753 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
16754 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
16755 
16757 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
16758 
16762 #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
16763 #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
16764 #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
16765 
16769 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
16770 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
16771 
16773 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
16774 
16778 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
16779 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
16780 
16782 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
16783 
16787 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
16788 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
16789 
16791 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
16792 
16796 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
16797 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
16798 
16800 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
16801 
16805 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
16806 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
16807 
16809 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
16810 
16814 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
16815 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
16816 
16818 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
16819 
16823 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
16824 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
16825 
16827 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
16828 
16832 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
16833 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
16834 
16836 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
16837 
16841 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
16842 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
16843 
16845 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
16846 
16850 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
16851 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
16852 
16854 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
16855 
16859 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
16860 #define ENET_RMON_R_P64_COUNT_SHIFT (0U)
16861 
16863 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
16864 
16868 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
16869 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
16870 
16872 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
16873 
16877 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
16878 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
16879 
16881 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
16882 
16886 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
16887 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
16888 
16890 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
16891 
16895 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
16896 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
16897 
16899 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
16900 
16904 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
16905 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
16906 
16908 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
16909 
16913 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
16914 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
16915 
16917 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
16918 
16922 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
16923 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
16924 
16926 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
16927 
16931 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
16932 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
16933 
16935 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
16936 
16940 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
16941 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
16942 
16944 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
16945 
16949 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
16950 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
16951 
16953 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
16954 
16958 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
16959 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
16960 
16962 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
16963 
16967 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
16968 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
16969 
16971 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
16972 
16976 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
16977 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
16978 
16980 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
16981 
16985 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
16986 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
16987 
16989 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
16990 
16994 #define ENET_ATCR_EN_MASK (0x1U)
16995 #define ENET_ATCR_EN_SHIFT (0U)
16996 
17000 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
17001 #define ENET_ATCR_OFFEN_MASK (0x4U)
17002 #define ENET_ATCR_OFFEN_SHIFT (2U)
17003 
17009 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
17010 #define ENET_ATCR_OFFRST_MASK (0x8U)
17011 #define ENET_ATCR_OFFRST_SHIFT (3U)
17012 
17016 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
17017 #define ENET_ATCR_PEREN_MASK (0x10U)
17018 #define ENET_ATCR_PEREN_SHIFT (4U)
17019 
17025 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
17026 #define ENET_ATCR_PINPER_MASK (0x80U)
17027 #define ENET_ATCR_PINPER_SHIFT (7U)
17028 
17032 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
17033 #define ENET_ATCR_RESTART_MASK (0x200U)
17034 #define ENET_ATCR_RESTART_SHIFT (9U)
17035 
17037 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
17038 #define ENET_ATCR_CAPTURE_MASK (0x800U)
17039 #define ENET_ATCR_CAPTURE_SHIFT (11U)
17040 
17044 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
17045 #define ENET_ATCR_SLAVE_MASK (0x2000U)
17046 #define ENET_ATCR_SLAVE_SHIFT (13U)
17047 
17052 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
17053 
17057 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
17058 #define ENET_ATVR_ATIME_SHIFT (0U)
17059 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
17060 
17064 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
17065 #define ENET_ATOFF_OFFSET_SHIFT (0U)
17066 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
17067 
17071 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
17072 #define ENET_ATPER_PERIOD_SHIFT (0U)
17073 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
17074 
17078 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
17079 #define ENET_ATCOR_COR_SHIFT (0U)
17080 
17082 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
17083 
17087 #define ENET_ATINC_INC_MASK (0x7FU)
17088 #define ENET_ATINC_INC_SHIFT (0U)
17089 
17091 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
17092 #define ENET_ATINC_INC_CORR_MASK (0x7F00U)
17093 #define ENET_ATINC_INC_CORR_SHIFT (8U)
17094 
17096 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
17097 
17101 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
17102 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
17103 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
17104 
17108 #define ENET_TGSR_TF0_MASK (0x1U)
17109 #define ENET_TGSR_TF0_SHIFT (0U)
17110 
17114 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
17115 #define ENET_TGSR_TF1_MASK (0x2U)
17116 #define ENET_TGSR_TF1_SHIFT (1U)
17117 
17121 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
17122 #define ENET_TGSR_TF2_MASK (0x4U)
17123 #define ENET_TGSR_TF2_SHIFT (2U)
17124 
17128 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
17129 #define ENET_TGSR_TF3_MASK (0x8U)
17130 #define ENET_TGSR_TF3_SHIFT (3U)
17131 
17135 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
17136 
17140 #define ENET_TCSR_TDRE_MASK (0x1U)
17141 #define ENET_TCSR_TDRE_SHIFT (0U)
17142 
17146 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
17147 #define ENET_TCSR_TMODE_MASK (0x3CU)
17148 #define ENET_TCSR_TMODE_SHIFT (2U)
17149 
17165 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
17166 #define ENET_TCSR_TIE_MASK (0x40U)
17167 #define ENET_TCSR_TIE_SHIFT (6U)
17168 
17172 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
17173 #define ENET_TCSR_TF_MASK (0x80U)
17174 #define ENET_TCSR_TF_SHIFT (7U)
17175 
17179 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
17180 #define ENET_TCSR_TPWC_MASK (0xF800U)
17181 #define ENET_TCSR_TPWC_SHIFT (11U)
17182 
17189 #define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
17190 
17192 /* The count of ENET_TCSR */
17193 #define ENET_TCSR_COUNT (4U)
17194 
17197 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
17198 #define ENET_TCCR_TCC_SHIFT (0U)
17199 
17201 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
17202 
17204 /* The count of ENET_TCCR */
17205 #define ENET_TCCR_COUNT (4U)
17206 
17207  /* end of group ENET_Register_Masks */
17211 
17212 
17213 /* ENET - Peripheral instance base addresses */
17215 #define ENET_BASE (0x402D8000u)
17216 
17217 #define ENET ((ENET_Type *)ENET_BASE)
17218 
17219 #define ENET_BASE_ADDRS { ENET_BASE }
17220 
17221 #define ENET_BASE_PTRS { ENET }
17222 
17223 #define ENET_Transmit_IRQS { ENET_IRQn }
17224 #define ENET_Receive_IRQS { ENET_IRQn }
17225 #define ENET_Error_IRQS { ENET_IRQn }
17226 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
17227 /* ENET Buffer Descriptor and Buffer Address Alignment. */
17228 #define ENET_BUFF_ALIGNMENT (64U)
17229 
17230  /* end of group ENET_Peripheral_Access_Layer */
17234 
17235 
17236 /* ----------------------------------------------------------------------------
17237  -- EWM Peripheral Access Layer
17238  ---------------------------------------------------------------------------- */
17239 
17246 typedef struct {
17247  __IO uint8_t CTRL;
17248  __O uint8_t SERV;
17249  __IO uint8_t CMPL;
17250  __IO uint8_t CMPH;
17251  __IO uint8_t CLKCTRL;
17252  __IO uint8_t CLKPRESCALER;
17253 } EWM_Type;
17254 
17255 /* ----------------------------------------------------------------------------
17256  -- EWM Register Masks
17257  ---------------------------------------------------------------------------- */
17258 
17266 #define EWM_CTRL_EWMEN_MASK (0x1U)
17267 #define EWM_CTRL_EWMEN_SHIFT (0U)
17268 
17270 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
17271 #define EWM_CTRL_ASSIN_MASK (0x2U)
17272 #define EWM_CTRL_ASSIN_SHIFT (1U)
17273 
17275 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
17276 #define EWM_CTRL_INEN_MASK (0x4U)
17277 #define EWM_CTRL_INEN_SHIFT (2U)
17278 
17280 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
17281 #define EWM_CTRL_INTEN_MASK (0x8U)
17282 #define EWM_CTRL_INTEN_SHIFT (3U)
17283 
17285 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
17286 
17290 #define EWM_SERV_SERVICE_MASK (0xFFU)
17291 #define EWM_SERV_SERVICE_SHIFT (0U)
17292 
17294 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
17295 
17299 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
17300 #define EWM_CMPL_COMPAREL_SHIFT (0U)
17301 
17303 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
17304 
17308 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
17309 #define EWM_CMPH_COMPAREH_SHIFT (0U)
17310 
17312 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
17313 
17317 #define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
17318 #define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
17319 
17321 #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
17322 
17326 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
17327 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
17328 
17330 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
17331  /* end of group EWM_Register_Masks */
17337 
17338 
17339 /* EWM - Peripheral instance base addresses */
17341 #define EWM_BASE (0x400B4000u)
17342 
17343 #define EWM ((EWM_Type *)EWM_BASE)
17344 
17345 #define EWM_BASE_ADDRS { EWM_BASE }
17346 
17347 #define EWM_BASE_PTRS { EWM }
17348 
17349 #define EWM_IRQS { EWM_IRQn }
17350  /* end of group EWM_Peripheral_Access_Layer */
17354 
17355 
17356 /* ----------------------------------------------------------------------------
17357  -- FLEXIO Peripheral Access Layer
17358  ---------------------------------------------------------------------------- */
17359 
17366 typedef struct {
17367  __I uint32_t VERID;
17368  __I uint32_t PARAM;
17369  __IO uint32_t CTRL;
17370  __I uint32_t PIN;
17371  __IO uint32_t SHIFTSTAT;
17372  __IO uint32_t SHIFTERR;
17373  __IO uint32_t TIMSTAT;
17374  uint8_t RESERVED_0[4];
17375  __IO uint32_t SHIFTSIEN;
17376  __IO uint32_t SHIFTEIEN;
17377  __IO uint32_t TIMIEN;
17378  uint8_t RESERVED_1[4];
17379  __IO uint32_t SHIFTSDEN;
17380  uint8_t RESERVED_2[12];
17381  __IO uint32_t SHIFTSTATE;
17382  uint8_t RESERVED_3[60];
17383  __IO uint32_t SHIFTCTL[4];
17384  uint8_t RESERVED_4[112];
17385  __IO uint32_t SHIFTCFG[4];
17386  uint8_t RESERVED_5[240];
17387  __IO uint32_t SHIFTBUF[4];
17388  uint8_t RESERVED_6[112];
17389  __IO uint32_t SHIFTBUFBIS[4];
17390  uint8_t RESERVED_7[112];
17391  __IO uint32_t SHIFTBUFBYS[4];
17392  uint8_t RESERVED_8[112];
17393  __IO uint32_t SHIFTBUFBBS[4];
17394  uint8_t RESERVED_9[112];
17395  __IO uint32_t TIMCTL[4];
17396  uint8_t RESERVED_10[112];
17397  __IO uint32_t TIMCFG[4];
17398  uint8_t RESERVED_11[112];
17399  __IO uint32_t TIMCMP[4];
17400  uint8_t RESERVED_12[368];
17401  __IO uint32_t SHIFTBUFNBS[4];
17402  uint8_t RESERVED_13[112];
17403  __IO uint32_t SHIFTBUFHWS[4];
17404  uint8_t RESERVED_14[112];
17405  __IO uint32_t SHIFTBUFNIS[4];
17406 } FLEXIO_Type;
17407 
17408 /* ----------------------------------------------------------------------------
17409  -- FLEXIO Register Masks
17410  ---------------------------------------------------------------------------- */
17411 
17419 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
17420 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
17421 
17425 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
17426 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
17427 #define FLEXIO_VERID_MINOR_SHIFT (16U)
17428 
17430 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
17431 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
17432 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
17433 
17435 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
17436 
17440 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
17441 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
17442 
17444 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
17445 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
17446 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
17447 
17449 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
17450 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
17451 #define FLEXIO_PARAM_PIN_SHIFT (16U)
17452 
17454 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
17455 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
17456 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
17457 
17459 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
17460 
17464 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
17465 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
17466 
17470 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
17471 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
17472 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
17473 
17477 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
17478 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
17479 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
17480 
17484 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
17485 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
17486 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
17487 
17491 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
17492 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
17493 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
17494 
17498 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
17499 
17503 #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
17504 #define FLEXIO_PIN_PDI_SHIFT (0U)
17505 
17507 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
17508 
17512 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
17513 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
17514 
17516 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
17517 
17521 #define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
17522 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
17523 
17525 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
17526 
17530 #define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
17531 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
17532 
17534 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
17535 
17539 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
17540 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
17541 
17543 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
17544 
17548 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
17549 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
17550 
17552 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
17553 
17557 #define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
17558 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
17559 
17561 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
17562 
17566 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
17567 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
17568 
17570 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
17571 
17575 #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
17576 #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
17577 
17579 #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
17580 
17584 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
17585 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
17586 
17596 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
17597 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
17598 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
17599 
17603 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
17604 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
17605 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
17606 
17608 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
17609 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
17610 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
17611 
17617 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
17618 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
17619 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
17620 
17624 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
17625 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
17626 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
17627 
17629 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
17630 
17632 /* The count of FLEXIO_SHIFTCTL */
17633 #define FLEXIO_SHIFTCTL_COUNT (4U)
17634 
17637 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
17638 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
17639 
17645 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
17646 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
17647 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
17648 
17654 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
17655 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
17656 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
17657 
17661 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
17662 #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
17663 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
17664 
17666 #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
17667 
17669 /* The count of FLEXIO_SHIFTCFG */
17670 #define FLEXIO_SHIFTCFG_COUNT (4U)
17671 
17674 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
17675 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
17676 
17678 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
17679 
17681 /* The count of FLEXIO_SHIFTBUF */
17682 #define FLEXIO_SHIFTBUF_COUNT (4U)
17683 
17686 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
17687 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
17688 
17690 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
17691 
17693 /* The count of FLEXIO_SHIFTBUFBIS */
17694 #define FLEXIO_SHIFTBUFBIS_COUNT (4U)
17695 
17698 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
17699 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
17700 
17702 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
17703 
17705 /* The count of FLEXIO_SHIFTBUFBYS */
17706 #define FLEXIO_SHIFTBUFBYS_COUNT (4U)
17707 
17710 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
17711 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
17712 
17714 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
17715 
17717 /* The count of FLEXIO_SHIFTBUFBBS */
17718 #define FLEXIO_SHIFTBUFBBS_COUNT (4U)
17719 
17722 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
17723 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
17724 
17730 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
17731 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
17732 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
17733 
17737 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
17738 #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
17739 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
17740 
17742 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
17743 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
17744 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
17745 
17751 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
17752 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
17753 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
17754 
17758 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
17759 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
17760 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
17761 
17765 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
17766 #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
17767 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
17768 
17770 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
17771 
17773 /* The count of FLEXIO_TIMCTL */
17774 #define FLEXIO_TIMCTL_COUNT (4U)
17775 
17778 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
17779 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
17780 
17784 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
17785 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
17786 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
17787 
17793 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
17794 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
17795 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
17796 
17806 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
17807 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
17808 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
17809 
17819 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
17820 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
17821 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
17822 
17832 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
17833 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
17834 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
17835 
17841 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
17842 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
17843 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
17844 
17850 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
17851 
17853 /* The count of FLEXIO_TIMCFG */
17854 #define FLEXIO_TIMCFG_COUNT (4U)
17855 
17858 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
17859 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
17860 
17862 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
17863 
17865 /* The count of FLEXIO_TIMCMP */
17866 #define FLEXIO_TIMCMP_COUNT (4U)
17867 
17870 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
17871 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
17872 
17874 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
17875 
17877 /* The count of FLEXIO_SHIFTBUFNBS */
17878 #define FLEXIO_SHIFTBUFNBS_COUNT (4U)
17879 
17882 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
17883 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
17884 
17886 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
17887 
17889 /* The count of FLEXIO_SHIFTBUFHWS */
17890 #define FLEXIO_SHIFTBUFHWS_COUNT (4U)
17891 
17894 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
17895 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
17896 
17898 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
17899 
17901 /* The count of FLEXIO_SHIFTBUFNIS */
17902 #define FLEXIO_SHIFTBUFNIS_COUNT (4U)
17903 
17904  /* end of group FLEXIO_Register_Masks */
17908 
17909 
17910 /* FLEXIO - Peripheral instance base addresses */
17912 #define FLEXIO1_BASE (0x401AC000u)
17913 
17914 #define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
17915 
17916 #define FLEXIO2_BASE (0x401B0000u)
17917 
17918 #define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
17919 
17920 #define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
17921 
17922 #define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
17923 
17924 #define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
17925  /* end of group FLEXIO_Peripheral_Access_Layer */
17929 
17930 
17931 /* ----------------------------------------------------------------------------
17932  -- FLEXRAM Peripheral Access Layer
17933  ---------------------------------------------------------------------------- */
17934 
17941 typedef struct {
17942  __IO uint32_t TCM_CTRL;
17943  uint8_t RESERVED_0[12];
17944  __IO uint32_t INT_STATUS;
17945  __IO uint32_t INT_STAT_EN;
17946  __IO uint32_t INT_SIG_EN;
17947 } FLEXRAM_Type;
17948 
17949 /* ----------------------------------------------------------------------------
17950  -- FLEXRAM Register Masks
17951  ---------------------------------------------------------------------------- */
17952 
17960 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
17961 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
17962 
17966 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
17967 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
17968 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
17969 
17973 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
17974 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
17975 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
17976 
17978 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
17979 
17983 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
17984 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
17985 
17989 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
17990 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
17991 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
17992 
17996 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
17997 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
17998 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
17999 
18003 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
18004 
18008 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
18009 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
18010 
18014 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
18015 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
18016 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
18017 
18021 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
18022 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
18023 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
18024 
18028 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
18029 
18033 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
18034 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
18035 
18039 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
18040 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
18041 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
18042 
18046 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
18047 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
18048 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
18049 
18053 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
18054  /* end of group FLEXRAM_Register_Masks */
18060 
18061 
18062 /* FLEXRAM - Peripheral instance base addresses */
18064 #define FLEXRAM_BASE (0x400B0000u)
18065 
18066 #define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
18067 
18068 #define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
18069 
18070 #define FLEXRAM_BASE_PTRS { FLEXRAM }
18071 
18072 #define FLEXRAM_IRQS { FLEXRAM_IRQn }
18073  /* end of group FLEXRAM_Peripheral_Access_Layer */
18077 
18078 
18079 /* ----------------------------------------------------------------------------
18080  -- FLEXSPI Peripheral Access Layer
18081  ---------------------------------------------------------------------------- */
18082 
18089 typedef struct {
18090  __IO uint32_t MCR0;
18091  __IO uint32_t MCR1;
18092  __IO uint32_t MCR2;
18093  __IO uint32_t AHBCR;
18094  __IO uint32_t INTEN;
18095  __IO uint32_t INTR;
18096  __IO uint32_t LUTKEY;
18097  __IO uint32_t LUTCR;
18098  __IO uint32_t AHBRXBUFCR0[4];
18099  uint8_t RESERVED_0[48];
18100  __IO uint32_t FLSHCR0[4];
18101  __IO uint32_t FLSHCR1[4];
18102  __IO uint32_t FLSHCR2[4];
18103  uint8_t RESERVED_1[4];
18104  __IO uint32_t FLSHCR4;
18105  uint8_t RESERVED_2[8];
18106  __IO uint32_t IPCR0;
18107  __IO uint32_t IPCR1;
18108  uint8_t RESERVED_3[8];
18109  __IO uint32_t IPCMD;
18110  uint8_t RESERVED_4[4];
18111  __IO uint32_t IPRXFCR;
18112  __IO uint32_t IPTXFCR;
18113  __IO uint32_t DLLCR[2];
18114  uint8_t RESERVED_5[24];
18115  __I uint32_t STS0;
18116  __I uint32_t STS1;
18117  __I uint32_t STS2;
18118  __I uint32_t AHBSPNDSTS;
18119  __I uint32_t IPRXFSTS;
18120  __I uint32_t IPTXFSTS;
18121  uint8_t RESERVED_6[8];
18122  __I uint32_t RFDR[32];
18123  __O uint32_t TFDR[32];
18124  __IO uint32_t LUT[64];
18125 } FLEXSPI_Type;
18126 
18127 /* ----------------------------------------------------------------------------
18128  -- FLEXSPI Register Masks
18129  ---------------------------------------------------------------------------- */
18130 
18138 #define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
18139 #define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
18140 
18142 #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
18143 #define FLEXSPI_MCR0_MDIS_MASK (0x2U)
18144 #define FLEXSPI_MCR0_MDIS_SHIFT (1U)
18145 
18147 #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
18148 #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
18149 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
18150 
18156 #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
18157 #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
18158 #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
18159 
18163 #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
18164 #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
18165 #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
18166 
18170 #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
18171 #define FLEXSPI_MCR0_HSEN_MASK (0x800U)
18172 #define FLEXSPI_MCR0_HSEN_SHIFT (11U)
18173 
18177 #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
18178 #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
18179 #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
18180 
18184 #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
18185 #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
18186 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
18187 
18191 #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
18192 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
18193 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
18194 
18200 #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
18201 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
18202 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
18203 
18205 #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
18206 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
18207 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
18208 
18210 #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
18211 
18215 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
18216 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
18217 #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
18218 #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
18219 #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
18220 #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
18221 
18225 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
18226 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
18227 
18234 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
18235 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
18236 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
18237 
18240 #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
18241 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
18242 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
18243 
18250 #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
18251 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
18252 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
18253 
18259 #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
18260 #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
18261 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
18262 
18264 #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
18265 
18269 #define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
18270 #define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
18271 
18275 #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
18276 #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
18277 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
18278 
18282 #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
18283 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
18284 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
18285 
18292 #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
18293 #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
18294 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
18295 
18297 #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
18298 #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
18299 #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
18300 
18305 #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
18306 
18310 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
18311 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
18312 
18314 #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
18315 #define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
18316 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
18317 
18319 #define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
18320 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
18321 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
18322 
18324 #define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
18325 #define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
18326 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
18327 
18329 #define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
18330 #define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
18331 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
18332 
18334 #define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
18335 #define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
18336 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
18337 
18339 #define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
18340 #define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
18341 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
18342 
18344 #define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
18345 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
18346 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
18347 
18349 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
18350 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
18351 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
18352 
18354 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
18355 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
18356 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
18357 
18359 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
18360 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
18361 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
18362 
18364 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
18365 
18369 #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
18370 #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
18371 
18374 #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
18375 #define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
18376 #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
18377 
18379 #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
18380 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
18381 #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
18382 
18384 #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
18385 #define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
18386 #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
18387 
18390 #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
18391 #define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
18392 #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
18393 
18396 #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
18397 #define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
18398 #define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
18399 
18401 #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
18402 #define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
18403 #define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
18404 
18406 #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
18407 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
18408 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
18409 
18411 #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
18412 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
18413 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
18414 
18416 #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
18417 #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
18418 #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
18419 
18421 #define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
18422 #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
18423 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
18424 
18426 #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
18427 
18431 #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
18432 #define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
18433 
18435 #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
18436 
18440 #define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
18441 #define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
18442 
18444 #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
18445 #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
18446 #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
18447 
18449 #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
18450 
18454 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
18455 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
18456 
18458 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
18459 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
18460 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
18461 
18463 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
18464 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
18465 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
18466 
18468 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
18469 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
18470 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
18471 
18473 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
18474 
18476 /* The count of FLEXSPI_AHBRXBUFCR0 */
18477 #define FLEXSPI_AHBRXBUFCR0_COUNT (4U)
18478 
18481 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
18482 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
18483 
18485 #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
18486 
18488 /* The count of FLEXSPI_FLSHCR0 */
18489 #define FLEXSPI_FLSHCR0_COUNT (4U)
18490 
18493 #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
18494 #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
18495 
18497 #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
18498 #define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
18499 #define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
18500 
18502 #define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
18503 #define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
18504 #define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
18505 
18507 #define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
18508 #define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
18509 #define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
18510 
18512 #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
18513 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
18514 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
18515 
18519 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
18520 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
18521 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
18522 
18527 #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
18528 
18530 /* The count of FLEXSPI_FLSHCR1 */
18531 #define FLEXSPI_FLSHCR1_COUNT (4U)
18532 
18535 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
18536 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
18537 
18539 #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
18540 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
18541 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
18542 
18544 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
18545 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
18546 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
18547 
18549 #define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
18550 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
18551 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
18552 
18554 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
18555 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
18556 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
18557 #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
18558 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
18559 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
18560 
18570 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
18571 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
18572 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
18573 
18576 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
18577 
18579 /* The count of FLEXSPI_FLSHCR2 */
18580 #define FLEXSPI_FLSHCR2_COUNT (4U)
18581 
18584 #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
18585 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
18586 
18592 #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
18593 #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
18594 #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
18595 
18600 #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
18601 #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
18602 #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
18603 
18608 #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
18609 
18613 #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
18614 #define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
18615 
18617 #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
18618 
18622 #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
18623 #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
18624 
18626 #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
18627 #define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
18628 #define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
18629 
18631 #define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
18632 #define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
18633 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
18634 
18636 #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
18637 #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
18638 #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
18639 
18643 #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
18644 
18648 #define FLEXSPI_IPCMD_TRG_MASK (0x1U)
18649 #define FLEXSPI_IPCMD_TRG_SHIFT (0U)
18650 
18652 #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
18653 
18657 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
18658 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
18659 
18661 #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
18662 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
18663 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
18664 
18668 #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
18669 #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
18670 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
18671 
18673 #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
18674 
18678 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
18679 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
18680 
18682 #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
18683 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
18684 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
18685 
18689 #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
18690 #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
18691 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
18692 
18694 #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
18695 
18699 #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
18700 #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
18701 
18703 #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
18704 #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
18705 #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
18706 
18711 #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
18712 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
18713 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
18714 
18716 #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
18717 #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
18718 #define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
18719 
18721 #define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
18722 #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
18723 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
18724 
18726 #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
18727 
18729 /* The count of FLEXSPI_DLLCR */
18730 #define FLEXSPI_DLLCR_COUNT (2U)
18731 
18734 #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
18735 #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
18736 
18739 #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
18740 #define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
18741 #define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
18742 
18747 #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
18748 #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
18749 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
18750 
18757 #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
18758 
18762 #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
18763 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
18764 
18767 #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
18768 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
18769 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
18770 
18779 #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
18780 #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
18781 #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
18782 
18785 #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
18786 #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
18787 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
18788 
18799 #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
18800 
18804 #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
18805 #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
18806 
18808 #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
18809 #define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
18810 #define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
18811 
18813 #define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
18814 #define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
18815 #define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
18816 
18818 #define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
18819 #define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
18820 #define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
18821 
18823 #define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
18824 #define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
18825 #define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
18826 
18828 #define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
18829 #define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
18830 #define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
18831 
18833 #define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
18834 #define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
18835 #define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
18836 
18838 #define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
18839 #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
18840 #define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
18841 
18843 #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
18844 
18848 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
18849 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
18850 
18852 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
18853 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
18854 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
18855 
18857 #define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
18858 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
18859 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
18860 
18862 #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
18863 
18867 #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
18868 #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
18869 
18871 #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
18872 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
18873 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
18874 
18876 #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
18877 
18881 #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
18882 #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
18883 
18885 #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
18886 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
18887 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
18888 
18890 #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
18891 
18895 #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
18896 #define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
18897 
18899 #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
18900 
18902 /* The count of FLEXSPI_RFDR */
18903 #define FLEXSPI_RFDR_COUNT (32U)
18904 
18907 #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
18908 #define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
18909 
18911 #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
18912 
18914 /* The count of FLEXSPI_TFDR */
18915 #define FLEXSPI_TFDR_COUNT (32U)
18916 
18919 #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
18920 #define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
18921 
18923 #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
18924 #define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
18925 #define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
18926 
18928 #define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
18929 #define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
18930 #define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
18931 
18933 #define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
18934 #define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
18935 #define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
18936 
18938 #define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
18939 #define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
18940 #define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
18941 
18943 #define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
18944 #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
18945 #define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
18946 
18948 #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
18949 
18951 /* The count of FLEXSPI_LUT */
18952 #define FLEXSPI_LUT_COUNT (64U)
18953 
18954  /* end of group FLEXSPI_Register_Masks */
18958 
18959 
18960 /* FLEXSPI - Peripheral instance base addresses */
18962 #define FLEXSPI_BASE (0x402A8000u)
18963 
18964 #define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
18965 
18966 #define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE }
18967 
18968 #define FLEXSPI_BASE_PTRS { FLEXSPI }
18969 
18970 #define FLEXSPI_IRQS { FLEXSPI_IRQn }
18971 /* FlexSPI AMBA address. */
18972 #define FlexSPI_AMBA_BASE (0x60000000U)
18973 /* FlexSPI ASFM address. */
18974 #define FlexSPI_ASFM_BASE (0x00000000U)
18975 /* Base Address of AHB address space mapped to IP RX FIFO. */
18976 #define FlexSPI_ARDF_BASE (0x7FC00000U)
18977 /* Base Address of AHB address space mapped to IP TX FIFO. */
18978 #define FlexSPI_ATDF_BASE (0x7F800000U)
18979 
18980  /* end of group FLEXSPI_Peripheral_Access_Layer */
18984 
18985 
18986 /* ----------------------------------------------------------------------------
18987  -- GPC Peripheral Access Layer
18988  ---------------------------------------------------------------------------- */
18989 
18996 typedef struct {
18997  __IO uint32_t CNTR;
18998  uint8_t RESERVED_0[4];
18999  __IO uint32_t IMR[4];
19000  __I uint32_t ISR[4];
19001  uint8_t RESERVED_1[12];
19002  __IO uint32_t IMR5;
19003  __I uint32_t ISR5;
19004 } GPC_Type;
19005 
19006 /* ----------------------------------------------------------------------------
19007  -- GPC Register Masks
19008  ---------------------------------------------------------------------------- */
19009 
19017 #define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
19018 #define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
19019 
19023 #define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
19024 #define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
19025 #define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
19026 
19030 #define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
19031 #define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
19032 #define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
19033 
19037 #define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
19038 
19042 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
19043 #define GPC_IMR_IMR1_SHIFT (0U)
19044 #define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
19045 #define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
19046 #define GPC_IMR_IMR2_SHIFT (0U)
19047 #define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
19048 #define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
19049 #define GPC_IMR_IMR3_SHIFT (0U)
19050 #define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
19051 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
19052 #define GPC_IMR_IMR4_SHIFT (0U)
19053 #define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
19054 
19056 /* The count of GPC_IMR */
19057 #define GPC_IMR_COUNT (4U)
19058 
19061 #define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
19062 #define GPC_ISR_ISR1_SHIFT (0U)
19063 #define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
19064 #define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
19065 #define GPC_ISR_ISR2_SHIFT (0U)
19066 #define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
19067 #define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
19068 #define GPC_ISR_ISR3_SHIFT (0U)
19069 #define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
19070 #define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
19071 #define GPC_ISR_ISR4_SHIFT (0U)
19072 #define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
19073 
19075 /* The count of GPC_ISR */
19076 #define GPC_ISR_COUNT (4U)
19077 
19080 #define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
19081 #define GPC_IMR5_IMR5_SHIFT (0U)
19082 #define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
19083 
19087 #define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)
19088 #define GPC_ISR5_ISR4_SHIFT (0U)
19089 #define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)
19090  /* end of group GPC_Register_Masks */
19096 
19097 
19098 /* GPC - Peripheral instance base addresses */
19100 #define GPC_BASE (0x400F4000u)
19101 
19102 #define GPC ((GPC_Type *)GPC_BASE)
19103 
19104 #define GPC_BASE_ADDRS { GPC_BASE }
19105 
19106 #define GPC_BASE_PTRS { GPC }
19107 
19108 #define GPC_IRQS { GPC_IRQn }
19109  /* end of group GPC_Peripheral_Access_Layer */
19113 
19114 
19115 /* ----------------------------------------------------------------------------
19116  -- GPIO Peripheral Access Layer
19117  ---------------------------------------------------------------------------- */
19118 
19125 typedef struct {
19126  __IO uint32_t DR;
19127  __IO uint32_t GDIR;
19128  __I uint32_t PSR;
19129  __IO uint32_t ICR1;
19130  __IO uint32_t ICR2;
19131  __IO uint32_t IMR;
19132  __IO uint32_t ISR;
19133  __IO uint32_t EDGE_SEL;
19134  uint8_t RESERVED_0[100];
19135  __O uint32_t DR_SET;
19136  __O uint32_t DR_CLEAR;
19137  __O uint32_t DR_TOGGLE;
19138 } GPIO_Type;
19139 
19140 /* ----------------------------------------------------------------------------
19141  -- GPIO Register Masks
19142  ---------------------------------------------------------------------------- */
19143 
19151 #define GPIO_DR_DR_MASK (0xFFFFFFFFU)
19152 #define GPIO_DR_DR_SHIFT (0U)
19153 
19155 #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
19156 
19160 #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
19161 #define GPIO_GDIR_GDIR_SHIFT (0U)
19162 
19164 #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
19165 
19169 #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
19170 #define GPIO_PSR_PSR_SHIFT (0U)
19171 
19173 #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
19174 
19178 #define GPIO_ICR1_ICR0_MASK (0x3U)
19179 #define GPIO_ICR1_ICR0_SHIFT (0U)
19180 
19186 #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
19187 #define GPIO_ICR1_ICR1_MASK (0xCU)
19188 #define GPIO_ICR1_ICR1_SHIFT (2U)
19189 
19195 #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
19196 #define GPIO_ICR1_ICR2_MASK (0x30U)
19197 #define GPIO_ICR1_ICR2_SHIFT (4U)
19198 
19204 #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
19205 #define GPIO_ICR1_ICR3_MASK (0xC0U)
19206 #define GPIO_ICR1_ICR3_SHIFT (6U)
19207 
19213 #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
19214 #define GPIO_ICR1_ICR4_MASK (0x300U)
19215 #define GPIO_ICR1_ICR4_SHIFT (8U)
19216 
19222 #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
19223 #define GPIO_ICR1_ICR5_MASK (0xC00U)
19224 #define GPIO_ICR1_ICR5_SHIFT (10U)
19225 
19231 #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
19232 #define GPIO_ICR1_ICR6_MASK (0x3000U)
19233 #define GPIO_ICR1_ICR6_SHIFT (12U)
19234 
19240 #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
19241 #define GPIO_ICR1_ICR7_MASK (0xC000U)
19242 #define GPIO_ICR1_ICR7_SHIFT (14U)
19243 
19249 #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
19250 #define GPIO_ICR1_ICR8_MASK (0x30000U)
19251 #define GPIO_ICR1_ICR8_SHIFT (16U)
19252 
19258 #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
19259 #define GPIO_ICR1_ICR9_MASK (0xC0000U)
19260 #define GPIO_ICR1_ICR9_SHIFT (18U)
19261 
19267 #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
19268 #define GPIO_ICR1_ICR10_MASK (0x300000U)
19269 #define GPIO_ICR1_ICR10_SHIFT (20U)
19270 
19276 #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
19277 #define GPIO_ICR1_ICR11_MASK (0xC00000U)
19278 #define GPIO_ICR1_ICR11_SHIFT (22U)
19279 
19285 #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
19286 #define GPIO_ICR1_ICR12_MASK (0x3000000U)
19287 #define GPIO_ICR1_ICR12_SHIFT (24U)
19288 
19294 #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
19295 #define GPIO_ICR1_ICR13_MASK (0xC000000U)
19296 #define GPIO_ICR1_ICR13_SHIFT (26U)
19297 
19303 #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
19304 #define GPIO_ICR1_ICR14_MASK (0x30000000U)
19305 #define GPIO_ICR1_ICR14_SHIFT (28U)
19306 
19312 #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
19313 #define GPIO_ICR1_ICR15_MASK (0xC0000000U)
19314 #define GPIO_ICR1_ICR15_SHIFT (30U)
19315 
19321 #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
19322 
19326 #define GPIO_ICR2_ICR16_MASK (0x3U)
19327 #define GPIO_ICR2_ICR16_SHIFT (0U)
19328 
19334 #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
19335 #define GPIO_ICR2_ICR17_MASK (0xCU)
19336 #define GPIO_ICR2_ICR17_SHIFT (2U)
19337 
19343 #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
19344 #define GPIO_ICR2_ICR18_MASK (0x30U)
19345 #define GPIO_ICR2_ICR18_SHIFT (4U)
19346 
19352 #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
19353 #define GPIO_ICR2_ICR19_MASK (0xC0U)
19354 #define GPIO_ICR2_ICR19_SHIFT (6U)
19355 
19361 #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
19362 #define GPIO_ICR2_ICR20_MASK (0x300U)
19363 #define GPIO_ICR2_ICR20_SHIFT (8U)
19364 
19370 #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
19371 #define GPIO_ICR2_ICR21_MASK (0xC00U)
19372 #define GPIO_ICR2_ICR21_SHIFT (10U)
19373 
19379 #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
19380 #define GPIO_ICR2_ICR22_MASK (0x3000U)
19381 #define GPIO_ICR2_ICR22_SHIFT (12U)
19382 
19388 #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
19389 #define GPIO_ICR2_ICR23_MASK (0xC000U)
19390 #define GPIO_ICR2_ICR23_SHIFT (14U)
19391 
19397 #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
19398 #define GPIO_ICR2_ICR24_MASK (0x30000U)
19399 #define GPIO_ICR2_ICR24_SHIFT (16U)
19400 
19406 #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
19407 #define GPIO_ICR2_ICR25_MASK (0xC0000U)
19408 #define GPIO_ICR2_ICR25_SHIFT (18U)
19409 
19415 #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
19416 #define GPIO_ICR2_ICR26_MASK (0x300000U)
19417 #define GPIO_ICR2_ICR26_SHIFT (20U)
19418 
19424 #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
19425 #define GPIO_ICR2_ICR27_MASK (0xC00000U)
19426 #define GPIO_ICR2_ICR27_SHIFT (22U)
19427 
19433 #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
19434 #define GPIO_ICR2_ICR28_MASK (0x3000000U)
19435 #define GPIO_ICR2_ICR28_SHIFT (24U)
19436 
19442 #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
19443 #define GPIO_ICR2_ICR29_MASK (0xC000000U)
19444 #define GPIO_ICR2_ICR29_SHIFT (26U)
19445 
19451 #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
19452 #define GPIO_ICR2_ICR30_MASK (0x30000000U)
19453 #define GPIO_ICR2_ICR30_SHIFT (28U)
19454 
19460 #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
19461 #define GPIO_ICR2_ICR31_MASK (0xC0000000U)
19462 #define GPIO_ICR2_ICR31_SHIFT (30U)
19463 
19469 #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
19470 
19474 #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
19475 #define GPIO_IMR_IMR_SHIFT (0U)
19476 
19478 #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
19479 
19483 #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
19484 #define GPIO_ISR_ISR_SHIFT (0U)
19485 
19487 #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
19488 
19492 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
19493 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
19494 
19496 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
19497 
19501 #define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
19502 #define GPIO_DR_SET_DR_SET_SHIFT (0U)
19503 
19505 #define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
19506 
19510 #define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
19511 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
19512 
19514 #define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
19515 
19519 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
19520 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
19521 
19523 #define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
19524  /* end of group GPIO_Register_Masks */
19530 
19531 
19532 /* GPIO - Peripheral instance base addresses */
19534 #define GPIO1_BASE (0x401B8000u)
19535 
19536 #define GPIO1 ((GPIO_Type *)GPIO1_BASE)
19537 
19538 #define GPIO2_BASE (0x401BC000u)
19539 
19540 #define GPIO2 ((GPIO_Type *)GPIO2_BASE)
19541 
19542 #define GPIO3_BASE (0x401C0000u)
19543 
19544 #define GPIO3 ((GPIO_Type *)GPIO3_BASE)
19545 
19546 #define GPIO4_BASE (0x401C4000u)
19547 
19548 #define GPIO4 ((GPIO_Type *)GPIO4_BASE)
19549 
19550 #define GPIO5_BASE (0x400C0000u)
19551 
19552 #define GPIO5 ((GPIO_Type *)GPIO5_BASE)
19553 
19554 #define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
19555 
19556 #define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
19557 
19558 #define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
19559 #define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
19560 #define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
19561  /* end of group GPIO_Peripheral_Access_Layer */
19565 
19566 
19567 /* ----------------------------------------------------------------------------
19568  -- GPT Peripheral Access Layer
19569  ---------------------------------------------------------------------------- */
19570 
19577 typedef struct {
19578  __IO uint32_t CR;
19579  __IO uint32_t PR;
19580  __IO uint32_t SR;
19581  __IO uint32_t IR;
19582  __IO uint32_t OCR[3];
19583  __I uint32_t ICR[2];
19584  __I uint32_t CNT;
19585 } GPT_Type;
19586 
19587 /* ----------------------------------------------------------------------------
19588  -- GPT Register Masks
19589  ---------------------------------------------------------------------------- */
19590 
19598 #define GPT_CR_EN_MASK (0x1U)
19599 #define GPT_CR_EN_SHIFT (0U)
19600 
19604 #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
19605 #define GPT_CR_ENMOD_MASK (0x2U)
19606 #define GPT_CR_ENMOD_SHIFT (1U)
19607 
19611 #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
19612 #define GPT_CR_DBGEN_MASK (0x4U)
19613 #define GPT_CR_DBGEN_SHIFT (2U)
19614 
19618 #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
19619 #define GPT_CR_WAITEN_MASK (0x8U)
19620 #define GPT_CR_WAITEN_SHIFT (3U)
19621 
19625 #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
19626 #define GPT_CR_DOZEEN_MASK (0x10U)
19627 #define GPT_CR_DOZEEN_SHIFT (4U)
19628 
19632 #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
19633 #define GPT_CR_STOPEN_MASK (0x20U)
19634 #define GPT_CR_STOPEN_SHIFT (5U)
19635 
19639 #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
19640 #define GPT_CR_CLKSRC_MASK (0x1C0U)
19641 #define GPT_CR_CLKSRC_SHIFT (6U)
19642 
19650 #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
19651 #define GPT_CR_FRR_MASK (0x200U)
19652 #define GPT_CR_FRR_SHIFT (9U)
19653 
19657 #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
19658 #define GPT_CR_EN_24M_MASK (0x400U)
19659 #define GPT_CR_EN_24M_SHIFT (10U)
19660 
19664 #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
19665 #define GPT_CR_SWR_MASK (0x8000U)
19666 #define GPT_CR_SWR_SHIFT (15U)
19667 
19671 #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
19672 #define GPT_CR_IM1_MASK (0x30000U)
19673 #define GPT_CR_IM1_SHIFT (16U)
19674 #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
19675 #define GPT_CR_IM2_MASK (0xC0000U)
19676 #define GPT_CR_IM2_SHIFT (18U)
19677 
19683 #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
19684 #define GPT_CR_OM1_MASK (0x700000U)
19685 #define GPT_CR_OM1_SHIFT (20U)
19686 #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
19687 #define GPT_CR_OM2_MASK (0x3800000U)
19688 #define GPT_CR_OM2_SHIFT (23U)
19689 #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
19690 #define GPT_CR_OM3_MASK (0x1C000000U)
19691 #define GPT_CR_OM3_SHIFT (26U)
19692 
19699 #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
19700 #define GPT_CR_FO1_MASK (0x20000000U)
19701 #define GPT_CR_FO1_SHIFT (29U)
19702 #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
19703 #define GPT_CR_FO2_MASK (0x40000000U)
19704 #define GPT_CR_FO2_SHIFT (30U)
19705 #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
19706 #define GPT_CR_FO3_MASK (0x80000000U)
19707 #define GPT_CR_FO3_SHIFT (31U)
19708 
19712 #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
19713 
19717 #define GPT_PR_PRESCALER_MASK (0xFFFU)
19718 #define GPT_PR_PRESCALER_SHIFT (0U)
19719 
19724 #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
19725 #define GPT_PR_PRESCALER24M_MASK (0xF000U)
19726 #define GPT_PR_PRESCALER24M_SHIFT (12U)
19727 
19732 #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
19733 
19737 #define GPT_SR_OF1_MASK (0x1U)
19738 #define GPT_SR_OF1_SHIFT (0U)
19739 #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
19740 #define GPT_SR_OF2_MASK (0x2U)
19741 #define GPT_SR_OF2_SHIFT (1U)
19742 #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
19743 #define GPT_SR_OF3_MASK (0x4U)
19744 #define GPT_SR_OF3_SHIFT (2U)
19745 
19749 #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
19750 #define GPT_SR_IF1_MASK (0x8U)
19751 #define GPT_SR_IF1_SHIFT (3U)
19752 #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
19753 #define GPT_SR_IF2_MASK (0x10U)
19754 #define GPT_SR_IF2_SHIFT (4U)
19755 
19759 #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
19760 #define GPT_SR_ROV_MASK (0x20U)
19761 #define GPT_SR_ROV_SHIFT (5U)
19762 
19766 #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
19767 
19771 #define GPT_IR_OF1IE_MASK (0x1U)
19772 #define GPT_IR_OF1IE_SHIFT (0U)
19773 #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
19774 #define GPT_IR_OF2IE_MASK (0x2U)
19775 #define GPT_IR_OF2IE_SHIFT (1U)
19776 #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
19777 #define GPT_IR_OF3IE_MASK (0x4U)
19778 #define GPT_IR_OF3IE_SHIFT (2U)
19779 
19783 #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
19784 #define GPT_IR_IF1IE_MASK (0x8U)
19785 #define GPT_IR_IF1IE_SHIFT (3U)
19786 #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
19787 #define GPT_IR_IF2IE_MASK (0x10U)
19788 #define GPT_IR_IF2IE_SHIFT (4U)
19789 
19793 #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
19794 #define GPT_IR_ROVIE_MASK (0x20U)
19795 #define GPT_IR_ROVIE_SHIFT (5U)
19796 
19800 #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
19801 
19805 #define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
19806 #define GPT_OCR_COMP_SHIFT (0U)
19807 #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
19808 
19810 /* The count of GPT_OCR */
19811 #define GPT_OCR_COUNT (3U)
19812 
19815 #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
19816 #define GPT_ICR_CAPT_SHIFT (0U)
19817 #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
19818 
19820 /* The count of GPT_ICR */
19821 #define GPT_ICR_COUNT (2U)
19822 
19825 #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
19826 #define GPT_CNT_COUNT_SHIFT (0U)
19827 #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
19828  /* end of group GPT_Register_Masks */
19834 
19835 
19836 /* GPT - Peripheral instance base addresses */
19838 #define GPT1_BASE (0x401EC000u)
19839 
19840 #define GPT1 ((GPT_Type *)GPT1_BASE)
19841 
19842 #define GPT2_BASE (0x401F0000u)
19843 
19844 #define GPT2 ((GPT_Type *)GPT2_BASE)
19845 
19846 #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
19847 
19848 #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
19849 
19850 #define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
19851  /* end of group GPT_Peripheral_Access_Layer */
19855 
19856 
19857 /* ----------------------------------------------------------------------------
19858  -- I2S Peripheral Access Layer
19859  ---------------------------------------------------------------------------- */
19860 
19867 typedef struct {
19868  __I uint32_t VERID;
19869  __I uint32_t PARAM;
19870  __IO uint32_t TCSR;
19871  __IO uint32_t TCR1;
19872  __IO uint32_t TCR2;
19873  __IO uint32_t TCR3;
19874  __IO uint32_t TCR4;
19875  __IO uint32_t TCR5;
19876  __O uint32_t TDR[4];
19877  uint8_t RESERVED_0[16];
19878  __I uint32_t TFR[4];
19879  uint8_t RESERVED_1[16];
19880  __IO uint32_t TMR;
19881  uint8_t RESERVED_2[36];
19882  __IO uint32_t RCSR;
19883  __IO uint32_t RCR1;
19884  __IO uint32_t RCR2;
19885  __IO uint32_t RCR3;
19886  __IO uint32_t RCR4;
19887  __IO uint32_t RCR5;
19888  __I uint32_t RDR[4];
19889  uint8_t RESERVED_3[16];
19890  __I uint32_t RFR[4];
19891  uint8_t RESERVED_4[16];
19892  __IO uint32_t RMR;
19893 } I2S_Type;
19894 
19895 /* ----------------------------------------------------------------------------
19896  -- I2S Register Masks
19897  ---------------------------------------------------------------------------- */
19898 
19906 #define I2S_VERID_FEATURE_MASK (0xFFFFU)
19907 #define I2S_VERID_FEATURE_SHIFT (0U)
19908 
19911 #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
19912 #define I2S_VERID_MINOR_MASK (0xFF0000U)
19913 #define I2S_VERID_MINOR_SHIFT (16U)
19914 
19916 #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
19917 #define I2S_VERID_MAJOR_MASK (0xFF000000U)
19918 #define I2S_VERID_MAJOR_SHIFT (24U)
19919 
19921 #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
19922 
19926 #define I2S_PARAM_DATALINE_MASK (0xFU)
19927 #define I2S_PARAM_DATALINE_SHIFT (0U)
19928 
19930 #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
19931 #define I2S_PARAM_FIFO_MASK (0xF00U)
19932 #define I2S_PARAM_FIFO_SHIFT (8U)
19933 
19935 #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
19936 #define I2S_PARAM_FRAME_MASK (0xF0000U)
19937 #define I2S_PARAM_FRAME_SHIFT (16U)
19938 
19940 #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
19941 
19945 #define I2S_TCSR_FRDE_MASK (0x1U)
19946 #define I2S_TCSR_FRDE_SHIFT (0U)
19947 
19951 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
19952 #define I2S_TCSR_FWDE_MASK (0x2U)
19953 #define I2S_TCSR_FWDE_SHIFT (1U)
19954 
19958 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
19959 #define I2S_TCSR_FRIE_MASK (0x100U)
19960 #define I2S_TCSR_FRIE_SHIFT (8U)
19961 
19965 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
19966 #define I2S_TCSR_FWIE_MASK (0x200U)
19967 #define I2S_TCSR_FWIE_SHIFT (9U)
19968 
19972 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
19973 #define I2S_TCSR_FEIE_MASK (0x400U)
19974 #define I2S_TCSR_FEIE_SHIFT (10U)
19975 
19979 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
19980 #define I2S_TCSR_SEIE_MASK (0x800U)
19981 #define I2S_TCSR_SEIE_SHIFT (11U)
19982 
19986 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
19987 #define I2S_TCSR_WSIE_MASK (0x1000U)
19988 #define I2S_TCSR_WSIE_SHIFT (12U)
19989 
19993 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
19994 #define I2S_TCSR_FRF_MASK (0x10000U)
19995 #define I2S_TCSR_FRF_SHIFT (16U)
19996 
20000 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
20001 #define I2S_TCSR_FWF_MASK (0x20000U)
20002 #define I2S_TCSR_FWF_SHIFT (17U)
20003 
20007 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
20008 #define I2S_TCSR_FEF_MASK (0x40000U)
20009 #define I2S_TCSR_FEF_SHIFT (18U)
20010 
20014 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
20015 #define I2S_TCSR_SEF_MASK (0x80000U)
20016 #define I2S_TCSR_SEF_SHIFT (19U)
20017 
20021 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
20022 #define I2S_TCSR_WSF_MASK (0x100000U)
20023 #define I2S_TCSR_WSF_SHIFT (20U)
20024 
20028 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
20029 #define I2S_TCSR_SR_MASK (0x1000000U)
20030 #define I2S_TCSR_SR_SHIFT (24U)
20031 
20035 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
20036 #define I2S_TCSR_FR_MASK (0x2000000U)
20037 #define I2S_TCSR_FR_SHIFT (25U)
20038 
20042 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
20043 #define I2S_TCSR_BCE_MASK (0x10000000U)
20044 #define I2S_TCSR_BCE_SHIFT (28U)
20045 
20049 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
20050 #define I2S_TCSR_DBGE_MASK (0x20000000U)
20051 #define I2S_TCSR_DBGE_SHIFT (29U)
20052 
20056 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
20057 #define I2S_TCSR_STOPE_MASK (0x40000000U)
20058 #define I2S_TCSR_STOPE_SHIFT (30U)
20059 
20063 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
20064 #define I2S_TCSR_TE_MASK (0x80000000U)
20065 #define I2S_TCSR_TE_SHIFT (31U)
20066 
20070 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
20071 
20075 #define I2S_TCR1_TFW_MASK (0x1FU)
20076 #define I2S_TCR1_TFW_SHIFT (0U)
20077 
20079 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
20080 
20084 #define I2S_TCR2_DIV_MASK (0xFFU)
20085 #define I2S_TCR2_DIV_SHIFT (0U)
20086 
20088 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
20089 #define I2S_TCR2_BCD_MASK (0x1000000U)
20090 #define I2S_TCR2_BCD_SHIFT (24U)
20091 
20095 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
20096 #define I2S_TCR2_BCP_MASK (0x2000000U)
20097 #define I2S_TCR2_BCP_SHIFT (25U)
20098 
20102 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
20103 #define I2S_TCR2_MSEL_MASK (0xC000000U)
20104 #define I2S_TCR2_MSEL_SHIFT (26U)
20105 
20111 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
20112 #define I2S_TCR2_BCI_MASK (0x10000000U)
20113 #define I2S_TCR2_BCI_SHIFT (28U)
20114 
20118 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
20119 #define I2S_TCR2_BCS_MASK (0x20000000U)
20120 #define I2S_TCR2_BCS_SHIFT (29U)
20121 
20125 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
20126 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
20127 #define I2S_TCR2_SYNC_SHIFT (30U)
20128 
20134 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
20135 
20139 #define I2S_TCR3_WDFL_MASK (0x1FU)
20140 #define I2S_TCR3_WDFL_SHIFT (0U)
20141 
20143 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
20144 #define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
20145 #define I2S_TCR3_TCE_SHIFT (16U)
20146 
20148 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
20149 #define I2S_TCR3_CFR_MASK (0xF000000U)
20150 #define I2S_TCR3_CFR_SHIFT (24U)
20151 
20153 #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
20154 
20158 #define I2S_TCR4_FSD_MASK (0x1U)
20159 #define I2S_TCR4_FSD_SHIFT (0U)
20160 
20164 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
20165 #define I2S_TCR4_FSP_MASK (0x2U)
20166 #define I2S_TCR4_FSP_SHIFT (1U)
20167 
20171 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
20172 #define I2S_TCR4_ONDEM_MASK (0x4U)
20173 #define I2S_TCR4_ONDEM_SHIFT (2U)
20174 
20178 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
20179 #define I2S_TCR4_FSE_MASK (0x8U)
20180 #define I2S_TCR4_FSE_SHIFT (3U)
20181 
20185 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
20186 #define I2S_TCR4_MF_MASK (0x10U)
20187 #define I2S_TCR4_MF_SHIFT (4U)
20188 
20192 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
20193 #define I2S_TCR4_CHMOD_MASK (0x20U)
20194 #define I2S_TCR4_CHMOD_SHIFT (5U)
20195 
20199 #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
20200 #define I2S_TCR4_SYWD_MASK (0x1F00U)
20201 #define I2S_TCR4_SYWD_SHIFT (8U)
20202 
20204 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
20205 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
20206 #define I2S_TCR4_FRSZ_SHIFT (16U)
20207 
20209 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
20210 #define I2S_TCR4_FPACK_MASK (0x3000000U)
20211 #define I2S_TCR4_FPACK_SHIFT (24U)
20212 
20218 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
20219 #define I2S_TCR4_FCOMB_MASK (0xC000000U)
20220 #define I2S_TCR4_FCOMB_SHIFT (26U)
20221 
20227 #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
20228 #define I2S_TCR4_FCONT_MASK (0x10000000U)
20229 #define I2S_TCR4_FCONT_SHIFT (28U)
20230 
20234 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
20235 
20239 #define I2S_TCR5_FBT_MASK (0x1F00U)
20240 #define I2S_TCR5_FBT_SHIFT (8U)
20241 
20243 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
20244 #define I2S_TCR5_W0W_MASK (0x1F0000U)
20245 #define I2S_TCR5_W0W_SHIFT (16U)
20246 
20248 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
20249 #define I2S_TCR5_WNW_MASK (0x1F000000U)
20250 #define I2S_TCR5_WNW_SHIFT (24U)
20251 
20253 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
20254 
20258 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
20259 #define I2S_TDR_TDR_SHIFT (0U)
20260 
20262 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
20263 
20265 /* The count of I2S_TDR */
20266 #define I2S_TDR_COUNT (4U)
20267 
20270 #define I2S_TFR_RFP_MASK (0x3FU)
20271 #define I2S_TFR_RFP_SHIFT (0U)
20272 
20274 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
20275 #define I2S_TFR_WFP_MASK (0x3F0000U)
20276 #define I2S_TFR_WFP_SHIFT (16U)
20277 
20279 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
20280 #define I2S_TFR_WCP_MASK (0x80000000U)
20281 #define I2S_TFR_WCP_SHIFT (31U)
20282 
20286 #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
20287 
20289 /* The count of I2S_TFR */
20290 #define I2S_TFR_COUNT (4U)
20291 
20294 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
20295 #define I2S_TMR_TWM_SHIFT (0U)
20296 
20300 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
20301 
20305 #define I2S_RCSR_FRDE_MASK (0x1U)
20306 #define I2S_RCSR_FRDE_SHIFT (0U)
20307 
20311 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
20312 #define I2S_RCSR_FWDE_MASK (0x2U)
20313 #define I2S_RCSR_FWDE_SHIFT (1U)
20314 
20318 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
20319 #define I2S_RCSR_FRIE_MASK (0x100U)
20320 #define I2S_RCSR_FRIE_SHIFT (8U)
20321 
20325 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
20326 #define I2S_RCSR_FWIE_MASK (0x200U)
20327 #define I2S_RCSR_FWIE_SHIFT (9U)
20328 
20332 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
20333 #define I2S_RCSR_FEIE_MASK (0x400U)
20334 #define I2S_RCSR_FEIE_SHIFT (10U)
20335 
20339 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
20340 #define I2S_RCSR_SEIE_MASK (0x800U)
20341 #define I2S_RCSR_SEIE_SHIFT (11U)
20342 
20346 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
20347 #define I2S_RCSR_WSIE_MASK (0x1000U)
20348 #define I2S_RCSR_WSIE_SHIFT (12U)
20349 
20353 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
20354 #define I2S_RCSR_FRF_MASK (0x10000U)
20355 #define I2S_RCSR_FRF_SHIFT (16U)
20356 
20360 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
20361 #define I2S_RCSR_FWF_MASK (0x20000U)
20362 #define I2S_RCSR_FWF_SHIFT (17U)
20363 
20367 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
20368 #define I2S_RCSR_FEF_MASK (0x40000U)
20369 #define I2S_RCSR_FEF_SHIFT (18U)
20370 
20374 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
20375 #define I2S_RCSR_SEF_MASK (0x80000U)
20376 #define I2S_RCSR_SEF_SHIFT (19U)
20377 
20381 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
20382 #define I2S_RCSR_WSF_MASK (0x100000U)
20383 #define I2S_RCSR_WSF_SHIFT (20U)
20384 
20388 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
20389 #define I2S_RCSR_SR_MASK (0x1000000U)
20390 #define I2S_RCSR_SR_SHIFT (24U)
20391 
20395 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
20396 #define I2S_RCSR_FR_MASK (0x2000000U)
20397 #define I2S_RCSR_FR_SHIFT (25U)
20398 
20402 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
20403 #define I2S_RCSR_BCE_MASK (0x10000000U)
20404 #define I2S_RCSR_BCE_SHIFT (28U)
20405 
20409 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
20410 #define I2S_RCSR_DBGE_MASK (0x20000000U)
20411 #define I2S_RCSR_DBGE_SHIFT (29U)
20412 
20416 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
20417 #define I2S_RCSR_STOPE_MASK (0x40000000U)
20418 #define I2S_RCSR_STOPE_SHIFT (30U)
20419 
20423 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
20424 #define I2S_RCSR_RE_MASK (0x80000000U)
20425 #define I2S_RCSR_RE_SHIFT (31U)
20426 
20430 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
20431 
20435 #define I2S_RCR1_RFW_MASK (0x1FU)
20436 #define I2S_RCR1_RFW_SHIFT (0U)
20437 
20439 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
20440 
20444 #define I2S_RCR2_DIV_MASK (0xFFU)
20445 #define I2S_RCR2_DIV_SHIFT (0U)
20446 
20448 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
20449 #define I2S_RCR2_BCD_MASK (0x1000000U)
20450 #define I2S_RCR2_BCD_SHIFT (24U)
20451 
20455 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
20456 #define I2S_RCR2_BCP_MASK (0x2000000U)
20457 #define I2S_RCR2_BCP_SHIFT (25U)
20458 
20462 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
20463 #define I2S_RCR2_MSEL_MASK (0xC000000U)
20464 #define I2S_RCR2_MSEL_SHIFT (26U)
20465 
20471 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
20472 #define I2S_RCR2_BCI_MASK (0x10000000U)
20473 #define I2S_RCR2_BCI_SHIFT (28U)
20474 
20478 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
20479 #define I2S_RCR2_BCS_MASK (0x20000000U)
20480 #define I2S_RCR2_BCS_SHIFT (29U)
20481 
20485 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
20486 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
20487 #define I2S_RCR2_SYNC_SHIFT (30U)
20488 
20494 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
20495 
20499 #define I2S_RCR3_WDFL_MASK (0x1FU)
20500 #define I2S_RCR3_WDFL_SHIFT (0U)
20501 
20503 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
20504 #define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
20505 #define I2S_RCR3_RCE_SHIFT (16U)
20506 
20508 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
20509 #define I2S_RCR3_CFR_MASK (0xF000000U)
20510 #define I2S_RCR3_CFR_SHIFT (24U)
20511 
20513 #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
20514 
20518 #define I2S_RCR4_FSD_MASK (0x1U)
20519 #define I2S_RCR4_FSD_SHIFT (0U)
20520 
20524 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
20525 #define I2S_RCR4_FSP_MASK (0x2U)
20526 #define I2S_RCR4_FSP_SHIFT (1U)
20527 
20531 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
20532 #define I2S_RCR4_ONDEM_MASK (0x4U)
20533 #define I2S_RCR4_ONDEM_SHIFT (2U)
20534 
20538 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
20539 #define I2S_RCR4_FSE_MASK (0x8U)
20540 #define I2S_RCR4_FSE_SHIFT (3U)
20541 
20545 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
20546 #define I2S_RCR4_MF_MASK (0x10U)
20547 #define I2S_RCR4_MF_SHIFT (4U)
20548 
20552 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
20553 #define I2S_RCR4_SYWD_MASK (0x1F00U)
20554 #define I2S_RCR4_SYWD_SHIFT (8U)
20555 
20557 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
20558 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
20559 #define I2S_RCR4_FRSZ_SHIFT (16U)
20560 
20562 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
20563 #define I2S_RCR4_FPACK_MASK (0x3000000U)
20564 #define I2S_RCR4_FPACK_SHIFT (24U)
20565 
20571 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
20572 #define I2S_RCR4_FCOMB_MASK (0xC000000U)
20573 #define I2S_RCR4_FCOMB_SHIFT (26U)
20574 
20580 #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
20581 #define I2S_RCR4_FCONT_MASK (0x10000000U)
20582 #define I2S_RCR4_FCONT_SHIFT (28U)
20583 
20587 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
20588 
20592 #define I2S_RCR5_FBT_MASK (0x1F00U)
20593 #define I2S_RCR5_FBT_SHIFT (8U)
20594 
20596 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
20597 #define I2S_RCR5_W0W_MASK (0x1F0000U)
20598 #define I2S_RCR5_W0W_SHIFT (16U)
20599 
20601 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
20602 #define I2S_RCR5_WNW_MASK (0x1F000000U)
20603 #define I2S_RCR5_WNW_SHIFT (24U)
20604 
20606 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
20607 
20611 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
20612 #define I2S_RDR_RDR_SHIFT (0U)
20613 
20615 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
20616 
20618 /* The count of I2S_RDR */
20619 #define I2S_RDR_COUNT (4U)
20620 
20623 #define I2S_RFR_RFP_MASK (0x3FU)
20624 #define I2S_RFR_RFP_SHIFT (0U)
20625 
20627 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
20628 #define I2S_RFR_RCP_MASK (0x8000U)
20629 #define I2S_RFR_RCP_SHIFT (15U)
20630 
20634 #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
20635 #define I2S_RFR_WFP_MASK (0x3F0000U)
20636 #define I2S_RFR_WFP_SHIFT (16U)
20637 
20639 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
20640 
20642 /* The count of I2S_RFR */
20643 #define I2S_RFR_COUNT (4U)
20644 
20647 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
20648 #define I2S_RMR_RWM_SHIFT (0U)
20649 
20653 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
20654  /* end of group I2S_Register_Masks */
20660 
20661 
20662 /* I2S - Peripheral instance base addresses */
20664 #define SAI1_BASE (0x40384000u)
20665 
20666 #define SAI1 ((I2S_Type *)SAI1_BASE)
20667 
20668 #define SAI2_BASE (0x40388000u)
20669 
20670 #define SAI2 ((I2S_Type *)SAI2_BASE)
20671 
20672 #define SAI3_BASE (0x4038C000u)
20673 
20674 #define SAI3 ((I2S_Type *)SAI3_BASE)
20675 
20676 #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
20677 
20678 #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
20679 
20680 #define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
20681 #define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
20682  /* end of group I2S_Peripheral_Access_Layer */
20686 
20687 
20688 /* ----------------------------------------------------------------------------
20689  -- IOMUXC Peripheral Access Layer
20690  ---------------------------------------------------------------------------- */
20691 
20698 typedef struct {
20699  uint8_t RESERVED_0[20];
20700  __IO uint32_t SW_MUX_CTL_PAD[124];
20701  __IO uint32_t SW_PAD_CTL_PAD[124];
20702  __IO uint32_t SELECT_INPUT[154];
20703 } IOMUXC_Type;
20704 
20705 /* ----------------------------------------------------------------------------
20706  -- IOMUXC Register Masks
20707  ---------------------------------------------------------------------------- */
20708 
20716 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
20717 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
20718 
20726 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
20727 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
20728 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
20729 
20733 #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
20734 
20736 /* The count of IOMUXC_SW_MUX_CTL_PAD */
20737 #define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)
20738 
20741 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
20742 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
20743 
20747 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
20748 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
20749 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
20750 
20760 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
20761 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
20762 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
20763 
20769 #define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
20770 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
20771 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
20772 
20776 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
20777 #define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
20778 #define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
20779 
20783 #define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
20784 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
20785 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
20786 
20790 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
20791 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
20792 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
20793 
20799 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
20800 #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
20801 #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
20802 
20806 #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
20807 
20809 /* The count of IOMUXC_SW_PAD_CTL_PAD */
20810 #define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)
20811 
20814 #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
20815 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
20816 
20820 #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
20821 
20823 /* The count of IOMUXC_SELECT_INPUT */
20824 #define IOMUXC_SELECT_INPUT_COUNT (154U)
20825 
20826  /* end of group IOMUXC_Register_Masks */
20830 
20831 
20832 /* IOMUXC - Peripheral instance base addresses */
20834 #define IOMUXC_BASE (0x401F8000u)
20835 
20836 #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
20837 
20838 #define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
20839 
20840 #define IOMUXC_BASE_PTRS { IOMUXC }
20841  /* end of group IOMUXC_Peripheral_Access_Layer */
20845 
20846 
20847 /* ----------------------------------------------------------------------------
20848  -- IOMUXC_GPR Peripheral Access Layer
20849  ---------------------------------------------------------------------------- */
20850 
20857 typedef struct {
20858  uint32_t GPR0;
20859  __IO uint32_t GPR1;
20860  __IO uint32_t GPR2;
20861  __IO uint32_t GPR3;
20862  __IO uint32_t GPR4;
20863  __IO uint32_t GPR5;
20864  __IO uint32_t GPR6;
20865  __IO uint32_t GPR7;
20866  __IO uint32_t GPR8;
20867  uint32_t GPR9;
20868  __IO uint32_t GPR10;
20869  __IO uint32_t GPR11;
20870  __IO uint32_t GPR12;
20871  __IO uint32_t GPR13;
20872  __IO uint32_t GPR14;
20873  uint32_t GPR15;
20874  __IO uint32_t GPR16;
20875  __IO uint32_t GPR17;
20876  __IO uint32_t GPR18;
20877  __IO uint32_t GPR19;
20878  __IO uint32_t GPR20;
20879  __IO uint32_t GPR21;
20880  __IO uint32_t GPR22;
20881  __IO uint32_t GPR23;
20882  __IO uint32_t GPR24;
20883  __IO uint32_t GPR25;
20884 } IOMUXC_GPR_Type;
20885 
20886 /* ----------------------------------------------------------------------------
20887  -- IOMUXC_GPR Register Masks
20888  ---------------------------------------------------------------------------- */
20889 
20897 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
20898 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
20899 
20909 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
20910 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
20911 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
20912 
20922 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
20923 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
20924 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
20925 
20931 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
20932 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
20933 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
20934 
20940 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
20941 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
20942 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
20943 
20949 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
20950 #define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
20951 #define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
20952 
20956 #define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
20957 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)
20958 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)
20959 
20964 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
20965 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)
20966 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)
20967 
20971 #define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
20972 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)
20973 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)
20974 
20978 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
20979 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
20980 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
20981 
20985 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
20986 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
20987 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
20988 
20992 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
20993 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
20994 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
20995 
20999 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
21000 #define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
21001 #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
21002 
21006 #define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
21007 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)
21008 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)
21009 
21013 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
21014 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
21015 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
21016 
21020 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
21021 
21025 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
21026 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
21027 
21031 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
21032 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
21033 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
21034 
21038 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
21039 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
21040 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
21041 
21299 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
21300 #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
21301 #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
21302 
21306 #define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
21307 #define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
21308 #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
21309 
21313 #define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
21314 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
21315 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
21316 
21320 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
21321 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
21322 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
21323 
21327 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
21328 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
21329 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
21330 
21334 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
21335 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
21336 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
21337 
21341 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
21342 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
21343 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
21344 
21348 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
21349 
21353 #define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)
21354 #define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)
21355 #define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
21356 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
21357 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
21358 
21362 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
21363 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)
21364 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)
21365 
21369 #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
21370 
21374 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
21375 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
21376 
21380 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
21381 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
21382 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
21383 
21387 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
21388 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
21389 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
21390 
21394 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
21395 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
21396 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
21397 
21401 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
21402 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
21403 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
21404 
21408 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
21409 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
21410 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
21411 
21415 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
21416 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
21417 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
21418 
21422 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
21423 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
21424 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
21425 
21429 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
21430 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
21431 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
21432 
21436 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
21437 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
21438 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
21439 
21443 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
21444 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
21445 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
21446 
21450 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
21451 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
21452 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
21453 
21457 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
21458 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
21459 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
21460 
21464 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
21465 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
21466 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
21467 
21471 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
21472 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
21473 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
21474 
21478 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
21479 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
21480 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
21481 
21485 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
21486 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
21487 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
21488 
21492 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
21493 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
21494 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
21495 
21499 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
21500 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
21501 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
21502 
21506 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
21507 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
21508 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
21509 
21513 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
21514 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
21515 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
21516 
21520 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
21521 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
21522 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
21523 
21527 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
21528 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
21529 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
21530 
21534 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
21535 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
21536 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
21537 
21541 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
21542 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
21543 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
21544 
21548 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
21549 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
21550 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
21551 
21555 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
21556 
21560 #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
21561 #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
21562 
21566 #define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
21567 #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
21568 #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
21569 
21573 #define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
21574 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
21575 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
21576 
21580 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
21581 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
21582 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
21583 
21587 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
21588 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
21589 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
21590 
21594 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
21595 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
21596 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
21597 
21601 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
21602 
21606 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
21607 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
21608 
21612 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
21613 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
21614 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
21615 
21619 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
21620 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
21621 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
21622 
21626 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
21627 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
21628 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
21629 
21633 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
21634 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
21635 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
21636 
21640 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
21641 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
21642 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
21643 
21647 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
21648 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
21649 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
21650 
21654 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
21655 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
21656 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
21657 
21661 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
21662 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
21663 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
21664 
21668 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
21669 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
21670 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
21671 
21675 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
21676 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
21677 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
21678 
21682 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
21683 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
21684 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
21685 
21689 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
21690 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
21691 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
21692 
21696 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
21697 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
21698 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
21699 
21703 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
21704 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
21705 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
21706 
21710 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
21711 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
21712 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
21713 
21717 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
21718 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
21719 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
21720 
21724 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
21725 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
21726 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
21727 
21731 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
21732 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
21733 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
21734 
21738 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
21739 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
21740 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
21741 
21745 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
21746 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
21747 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
21748 
21752 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
21753 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
21754 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
21755 
21759 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
21760 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
21761 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
21762 
21766 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
21767 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
21768 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
21769 
21773 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
21774 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
21775 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
21776 
21780 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
21781 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
21782 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
21783 
21787 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
21788 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
21789 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
21790 
21794 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
21795 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
21796 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
21797 
21801 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
21802 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
21803 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
21804 
21808 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
21809 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
21810 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
21811 
21815 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
21816 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
21817 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
21818 
21822 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
21823 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
21824 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
21825 
21829 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
21830 
21834 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
21835 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
21836 
21840 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
21841 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
21842 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
21843 
21847 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
21848 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
21849 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
21850 
21854 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
21855 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
21856 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
21857 
21861 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
21862 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
21863 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
21864 
21868 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
21869 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
21870 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
21871 
21875 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
21876 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
21877 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
21878 
21882 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
21883 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
21884 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
21885 
21889 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
21890 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
21891 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
21892 
21896 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
21897 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
21898 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
21899 
21903 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
21904 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
21905 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
21906 
21910 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
21911 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
21912 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
21913 
21917 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
21918 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
21919 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
21920 
21924 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
21925 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
21926 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
21927 
21931 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
21932 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
21933 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
21934 
21938 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
21939 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
21940 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
21941 
21945 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
21946 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
21947 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
21948 
21952 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
21953 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
21954 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
21955 
21959 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
21960 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
21961 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
21962 
21966 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
21967 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
21968 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
21969 
21973 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
21974 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
21975 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
21976 
21980 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
21981 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
21982 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
21983 
21987 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
21988 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
21989 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
21990 
21994 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
21995 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
21996 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
21997 
22001 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
22002 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
22003 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
22004 
22008 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
22009 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
22010 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
22011 
22015 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
22016 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
22017 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
22018 
22022 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
22023 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
22024 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
22025 
22029 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
22030 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
22031 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
22032 
22036 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
22037 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
22038 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
22039 
22043 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
22044 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
22045 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
22046 
22050 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
22051 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
22052 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
22053 
22057 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
22058 
22062 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
22063 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
22064 
22068 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
22069 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
22070 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
22071 
22075 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
22076 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
22077 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
22078 
22082 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
22083 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
22084 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
22085 
22089 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
22090 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
22091 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
22092 
22096 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
22097 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
22098 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
22099 
22103 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
22104 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
22105 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
22106 
22110 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
22111 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
22112 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
22113 
22117 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
22118 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
22119 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
22120 
22124 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
22125 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
22126 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
22127 
22131 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
22132 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
22133 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
22134 
22138 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
22139 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
22140 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
22141 
22145 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
22146 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
22147 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
22148 
22152 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
22153 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
22154 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
22155 
22159 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
22160 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
22161 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
22162 
22166 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
22167 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
22168 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
22169 
22173 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
22174 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
22175 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
22176 
22180 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
22181 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
22182 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
22183 
22187 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
22188 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
22189 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
22190 
22194 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
22195 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
22196 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
22197 
22201 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
22202 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
22203 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
22204 
22208 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
22209 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
22210 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
22211 
22215 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
22216 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
22217 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
22218 
22222 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
22223 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
22224 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
22225 
22229 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
22230 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
22231 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
22232 
22236 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
22237 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
22238 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
22239 
22243 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
22244 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
22245 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
22246 
22250 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
22251 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
22252 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
22253 
22257 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
22258 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
22259 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
22260 
22264 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
22265 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
22266 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
22267 
22271 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
22272 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
22273 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
22274 
22278 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
22279 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
22280 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
22281 
22285 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
22286 
22290 #define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
22291 #define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
22292 
22296 #define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
22297 #define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
22298 #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
22299 
22303 #define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
22304 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
22305 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
22306 
22310 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
22311 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
22312 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
22313 
22317 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
22318 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
22319 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
22320 
22325 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
22326 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
22327 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
22328 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
22329 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
22330 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
22331 
22335 #define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
22336 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
22337 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
22338 
22342 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
22343 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
22344 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
22345 
22349 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
22350 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
22351 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
22352 
22356 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
22357 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
22358 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
22359 
22363 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
22364 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
22365 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
22366 
22370 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
22371 
22375 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
22376 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
22377 
22383 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
22384 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
22385 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
22386 
22392 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
22393 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
22394 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
22395 
22401 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
22402 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
22403 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
22404 
22410 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
22411 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
22412 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
22413 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
22414 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)
22415 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)
22416 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
22417 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)
22418 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)
22419 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
22420 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)
22421 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)
22422 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
22423 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)
22424 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)
22425 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
22426 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)
22427 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)
22428 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
22429 
22433 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
22434 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
22435 
22439 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
22440 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
22441 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
22442 
22446 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
22447 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
22448 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
22449 
22453 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
22454 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
22455 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
22456 
22460 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
22461 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
22462 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
22463 
22467 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
22468 
22472 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
22473 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
22474 
22478 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
22479 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
22480 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
22481 
22485 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
22486 #define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
22487 #define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
22488 
22492 #define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
22493 #define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
22494 #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
22495 
22499 #define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
22500 
22504 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
22505 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
22506 
22510 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
22511 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
22512 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
22513 
22517 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
22518 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
22519 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
22520 
22524 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
22525 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
22526 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
22527 
22531 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
22532 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
22533 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
22534 
22538 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
22539 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
22540 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
22541 
22545 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
22546 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
22547 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
22548 
22552 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
22553 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
22554 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
22555 
22559 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
22560 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
22561 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
22562 
22566 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
22567 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
22568 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
22569 
22573 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
22574 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
22575 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
22576 
22580 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
22581 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
22582 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
22583 
22587 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
22588 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
22589 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
22590 
22601 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
22602 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
22603 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
22604 
22615 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
22616 
22620 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
22621 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
22622 
22626 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
22627 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
22628 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
22629 
22633 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
22634 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
22635 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
22636 
22640 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
22641 
22645 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
22646 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
22647 
22649 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
22650 
22654 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
22655 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
22656 
22660 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
22661 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
22662 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
22663 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
22664 
22668 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
22669 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
22670 
22674 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
22675 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
22676 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
22677 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
22678 
22682 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
22683 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
22684 
22688 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
22689 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
22690 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
22691 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
22692 
22696 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
22697 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
22698 
22702 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
22703 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
22704 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
22705 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
22706 
22710 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
22711 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
22712 
22716 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
22717 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
22718 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
22719 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
22720 
22724 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
22725 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
22726 
22730 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
22731 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
22732 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
22733 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
22734 
22738 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
22739 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
22740 
22744 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
22745 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
22746 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
22747 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
22748 
22752 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
22753 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
22754 
22758 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
22759 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
22760 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
22761 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
22762  /* end of group IOMUXC_GPR_Register_Masks */
22768 
22769 
22770 /* IOMUXC_GPR - Peripheral instance base addresses */
22772 #define IOMUXC_GPR_BASE (0x400AC000u)
22773 
22774 #define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
22775 
22776 #define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
22777 
22778 #define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
22779  /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
22783 
22784 
22785 /* ----------------------------------------------------------------------------
22786  -- IOMUXC_SNVS Peripheral Access Layer
22787  ---------------------------------------------------------------------------- */
22788 
22795 typedef struct {
22796  __IO uint32_t SW_MUX_CTL_PAD_WAKEUP;
22797  __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ;
22798  __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ;
22799  __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE;
22800  __IO uint32_t SW_PAD_CTL_PAD_POR_B;
22801  __IO uint32_t SW_PAD_CTL_PAD_ONOFF;
22802  __IO uint32_t SW_PAD_CTL_PAD_WAKEUP;
22803  __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ;
22804  __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ;
22805 } IOMUXC_SNVS_Type;
22806 
22807 /* ----------------------------------------------------------------------------
22808  -- IOMUXC_SNVS Register Masks
22809  ---------------------------------------------------------------------------- */
22810 
22818 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
22819 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
22820 
22824 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
22825 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
22826 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
22827 
22831 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
22832 
22836 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
22837 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
22838 
22842 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
22843 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
22844 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
22845 
22849 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
22850 
22854 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
22855 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
22856 
22860 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
22861 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
22862 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
22863 
22867 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
22868 
22872 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
22873 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
22874 
22878 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
22879 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
22880 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
22881 
22891 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
22892 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
22893 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
22894 
22897 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
22898 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
22899 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
22900 
22904 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
22905 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
22906 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
22907 
22911 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
22912 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
22913 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
22914 
22918 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
22919 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
22920 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
22921 
22927 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
22928 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
22929 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
22930 
22934 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
22935 
22939 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
22940 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
22941 
22945 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
22946 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
22947 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
22948 
22958 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
22959 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
22960 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
22961 
22964 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
22965 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
22966 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
22967 
22971 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
22972 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
22973 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
22974 
22978 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
22979 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
22980 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
22981 
22985 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
22986 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
22987 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
22988 
22994 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
22995 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
22996 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
22997 
23001 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
23002 
23006 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
23007 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
23008 
23012 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
23013 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
23014 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
23015 
23025 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
23026 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
23027 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
23028 
23031 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
23032 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
23033 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
23034 
23038 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
23039 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
23040 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
23041 
23045 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
23046 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
23047 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
23048 
23052 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
23053 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
23054 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
23055 
23061 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
23062 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
23063 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
23064 
23068 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
23069 
23073 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
23074 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
23075 
23079 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
23080 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
23081 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
23082 
23092 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
23093 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
23094 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
23095 
23098 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
23099 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
23100 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
23101 
23105 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
23106 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
23107 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
23108 
23112 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
23113 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
23114 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
23115 
23119 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
23120 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
23121 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
23122 
23128 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
23129 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
23130 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
23131 
23135 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
23136 
23140 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
23141 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
23142 
23146 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
23147 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
23148 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
23149 
23159 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
23160 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
23161 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
23162 
23165 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
23166 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
23167 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
23168 
23172 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
23173 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
23174 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
23175 
23179 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
23180 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
23181 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
23182 
23186 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
23187 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
23188 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
23189 
23195 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
23196 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
23197 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
23198 
23202 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
23203 
23207 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
23208 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
23209 
23213 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
23214 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
23215 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
23216 
23226 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
23227 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
23228 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
23229 
23232 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
23233 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
23234 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
23235 
23239 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
23240 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
23241 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
23242 
23246 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
23247 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
23248 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
23249 
23253 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
23254 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
23255 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
23256 
23262 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
23263 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
23264 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
23265 
23269 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
23270  /* end of group IOMUXC_SNVS_Register_Masks */
23276 
23277 
23278 /* IOMUXC_SNVS - Peripheral instance base addresses */
23280 #define IOMUXC_SNVS_BASE (0x400A8000u)
23281 
23282 #define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
23283 
23284 #define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
23285 
23286 #define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
23287  /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
23291 
23292 
23293 /* ----------------------------------------------------------------------------
23294  -- IOMUXC_SNVS_GPR Peripheral Access Layer
23295  ---------------------------------------------------------------------------- */
23296 
23303 typedef struct {
23304  uint32_t GPR0;
23305  uint32_t GPR1;
23306  uint32_t GPR2;
23307  __IO uint32_t GPR3;
23308 } IOMUXC_SNVS_GPR_Type;
23309 
23310 /* ----------------------------------------------------------------------------
23311  -- IOMUXC_SNVS_GPR Register Masks
23312  ---------------------------------------------------------------------------- */
23313 
23321 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
23322 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
23323 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
23324 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
23325 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
23326 
23328 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
23329 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
23330 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
23331 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
23332 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
23333 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
23334 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
23335 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
23336 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
23337 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
23338 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
23339 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
23340 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
23341 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
23342 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
23343 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
23344  /* end of group IOMUXC_SNVS_GPR_Register_Masks */
23350 
23351 
23352 /* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
23354 #define IOMUXC_SNVS_GPR_BASE (0x400A4000u)
23355 
23356 #define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
23357 
23358 #define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
23359 
23360 #define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
23361  /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
23365 
23366 
23367 /* ----------------------------------------------------------------------------
23368  -- KPP Peripheral Access Layer
23369  ---------------------------------------------------------------------------- */
23370 
23377 typedef struct {
23378  __IO uint16_t KPCR;
23379  __IO uint16_t KPSR;
23380  __IO uint16_t KDDR;
23381  __IO uint16_t KPDR;
23382 } KPP_Type;
23383 
23384 /* ----------------------------------------------------------------------------
23385  -- KPP Register Masks
23386  ---------------------------------------------------------------------------- */
23387 
23395 #define KPP_KPCR_KRE_MASK (0xFFU)
23396 #define KPP_KPCR_KRE_SHIFT (0U)
23397 
23401 #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
23402 #define KPP_KPCR_KCO_MASK (0xFF00U)
23403 #define KPP_KPCR_KCO_SHIFT (8U)
23404 
23408 #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
23409 
23413 #define KPP_KPSR_KPKD_MASK (0x1U)
23414 #define KPP_KPSR_KPKD_SHIFT (0U)
23415 
23419 #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
23420 #define KPP_KPSR_KPKR_MASK (0x2U)
23421 #define KPP_KPSR_KPKR_SHIFT (1U)
23422 
23426 #define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
23427 #define KPP_KPSR_KDSC_MASK (0x4U)
23428 #define KPP_KPSR_KDSC_SHIFT (2U)
23429 
23433 #define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
23434 #define KPP_KPSR_KRSS_MASK (0x8U)
23435 #define KPP_KPSR_KRSS_SHIFT (3U)
23436 
23440 #define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
23441 #define KPP_KPSR_KDIE_MASK (0x100U)
23442 #define KPP_KPSR_KDIE_SHIFT (8U)
23443 
23447 #define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
23448 #define KPP_KPSR_KRIE_MASK (0x200U)
23449 #define KPP_KPSR_KRIE_SHIFT (9U)
23450 
23454 #define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
23455 
23459 #define KPP_KDDR_KRDD_MASK (0xFFU)
23460 #define KPP_KDDR_KRDD_SHIFT (0U)
23461 
23465 #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
23466 #define KPP_KDDR_KCDD_MASK (0xFF00U)
23467 #define KPP_KDDR_KCDD_SHIFT (8U)
23468 
23472 #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
23473 
23477 #define KPP_KPDR_KRD_MASK (0xFFU)
23478 #define KPP_KPDR_KRD_SHIFT (0U)
23479 #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
23480 #define KPP_KPDR_KCD_MASK (0xFF00U)
23481 #define KPP_KPDR_KCD_SHIFT (8U)
23482 #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
23483  /* end of group KPP_Register_Masks */
23489 
23490 
23491 /* KPP - Peripheral instance base addresses */
23493 #define KPP_BASE (0x401FC000u)
23494 
23495 #define KPP ((KPP_Type *)KPP_BASE)
23496 
23497 #define KPP_BASE_ADDRS { KPP_BASE }
23498 
23499 #define KPP_BASE_PTRS { KPP }
23500 
23501 #define KPP_IRQS { KPP_IRQn }
23502  /* end of group KPP_Peripheral_Access_Layer */
23506 
23507 
23508 /* ----------------------------------------------------------------------------
23509  -- LCDIF Peripheral Access Layer
23510  ---------------------------------------------------------------------------- */
23511 
23518 typedef struct {
23519  __IO uint32_t CTRL;
23520  __IO uint32_t CTRL_SET;
23521  __IO uint32_t CTRL_CLR;
23522  __IO uint32_t CTRL_TOG;
23523  __IO uint32_t CTRL1;
23524  __IO uint32_t CTRL1_SET;
23525  __IO uint32_t CTRL1_CLR;
23526  __IO uint32_t CTRL1_TOG;
23527  __IO uint32_t CTRL2;
23528  __IO uint32_t CTRL2_SET;
23529  __IO uint32_t CTRL2_CLR;
23530  __IO uint32_t CTRL2_TOG;
23531  __IO uint32_t TRANSFER_COUNT;
23532  uint8_t RESERVED_0[12];
23533  __IO uint32_t CUR_BUF;
23534  uint8_t RESERVED_1[12];
23535  __IO uint32_t NEXT_BUF;
23536  uint8_t RESERVED_2[28];
23537  __IO uint32_t VDCTRL0;
23538  __IO uint32_t VDCTRL0_SET;
23539  __IO uint32_t VDCTRL0_CLR;
23540  __IO uint32_t VDCTRL0_TOG;
23541  __IO uint32_t VDCTRL1;
23542  uint8_t RESERVED_3[12];
23543  __IO uint32_t VDCTRL2;
23544  uint8_t RESERVED_4[12];
23545  __IO uint32_t VDCTRL3;
23546  uint8_t RESERVED_5[12];
23547  __IO uint32_t VDCTRL4;
23548  uint8_t RESERVED_6[220];
23549  __IO uint32_t BM_ERROR_STAT;
23550  uint8_t RESERVED_7[12];
23551  __IO uint32_t CRC_STAT;
23552  uint8_t RESERVED_8[12];
23553  __I uint32_t STAT;
23554  uint8_t RESERVED_9[76];
23555  __IO uint32_t THRES;
23556  uint8_t RESERVED_10[380];
23557  __IO uint32_t PIGEONCTRL0;
23558  __IO uint32_t PIGEONCTRL0_SET;
23559  __IO uint32_t PIGEONCTRL0_CLR;
23560  __IO uint32_t PIGEONCTRL0_TOG;
23561  __IO uint32_t PIGEONCTRL1;
23562  __IO uint32_t PIGEONCTRL1_SET;
23563  __IO uint32_t PIGEONCTRL1_CLR;
23564  __IO uint32_t PIGEONCTRL1_TOG;
23565  __IO uint32_t PIGEONCTRL2;
23566  __IO uint32_t PIGEONCTRL2_SET;
23567  __IO uint32_t PIGEONCTRL2_CLR;
23568  __IO uint32_t PIGEONCTRL2_TOG;
23569  uint8_t RESERVED_11[1104];
23570  struct { /* offset: 0x800, array step: 0x40 */
23571  __IO uint32_t PIGEON_0;
23572  uint8_t RESERVED_0[12];
23573  __IO uint32_t PIGEON_1;
23574  uint8_t RESERVED_1[12];
23575  __IO uint32_t PIGEON_2;
23576  uint8_t RESERVED_2[28];
23577  } PIGEON[12];
23578  __IO uint32_t LUT_CTRL;
23579  uint8_t RESERVED_12[12];
23580  __IO uint32_t LUT0_ADDR;
23581  uint8_t RESERVED_13[12];
23582  __IO uint32_t LUT0_DATA;
23583  uint8_t RESERVED_14[12];
23584  __IO uint32_t LUT1_ADDR;
23585  uint8_t RESERVED_15[12];
23586  __IO uint32_t LUT1_DATA;
23587 } LCDIF_Type;
23588 
23589 /* ----------------------------------------------------------------------------
23590  -- LCDIF Register Masks
23591  ---------------------------------------------------------------------------- */
23592 
23600 #define LCDIF_CTRL_RUN_MASK (0x1U)
23601 #define LCDIF_CTRL_RUN_SHIFT (0U)
23602 #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
23603 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
23604 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
23605 
23610 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
23611 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
23612 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
23613 
23617 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
23618 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
23619 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
23620 #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
23621 #define LCDIF_CTRL_RSRVD0_MASK (0x10U)
23622 #define LCDIF_CTRL_RSRVD0_SHIFT (4U)
23623 #define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
23624 #define LCDIF_CTRL_MASTER_MASK (0x20U)
23625 #define LCDIF_CTRL_MASTER_SHIFT (5U)
23626 #define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
23627 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
23628 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
23629 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
23630 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
23631 #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
23632 
23638 #define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
23639 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
23640 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
23641 
23647 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
23648 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
23649 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
23650 
23658 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
23659 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
23660 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
23661 
23669 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
23670 #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
23671 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
23672 #define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
23673 #define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
23674 #define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
23675 #define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
23676 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
23677 #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
23678 #define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
23679 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
23680 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
23681 
23685 #define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
23686 #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
23687 #define LCDIF_CTRL_CLKGATE_SHIFT (30U)
23688 #define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
23689 #define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
23690 #define LCDIF_CTRL_SFTRST_SHIFT (31U)
23691 #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
23692 
23696 #define LCDIF_CTRL_SET_RUN_MASK (0x1U)
23697 #define LCDIF_CTRL_SET_RUN_SHIFT (0U)
23698 #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
23699 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
23700 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
23701 
23706 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
23707 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
23708 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
23709 
23713 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
23714 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
23715 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
23716 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
23717 #define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
23718 #define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
23719 #define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
23720 #define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
23721 #define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
23722 #define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
23723 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
23724 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
23725 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
23726 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
23727 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
23728 
23734 #define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
23735 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
23736 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
23737 
23743 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
23744 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
23745 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
23746 
23754 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
23755 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
23756 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
23757 
23765 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
23766 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
23767 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
23768 #define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
23769 #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
23770 #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
23771 #define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
23772 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
23773 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
23774 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
23775 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
23776 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
23777 
23781 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
23782 #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
23783 #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
23784 #define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
23785 #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
23786 #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
23787 #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
23788 
23792 #define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
23793 #define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
23794 #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
23795 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
23796 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
23797 
23802 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
23803 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
23804 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
23805 
23809 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
23810 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
23811 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
23812 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
23813 #define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
23814 #define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
23815 #define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
23816 #define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
23817 #define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
23818 #define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
23819 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
23820 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
23821 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
23822 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
23823 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
23824 
23830 #define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
23831 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
23832 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
23833 
23839 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
23840 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
23841 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
23842 
23850 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
23851 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
23852 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
23853 
23861 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
23862 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
23863 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
23864 #define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
23865 #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
23866 #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
23867 #define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
23868 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
23869 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
23870 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
23871 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
23872 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
23873 
23877 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
23878 #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
23879 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
23880 #define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
23881 #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
23882 #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
23883 #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
23884 
23888 #define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
23889 #define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
23890 #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
23891 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
23892 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
23893 
23898 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
23899 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
23900 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
23901 
23905 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
23906 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
23907 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
23908 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
23909 #define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
23910 #define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
23911 #define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
23912 #define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
23913 #define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
23914 #define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
23915 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
23916 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
23917 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
23918 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
23919 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
23920 
23926 #define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
23927 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
23928 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
23929 
23935 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
23936 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
23937 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
23938 
23946 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
23947 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
23948 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
23949 
23957 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
23958 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
23959 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
23960 #define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
23961 #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
23962 #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
23963 #define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
23964 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
23965 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
23966 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
23967 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
23968 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
23969 
23973 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
23974 #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
23975 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
23976 #define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
23977 #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
23978 #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
23979 #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
23980 
23984 #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
23985 #define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
23986 #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
23987 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
23988 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
23989 
23993 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
23994 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
23995 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
23996 
24000 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
24001 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
24002 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
24003 
24007 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
24008 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
24009 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
24010 
24014 #define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
24015 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
24016 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
24017 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
24018 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
24019 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
24020 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
24021 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
24022 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
24023 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
24024 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
24025 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
24026 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
24027 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
24028 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
24029 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
24030 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
24031 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
24032 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
24033 #define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
24034 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
24035 #define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
24036 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
24037 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
24038 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
24039 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
24040 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
24041 #define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
24042 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
24043 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
24044 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
24045 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
24046 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
24047 
24051 #define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
24052 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
24053 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
24054 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
24055 #define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
24056 #define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
24057 #define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
24058 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
24059 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
24060 #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
24061 
24065 #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
24066 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
24067 #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
24068 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
24069 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
24070 
24074 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
24075 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
24076 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
24077 
24081 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
24082 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
24083 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
24084 
24088 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
24089 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
24090 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
24091 
24095 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
24096 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
24097 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
24098 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
24099 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
24100 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
24101 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
24102 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
24103 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
24104 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
24105 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
24106 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
24107 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
24108 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
24109 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
24110 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
24111 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
24112 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
24113 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
24114 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
24115 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
24116 #define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
24117 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
24118 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
24119 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
24120 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
24121 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
24122 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
24123 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
24124 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
24125 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
24126 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
24127 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
24128 
24132 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
24133 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
24134 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
24135 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
24136 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
24137 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
24138 #define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
24139 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
24140 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
24141 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
24142 
24146 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
24147 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
24148 #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
24149 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
24150 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
24151 
24155 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
24156 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
24157 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
24158 
24162 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
24163 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
24164 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
24165 
24169 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
24170 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
24171 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
24172 
24176 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
24177 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
24178 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
24179 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
24180 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
24181 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
24182 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
24183 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
24184 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
24185 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
24186 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
24187 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
24188 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
24189 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
24190 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
24191 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
24192 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
24193 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
24194 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
24195 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
24196 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
24197 #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
24198 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
24199 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
24200 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
24201 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
24202 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
24203 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
24204 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
24205 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
24206 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
24207 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
24208 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
24209 
24213 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
24214 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
24215 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
24216 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
24217 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
24218 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
24219 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
24220 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
24221 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
24222 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
24223 
24227 #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
24228 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
24229 #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
24230 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
24231 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
24232 
24236 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
24237 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
24238 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
24239 
24243 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
24244 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
24245 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
24246 
24250 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
24251 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
24252 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
24253 
24257 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
24258 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
24259 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
24260 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
24261 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
24262 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
24263 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
24264 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
24265 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
24266 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
24267 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
24268 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
24269 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
24270 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
24271 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
24272 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
24273 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
24274 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
24275 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
24276 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
24277 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
24278 #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
24279 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
24280 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
24281 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
24282 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
24283 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
24284 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
24285 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
24286 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
24287 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
24288 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
24289 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
24290 
24294 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
24295 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
24296 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
24297 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
24298 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
24299 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
24300 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
24301 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
24302 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
24303 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
24304 
24308 #define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
24309 #define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
24310 #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
24311 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
24312 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
24313 
24321 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
24322 #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
24323 #define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
24324 #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
24325 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
24326 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
24327 
24335 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
24336 #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
24337 #define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
24338 #define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
24339 #define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
24340 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
24341 #define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
24342 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
24343 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
24344 
24351 #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
24352 #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
24353 #define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
24354 #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
24355 
24359 #define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
24360 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
24361 #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
24362 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
24363 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
24364 
24372 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
24373 #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
24374 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
24375 #define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
24376 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
24377 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
24378 
24386 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
24387 #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
24388 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
24389 #define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
24390 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
24391 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
24392 #define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
24393 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
24394 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
24395 
24402 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
24403 #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
24404 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
24405 #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
24406 
24410 #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
24411 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
24412 #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
24413 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
24414 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
24415 
24423 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
24424 #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
24425 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
24426 #define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
24427 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
24428 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
24429 
24437 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
24438 #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
24439 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
24440 #define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
24441 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
24442 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
24443 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
24444 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
24445 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
24446 
24453 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
24454 #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
24455 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
24456 #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
24457 
24461 #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
24462 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
24463 #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
24464 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
24465 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
24466 
24474 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
24475 #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
24476 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
24477 #define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
24478 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
24479 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
24480 
24488 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
24489 #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
24490 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
24491 #define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
24492 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
24493 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
24494 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
24495 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
24496 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
24497 
24504 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
24505 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
24506 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
24507 #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
24508 
24512 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
24513 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
24514 #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
24515 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
24516 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
24517 #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
24518 
24522 #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
24523 #define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
24524 #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
24525 
24529 #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
24530 #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
24531 #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
24532 
24536 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
24537 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
24538 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
24539 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
24540 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
24541 #define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
24542 #define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
24543 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
24544 #define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
24545 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
24546 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
24547 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
24548 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
24549 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
24550 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
24551 #define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
24552 #define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
24553 #define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
24554 #define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
24555 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
24556 #define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
24557 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
24558 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
24559 #define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
24560 #define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
24561 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
24562 #define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
24563 #define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
24564 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
24565 #define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
24566 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
24567 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
24568 #define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
24569 #define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)
24570 #define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U)
24571 #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
24572 
24576 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
24577 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
24578 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
24579 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
24580 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
24581 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
24582 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
24583 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
24584 #define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
24585 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
24586 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
24587 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
24588 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
24589 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
24590 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
24591 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
24592 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
24593 #define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
24594 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
24595 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
24596 #define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
24597 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
24598 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
24599 #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
24600 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
24601 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
24602 #define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
24603 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
24604 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
24605 #define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
24606 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
24607 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
24608 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
24609 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)
24610 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)
24611 #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
24612 
24616 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
24617 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
24618 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
24619 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
24620 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
24621 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
24622 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
24623 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
24624 #define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
24625 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
24626 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
24627 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
24628 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
24629 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
24630 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
24631 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
24632 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
24633 #define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
24634 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
24635 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
24636 #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
24637 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
24638 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
24639 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
24640 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
24641 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
24642 #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
24643 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
24644 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
24645 #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
24646 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
24647 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
24648 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
24649 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)
24650 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)
24651 #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
24652 
24656 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
24657 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
24658 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
24659 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
24660 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
24661 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
24662 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
24663 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
24664 #define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
24665 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
24666 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
24667 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
24668 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
24669 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
24670 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
24671 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
24672 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
24673 #define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
24674 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
24675 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
24676 #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
24677 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
24678 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
24679 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
24680 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
24681 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
24682 #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
24683 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
24684 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
24685 #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
24686 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
24687 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
24688 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
24689 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)
24690 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)
24691 #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
24692 
24696 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
24697 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
24698 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
24699 
24703 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
24704 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
24705 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
24706 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
24707 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
24708 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
24709 
24713 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
24714 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
24715 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
24716 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
24717 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
24718 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
24719 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
24720 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
24721 #define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
24722 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
24723 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
24724 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
24725 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
24726 #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
24727 #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
24728 
24732 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
24733 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
24734 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
24735 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
24736 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
24737 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
24738 #define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
24739 #define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
24740 #define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
24741 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
24742 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
24743 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
24744 
24748 #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
24749 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
24750 #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
24751 
24755 #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
24756 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
24757 #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
24758 
24762 #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
24763 #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
24764 #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
24765 #define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
24766 #define LCDIF_STAT_RSRVD0_SHIFT (9U)
24767 #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
24768 #define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
24769 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
24770 #define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
24771 #define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
24772 #define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
24773 #define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
24774 #define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
24775 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
24776 #define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
24777 #define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
24778 #define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
24779 #define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
24780 #define LCDIF_STAT_DMA_REQ_MASK (0x40000000U)
24781 #define LCDIF_STAT_DMA_REQ_SHIFT (30U)
24782 #define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
24783 #define LCDIF_STAT_PRESENT_MASK (0x80000000U)
24784 #define LCDIF_STAT_PRESENT_SHIFT (31U)
24785 #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
24786 
24790 #define LCDIF_THRES_PANIC_MASK (0x1FFU)
24791 #define LCDIF_THRES_PANIC_SHIFT (0U)
24792 #define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)
24793 #define LCDIF_THRES_RSRVD1_MASK (0xFE00U)
24794 #define LCDIF_THRES_RSRVD1_SHIFT (9U)
24795 #define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
24796 #define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)
24797 #define LCDIF_THRES_FASTCLOCK_SHIFT (16U)
24798 #define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
24799 #define LCDIF_THRES_RSRVD2_MASK (0xFE000000U)
24800 #define LCDIF_THRES_RSRVD2_SHIFT (25U)
24801 #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
24802 
24806 #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
24807 #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
24808 #define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
24809 #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
24810 #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
24811 #define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
24812 
24816 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
24817 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
24818 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
24819 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
24820 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
24821 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
24822 
24826 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
24827 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
24828 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
24829 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
24830 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
24831 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
24832 
24836 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
24837 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
24838 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
24839 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
24840 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
24841 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
24842 
24846 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
24847 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
24848 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
24849 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
24850 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
24851 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
24852 
24856 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
24857 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
24858 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
24859 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
24860 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
24861 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
24862 
24866 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
24867 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
24868 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
24869 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
24870 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
24871 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
24872 
24876 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
24877 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
24878 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
24879 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
24880 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
24881 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
24882 
24886 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
24887 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
24888 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
24889 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
24890 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
24891 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
24892 
24896 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
24897 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
24898 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
24899 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
24900 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
24901 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
24902 
24906 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
24907 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
24908 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
24909 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
24910 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
24911 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
24912 
24916 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
24917 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
24918 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
24919 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
24920 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
24921 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
24922 
24926 #define LCDIF_PIGEON_0_EN_MASK (0x1U)
24927 #define LCDIF_PIGEON_0_EN_SHIFT (0U)
24928 #define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
24929 #define LCDIF_PIGEON_0_POL_MASK (0x2U)
24930 #define LCDIF_PIGEON_0_POL_SHIFT (1U)
24931 
24935 #define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
24936 #define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
24937 #define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
24938 
24944 #define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
24945 #define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
24946 #define LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
24947 #define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
24948 #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
24949 #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
24950 
24960 #define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
24961 #define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
24962 #define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
24963 #define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
24964 #define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
24965 #define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
24966 
24976 #define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
24977 
24979 /* The count of LCDIF_PIGEON_0 */
24980 #define LCDIF_PIGEON_0_COUNT (12U)
24981 
24984 #define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
24985 #define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
24986 
24989 #define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
24990 #define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
24991 #define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
24992 
24995 #define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
24996 
24998 /* The count of LCDIF_PIGEON_1 */
24999 #define LCDIF_PIGEON_1_COUNT (12U)
25000 
25003 #define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
25004 #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
25005 
25011 #define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
25012 #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
25013 #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
25014 
25017 #define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
25018 #define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
25019 #define LCDIF_PIGEON_2_RSVD_SHIFT (9U)
25020 #define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
25021 
25023 /* The count of LCDIF_PIGEON_2 */
25024 #define LCDIF_PIGEON_2_COUNT (12U)
25025 
25028 #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
25029 #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
25030 #define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
25031 
25035 #define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
25036 #define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
25037 #define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
25038 
25042 #define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
25043 #define LCDIF_LUT0_DATA_DATA_SHIFT (0U)
25044 #define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
25045 
25049 #define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
25050 #define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
25051 #define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
25052 
25056 #define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
25057 #define LCDIF_LUT1_DATA_DATA_SHIFT (0U)
25058 #define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
25059  /* end of group LCDIF_Register_Masks */
25065 
25066 
25067 /* LCDIF - Peripheral instance base addresses */
25069 #define LCDIF_BASE (0x402B8000u)
25070 
25071 #define LCDIF ((LCDIF_Type *)LCDIF_BASE)
25072 
25073 #define LCDIF_BASE_ADDRS { LCDIF_BASE }
25074 
25075 #define LCDIF_BASE_PTRS { LCDIF }
25076 
25077 #define LCDIF_IRQ0_IRQS { LCDIF_IRQn }
25078  /* end of group LCDIF_Peripheral_Access_Layer */
25082 
25083 
25084 /* ----------------------------------------------------------------------------
25085  -- LPI2C Peripheral Access Layer
25086  ---------------------------------------------------------------------------- */
25087 
25094 typedef struct {
25095  __I uint32_t VERID;
25096  __I uint32_t PARAM;
25097  uint8_t RESERVED_0[8];
25098  __IO uint32_t MCR;
25099  __IO uint32_t MSR;
25100  __IO uint32_t MIER;
25101  __IO uint32_t MDER;
25102  __IO uint32_t MCFGR0;
25103  __IO uint32_t MCFGR1;
25104  __IO uint32_t MCFGR2;
25105  __IO uint32_t MCFGR3;
25106  uint8_t RESERVED_1[16];
25107  __IO uint32_t MDMR;
25108  uint8_t RESERVED_2[4];
25109  __IO uint32_t MCCR0;
25110  uint8_t RESERVED_3[4];
25111  __IO uint32_t MCCR1;
25112  uint8_t RESERVED_4[4];
25113  __IO uint32_t MFCR;
25114  __I uint32_t MFSR;
25115  __O uint32_t MTDR;
25116  uint8_t RESERVED_5[12];
25117  __I uint32_t MRDR;
25118  uint8_t RESERVED_6[156];
25119  __IO uint32_t SCR;
25120  __IO uint32_t SSR;
25121  __IO uint32_t SIER;
25122  __IO uint32_t SDER;
25123  uint8_t RESERVED_7[4];
25124  __IO uint32_t SCFGR1;
25125  __IO uint32_t SCFGR2;
25126  uint8_t RESERVED_8[20];
25127  __IO uint32_t SAMR;
25128  uint8_t RESERVED_9[12];
25129  __I uint32_t SASR;
25130  __IO uint32_t STAR;
25131  uint8_t RESERVED_10[8];
25132  __O uint32_t STDR;
25133  uint8_t RESERVED_11[12];
25134  __I uint32_t SRDR;
25135 } LPI2C_Type;
25136 
25137 /* ----------------------------------------------------------------------------
25138  -- LPI2C Register Masks
25139  ---------------------------------------------------------------------------- */
25140 
25148 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
25149 #define LPI2C_VERID_FEATURE_SHIFT (0U)
25150 
25154 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
25155 #define LPI2C_VERID_MINOR_MASK (0xFF0000U)
25156 #define LPI2C_VERID_MINOR_SHIFT (16U)
25157 
25159 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
25160 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
25161 #define LPI2C_VERID_MAJOR_SHIFT (24U)
25162 
25164 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
25165 
25169 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
25170 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
25171 
25173 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
25174 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
25175 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
25176 
25178 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
25179 
25183 #define LPI2C_MCR_MEN_MASK (0x1U)
25184 #define LPI2C_MCR_MEN_SHIFT (0U)
25185 
25189 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
25190 #define LPI2C_MCR_RST_MASK (0x2U)
25191 #define LPI2C_MCR_RST_SHIFT (1U)
25192 
25196 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
25197 #define LPI2C_MCR_DOZEN_MASK (0x4U)
25198 #define LPI2C_MCR_DOZEN_SHIFT (2U)
25199 
25203 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
25204 #define LPI2C_MCR_DBGEN_MASK (0x8U)
25205 #define LPI2C_MCR_DBGEN_SHIFT (3U)
25206 
25210 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
25211 #define LPI2C_MCR_RTF_MASK (0x100U)
25212 #define LPI2C_MCR_RTF_SHIFT (8U)
25213 
25217 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
25218 #define LPI2C_MCR_RRF_MASK (0x200U)
25219 #define LPI2C_MCR_RRF_SHIFT (9U)
25220 
25224 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
25225 
25229 #define LPI2C_MSR_TDF_MASK (0x1U)
25230 #define LPI2C_MSR_TDF_SHIFT (0U)
25231 
25235 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
25236 #define LPI2C_MSR_RDF_MASK (0x2U)
25237 #define LPI2C_MSR_RDF_SHIFT (1U)
25238 
25242 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
25243 #define LPI2C_MSR_EPF_MASK (0x100U)
25244 #define LPI2C_MSR_EPF_SHIFT (8U)
25245 
25249 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
25250 #define LPI2C_MSR_SDF_MASK (0x200U)
25251 #define LPI2C_MSR_SDF_SHIFT (9U)
25252 
25256 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
25257 #define LPI2C_MSR_NDF_MASK (0x400U)
25258 #define LPI2C_MSR_NDF_SHIFT (10U)
25259 
25263 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
25264 #define LPI2C_MSR_ALF_MASK (0x800U)
25265 #define LPI2C_MSR_ALF_SHIFT (11U)
25266 
25270 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
25271 #define LPI2C_MSR_FEF_MASK (0x1000U)
25272 #define LPI2C_MSR_FEF_SHIFT (12U)
25273 
25277 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
25278 #define LPI2C_MSR_PLTF_MASK (0x2000U)
25279 #define LPI2C_MSR_PLTF_SHIFT (13U)
25280 
25284 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
25285 #define LPI2C_MSR_DMF_MASK (0x4000U)
25286 #define LPI2C_MSR_DMF_SHIFT (14U)
25287 
25291 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
25292 #define LPI2C_MSR_MBF_MASK (0x1000000U)
25293 #define LPI2C_MSR_MBF_SHIFT (24U)
25294 
25298 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
25299 #define LPI2C_MSR_BBF_MASK (0x2000000U)
25300 #define LPI2C_MSR_BBF_SHIFT (25U)
25301 
25305 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
25306 
25310 #define LPI2C_MIER_TDIE_MASK (0x1U)
25311 #define LPI2C_MIER_TDIE_SHIFT (0U)
25312 
25316 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
25317 #define LPI2C_MIER_RDIE_MASK (0x2U)
25318 #define LPI2C_MIER_RDIE_SHIFT (1U)
25319 
25323 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
25324 #define LPI2C_MIER_EPIE_MASK (0x100U)
25325 #define LPI2C_MIER_EPIE_SHIFT (8U)
25326 
25330 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
25331 #define LPI2C_MIER_SDIE_MASK (0x200U)
25332 #define LPI2C_MIER_SDIE_SHIFT (9U)
25333 
25337 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
25338 #define LPI2C_MIER_NDIE_MASK (0x400U)
25339 #define LPI2C_MIER_NDIE_SHIFT (10U)
25340 
25344 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
25345 #define LPI2C_MIER_ALIE_MASK (0x800U)
25346 #define LPI2C_MIER_ALIE_SHIFT (11U)
25347 
25351 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
25352 #define LPI2C_MIER_FEIE_MASK (0x1000U)
25353 #define LPI2C_MIER_FEIE_SHIFT (12U)
25354 
25358 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
25359 #define LPI2C_MIER_PLTIE_MASK (0x2000U)
25360 #define LPI2C_MIER_PLTIE_SHIFT (13U)
25361 
25365 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
25366 #define LPI2C_MIER_DMIE_MASK (0x4000U)
25367 #define LPI2C_MIER_DMIE_SHIFT (14U)
25368 
25372 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
25373 
25377 #define LPI2C_MDER_TDDE_MASK (0x1U)
25378 #define LPI2C_MDER_TDDE_SHIFT (0U)
25379 
25383 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
25384 #define LPI2C_MDER_RDDE_MASK (0x2U)
25385 #define LPI2C_MDER_RDDE_SHIFT (1U)
25386 
25390 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
25391 
25395 #define LPI2C_MCFGR0_HREN_MASK (0x1U)
25396 #define LPI2C_MCFGR0_HREN_SHIFT (0U)
25397 
25401 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
25402 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
25403 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
25404 
25408 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
25409 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
25410 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
25411 
25415 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
25416 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
25417 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
25418 
25422 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
25423 #define LPI2C_MCFGR0_RDMO_MASK (0x200U)
25424 #define LPI2C_MCFGR0_RDMO_SHIFT (9U)
25425 
25429 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
25430 
25434 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
25435 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
25436 
25446 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
25447 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
25448 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
25449 
25453 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
25454 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
25455 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
25456 
25460 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
25461 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
25462 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
25463 
25467 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
25468 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
25469 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
25470 
25480 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
25481 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
25482 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
25483 
25493 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
25494 
25498 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
25499 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
25500 
25502 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
25503 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
25504 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
25505 
25507 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
25508 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
25509 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
25510 
25512 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
25513 
25517 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
25518 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
25519 
25521 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
25522 
25526 #define LPI2C_MDMR_MATCH0_MASK (0xFFU)
25527 #define LPI2C_MDMR_MATCH0_SHIFT (0U)
25528 
25530 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
25531 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
25532 #define LPI2C_MDMR_MATCH1_SHIFT (16U)
25533 
25535 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
25536 
25540 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
25541 #define LPI2C_MCCR0_CLKLO_SHIFT (0U)
25542 
25544 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
25545 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
25546 #define LPI2C_MCCR0_CLKHI_SHIFT (8U)
25547 
25549 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
25550 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
25551 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
25552 
25554 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
25555 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
25556 #define LPI2C_MCCR0_DATAVD_SHIFT (24U)
25557 
25559 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
25560 
25564 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
25565 #define LPI2C_MCCR1_CLKLO_SHIFT (0U)
25566 
25568 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
25569 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
25570 #define LPI2C_MCCR1_CLKHI_SHIFT (8U)
25571 
25573 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
25574 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
25575 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
25576 
25578 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
25579 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
25580 #define LPI2C_MCCR1_DATAVD_SHIFT (24U)
25581 
25583 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
25584 
25588 #define LPI2C_MFCR_TXWATER_MASK (0x3U)
25589 #define LPI2C_MFCR_TXWATER_SHIFT (0U)
25590 
25592 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
25593 #define LPI2C_MFCR_RXWATER_MASK (0x30000U)
25594 #define LPI2C_MFCR_RXWATER_SHIFT (16U)
25595 
25597 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
25598 
25602 #define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
25603 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
25604 
25606 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
25607 #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
25608 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
25609 
25611 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
25612 
25616 #define LPI2C_MTDR_DATA_MASK (0xFFU)
25617 #define LPI2C_MTDR_DATA_SHIFT (0U)
25618 
25620 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
25621 #define LPI2C_MTDR_CMD_MASK (0x700U)
25622 #define LPI2C_MTDR_CMD_SHIFT (8U)
25623 
25633 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
25634 
25638 #define LPI2C_MRDR_DATA_MASK (0xFFU)
25639 #define LPI2C_MRDR_DATA_SHIFT (0U)
25640 
25642 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
25643 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
25644 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
25645 
25649 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
25650 
25654 #define LPI2C_SCR_SEN_MASK (0x1U)
25655 #define LPI2C_SCR_SEN_SHIFT (0U)
25656 
25660 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
25661 #define LPI2C_SCR_RST_MASK (0x2U)
25662 #define LPI2C_SCR_RST_SHIFT (1U)
25663 
25667 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
25668 #define LPI2C_SCR_FILTEN_MASK (0x10U)
25669 #define LPI2C_SCR_FILTEN_SHIFT (4U)
25670 
25674 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
25675 #define LPI2C_SCR_FILTDZ_MASK (0x20U)
25676 #define LPI2C_SCR_FILTDZ_SHIFT (5U)
25677 
25681 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
25682 #define LPI2C_SCR_RTF_MASK (0x100U)
25683 #define LPI2C_SCR_RTF_SHIFT (8U)
25684 
25688 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
25689 #define LPI2C_SCR_RRF_MASK (0x200U)
25690 #define LPI2C_SCR_RRF_SHIFT (9U)
25691 
25695 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
25696 
25700 #define LPI2C_SSR_TDF_MASK (0x1U)
25701 #define LPI2C_SSR_TDF_SHIFT (0U)
25702 
25706 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
25707 #define LPI2C_SSR_RDF_MASK (0x2U)
25708 #define LPI2C_SSR_RDF_SHIFT (1U)
25709 
25713 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
25714 #define LPI2C_SSR_AVF_MASK (0x4U)
25715 #define LPI2C_SSR_AVF_SHIFT (2U)
25716 
25720 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
25721 #define LPI2C_SSR_TAF_MASK (0x8U)
25722 #define LPI2C_SSR_TAF_SHIFT (3U)
25723 
25727 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
25728 #define LPI2C_SSR_RSF_MASK (0x100U)
25729 #define LPI2C_SSR_RSF_SHIFT (8U)
25730 
25734 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
25735 #define LPI2C_SSR_SDF_MASK (0x200U)
25736 #define LPI2C_SSR_SDF_SHIFT (9U)
25737 
25741 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
25742 #define LPI2C_SSR_BEF_MASK (0x400U)
25743 #define LPI2C_SSR_BEF_SHIFT (10U)
25744 
25748 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
25749 #define LPI2C_SSR_FEF_MASK (0x800U)
25750 #define LPI2C_SSR_FEF_SHIFT (11U)
25751 
25755 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
25756 #define LPI2C_SSR_AM0F_MASK (0x1000U)
25757 #define LPI2C_SSR_AM0F_SHIFT (12U)
25758 
25762 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
25763 #define LPI2C_SSR_AM1F_MASK (0x2000U)
25764 #define LPI2C_SSR_AM1F_SHIFT (13U)
25765 
25769 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
25770 #define LPI2C_SSR_GCF_MASK (0x4000U)
25771 #define LPI2C_SSR_GCF_SHIFT (14U)
25772 
25776 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
25777 #define LPI2C_SSR_SARF_MASK (0x8000U)
25778 #define LPI2C_SSR_SARF_SHIFT (15U)
25779 
25783 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
25784 #define LPI2C_SSR_SBF_MASK (0x1000000U)
25785 #define LPI2C_SSR_SBF_SHIFT (24U)
25786 
25790 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
25791 #define LPI2C_SSR_BBF_MASK (0x2000000U)
25792 #define LPI2C_SSR_BBF_SHIFT (25U)
25793 
25797 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
25798 
25802 #define LPI2C_SIER_TDIE_MASK (0x1U)
25803 #define LPI2C_SIER_TDIE_SHIFT (0U)
25804 
25808 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
25809 #define LPI2C_SIER_RDIE_MASK (0x2U)
25810 #define LPI2C_SIER_RDIE_SHIFT (1U)
25811 
25815 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
25816 #define LPI2C_SIER_AVIE_MASK (0x4U)
25817 #define LPI2C_SIER_AVIE_SHIFT (2U)
25818 
25822 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
25823 #define LPI2C_SIER_TAIE_MASK (0x8U)
25824 #define LPI2C_SIER_TAIE_SHIFT (3U)
25825 
25829 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
25830 #define LPI2C_SIER_RSIE_MASK (0x100U)
25831 #define LPI2C_SIER_RSIE_SHIFT (8U)
25832 
25836 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
25837 #define LPI2C_SIER_SDIE_MASK (0x200U)
25838 #define LPI2C_SIER_SDIE_SHIFT (9U)
25839 
25843 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
25844 #define LPI2C_SIER_BEIE_MASK (0x400U)
25845 #define LPI2C_SIER_BEIE_SHIFT (10U)
25846 
25850 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
25851 #define LPI2C_SIER_FEIE_MASK (0x800U)
25852 #define LPI2C_SIER_FEIE_SHIFT (11U)
25853 
25857 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
25858 #define LPI2C_SIER_AM0IE_MASK (0x1000U)
25859 #define LPI2C_SIER_AM0IE_SHIFT (12U)
25860 
25864 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
25865 #define LPI2C_SIER_AM1F_MASK (0x2000U)
25866 #define LPI2C_SIER_AM1F_SHIFT (13U)
25867 
25871 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
25872 #define LPI2C_SIER_GCIE_MASK (0x4000U)
25873 #define LPI2C_SIER_GCIE_SHIFT (14U)
25874 
25878 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
25879 #define LPI2C_SIER_SARIE_MASK (0x8000U)
25880 #define LPI2C_SIER_SARIE_SHIFT (15U)
25881 
25885 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
25886 
25890 #define LPI2C_SDER_TDDE_MASK (0x1U)
25891 #define LPI2C_SDER_TDDE_SHIFT (0U)
25892 
25896 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
25897 #define LPI2C_SDER_RDDE_MASK (0x2U)
25898 #define LPI2C_SDER_RDDE_SHIFT (1U)
25899 
25903 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
25904 #define LPI2C_SDER_AVDE_MASK (0x4U)
25905 #define LPI2C_SDER_AVDE_SHIFT (2U)
25906 
25910 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
25911 
25915 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
25916 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
25917 
25921 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
25922 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
25923 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
25924 
25928 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
25929 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
25930 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
25931 
25935 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
25936 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
25937 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
25938 
25942 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
25943 #define LPI2C_SCFGR1_GCEN_MASK (0x100U)
25944 #define LPI2C_SCFGR1_GCEN_SHIFT (8U)
25945 
25949 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
25950 #define LPI2C_SCFGR1_SAEN_MASK (0x200U)
25951 #define LPI2C_SCFGR1_SAEN_SHIFT (9U)
25952 
25956 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
25957 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
25958 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
25959 
25963 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
25964 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
25965 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
25966 
25972 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
25973 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
25974 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
25975 
25979 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
25980 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
25981 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
25982 
25986 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
25987 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
25988 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
25989 
25999 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
26000 
26004 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
26005 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
26006 
26008 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
26009 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
26010 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
26011 
26013 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
26014 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
26015 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
26016 
26018 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
26019 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
26020 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
26021 
26023 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
26024 
26028 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
26029 #define LPI2C_SAMR_ADDR0_SHIFT (1U)
26030 
26032 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
26033 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
26034 #define LPI2C_SAMR_ADDR1_SHIFT (17U)
26035 
26037 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
26038 
26042 #define LPI2C_SASR_RADDR_MASK (0x7FFU)
26043 #define LPI2C_SASR_RADDR_SHIFT (0U)
26044 
26046 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
26047 #define LPI2C_SASR_ANV_MASK (0x4000U)
26048 #define LPI2C_SASR_ANV_SHIFT (14U)
26049 
26053 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
26054 
26058 #define LPI2C_STAR_TXNACK_MASK (0x1U)
26059 #define LPI2C_STAR_TXNACK_SHIFT (0U)
26060 
26064 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
26065 
26069 #define LPI2C_STDR_DATA_MASK (0xFFU)
26070 #define LPI2C_STDR_DATA_SHIFT (0U)
26071 
26073 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
26074 
26078 #define LPI2C_SRDR_DATA_MASK (0xFFU)
26079 #define LPI2C_SRDR_DATA_SHIFT (0U)
26080 
26082 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
26083 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
26084 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
26085 
26089 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
26090 #define LPI2C_SRDR_SOF_MASK (0x8000U)
26091 #define LPI2C_SRDR_SOF_SHIFT (15U)
26092 
26096 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
26097  /* end of group LPI2C_Register_Masks */
26103 
26104 
26105 /* LPI2C - Peripheral instance base addresses */
26107 #define LPI2C1_BASE (0x403F0000u)
26108 
26109 #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
26110 
26111 #define LPI2C2_BASE (0x403F4000u)
26112 
26113 #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
26114 
26115 #define LPI2C3_BASE (0x403F8000u)
26116 
26117 #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
26118 
26119 #define LPI2C4_BASE (0x403FC000u)
26120 
26121 #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
26122 
26123 #define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
26124 
26125 #define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
26126 
26127 #define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
26128  /* end of group LPI2C_Peripheral_Access_Layer */
26132 
26133 
26134 /* ----------------------------------------------------------------------------
26135  -- LPSPI Peripheral Access Layer
26136  ---------------------------------------------------------------------------- */
26137 
26144 typedef struct {
26145  __I uint32_t VERID;
26146  __I uint32_t PARAM;
26147  uint8_t RESERVED_0[8];
26148  __IO uint32_t CR;
26149  __IO uint32_t SR;
26150  __IO uint32_t IER;
26151  __IO uint32_t DER;
26152  __IO uint32_t CFGR0;
26153  __IO uint32_t CFGR1;
26154  uint8_t RESERVED_1[8];
26155  __IO uint32_t DMR0;
26156  __IO uint32_t DMR1;
26157  uint8_t RESERVED_2[8];
26158  __IO uint32_t CCR;
26159  uint8_t RESERVED_3[20];
26160  __IO uint32_t FCR;
26161  __I uint32_t FSR;
26162  __IO uint32_t TCR;
26163  __O uint32_t TDR;
26164  uint8_t RESERVED_4[8];
26165  __I uint32_t RSR;
26166  __I uint32_t RDR;
26167 } LPSPI_Type;
26168 
26169 /* ----------------------------------------------------------------------------
26170  -- LPSPI Register Masks
26171  ---------------------------------------------------------------------------- */
26172 
26180 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
26181 #define LPSPI_VERID_FEATURE_SHIFT (0U)
26182 
26185 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
26186 #define LPSPI_VERID_MINOR_MASK (0xFF0000U)
26187 #define LPSPI_VERID_MINOR_SHIFT (16U)
26188 
26190 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
26191 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
26192 #define LPSPI_VERID_MAJOR_SHIFT (24U)
26193 
26195 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
26196 
26200 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
26201 #define LPSPI_PARAM_TXFIFO_SHIFT (0U)
26202 
26204 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
26205 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
26206 #define LPSPI_PARAM_RXFIFO_SHIFT (8U)
26207 
26209 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
26210 #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
26211 #define LPSPI_PARAM_PCSNUM_SHIFT (16U)
26212 
26214 #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
26215 
26219 #define LPSPI_CR_MEN_MASK (0x1U)
26220 #define LPSPI_CR_MEN_SHIFT (0U)
26221 
26225 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
26226 #define LPSPI_CR_RST_MASK (0x2U)
26227 #define LPSPI_CR_RST_SHIFT (1U)
26228 
26232 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
26233 #define LPSPI_CR_DOZEN_MASK (0x4U)
26234 #define LPSPI_CR_DOZEN_SHIFT (2U)
26235 
26239 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
26240 #define LPSPI_CR_DBGEN_MASK (0x8U)
26241 #define LPSPI_CR_DBGEN_SHIFT (3U)
26242 
26246 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
26247 #define LPSPI_CR_RTF_MASK (0x100U)
26248 #define LPSPI_CR_RTF_SHIFT (8U)
26249 
26253 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
26254 #define LPSPI_CR_RRF_MASK (0x200U)
26255 #define LPSPI_CR_RRF_SHIFT (9U)
26256 
26260 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
26261 
26265 #define LPSPI_SR_TDF_MASK (0x1U)
26266 #define LPSPI_SR_TDF_SHIFT (0U)
26267 
26271 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
26272 #define LPSPI_SR_RDF_MASK (0x2U)
26273 #define LPSPI_SR_RDF_SHIFT (1U)
26274 
26278 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
26279 #define LPSPI_SR_WCF_MASK (0x100U)
26280 #define LPSPI_SR_WCF_SHIFT (8U)
26281 
26285 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
26286 #define LPSPI_SR_FCF_MASK (0x200U)
26287 #define LPSPI_SR_FCF_SHIFT (9U)
26288 
26292 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
26293 #define LPSPI_SR_TCF_MASK (0x400U)
26294 #define LPSPI_SR_TCF_SHIFT (10U)
26295 
26299 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
26300 #define LPSPI_SR_TEF_MASK (0x800U)
26301 #define LPSPI_SR_TEF_SHIFT (11U)
26302 
26306 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
26307 #define LPSPI_SR_REF_MASK (0x1000U)
26308 #define LPSPI_SR_REF_SHIFT (12U)
26309 
26313 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
26314 #define LPSPI_SR_DMF_MASK (0x2000U)
26315 #define LPSPI_SR_DMF_SHIFT (13U)
26316 
26320 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
26321 #define LPSPI_SR_MBF_MASK (0x1000000U)
26322 #define LPSPI_SR_MBF_SHIFT (24U)
26323 
26327 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
26328 
26332 #define LPSPI_IER_TDIE_MASK (0x1U)
26333 #define LPSPI_IER_TDIE_SHIFT (0U)
26334 
26338 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
26339 #define LPSPI_IER_RDIE_MASK (0x2U)
26340 #define LPSPI_IER_RDIE_SHIFT (1U)
26341 
26345 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
26346 #define LPSPI_IER_WCIE_MASK (0x100U)
26347 #define LPSPI_IER_WCIE_SHIFT (8U)
26348 
26352 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
26353 #define LPSPI_IER_FCIE_MASK (0x200U)
26354 #define LPSPI_IER_FCIE_SHIFT (9U)
26355 
26359 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
26360 #define LPSPI_IER_TCIE_MASK (0x400U)
26361 #define LPSPI_IER_TCIE_SHIFT (10U)
26362 
26366 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
26367 #define LPSPI_IER_TEIE_MASK (0x800U)
26368 #define LPSPI_IER_TEIE_SHIFT (11U)
26369 
26373 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
26374 #define LPSPI_IER_REIE_MASK (0x1000U)
26375 #define LPSPI_IER_REIE_SHIFT (12U)
26376 
26380 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
26381 #define LPSPI_IER_DMIE_MASK (0x2000U)
26382 #define LPSPI_IER_DMIE_SHIFT (13U)
26383 
26387 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
26388 
26392 #define LPSPI_DER_TDDE_MASK (0x1U)
26393 #define LPSPI_DER_TDDE_SHIFT (0U)
26394 
26398 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
26399 #define LPSPI_DER_RDDE_MASK (0x2U)
26400 #define LPSPI_DER_RDDE_SHIFT (1U)
26401 
26405 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
26406 
26410 #define LPSPI_CFGR0_HREN_MASK (0x1U)
26411 #define LPSPI_CFGR0_HREN_SHIFT (0U)
26412 
26416 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
26417 #define LPSPI_CFGR0_HRPOL_MASK (0x2U)
26418 #define LPSPI_CFGR0_HRPOL_SHIFT (1U)
26419 
26423 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
26424 #define LPSPI_CFGR0_HRSEL_MASK (0x4U)
26425 #define LPSPI_CFGR0_HRSEL_SHIFT (2U)
26426 
26430 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
26431 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
26432 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
26433 
26437 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
26438 #define LPSPI_CFGR0_RDMO_MASK (0x200U)
26439 #define LPSPI_CFGR0_RDMO_SHIFT (9U)
26440 
26444 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
26445 
26449 #define LPSPI_CFGR1_MASTER_MASK (0x1U)
26450 #define LPSPI_CFGR1_MASTER_SHIFT (0U)
26451 
26455 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
26456 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
26457 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
26458 
26462 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
26463 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
26464 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
26465 
26469 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
26470 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
26471 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
26472 
26476 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
26477 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
26478 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
26479 
26483 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
26484 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
26485 #define LPSPI_CFGR1_MATCFG_SHIFT (16U)
26486 
26498 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
26499 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
26500 #define LPSPI_CFGR1_PINCFG_SHIFT (24U)
26501 
26507 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
26508 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
26509 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
26510 
26514 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
26515 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
26516 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
26517 
26521 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
26522 
26526 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
26527 #define LPSPI_DMR0_MATCH0_SHIFT (0U)
26528 
26530 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
26531 
26535 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
26536 #define LPSPI_DMR1_MATCH1_SHIFT (0U)
26537 
26539 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
26540 
26544 #define LPSPI_CCR_SCKDIV_MASK (0xFFU)
26545 #define LPSPI_CCR_SCKDIV_SHIFT (0U)
26546 
26548 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
26549 #define LPSPI_CCR_DBT_MASK (0xFF00U)
26550 #define LPSPI_CCR_DBT_SHIFT (8U)
26551 
26553 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
26554 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
26555 #define LPSPI_CCR_PCSSCK_SHIFT (16U)
26556 
26558 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
26559 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
26560 #define LPSPI_CCR_SCKPCS_SHIFT (24U)
26561 
26563 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
26564 
26568 #define LPSPI_FCR_TXWATER_MASK (0xFU)
26569 #define LPSPI_FCR_TXWATER_SHIFT (0U)
26570 
26572 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
26573 #define LPSPI_FCR_RXWATER_MASK (0xF0000U)
26574 #define LPSPI_FCR_RXWATER_SHIFT (16U)
26575 
26577 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
26578 
26582 #define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
26583 #define LPSPI_FSR_TXCOUNT_SHIFT (0U)
26584 
26586 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
26587 #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
26588 #define LPSPI_FSR_RXCOUNT_SHIFT (16U)
26589 
26591 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
26592 
26596 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
26597 #define LPSPI_TCR_FRAMESZ_SHIFT (0U)
26598 
26600 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
26601 #define LPSPI_TCR_WIDTH_MASK (0x30000U)
26602 #define LPSPI_TCR_WIDTH_SHIFT (16U)
26603 
26609 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
26610 #define LPSPI_TCR_TXMSK_MASK (0x40000U)
26611 #define LPSPI_TCR_TXMSK_SHIFT (18U)
26612 
26616 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
26617 #define LPSPI_TCR_RXMSK_MASK (0x80000U)
26618 #define LPSPI_TCR_RXMSK_SHIFT (19U)
26619 
26623 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
26624 #define LPSPI_TCR_CONTC_MASK (0x100000U)
26625 #define LPSPI_TCR_CONTC_SHIFT (20U)
26626 
26630 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
26631 #define LPSPI_TCR_CONT_MASK (0x200000U)
26632 #define LPSPI_TCR_CONT_SHIFT (21U)
26633 
26637 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
26638 #define LPSPI_TCR_BYSW_MASK (0x400000U)
26639 #define LPSPI_TCR_BYSW_SHIFT (22U)
26640 
26644 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
26645 #define LPSPI_TCR_LSBF_MASK (0x800000U)
26646 #define LPSPI_TCR_LSBF_SHIFT (23U)
26647 
26651 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
26652 #define LPSPI_TCR_PCS_MASK (0x3000000U)
26653 #define LPSPI_TCR_PCS_SHIFT (24U)
26654 
26660 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
26661 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
26662 #define LPSPI_TCR_PRESCALE_SHIFT (27U)
26663 
26673 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
26674 #define LPSPI_TCR_CPHA_MASK (0x40000000U)
26675 #define LPSPI_TCR_CPHA_SHIFT (30U)
26676 
26680 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
26681 #define LPSPI_TCR_CPOL_MASK (0x80000000U)
26682 #define LPSPI_TCR_CPOL_SHIFT (31U)
26683 
26687 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
26688 
26692 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
26693 #define LPSPI_TDR_DATA_SHIFT (0U)
26694 
26696 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
26697 
26701 #define LPSPI_RSR_SOF_MASK (0x1U)
26702 #define LPSPI_RSR_SOF_SHIFT (0U)
26703 
26707 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
26708 #define LPSPI_RSR_RXEMPTY_MASK (0x2U)
26709 #define LPSPI_RSR_RXEMPTY_SHIFT (1U)
26710 
26714 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
26715 
26719 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
26720 #define LPSPI_RDR_DATA_SHIFT (0U)
26721 
26723 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
26724  /* end of group LPSPI_Register_Masks */
26730 
26731 
26732 /* LPSPI - Peripheral instance base addresses */
26734 #define LPSPI1_BASE (0x40394000u)
26735 
26736 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
26737 
26738 #define LPSPI2_BASE (0x40398000u)
26739 
26740 #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
26741 
26742 #define LPSPI3_BASE (0x4039C000u)
26743 
26744 #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
26745 
26746 #define LPSPI4_BASE (0x403A0000u)
26747 
26748 #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
26749 
26750 #define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
26751 
26752 #define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
26753 
26754 #define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
26755  /* end of group LPSPI_Peripheral_Access_Layer */
26759 
26760 
26761 /* ----------------------------------------------------------------------------
26762  -- LPUART Peripheral Access Layer
26763  ---------------------------------------------------------------------------- */
26764 
26771 typedef struct {
26772  __I uint32_t VERID;
26773  __I uint32_t PARAM;
26774  __IO uint32_t GLOBAL;
26775  __IO uint32_t PINCFG;
26776  __IO uint32_t BAUD;
26777  __IO uint32_t STAT;
26778  __IO uint32_t CTRL;
26779  __IO uint32_t DATA;
26780  __IO uint32_t MATCH;
26781  __IO uint32_t MODIR;
26782  __IO uint32_t FIFO;
26783  __IO uint32_t WATER;
26784 } LPUART_Type;
26785 
26786 /* ----------------------------------------------------------------------------
26787  -- LPUART Register Masks
26788  ---------------------------------------------------------------------------- */
26789 
26797 #define LPUART_VERID_FEATURE_MASK (0xFFFFU)
26798 #define LPUART_VERID_FEATURE_SHIFT (0U)
26799 
26803 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
26804 #define LPUART_VERID_MINOR_MASK (0xFF0000U)
26805 #define LPUART_VERID_MINOR_SHIFT (16U)
26806 
26808 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
26809 #define LPUART_VERID_MAJOR_MASK (0xFF000000U)
26810 #define LPUART_VERID_MAJOR_SHIFT (24U)
26811 
26813 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
26814 
26818 #define LPUART_PARAM_TXFIFO_MASK (0xFFU)
26819 #define LPUART_PARAM_TXFIFO_SHIFT (0U)
26820 
26822 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
26823 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
26824 #define LPUART_PARAM_RXFIFO_SHIFT (8U)
26825 
26827 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
26828 
26832 #define LPUART_GLOBAL_RST_MASK (0x2U)
26833 #define LPUART_GLOBAL_RST_SHIFT (1U)
26834 
26838 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
26839 
26843 #define LPUART_PINCFG_TRGSEL_MASK (0x3U)
26844 #define LPUART_PINCFG_TRGSEL_SHIFT (0U)
26845 
26851 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
26852 
26856 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
26857 #define LPUART_BAUD_SBR_SHIFT (0U)
26858 
26860 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
26861 #define LPUART_BAUD_SBNS_MASK (0x2000U)
26862 #define LPUART_BAUD_SBNS_SHIFT (13U)
26863 
26867 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
26868 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
26869 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
26870 
26874 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
26875 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
26876 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
26877 
26881 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
26882 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
26883 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
26884 
26888 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
26889 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
26890 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
26891 
26895 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
26896 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
26897 #define LPUART_BAUD_MATCFG_SHIFT (18U)
26898 
26904 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
26905 #define LPUART_BAUD_RIDMAE_MASK (0x100000U)
26906 #define LPUART_BAUD_RIDMAE_SHIFT (20U)
26907 
26911 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
26912 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
26913 #define LPUART_BAUD_RDMAE_SHIFT (21U)
26914 
26918 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
26919 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
26920 #define LPUART_BAUD_TDMAE_SHIFT (23U)
26921 
26925 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
26926 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
26927 #define LPUART_BAUD_OSR_SHIFT (24U)
26928 
26962 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
26963 #define LPUART_BAUD_M10_MASK (0x20000000U)
26964 #define LPUART_BAUD_M10_SHIFT (29U)
26965 
26969 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
26970 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
26971 #define LPUART_BAUD_MAEN2_SHIFT (30U)
26972 
26976 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
26977 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
26978 #define LPUART_BAUD_MAEN1_SHIFT (31U)
26979 
26983 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
26984 
26988 #define LPUART_STAT_MA2F_MASK (0x4000U)
26989 #define LPUART_STAT_MA2F_SHIFT (14U)
26990 
26994 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
26995 #define LPUART_STAT_MA1F_MASK (0x8000U)
26996 #define LPUART_STAT_MA1F_SHIFT (15U)
26997 
27001 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
27002 #define LPUART_STAT_PF_MASK (0x10000U)
27003 #define LPUART_STAT_PF_SHIFT (16U)
27004 
27008 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
27009 #define LPUART_STAT_FE_MASK (0x20000U)
27010 #define LPUART_STAT_FE_SHIFT (17U)
27011 
27015 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
27016 #define LPUART_STAT_NF_MASK (0x40000U)
27017 #define LPUART_STAT_NF_SHIFT (18U)
27018 
27022 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
27023 #define LPUART_STAT_OR_MASK (0x80000U)
27024 #define LPUART_STAT_OR_SHIFT (19U)
27025 
27029 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
27030 #define LPUART_STAT_IDLE_MASK (0x100000U)
27031 #define LPUART_STAT_IDLE_SHIFT (20U)
27032 
27036 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
27037 #define LPUART_STAT_RDRF_MASK (0x200000U)
27038 #define LPUART_STAT_RDRF_SHIFT (21U)
27039 
27043 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
27044 #define LPUART_STAT_TC_MASK (0x400000U)
27045 #define LPUART_STAT_TC_SHIFT (22U)
27046 
27050 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
27051 #define LPUART_STAT_TDRE_MASK (0x800000U)
27052 #define LPUART_STAT_TDRE_SHIFT (23U)
27053 
27057 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
27058 #define LPUART_STAT_RAF_MASK (0x1000000U)
27059 #define LPUART_STAT_RAF_SHIFT (24U)
27060 
27064 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
27065 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
27066 #define LPUART_STAT_LBKDE_SHIFT (25U)
27067 
27071 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
27072 #define LPUART_STAT_BRK13_MASK (0x4000000U)
27073 #define LPUART_STAT_BRK13_SHIFT (26U)
27074 
27078 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
27079 #define LPUART_STAT_RWUID_MASK (0x8000000U)
27080 #define LPUART_STAT_RWUID_SHIFT (27U)
27081 
27087 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
27088 #define LPUART_STAT_RXINV_MASK (0x10000000U)
27089 #define LPUART_STAT_RXINV_SHIFT (28U)
27090 
27094 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
27095 #define LPUART_STAT_MSBF_MASK (0x20000000U)
27096 #define LPUART_STAT_MSBF_SHIFT (29U)
27097 
27104 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
27105 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
27106 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
27107 
27111 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
27112 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
27113 #define LPUART_STAT_LBKDIF_SHIFT (31U)
27114 
27118 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
27119 
27123 #define LPUART_CTRL_PT_MASK (0x1U)
27124 #define LPUART_CTRL_PT_SHIFT (0U)
27125 
27129 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
27130 #define LPUART_CTRL_PE_MASK (0x2U)
27131 #define LPUART_CTRL_PE_SHIFT (1U)
27132 
27136 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
27137 #define LPUART_CTRL_ILT_MASK (0x4U)
27138 #define LPUART_CTRL_ILT_SHIFT (2U)
27139 
27143 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
27144 #define LPUART_CTRL_WAKE_MASK (0x8U)
27145 #define LPUART_CTRL_WAKE_SHIFT (3U)
27146 
27150 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
27151 #define LPUART_CTRL_M_MASK (0x10U)
27152 #define LPUART_CTRL_M_SHIFT (4U)
27153 
27157 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
27158 #define LPUART_CTRL_RSRC_MASK (0x20U)
27159 #define LPUART_CTRL_RSRC_SHIFT (5U)
27160 
27164 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
27165 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
27166 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
27167 
27171 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
27172 #define LPUART_CTRL_LOOPS_MASK (0x80U)
27173 #define LPUART_CTRL_LOOPS_SHIFT (7U)
27174 
27178 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
27179 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
27180 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
27181 
27191 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
27192 #define LPUART_CTRL_M7_MASK (0x800U)
27193 #define LPUART_CTRL_M7_SHIFT (11U)
27194 
27198 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
27199 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
27200 #define LPUART_CTRL_MA2IE_SHIFT (14U)
27201 
27205 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
27206 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
27207 #define LPUART_CTRL_MA1IE_SHIFT (15U)
27208 
27212 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
27213 #define LPUART_CTRL_SBK_MASK (0x10000U)
27214 #define LPUART_CTRL_SBK_SHIFT (16U)
27215 
27219 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
27220 #define LPUART_CTRL_RWU_MASK (0x20000U)
27221 #define LPUART_CTRL_RWU_SHIFT (17U)
27222 
27226 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
27227 #define LPUART_CTRL_RE_MASK (0x40000U)
27228 #define LPUART_CTRL_RE_SHIFT (18U)
27229 
27233 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
27234 #define LPUART_CTRL_TE_MASK (0x80000U)
27235 #define LPUART_CTRL_TE_SHIFT (19U)
27236 
27240 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
27241 #define LPUART_CTRL_ILIE_MASK (0x100000U)
27242 #define LPUART_CTRL_ILIE_SHIFT (20U)
27243 
27247 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
27248 #define LPUART_CTRL_RIE_MASK (0x200000U)
27249 #define LPUART_CTRL_RIE_SHIFT (21U)
27250 
27254 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
27255 #define LPUART_CTRL_TCIE_MASK (0x400000U)
27256 #define LPUART_CTRL_TCIE_SHIFT (22U)
27257 
27261 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
27262 #define LPUART_CTRL_TIE_MASK (0x800000U)
27263 #define LPUART_CTRL_TIE_SHIFT (23U)
27264 
27268 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
27269 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
27270 #define LPUART_CTRL_PEIE_SHIFT (24U)
27271 
27275 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
27276 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
27277 #define LPUART_CTRL_FEIE_SHIFT (25U)
27278 
27282 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
27283 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
27284 #define LPUART_CTRL_NEIE_SHIFT (26U)
27285 
27289 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
27290 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
27291 #define LPUART_CTRL_ORIE_SHIFT (27U)
27292 
27296 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
27297 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
27298 #define LPUART_CTRL_TXINV_SHIFT (28U)
27299 
27303 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
27304 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
27305 #define LPUART_CTRL_TXDIR_SHIFT (29U)
27306 
27310 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
27311 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
27312 #define LPUART_CTRL_R9T8_SHIFT (30U)
27313 
27315 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
27316 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
27317 #define LPUART_CTRL_R8T9_SHIFT (31U)
27318 
27320 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
27321 
27325 #define LPUART_DATA_R0T0_MASK (0x1U)
27326 #define LPUART_DATA_R0T0_SHIFT (0U)
27327 
27329 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
27330 #define LPUART_DATA_R1T1_MASK (0x2U)
27331 #define LPUART_DATA_R1T1_SHIFT (1U)
27332 
27334 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
27335 #define LPUART_DATA_R2T2_MASK (0x4U)
27336 #define LPUART_DATA_R2T2_SHIFT (2U)
27337 
27339 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
27340 #define LPUART_DATA_R3T3_MASK (0x8U)
27341 #define LPUART_DATA_R3T3_SHIFT (3U)
27342 
27344 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
27345 #define LPUART_DATA_R4T4_MASK (0x10U)
27346 #define LPUART_DATA_R4T4_SHIFT (4U)
27347 
27349 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
27350 #define LPUART_DATA_R5T5_MASK (0x20U)
27351 #define LPUART_DATA_R5T5_SHIFT (5U)
27352 
27354 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
27355 #define LPUART_DATA_R6T6_MASK (0x40U)
27356 #define LPUART_DATA_R6T6_SHIFT (6U)
27357 
27359 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
27360 #define LPUART_DATA_R7T7_MASK (0x80U)
27361 #define LPUART_DATA_R7T7_SHIFT (7U)
27362 
27364 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
27365 #define LPUART_DATA_R8T8_MASK (0x100U)
27366 #define LPUART_DATA_R8T8_SHIFT (8U)
27367 
27369 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
27370 #define LPUART_DATA_R9T9_MASK (0x200U)
27371 #define LPUART_DATA_R9T9_SHIFT (9U)
27372 
27374 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
27375 #define LPUART_DATA_IDLINE_MASK (0x800U)
27376 #define LPUART_DATA_IDLINE_SHIFT (11U)
27377 
27381 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
27382 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
27383 #define LPUART_DATA_RXEMPT_SHIFT (12U)
27384 
27388 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
27389 #define LPUART_DATA_FRETSC_MASK (0x2000U)
27390 #define LPUART_DATA_FRETSC_SHIFT (13U)
27391 
27395 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
27396 #define LPUART_DATA_PARITYE_MASK (0x4000U)
27397 #define LPUART_DATA_PARITYE_SHIFT (14U)
27398 
27402 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
27403 #define LPUART_DATA_NOISY_MASK (0x8000U)
27404 #define LPUART_DATA_NOISY_SHIFT (15U)
27405 
27409 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
27410 
27414 #define LPUART_MATCH_MA1_MASK (0x3FFU)
27415 #define LPUART_MATCH_MA1_SHIFT (0U)
27416 
27418 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
27419 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
27420 #define LPUART_MATCH_MA2_SHIFT (16U)
27421 
27423 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
27424 
27428 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
27429 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
27430 
27437 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
27438 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
27439 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
27440 
27446 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
27447 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
27448 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
27449 
27453 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
27454 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
27455 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
27456 
27462 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
27463 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
27464 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
27465 
27469 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
27470 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
27471 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
27472 
27476 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
27477 #define LPUART_MODIR_RTSWATER_MASK (0x300U)
27478 #define LPUART_MODIR_RTSWATER_SHIFT (8U)
27479 
27481 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
27482 #define LPUART_MODIR_TNP_MASK (0x30000U)
27483 #define LPUART_MODIR_TNP_SHIFT (16U)
27484 
27490 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
27491 #define LPUART_MODIR_IREN_MASK (0x40000U)
27492 #define LPUART_MODIR_IREN_SHIFT (18U)
27493 
27497 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
27498 
27502 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
27503 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
27504 
27514 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
27515 #define LPUART_FIFO_RXFE_MASK (0x8U)
27516 #define LPUART_FIFO_RXFE_SHIFT (3U)
27517 
27521 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
27522 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
27523 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
27524 
27534 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
27535 #define LPUART_FIFO_TXFE_MASK (0x80U)
27536 #define LPUART_FIFO_TXFE_SHIFT (7U)
27537 
27541 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
27542 #define LPUART_FIFO_RXUFE_MASK (0x100U)
27543 #define LPUART_FIFO_RXUFE_SHIFT (8U)
27544 
27548 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
27549 #define LPUART_FIFO_TXOFE_MASK (0x200U)
27550 #define LPUART_FIFO_TXOFE_SHIFT (9U)
27551 
27555 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
27556 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
27557 #define LPUART_FIFO_RXIDEN_SHIFT (10U)
27558 
27568 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
27569 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
27570 #define LPUART_FIFO_RXFLUSH_SHIFT (14U)
27571 
27575 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
27576 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
27577 #define LPUART_FIFO_TXFLUSH_SHIFT (15U)
27578 
27582 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
27583 #define LPUART_FIFO_RXUF_MASK (0x10000U)
27584 #define LPUART_FIFO_RXUF_SHIFT (16U)
27585 
27589 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
27590 #define LPUART_FIFO_TXOF_MASK (0x20000U)
27591 #define LPUART_FIFO_TXOF_SHIFT (17U)
27592 
27596 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
27597 #define LPUART_FIFO_RXEMPT_MASK (0x400000U)
27598 #define LPUART_FIFO_RXEMPT_SHIFT (22U)
27599 
27603 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
27604 #define LPUART_FIFO_TXEMPT_MASK (0x800000U)
27605 #define LPUART_FIFO_TXEMPT_SHIFT (23U)
27606 
27610 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
27611 
27615 #define LPUART_WATER_TXWATER_MASK (0x3U)
27616 #define LPUART_WATER_TXWATER_SHIFT (0U)
27617 
27619 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
27620 #define LPUART_WATER_TXCOUNT_MASK (0x700U)
27621 #define LPUART_WATER_TXCOUNT_SHIFT (8U)
27622 
27624 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
27625 #define LPUART_WATER_RXWATER_MASK (0x30000U)
27626 #define LPUART_WATER_RXWATER_SHIFT (16U)
27627 
27629 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
27630 #define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
27631 #define LPUART_WATER_RXCOUNT_SHIFT (24U)
27632 
27634 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
27635  /* end of group LPUART_Register_Masks */
27641 
27642 
27643 /* LPUART - Peripheral instance base addresses */
27645 #define LPUART1_BASE (0x40184000u)
27646 
27647 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
27648 
27649 #define LPUART2_BASE (0x40188000u)
27650 
27651 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
27652 
27653 #define LPUART3_BASE (0x4018C000u)
27654 
27655 #define LPUART3 ((LPUART_Type *)LPUART3_BASE)
27656 
27657 #define LPUART4_BASE (0x40190000u)
27658 
27659 #define LPUART4 ((LPUART_Type *)LPUART4_BASE)
27660 
27661 #define LPUART5_BASE (0x40194000u)
27662 
27663 #define LPUART5 ((LPUART_Type *)LPUART5_BASE)
27664 
27665 #define LPUART6_BASE (0x40198000u)
27666 
27667 #define LPUART6 ((LPUART_Type *)LPUART6_BASE)
27668 
27669 #define LPUART7_BASE (0x4019C000u)
27670 
27671 #define LPUART7 ((LPUART_Type *)LPUART7_BASE)
27672 
27673 #define LPUART8_BASE (0x401A0000u)
27674 
27675 #define LPUART8 ((LPUART_Type *)LPUART8_BASE)
27676 
27677 #define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
27678 
27679 #define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
27680 
27681 #define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
27682  /* end of group LPUART_Peripheral_Access_Layer */
27686 
27687 
27688 /* ----------------------------------------------------------------------------
27689  -- OCOTP Peripheral Access Layer
27690  ---------------------------------------------------------------------------- */
27691 
27698 typedef struct {
27699  __IO uint32_t CTRL;
27700  __IO uint32_t CTRL_SET;
27701  __IO uint32_t CTRL_CLR;
27702  __IO uint32_t CTRL_TOG;
27703  __IO uint32_t TIMING;
27704  uint8_t RESERVED_0[12];
27705  __IO uint32_t DATA;
27706  uint8_t RESERVED_1[12];
27707  __IO uint32_t READ_CTRL;
27708  uint8_t RESERVED_2[12];
27709  __IO uint32_t READ_FUSE_DATA;
27710  uint8_t RESERVED_3[12];
27711  __IO uint32_t SW_STICKY;
27712  uint8_t RESERVED_4[12];
27713  __IO uint32_t SCS;
27714  __IO uint32_t SCS_SET;
27715  __IO uint32_t SCS_CLR;
27716  __IO uint32_t SCS_TOG;
27717  uint8_t RESERVED_5[32];
27718  __I uint32_t VERSION;
27719  uint8_t RESERVED_6[108];
27720  __IO uint32_t TIMING2;
27721  uint8_t RESERVED_7[764];
27722  __IO uint32_t LOCK;
27723  uint8_t RESERVED_8[12];
27724  __IO uint32_t CFG0;
27725  uint8_t RESERVED_9[12];
27726  __IO uint32_t CFG1;
27727  uint8_t RESERVED_10[12];
27728  __IO uint32_t CFG2;
27729  uint8_t RESERVED_11[12];
27730  __IO uint32_t CFG3;
27731  uint8_t RESERVED_12[12];
27732  __IO uint32_t CFG4;
27733  uint8_t RESERVED_13[12];
27734  __IO uint32_t CFG5;
27735  uint8_t RESERVED_14[12];
27736  __IO uint32_t CFG6;
27737  uint8_t RESERVED_15[12];
27738  __IO uint32_t MEM0;
27739  uint8_t RESERVED_16[12];
27740  __IO uint32_t MEM1;
27741  uint8_t RESERVED_17[12];
27742  __IO uint32_t MEM2;
27743  uint8_t RESERVED_18[12];
27744  __IO uint32_t MEM3;
27745  uint8_t RESERVED_19[12];
27746  __IO uint32_t MEM4;
27747  uint8_t RESERVED_20[12];
27748  __IO uint32_t ANA0;
27749  uint8_t RESERVED_21[12];
27750  __IO uint32_t ANA1;
27751  uint8_t RESERVED_22[12];
27752  __IO uint32_t ANA2;
27753  uint8_t RESERVED_23[140];
27754  __IO uint32_t SRK0;
27755  uint8_t RESERVED_24[12];
27756  __IO uint32_t SRK1;
27757  uint8_t RESERVED_25[12];
27758  __IO uint32_t SRK2;
27759  uint8_t RESERVED_26[12];
27760  __IO uint32_t SRK3;
27761  uint8_t RESERVED_27[12];
27762  __IO uint32_t SRK4;
27763  uint8_t RESERVED_28[12];
27764  __IO uint32_t SRK5;
27765  uint8_t RESERVED_29[12];
27766  __IO uint32_t SRK6;
27767  uint8_t RESERVED_30[12];
27768  __IO uint32_t SRK7;
27769  uint8_t RESERVED_31[12];
27770  __IO uint32_t SJC_RESP0;
27771  uint8_t RESERVED_32[12];
27772  __IO uint32_t SJC_RESP1;
27773  uint8_t RESERVED_33[12];
27774  __IO uint32_t MAC0;
27775  uint8_t RESERVED_34[12];
27776  __IO uint32_t MAC1;
27777  uint8_t RESERVED_35[12];
27778  __IO uint32_t GP3;
27779  uint8_t RESERVED_36[28];
27780  __IO uint32_t GP1;
27781  uint8_t RESERVED_37[12];
27782  __IO uint32_t GP2;
27783  uint8_t RESERVED_38[12];
27784  __IO uint32_t SW_GP1;
27785  uint8_t RESERVED_39[12];
27786  __IO uint32_t SW_GP20;
27787  uint8_t RESERVED_40[12];
27788  __IO uint32_t SW_GP21;
27789  uint8_t RESERVED_41[12];
27790  __IO uint32_t SW_GP22;
27791  uint8_t RESERVED_42[12];
27792  __IO uint32_t SW_GP23;
27793  uint8_t RESERVED_43[12];
27794  __IO uint32_t MISC_CONF0;
27795  uint8_t RESERVED_44[12];
27796  __IO uint32_t MISC_CONF1;
27797  uint8_t RESERVED_45[12];
27798  __IO uint32_t SRK_REVOKE;
27799 } OCOTP_Type;
27800 
27801 /* ----------------------------------------------------------------------------
27802  -- OCOTP Register Masks
27803  ---------------------------------------------------------------------------- */
27804 
27812 #define OCOTP_CTRL_ADDR_MASK (0x3FU)
27813 #define OCOTP_CTRL_ADDR_SHIFT (0U)
27814 #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
27815 #define OCOTP_CTRL_BUSY_MASK (0x100U)
27816 #define OCOTP_CTRL_BUSY_SHIFT (8U)
27817 #define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
27818 #define OCOTP_CTRL_ERROR_MASK (0x200U)
27819 #define OCOTP_CTRL_ERROR_SHIFT (9U)
27820 #define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
27821 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
27822 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
27823 #define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
27824 #define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
27825 #define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
27826 #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
27827 
27831 #define OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
27832 #define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
27833 #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
27834 #define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
27835 #define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
27836 #define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
27837 #define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
27838 #define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
27839 #define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
27840 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
27841 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
27842 #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
27843 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
27844 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
27845 #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
27846 
27850 #define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
27851 #define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
27852 #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
27853 #define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
27854 #define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
27855 #define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
27856 #define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
27857 #define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
27858 #define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
27859 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
27860 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
27861 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
27862 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
27863 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
27864 #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
27865 
27869 #define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
27870 #define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
27871 #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
27872 #define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
27873 #define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
27874 #define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
27875 #define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
27876 #define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
27877 #define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
27878 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
27879 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
27880 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
27881 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
27882 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
27883 #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
27884 
27888 #define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
27889 #define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
27890 #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
27891 #define OCOTP_TIMING_RELAX_MASK (0xF000U)
27892 #define OCOTP_TIMING_RELAX_SHIFT (12U)
27893 #define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
27894 #define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
27895 #define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
27896 #define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
27897 #define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
27898 #define OCOTP_TIMING_WAIT_SHIFT (22U)
27899 #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
27900 
27904 #define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
27905 #define OCOTP_DATA_DATA_SHIFT (0U)
27906 #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
27907 
27911 #define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
27912 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
27913 #define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
27914 
27918 #define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
27919 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
27920 #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
27921 
27925 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)
27926 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)
27927 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)
27928 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
27929 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
27930 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
27931 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
27932 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
27933 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
27934 #define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
27935 #define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
27936 #define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
27937 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
27938 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
27939 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
27940 
27944 #define OCOTP_SCS_HAB_JDE_MASK (0x1U)
27945 #define OCOTP_SCS_HAB_JDE_SHIFT (0U)
27946 #define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
27947 #define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
27948 #define OCOTP_SCS_SPARE_SHIFT (1U)
27949 #define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
27950 #define OCOTP_SCS_LOCK_MASK (0x80000000U)
27951 #define OCOTP_SCS_LOCK_SHIFT (31U)
27952 #define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
27953 
27957 #define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
27958 #define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
27959 #define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
27960 #define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
27961 #define OCOTP_SCS_SET_SPARE_SHIFT (1U)
27962 #define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
27963 #define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
27964 #define OCOTP_SCS_SET_LOCK_SHIFT (31U)
27965 #define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
27966 
27970 #define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
27971 #define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
27972 #define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
27973 #define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
27974 #define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
27975 #define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
27976 #define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
27977 #define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
27978 #define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
27979 
27983 #define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
27984 #define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
27985 #define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
27986 #define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
27987 #define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
27988 #define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
27989 #define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
27990 #define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
27991 #define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
27992 
27996 #define OCOTP_VERSION_STEP_MASK (0xFFFFU)
27997 #define OCOTP_VERSION_STEP_SHIFT (0U)
27998 #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
27999 #define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
28000 #define OCOTP_VERSION_MINOR_SHIFT (16U)
28001 #define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
28002 #define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
28003 #define OCOTP_VERSION_MAJOR_SHIFT (24U)
28004 #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
28005 
28009 #define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
28010 #define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
28011 #define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
28012 #define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
28013 #define OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
28014 #define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
28015 #define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U)
28016 #define OCOTP_TIMING2_RELAX1_SHIFT (22U)
28017 #define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK)
28018 
28022 #define OCOTP_LOCK_TESTER_MASK (0x3U)
28023 #define OCOTP_LOCK_TESTER_SHIFT (0U)
28024 #define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)
28025 #define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
28026 #define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
28027 #define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
28028 #define OCOTP_LOCK_MEM_TRIM_MASK (0x30U)
28029 #define OCOTP_LOCK_MEM_TRIM_SHIFT (4U)
28030 #define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)
28031 #define OCOTP_LOCK_SJC_RESP_MASK (0x40U)
28032 #define OCOTP_LOCK_SJC_RESP_SHIFT (6U)
28033 #define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
28034 #define OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
28035 #define OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
28036 #define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
28037 #define OCOTP_LOCK_GP1_MASK (0xC00U)
28038 #define OCOTP_LOCK_GP1_SHIFT (10U)
28039 #define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
28040 #define OCOTP_LOCK_GP2_MASK (0x3000U)
28041 #define OCOTP_LOCK_GP2_SHIFT (12U)
28042 #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
28043 #define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U)
28044 #define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U)
28045 #define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK)
28046 #define OCOTP_LOCK_SW_GP1_MASK (0x10000U)
28047 #define OCOTP_LOCK_SW_GP1_SHIFT (16U)
28048 #define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
28049 #define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U)
28050 #define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U)
28051 #define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK)
28052 #define OCOTP_LOCK_ANALOG_MASK (0xC0000U)
28053 #define OCOTP_LOCK_ANALOG_SHIFT (18U)
28054 #define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
28055 #define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)
28056 #define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U)
28057 #define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)
28058 #define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
28059 #define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
28060 #define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
28061 #define OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
28062 #define OCOTP_LOCK_MISC_CONF_SHIFT (22U)
28063 #define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
28064 #define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
28065 #define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
28066 #define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
28067 #define OCOTP_LOCK_GP3_MASK (0xC000000U)
28068 #define OCOTP_LOCK_GP3_SHIFT (26U)
28069 #define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
28070 #define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)
28071 #define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U)
28072 #define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
28073 
28077 #define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
28078 #define OCOTP_CFG0_BITS_SHIFT (0U)
28079 #define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
28080 
28084 #define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
28085 #define OCOTP_CFG1_BITS_SHIFT (0U)
28086 #define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
28087 
28091 #define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
28092 #define OCOTP_CFG2_BITS_SHIFT (0U)
28093 #define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
28094 
28098 #define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
28099 #define OCOTP_CFG3_BITS_SHIFT (0U)
28100 #define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
28101 
28105 #define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
28106 #define OCOTP_CFG4_BITS_SHIFT (0U)
28107 #define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
28108 
28112 #define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
28113 #define OCOTP_CFG5_BITS_SHIFT (0U)
28114 #define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
28115 
28119 #define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
28120 #define OCOTP_CFG6_BITS_SHIFT (0U)
28121 #define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
28122 
28126 #define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
28127 #define OCOTP_MEM0_BITS_SHIFT (0U)
28128 #define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
28129 
28133 #define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
28134 #define OCOTP_MEM1_BITS_SHIFT (0U)
28135 #define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
28136 
28140 #define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
28141 #define OCOTP_MEM2_BITS_SHIFT (0U)
28142 #define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
28143 
28147 #define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
28148 #define OCOTP_MEM3_BITS_SHIFT (0U)
28149 #define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
28150 
28154 #define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
28155 #define OCOTP_MEM4_BITS_SHIFT (0U)
28156 #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
28157 
28161 #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
28162 #define OCOTP_ANA0_BITS_SHIFT (0U)
28163 #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
28164 
28168 #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
28169 #define OCOTP_ANA1_BITS_SHIFT (0U)
28170 #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
28171 
28175 #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
28176 #define OCOTP_ANA2_BITS_SHIFT (0U)
28177 #define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
28178 
28182 #define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
28183 #define OCOTP_SRK0_BITS_SHIFT (0U)
28184 #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
28185 
28189 #define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
28190 #define OCOTP_SRK1_BITS_SHIFT (0U)
28191 #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
28192 
28196 #define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
28197 #define OCOTP_SRK2_BITS_SHIFT (0U)
28198 #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
28199 
28203 #define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
28204 #define OCOTP_SRK3_BITS_SHIFT (0U)
28205 #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
28206 
28210 #define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
28211 #define OCOTP_SRK4_BITS_SHIFT (0U)
28212 #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
28213 
28217 #define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
28218 #define OCOTP_SRK5_BITS_SHIFT (0U)
28219 #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
28220 
28224 #define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
28225 #define OCOTP_SRK6_BITS_SHIFT (0U)
28226 #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
28227 
28231 #define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
28232 #define OCOTP_SRK7_BITS_SHIFT (0U)
28233 #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
28234 
28238 #define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
28239 #define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
28240 #define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
28241 
28245 #define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
28246 #define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
28247 #define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
28248 
28252 #define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
28253 #define OCOTP_MAC0_BITS_SHIFT (0U)
28254 #define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
28255 
28259 #define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
28260 #define OCOTP_MAC1_BITS_SHIFT (0U)
28261 #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
28262 
28266 #define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)
28267 #define OCOTP_GP3_BITS_SHIFT (0U)
28268 #define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)
28269 
28273 #define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
28274 #define OCOTP_GP1_BITS_SHIFT (0U)
28275 #define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
28276 
28280 #define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
28281 #define OCOTP_GP2_BITS_SHIFT (0U)
28282 #define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
28283 
28287 #define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
28288 #define OCOTP_SW_GP1_BITS_SHIFT (0U)
28289 #define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
28290 
28294 #define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
28295 #define OCOTP_SW_GP20_BITS_SHIFT (0U)
28296 #define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
28297 
28301 #define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
28302 #define OCOTP_SW_GP21_BITS_SHIFT (0U)
28303 #define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
28304 
28308 #define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
28309 #define OCOTP_SW_GP22_BITS_SHIFT (0U)
28310 #define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
28311 
28315 #define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
28316 #define OCOTP_SW_GP23_BITS_SHIFT (0U)
28317 #define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
28318 
28322 #define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
28323 #define OCOTP_MISC_CONF0_BITS_SHIFT (0U)
28324 #define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
28325 
28329 #define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
28330 #define OCOTP_MISC_CONF1_BITS_SHIFT (0U)
28331 #define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
28332 
28336 #define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
28337 #define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
28338 #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
28339  /* end of group OCOTP_Register_Masks */
28345 
28346 
28347 /* OCOTP - Peripheral instance base addresses */
28349 #define OCOTP_BASE (0x401F4000u)
28350 
28351 #define OCOTP ((OCOTP_Type *)OCOTP_BASE)
28352 
28353 #define OCOTP_BASE_ADDRS { OCOTP_BASE }
28354 
28355 #define OCOTP_BASE_PTRS { OCOTP }
28356  /* end of group OCOTP_Peripheral_Access_Layer */
28360 
28361 
28362 /* ----------------------------------------------------------------------------
28363  -- PGC Peripheral Access Layer
28364  ---------------------------------------------------------------------------- */
28365 
28372 typedef struct {
28373  uint8_t RESERVED_0[544];
28374  __IO uint32_t MEGA_CTRL;
28375  __IO uint32_t MEGA_PUPSCR;
28376  __IO uint32_t MEGA_PDNSCR;
28377  __IO uint32_t MEGA_SR;
28378  uint8_t RESERVED_1[112];
28379  __IO uint32_t CPU_CTRL;
28380  __IO uint32_t CPU_PUPSCR;
28381  __IO uint32_t CPU_PDNSCR;
28382  __IO uint32_t CPU_SR;
28383 } PGC_Type;
28384 
28385 /* ----------------------------------------------------------------------------
28386  -- PGC Register Masks
28387  ---------------------------------------------------------------------------- */
28388 
28396 #define PGC_MEGA_CTRL_PCR_MASK (0x1U)
28397 #define PGC_MEGA_CTRL_PCR_SHIFT (0U)
28398 
28402 #define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
28403 
28407 #define PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
28408 #define PGC_MEGA_PUPSCR_SW_SHIFT (0U)
28409 #define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
28410 #define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
28411 #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
28412 #define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
28413 
28417 #define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
28418 #define PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
28419 #define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
28420 #define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
28421 #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
28422 #define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
28423 
28427 #define PGC_MEGA_SR_PSR_MASK (0x1U)
28428 #define PGC_MEGA_SR_PSR_SHIFT (0U)
28429 
28433 #define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
28434 
28438 #define PGC_CPU_CTRL_PCR_MASK (0x1U)
28439 #define PGC_CPU_CTRL_PCR_SHIFT (0U)
28440 
28444 #define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
28445 
28449 #define PGC_CPU_PUPSCR_SW_MASK (0x3FU)
28450 #define PGC_CPU_PUPSCR_SW_SHIFT (0U)
28451 #define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
28452 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
28453 #define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
28454 #define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
28455 
28459 #define PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
28460 #define PGC_CPU_PDNSCR_ISO_SHIFT (0U)
28461 #define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
28462 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
28463 #define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
28464 #define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
28465 
28469 #define PGC_CPU_SR_PSR_MASK (0x1U)
28470 #define PGC_CPU_SR_PSR_SHIFT (0U)
28471 
28475 #define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
28476  /* end of group PGC_Register_Masks */
28482 
28483 
28484 /* PGC - Peripheral instance base addresses */
28486 #define PGC_BASE (0x400F4000u)
28487 
28488 #define PGC ((PGC_Type *)PGC_BASE)
28489 
28490 #define PGC_BASE_ADDRS { PGC_BASE }
28491 
28492 #define PGC_BASE_PTRS { PGC }
28493  /* end of group PGC_Peripheral_Access_Layer */
28497 
28498 
28499 /* ----------------------------------------------------------------------------
28500  -- PIT Peripheral Access Layer
28501  ---------------------------------------------------------------------------- */
28502 
28509 typedef struct {
28510  __IO uint32_t MCR;
28511  uint8_t RESERVED_0[220];
28512  __I uint32_t LTMR64H;
28513  __I uint32_t LTMR64L;
28514  uint8_t RESERVED_1[24];
28515  struct { /* offset: 0x100, array step: 0x10 */
28516  __IO uint32_t LDVAL;
28517  __I uint32_t CVAL;
28518  __IO uint32_t TCTRL;
28519  __IO uint32_t TFLG;
28520  } CHANNEL[4];
28521 } PIT_Type;
28522 
28523 /* ----------------------------------------------------------------------------
28524  -- PIT Register Masks
28525  ---------------------------------------------------------------------------- */
28526 
28534 #define PIT_MCR_FRZ_MASK (0x1U)
28535 #define PIT_MCR_FRZ_SHIFT (0U)
28536 
28540 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
28541 #define PIT_MCR_MDIS_MASK (0x2U)
28542 #define PIT_MCR_MDIS_SHIFT (1U)
28543 
28547 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
28548 
28552 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
28553 #define PIT_LTMR64H_LTH_SHIFT (0U)
28554 
28556 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
28557 
28561 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
28562 #define PIT_LTMR64L_LTL_SHIFT (0U)
28563 
28565 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
28566 
28570 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
28571 #define PIT_LDVAL_TSV_SHIFT (0U)
28572 
28574 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
28575 
28577 /* The count of PIT_LDVAL */
28578 #define PIT_LDVAL_COUNT (4U)
28579 
28582 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
28583 #define PIT_CVAL_TVL_SHIFT (0U)
28584 
28586 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
28587 
28589 /* The count of PIT_CVAL */
28590 #define PIT_CVAL_COUNT (4U)
28591 
28594 #define PIT_TCTRL_TEN_MASK (0x1U)
28595 #define PIT_TCTRL_TEN_SHIFT (0U)
28596 
28600 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
28601 #define PIT_TCTRL_TIE_MASK (0x2U)
28602 #define PIT_TCTRL_TIE_SHIFT (1U)
28603 
28607 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
28608 #define PIT_TCTRL_CHN_MASK (0x4U)
28609 #define PIT_TCTRL_CHN_SHIFT (2U)
28610 
28614 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
28615 
28617 /* The count of PIT_TCTRL */
28618 #define PIT_TCTRL_COUNT (4U)
28619 
28622 #define PIT_TFLG_TIF_MASK (0x1U)
28623 #define PIT_TFLG_TIF_SHIFT (0U)
28624 
28628 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
28629 
28631 /* The count of PIT_TFLG */
28632 #define PIT_TFLG_COUNT (4U)
28633 
28634  /* end of group PIT_Register_Masks */
28638 
28639 
28640 /* PIT - Peripheral instance base addresses */
28642 #define PIT_BASE (0x40084000u)
28643 
28644 #define PIT ((PIT_Type *)PIT_BASE)
28645 
28646 #define PIT_BASE_ADDRS { PIT_BASE }
28647 
28648 #define PIT_BASE_PTRS { PIT }
28649 
28650 #define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
28651  /* end of group PIT_Peripheral_Access_Layer */
28655 
28656 
28657 /* ----------------------------------------------------------------------------
28658  -- PMU Peripheral Access Layer
28659  ---------------------------------------------------------------------------- */
28660 
28667 typedef struct {
28668  uint8_t RESERVED_0[272];
28669  __IO uint32_t REG_1P1;
28670  __IO uint32_t REG_1P1_SET;
28671  __IO uint32_t REG_1P1_CLR;
28672  __IO uint32_t REG_1P1_TOG;
28673  __IO uint32_t REG_3P0;
28674  __IO uint32_t REG_3P0_SET;
28675  __IO uint32_t REG_3P0_CLR;
28676  __IO uint32_t REG_3P0_TOG;
28677  __IO uint32_t REG_2P5;
28678  __IO uint32_t REG_2P5_SET;
28679  __IO uint32_t REG_2P5_CLR;
28680  __IO uint32_t REG_2P5_TOG;
28681  __IO uint32_t REG_CORE;
28682  __IO uint32_t REG_CORE_SET;
28683  __IO uint32_t REG_CORE_CLR;
28684  __IO uint32_t REG_CORE_TOG;
28685  __IO uint32_t MISC0;
28686  __IO uint32_t MISC0_SET;
28687  __IO uint32_t MISC0_CLR;
28688  __IO uint32_t MISC0_TOG;
28689  __IO uint32_t MISC1;
28690  __IO uint32_t MISC1_SET;
28691  __IO uint32_t MISC1_CLR;
28692  __IO uint32_t MISC1_TOG;
28693  __IO uint32_t MISC2;
28694  __IO uint32_t MISC2_SET;
28695  __IO uint32_t MISC2_CLR;
28696  __IO uint32_t MISC2_TOG;
28697 } PMU_Type;
28698 
28699 /* ----------------------------------------------------------------------------
28700  -- PMU Register Masks
28701  ---------------------------------------------------------------------------- */
28702 
28710 #define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
28711 #define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
28712 #define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
28713 #define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
28714 #define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
28715 #define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
28716 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
28717 #define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
28718 #define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
28719 #define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
28720 #define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
28721 #define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
28722 #define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
28723 #define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
28724 #define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
28725 #define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
28726 #define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
28727 
28732 #define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
28733 #define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
28734 #define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
28735 #define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
28736 #define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
28737 #define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
28738 #define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
28739 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
28740 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
28741 #define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
28742 #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
28743 #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
28744 
28748 #define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
28749 
28753 #define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
28754 #define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
28755 #define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
28756 #define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
28757 #define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
28758 #define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
28759 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
28760 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
28761 #define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
28762 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
28763 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
28764 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
28765 #define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
28766 #define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
28767 #define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
28768 #define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
28769 #define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
28770 
28775 #define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
28776 #define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
28777 #define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
28778 #define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
28779 #define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
28780 #define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
28781 #define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
28782 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
28783 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
28784 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
28785 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
28786 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
28787 
28791 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
28792 
28796 #define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
28797 #define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
28798 #define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
28799 #define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
28800 #define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
28801 #define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
28802 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
28803 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
28804 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
28805 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
28806 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
28807 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
28808 #define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
28809 #define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
28810 #define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
28811 #define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
28812 #define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
28813 
28818 #define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
28819 #define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
28820 #define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
28821 #define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
28822 #define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
28823 #define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
28824 #define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
28825 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
28826 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
28827 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
28828 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
28829 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
28830 
28834 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
28835 
28839 #define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
28840 #define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
28841 #define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
28842 #define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
28843 #define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
28844 #define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
28845 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
28846 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
28847 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
28848 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
28849 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
28850 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
28851 #define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
28852 #define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
28853 #define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
28854 #define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
28855 #define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
28856 
28861 #define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
28862 #define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
28863 #define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
28864 #define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
28865 #define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
28866 #define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
28867 #define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
28868 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
28869 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
28870 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
28871 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
28872 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
28873 
28877 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
28878 
28882 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
28883 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
28884 #define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
28885 #define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
28886 #define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
28887 #define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
28888 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
28889 #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
28890 #define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
28891 #define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
28892 #define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
28893 #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
28894 #define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
28895 #define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
28896 
28900 #define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
28901 #define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
28902 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
28903 
28908 #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
28909 #define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
28910 #define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
28911 #define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
28912 #define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
28913 #define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
28914 #define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
28915 
28919 #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
28920 #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
28921 #define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
28922 #define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
28923 #define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
28924 #define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
28925 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
28926 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
28927 #define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
28928 #define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
28929 #define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
28930 #define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
28931 #define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
28932 #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
28933 
28937 #define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
28938 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
28939 #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
28940 
28945 #define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
28946 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
28947 #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
28948 #define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
28949 #define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
28950 #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
28951 #define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
28952 
28956 #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
28957 #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
28958 #define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
28959 #define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
28960 #define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
28961 #define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
28962 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
28963 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
28964 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
28965 #define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
28966 #define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
28967 #define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
28968 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
28969 #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
28970 
28974 #define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
28975 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
28976 #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
28977 
28982 #define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
28983 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
28984 #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
28985 #define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
28986 #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
28987 #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
28988 #define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
28989 
28993 #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
28994 #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
28995 #define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
28996 #define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
28997 #define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
28998 #define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
28999 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
29000 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
29001 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
29002 #define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
29003 #define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
29004 #define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
29005 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
29006 #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
29007 
29011 #define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
29012 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
29013 #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
29014 
29019 #define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
29020 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
29021 #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
29022 #define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
29023 #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
29024 #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
29025 #define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
29026 
29030 #define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
29031 #define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
29032 #define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
29033 #define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
29034 #define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
29035 #define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
29036 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
29037 #define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
29038 #define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
29039 #define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
29040 #define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
29041 #define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
29042 #define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
29043 #define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
29044 #define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
29045 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
29046 #define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
29047 
29052 #define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
29053 #define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
29054 #define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
29055 #define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
29056 #define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
29057 #define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
29058 #define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
29059 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
29060 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
29061 #define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
29062 
29066 #define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
29067 #define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
29068 #define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
29069 #define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
29070 #define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
29071 #define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
29072 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
29073 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
29074 #define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
29075 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
29076 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
29077 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
29078 #define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
29079 #define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
29080 #define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
29081 #define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
29082 #define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
29083 
29088 #define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
29089 #define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
29090 #define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
29091 #define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
29092 #define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
29093 #define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
29094 #define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
29095 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
29096 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
29097 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
29098 
29102 #define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
29103 #define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
29104 #define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
29105 #define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
29106 #define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
29107 #define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
29108 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
29109 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
29110 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
29111 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
29112 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
29113 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
29114 #define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
29115 #define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
29116 #define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
29117 #define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
29118 #define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
29119 
29124 #define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
29125 #define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
29126 #define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
29127 #define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
29128 #define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
29129 #define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
29130 #define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
29131 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
29132 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
29133 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
29134 
29138 #define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
29139 #define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
29140 #define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
29141 #define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
29142 #define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
29143 #define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
29144 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
29145 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
29146 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
29147 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
29148 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
29149 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
29150 #define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
29151 #define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
29152 #define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
29153 #define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
29154 #define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
29155 
29160 #define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
29161 #define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
29162 #define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
29163 #define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
29164 #define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
29165 #define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
29166 #define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
29167 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
29168 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
29169 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
29170 
29174 #define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
29175 #define PMU_REG_CORE_REG0_TARG_SHIFT (0U)
29176 
29185 #define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
29186 #define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
29187 #define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
29188 
29208 #define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
29209 #define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
29210 #define PMU_REG_CORE_REG1_TARG_SHIFT (9U)
29211 
29222 #define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
29223 #define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
29224 #define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
29225 
29245 #define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
29246 #define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
29247 #define PMU_REG_CORE_REG2_TARG_SHIFT (18U)
29248 
29257 #define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
29258 #define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
29259 #define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
29260 
29280 #define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
29281 #define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
29282 #define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
29283 
29289 #define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
29290 #define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
29291 #define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
29292 #define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
29293 
29297 #define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
29298 #define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
29299 
29308 #define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
29309 #define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
29310 #define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
29311 
29331 #define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
29332 #define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
29333 #define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
29334 
29345 #define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
29346 #define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
29347 #define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
29348 
29368 #define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
29369 #define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
29370 #define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
29371 
29380 #define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
29381 #define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
29382 #define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
29383 
29403 #define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
29404 #define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
29405 #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
29406 
29412 #define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
29413 #define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
29414 #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
29415 #define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
29416 
29420 #define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
29421 #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
29422 
29431 #define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
29432 #define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
29433 #define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
29434 
29454 #define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
29455 #define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
29456 #define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
29457 
29468 #define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
29469 #define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
29470 #define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
29471 
29491 #define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
29492 #define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
29493 #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
29494 
29503 #define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
29504 #define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
29505 #define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
29506 
29526 #define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
29527 #define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
29528 #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
29529 
29535 #define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
29536 #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
29537 #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
29538 #define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
29539 
29543 #define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
29544 #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
29545 
29554 #define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
29555 #define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
29556 #define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
29557 
29577 #define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
29578 #define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
29579 #define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
29580 
29591 #define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
29592 #define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
29593 #define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
29594 
29614 #define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
29615 #define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
29616 #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
29617 
29626 #define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
29627 #define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
29628 #define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
29629 
29649 #define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
29650 #define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
29651 #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
29652 
29658 #define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
29659 #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
29660 #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
29661 #define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
29662 
29666 #define PMU_MISC0_REFTOP_PWD_MASK (0x1U)
29667 #define PMU_MISC0_REFTOP_PWD_SHIFT (0U)
29668 #define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
29669 #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
29670 #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
29671 
29675 #define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
29676 #define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
29677 #define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
29678 
29688 #define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
29689 #define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
29690 #define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
29691 #define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
29692 #define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
29693 #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
29694 
29700 #define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
29701 #define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
29702 #define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
29703 
29707 #define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
29708 #define PMU_MISC0_OSC_I_MASK (0x6000U)
29709 #define PMU_MISC0_OSC_I_SHIFT (13U)
29710 
29716 #define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
29717 #define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
29718 #define PMU_MISC0_OSC_XTALOK_SHIFT (15U)
29719 #define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
29720 #define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
29721 #define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
29722 #define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
29723 #define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
29724 #define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
29725 
29729 #define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
29730 #define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
29731 #define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
29732 
29742 #define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
29743 #define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
29744 #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
29745 
29749 #define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
29750 #define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
29751 #define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
29752 #define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
29753 #define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
29754 #define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
29755 
29759 #define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
29760 
29764 #define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
29765 #define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
29766 #define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
29767 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
29768 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
29769 
29773 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
29774 #define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
29775 #define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
29776 
29786 #define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
29787 #define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
29788 #define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
29789 #define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
29790 #define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
29791 #define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
29792 
29798 #define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
29799 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
29800 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
29801 
29805 #define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
29806 #define PMU_MISC0_SET_OSC_I_MASK (0x6000U)
29807 #define PMU_MISC0_SET_OSC_I_SHIFT (13U)
29808 
29814 #define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
29815 #define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
29816 #define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
29817 #define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
29818 #define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
29819 #define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
29820 #define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
29821 #define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
29822 #define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
29823 
29827 #define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
29828 #define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
29829 #define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
29830 
29840 #define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
29841 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
29842 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
29843 
29847 #define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
29848 #define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
29849 #define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
29850 #define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
29851 #define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
29852 #define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
29853 
29857 #define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
29858 
29862 #define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
29863 #define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
29864 #define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
29865 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
29866 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
29867 
29871 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
29872 #define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
29873 #define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
29874 
29884 #define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
29885 #define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
29886 #define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
29887 #define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
29888 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
29889 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
29890 
29896 #define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
29897 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
29898 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
29899 
29903 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
29904 #define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
29905 #define PMU_MISC0_CLR_OSC_I_SHIFT (13U)
29906 
29912 #define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
29913 #define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
29914 #define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
29915 #define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
29916 #define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
29917 #define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
29918 #define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
29919 #define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
29920 #define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
29921 
29925 #define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
29926 #define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
29927 #define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
29928 
29938 #define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
29939 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
29940 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
29941 
29945 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
29946 #define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
29947 #define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
29948 #define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
29949 #define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
29950 #define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
29951 
29955 #define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
29956 
29960 #define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
29961 #define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
29962 #define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
29963 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
29964 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
29965 
29969 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
29970 #define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
29971 #define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
29972 
29982 #define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
29983 #define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
29984 #define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
29985 #define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
29986 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
29987 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
29988 
29994 #define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
29995 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
29996 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
29997 
30001 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
30002 #define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
30003 #define PMU_MISC0_TOG_OSC_I_SHIFT (13U)
30004 
30010 #define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
30011 #define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
30012 #define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
30013 #define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
30014 #define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
30015 #define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
30016 #define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
30017 #define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
30018 #define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
30019 
30023 #define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
30024 #define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
30025 #define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
30026 
30036 #define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
30037 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
30038 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
30039 
30043 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
30044 #define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
30045 #define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
30046 #define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
30047 #define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
30048 #define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
30049 
30053 #define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
30054 
30058 #define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
30059 #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
30060 
30078 #define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
30079 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
30080 #define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
30081 
30104 #define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
30105 #define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
30106 #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
30107 #define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
30108 #define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
30109 #define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
30110 #define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
30111 #define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
30112 #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
30113 #define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
30114 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
30115 #define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
30116 #define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
30117 #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
30118 #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
30119 #define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
30120 #define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
30121 #define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
30122 #define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
30123 #define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
30124 #define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
30125 #define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
30126 #define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
30127 #define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
30128 #define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
30129 #define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
30130 #define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
30131 #define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
30132 #define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
30133 #define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
30134 #define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
30135 #define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
30136 #define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
30137 #define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
30138 
30142 #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
30143 #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
30144 
30162 #define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
30163 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
30164 #define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
30165 
30188 #define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
30189 #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
30190 #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
30191 #define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
30192 #define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
30193 #define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
30194 #define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
30195 #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
30196 #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
30197 #define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
30198 #define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
30199 #define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
30200 #define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
30201 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
30202 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
30203 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
30204 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
30205 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
30206 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
30207 #define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
30208 #define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
30209 #define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
30210 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
30211 #define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
30212 #define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
30213 #define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
30214 #define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
30215 #define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
30216 #define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
30217 #define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
30218 #define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
30219 #define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
30220 #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
30221 #define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
30222 
30226 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
30227 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
30228 
30246 #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
30247 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
30248 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
30249 
30272 #define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
30273 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
30274 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
30275 #define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
30276 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
30277 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
30278 #define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
30279 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
30280 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
30281 #define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
30282 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
30283 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
30284 #define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
30285 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
30286 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
30287 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
30288 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
30289 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
30290 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
30291 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
30292 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
30293 #define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
30294 #define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
30295 #define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
30296 #define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
30297 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
30298 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
30299 #define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
30300 #define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
30301 #define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
30302 #define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
30303 #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
30304 #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
30305 #define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
30306 
30310 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
30311 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
30312 
30330 #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
30331 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
30332 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
30333 
30356 #define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
30357 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
30358 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
30359 #define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
30360 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
30361 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
30362 #define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
30363 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
30364 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
30365 #define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
30366 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
30367 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
30368 #define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
30369 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
30370 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
30371 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
30372 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
30373 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
30374 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
30375 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
30376 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
30377 #define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
30378 #define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
30379 #define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
30380 #define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
30381 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
30382 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
30383 #define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
30384 #define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
30385 #define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
30386 #define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
30387 #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
30388 #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
30389 #define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
30390 
30394 #define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
30395 #define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
30396 
30400 #define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
30401 #define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
30402 #define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
30403 
30406 #define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
30407 #define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
30408 #define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
30409 #define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
30410 #define PMU_MISC2_PLL3_disable_MASK (0x80U)
30411 #define PMU_MISC2_PLL3_disable_SHIFT (7U)
30412 #define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
30413 #define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
30414 #define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
30415 
30419 #define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
30420 #define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
30421 #define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
30422 
30425 #define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
30426 #define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
30427 #define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
30428 #define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
30429 #define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
30430 #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
30431 
30435 #define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
30436 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
30437 #define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
30438 
30442 #define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
30443 #define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
30444 #define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
30445 #define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
30446 #define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
30447 #define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
30448 #define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
30449 #define PMU_MISC2_REG2_OK_MASK (0x400000U)
30450 #define PMU_MISC2_REG2_OK_SHIFT (22U)
30451 #define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
30452 #define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
30453 #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
30454 
30458 #define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
30459 #define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
30460 #define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
30461 
30467 #define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
30468 #define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
30469 #define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
30470 
30476 #define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
30477 #define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
30478 #define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
30479 
30485 #define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
30486 #define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
30487 #define PMU_MISC2_VIDEO_DIV_SHIFT (30U)
30488 
30494 #define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
30495 
30499 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
30500 #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
30501 
30505 #define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
30506 #define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
30507 #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
30508 
30511 #define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
30512 #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
30513 #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
30514 #define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
30515 #define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
30516 #define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
30517 #define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
30518 #define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
30519 #define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
30520 
30524 #define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
30525 #define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
30526 #define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
30527 
30530 #define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
30531 #define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
30532 #define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
30533 #define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
30534 #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
30535 #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
30536 
30540 #define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
30541 #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
30542 #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
30543 
30547 #define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
30548 #define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
30549 #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
30550 #define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
30551 #define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
30552 #define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
30553 #define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
30554 #define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
30555 #define PMU_MISC2_SET_REG2_OK_SHIFT (22U)
30556 #define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
30557 #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
30558 #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
30559 
30563 #define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
30564 #define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
30565 #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
30566 
30572 #define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
30573 #define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
30574 #define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
30575 
30581 #define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
30582 #define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
30583 #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
30584 
30590 #define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
30591 #define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
30592 #define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
30593 
30599 #define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
30600 
30604 #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
30605 #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
30606 
30610 #define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
30611 #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
30612 #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
30613 
30616 #define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
30617 #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
30618 #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
30619 #define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
30620 #define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
30621 #define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
30622 #define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
30623 #define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
30624 #define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
30625 
30629 #define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
30630 #define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
30631 #define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
30632 
30635 #define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
30636 #define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
30637 #define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
30638 #define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
30639 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
30640 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
30641 
30645 #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
30646 #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
30647 #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
30648 
30652 #define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
30653 #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
30654 #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
30655 #define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
30656 #define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
30657 #define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
30658 #define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
30659 #define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
30660 #define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
30661 #define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
30662 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
30663 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
30664 
30668 #define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
30669 #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
30670 #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
30671 
30677 #define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
30678 #define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
30679 #define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
30680 
30686 #define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
30687 #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
30688 #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
30689 
30695 #define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
30696 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
30697 #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
30698 
30704 #define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
30705 
30709 #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
30710 #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
30711 
30715 #define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
30716 #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
30717 #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
30718 
30721 #define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
30722 #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
30723 #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
30724 #define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
30725 #define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
30726 #define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
30727 #define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
30728 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
30729 #define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
30730 
30734 #define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
30735 #define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
30736 #define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
30737 
30740 #define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
30741 #define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
30742 #define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
30743 #define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
30744 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
30745 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
30746 
30750 #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
30751 #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
30752 #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
30753 
30757 #define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
30758 #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
30759 #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
30760 #define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
30761 #define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
30762 #define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
30763 #define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
30764 #define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
30765 #define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
30766 #define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
30767 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
30768 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
30769 
30773 #define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
30774 #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
30775 #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
30776 
30782 #define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
30783 #define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
30784 #define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
30785 
30791 #define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
30792 #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
30793 #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
30794 
30800 #define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
30801 #define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
30802 #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
30803 
30809 #define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
30810  /* end of group PMU_Register_Masks */
30816 
30817 
30818 /* PMU - Peripheral instance base addresses */
30820 #define PMU_BASE (0x400D8000u)
30821 
30822 #define PMU ((PMU_Type *)PMU_BASE)
30823 
30824 #define PMU_BASE_ADDRS { PMU_BASE }
30825 
30826 #define PMU_BASE_PTRS { PMU }
30827  /* end of group PMU_Peripheral_Access_Layer */
30831 
30832 
30833 /* ----------------------------------------------------------------------------
30834  -- PWM Peripheral Access Layer
30835  ---------------------------------------------------------------------------- */
30836 
30843 typedef struct {
30844  struct { /* offset: 0x0, array step: 0x60 */
30845  __I uint16_t CNT;
30846  __IO uint16_t INIT;
30847  __IO uint16_t CTRL2;
30848  __IO uint16_t CTRL;
30849  uint8_t RESERVED_0[2];
30850  __IO uint16_t VAL0;
30851  __IO uint16_t FRACVAL1;
30852  __IO uint16_t VAL1;
30853  __IO uint16_t FRACVAL2;
30854  __IO uint16_t VAL2;
30855  __IO uint16_t FRACVAL3;
30856  __IO uint16_t VAL3;
30857  __IO uint16_t FRACVAL4;
30858  __IO uint16_t VAL4;
30859  __IO uint16_t FRACVAL5;
30860  __IO uint16_t VAL5;
30861  __IO uint16_t FRCTRL;
30862  __IO uint16_t OCTRL;
30863  __IO uint16_t STS;
30864  __IO uint16_t INTEN;
30865  __IO uint16_t DMAEN;
30866  __IO uint16_t TCTRL;
30867  __IO uint16_t DISMAP[2];
30868  __IO uint16_t DTCNT0;
30869  __IO uint16_t DTCNT1;
30870  __IO uint16_t CAPTCTRLA;
30871  __IO uint16_t CAPTCOMPA;
30872  __IO uint16_t CAPTCTRLB;
30873  __IO uint16_t CAPTCOMPB;
30874  __IO uint16_t CAPTCTRLX;
30875  __IO uint16_t CAPTCOMPX;
30876  __I uint16_t CVAL0;
30877  __I uint16_t CVAL0CYC;
30878  __I uint16_t CVAL1;
30879  __I uint16_t CVAL1CYC;
30880  __I uint16_t CVAL2;
30881  __I uint16_t CVAL2CYC;
30882  __I uint16_t CVAL3;
30883  __I uint16_t CVAL3CYC;
30884  __I uint16_t CVAL4;
30885  __I uint16_t CVAL4CYC;
30886  __I uint16_t CVAL5;
30887  __I uint16_t CVAL5CYC;
30888  uint8_t RESERVED_1[8];
30889  } SM[4];
30890  __IO uint16_t OUTEN;
30891  __IO uint16_t MASK;
30892  __IO uint16_t SWCOUT;
30893  __IO uint16_t DTSRCSEL;
30894  __IO uint16_t MCTRL;
30895  __IO uint16_t MCTRL2;
30896  __IO uint16_t FCTRL;
30897  __IO uint16_t FSTS;
30898  __IO uint16_t FFILT;
30899  __IO uint16_t FTST;
30900  __IO uint16_t FCTRL2;
30901 } PWM_Type;
30902 
30903 /* ----------------------------------------------------------------------------
30904  -- PWM Register Masks
30905  ---------------------------------------------------------------------------- */
30906 
30914 #define PWM_CNT_CNT_MASK (0xFFFFU)
30915 #define PWM_CNT_CNT_SHIFT (0U)
30916 
30918 #define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
30919 
30921 /* The count of PWM_CNT */
30922 #define PWM_CNT_COUNT (4U)
30923 
30926 #define PWM_INIT_INIT_MASK (0xFFFFU)
30927 #define PWM_INIT_INIT_SHIFT (0U)
30928 
30930 #define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
30931 
30933 /* The count of PWM_INIT */
30934 #define PWM_INIT_COUNT (4U)
30935 
30938 #define PWM_CTRL2_CLK_SEL_MASK (0x3U)
30939 #define PWM_CTRL2_CLK_SEL_SHIFT (0U)
30940 
30947 #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
30948 #define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
30949 #define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
30950 
30955 #define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
30956 #define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
30957 #define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
30958 
30971 #define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
30972 #define PWM_CTRL2_FORCE_MASK (0x40U)
30973 #define PWM_CTRL2_FORCE_SHIFT (6U)
30974 
30976 #define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
30977 #define PWM_CTRL2_FRCEN_MASK (0x80U)
30978 #define PWM_CTRL2_FRCEN_SHIFT (7U)
30979 
30983 #define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
30984 #define PWM_CTRL2_INIT_SEL_MASK (0x300U)
30985 #define PWM_CTRL2_INIT_SEL_SHIFT (8U)
30986 
30995 #define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
30996 #define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
30997 #define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
30998 
31000 #define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
31001 #define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
31002 #define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
31003 
31005 #define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
31006 #define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
31007 #define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
31008 
31010 #define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
31011 #define PWM_CTRL2_INDEP_MASK (0x2000U)
31012 #define PWM_CTRL2_INDEP_SHIFT (13U)
31013 
31017 #define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
31018 #define PWM_CTRL2_WAITEN_MASK (0x4000U)
31019 #define PWM_CTRL2_WAITEN_SHIFT (14U)
31020 
31022 #define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
31023 #define PWM_CTRL2_DBGEN_MASK (0x8000U)
31024 #define PWM_CTRL2_DBGEN_SHIFT (15U)
31025 
31027 #define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
31028 
31030 /* The count of PWM_CTRL2 */
31031 #define PWM_CTRL2_COUNT (4U)
31032 
31035 #define PWM_CTRL_DBLEN_MASK (0x1U)
31036 #define PWM_CTRL_DBLEN_SHIFT (0U)
31037 
31041 #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
31042 #define PWM_CTRL_DBLX_MASK (0x2U)
31043 #define PWM_CTRL_DBLX_SHIFT (1U)
31044 
31048 #define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
31049 #define PWM_CTRL_LDMOD_MASK (0x4U)
31050 #define PWM_CTRL_LDMOD_SHIFT (2U)
31051 
31056 #define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
31057 #define PWM_CTRL_SPLIT_MASK (0x8U)
31058 #define PWM_CTRL_SPLIT_SHIFT (3U)
31059 
31063 #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
31064 #define PWM_CTRL_PRSC_MASK (0x70U)
31065 #define PWM_CTRL_PRSC_SHIFT (4U)
31066 
31076 #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
31077 #define PWM_CTRL_COMPMODE_MASK (0x80U)
31078 #define PWM_CTRL_COMPMODE_SHIFT (7U)
31079 
31089 #define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
31090 #define PWM_CTRL_DT_MASK (0x300U)
31091 #define PWM_CTRL_DT_SHIFT (8U)
31092 
31094 #define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
31095 #define PWM_CTRL_FULL_MASK (0x400U)
31096 #define PWM_CTRL_FULL_SHIFT (10U)
31097 
31101 #define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
31102 #define PWM_CTRL_HALF_MASK (0x800U)
31103 #define PWM_CTRL_HALF_SHIFT (11U)
31104 
31108 #define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
31109 #define PWM_CTRL_LDFQ_MASK (0xF000U)
31110 #define PWM_CTRL_LDFQ_SHIFT (12U)
31111 
31129 #define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
31130 
31132 /* The count of PWM_CTRL */
31133 #define PWM_CTRL_COUNT (4U)
31134 
31137 #define PWM_VAL0_VAL0_MASK (0xFFFFU)
31138 #define PWM_VAL0_VAL0_SHIFT (0U)
31139 
31141 #define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
31142 
31144 /* The count of PWM_VAL0 */
31145 #define PWM_VAL0_COUNT (4U)
31146 
31149 #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
31150 #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
31151 
31153 #define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
31154 
31156 /* The count of PWM_FRACVAL1 */
31157 #define PWM_FRACVAL1_COUNT (4U)
31158 
31161 #define PWM_VAL1_VAL1_MASK (0xFFFFU)
31162 #define PWM_VAL1_VAL1_SHIFT (0U)
31163 
31165 #define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
31166 
31168 /* The count of PWM_VAL1 */
31169 #define PWM_VAL1_COUNT (4U)
31170 
31173 #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
31174 #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
31175 
31177 #define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
31178 
31180 /* The count of PWM_FRACVAL2 */
31181 #define PWM_FRACVAL2_COUNT (4U)
31182 
31185 #define PWM_VAL2_VAL2_MASK (0xFFFFU)
31186 #define PWM_VAL2_VAL2_SHIFT (0U)
31187 
31189 #define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
31190 
31192 /* The count of PWM_VAL2 */
31193 #define PWM_VAL2_COUNT (4U)
31194 
31197 #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
31198 #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
31199 
31201 #define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
31202 
31204 /* The count of PWM_FRACVAL3 */
31205 #define PWM_FRACVAL3_COUNT (4U)
31206 
31209 #define PWM_VAL3_VAL3_MASK (0xFFFFU)
31210 #define PWM_VAL3_VAL3_SHIFT (0U)
31211 
31213 #define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
31214 
31216 /* The count of PWM_VAL3 */
31217 #define PWM_VAL3_COUNT (4U)
31218 
31221 #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
31222 #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
31223 
31225 #define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
31226 
31228 /* The count of PWM_FRACVAL4 */
31229 #define PWM_FRACVAL4_COUNT (4U)
31230 
31233 #define PWM_VAL4_VAL4_MASK (0xFFFFU)
31234 #define PWM_VAL4_VAL4_SHIFT (0U)
31235 
31237 #define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
31238 
31240 /* The count of PWM_VAL4 */
31241 #define PWM_VAL4_COUNT (4U)
31242 
31245 #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
31246 #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
31247 
31249 #define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
31250 
31252 /* The count of PWM_FRACVAL5 */
31253 #define PWM_FRACVAL5_COUNT (4U)
31254 
31257 #define PWM_VAL5_VAL5_MASK (0xFFFFU)
31258 #define PWM_VAL5_VAL5_SHIFT (0U)
31259 
31261 #define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
31262 
31264 /* The count of PWM_VAL5 */
31265 #define PWM_VAL5_COUNT (4U)
31266 
31269 #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
31270 #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
31271 
31275 #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
31276 #define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
31277 #define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
31278 
31282 #define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
31283 #define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
31284 #define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
31285 
31289 #define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
31290 #define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
31291 #define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
31292 
31296 #define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
31297 #define PWM_FRCTRL_TEST_MASK (0x8000U)
31298 #define PWM_FRCTRL_TEST_SHIFT (15U)
31299 
31301 #define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
31302 
31304 /* The count of PWM_FRCTRL */
31305 #define PWM_FRCTRL_COUNT (4U)
31306 
31309 #define PWM_OCTRL_PWMXFS_MASK (0x3U)
31310 #define PWM_OCTRL_PWMXFS_SHIFT (0U)
31311 
31317 #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
31318 #define PWM_OCTRL_PWMBFS_MASK (0xCU)
31319 #define PWM_OCTRL_PWMBFS_SHIFT (2U)
31320 
31326 #define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
31327 #define PWM_OCTRL_PWMAFS_MASK (0x30U)
31328 #define PWM_OCTRL_PWMAFS_SHIFT (4U)
31329 
31335 #define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
31336 #define PWM_OCTRL_POLX_MASK (0x100U)
31337 #define PWM_OCTRL_POLX_SHIFT (8U)
31338 
31342 #define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
31343 #define PWM_OCTRL_POLB_MASK (0x200U)
31344 #define PWM_OCTRL_POLB_SHIFT (9U)
31345 
31349 #define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
31350 #define PWM_OCTRL_POLA_MASK (0x400U)
31351 #define PWM_OCTRL_POLA_SHIFT (10U)
31352 
31356 #define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
31357 #define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
31358 #define PWM_OCTRL_PWMX_IN_SHIFT (13U)
31359 
31361 #define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
31362 #define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
31363 #define PWM_OCTRL_PWMB_IN_SHIFT (14U)
31364 
31366 #define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
31367 #define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
31368 #define PWM_OCTRL_PWMA_IN_SHIFT (15U)
31369 
31371 #define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
31372 
31374 /* The count of PWM_OCTRL */
31375 #define PWM_OCTRL_COUNT (4U)
31376 
31379 #define PWM_STS_CMPF_MASK (0x3FU)
31380 #define PWM_STS_CMPF_SHIFT (0U)
31381 
31385 #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
31386 #define PWM_STS_CFX0_MASK (0x40U)
31387 #define PWM_STS_CFX0_SHIFT (6U)
31388 
31390 #define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
31391 #define PWM_STS_CFX1_MASK (0x80U)
31392 #define PWM_STS_CFX1_SHIFT (7U)
31393 
31395 #define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
31396 #define PWM_STS_CFB0_MASK (0x100U)
31397 #define PWM_STS_CFB0_SHIFT (8U)
31398 
31400 #define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
31401 #define PWM_STS_CFB1_MASK (0x200U)
31402 #define PWM_STS_CFB1_SHIFT (9U)
31403 
31405 #define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
31406 #define PWM_STS_CFA0_MASK (0x400U)
31407 #define PWM_STS_CFA0_SHIFT (10U)
31408 
31410 #define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
31411 #define PWM_STS_CFA1_MASK (0x800U)
31412 #define PWM_STS_CFA1_SHIFT (11U)
31413 
31415 #define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
31416 #define PWM_STS_RF_MASK (0x1000U)
31417 #define PWM_STS_RF_SHIFT (12U)
31418 
31422 #define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
31423 #define PWM_STS_REF_MASK (0x2000U)
31424 #define PWM_STS_REF_SHIFT (13U)
31425 
31429 #define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
31430 #define PWM_STS_RUF_MASK (0x4000U)
31431 #define PWM_STS_RUF_SHIFT (14U)
31432 
31436 #define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
31437 
31439 /* The count of PWM_STS */
31440 #define PWM_STS_COUNT (4U)
31441 
31444 #define PWM_INTEN_CMPIE_MASK (0x3FU)
31445 #define PWM_INTEN_CMPIE_SHIFT (0U)
31446 
31450 #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
31451 #define PWM_INTEN_CX0IE_MASK (0x40U)
31452 #define PWM_INTEN_CX0IE_SHIFT (6U)
31453 
31457 #define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
31458 #define PWM_INTEN_CX1IE_MASK (0x80U)
31459 #define PWM_INTEN_CX1IE_SHIFT (7U)
31460 
31464 #define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
31465 #define PWM_INTEN_CB0IE_MASK (0x100U)
31466 #define PWM_INTEN_CB0IE_SHIFT (8U)
31467 
31471 #define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
31472 #define PWM_INTEN_CB1IE_MASK (0x200U)
31473 #define PWM_INTEN_CB1IE_SHIFT (9U)
31474 
31478 #define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
31479 #define PWM_INTEN_CA0IE_MASK (0x400U)
31480 #define PWM_INTEN_CA0IE_SHIFT (10U)
31481 
31485 #define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
31486 #define PWM_INTEN_CA1IE_MASK (0x800U)
31487 #define PWM_INTEN_CA1IE_SHIFT (11U)
31488 
31492 #define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
31493 #define PWM_INTEN_RIE_MASK (0x1000U)
31494 #define PWM_INTEN_RIE_SHIFT (12U)
31495 
31499 #define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
31500 #define PWM_INTEN_REIE_MASK (0x2000U)
31501 #define PWM_INTEN_REIE_SHIFT (13U)
31502 
31506 #define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
31507 
31509 /* The count of PWM_INTEN */
31510 #define PWM_INTEN_COUNT (4U)
31511 
31514 #define PWM_DMAEN_CX0DE_MASK (0x1U)
31515 #define PWM_DMAEN_CX0DE_SHIFT (0U)
31516 
31518 #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
31519 #define PWM_DMAEN_CX1DE_MASK (0x2U)
31520 #define PWM_DMAEN_CX1DE_SHIFT (1U)
31521 
31523 #define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
31524 #define PWM_DMAEN_CB0DE_MASK (0x4U)
31525 #define PWM_DMAEN_CB0DE_SHIFT (2U)
31526 
31528 #define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
31529 #define PWM_DMAEN_CB1DE_MASK (0x8U)
31530 #define PWM_DMAEN_CB1DE_SHIFT (3U)
31531 
31533 #define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
31534 #define PWM_DMAEN_CA0DE_MASK (0x10U)
31535 #define PWM_DMAEN_CA0DE_SHIFT (4U)
31536 
31538 #define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
31539 #define PWM_DMAEN_CA1DE_MASK (0x20U)
31540 #define PWM_DMAEN_CA1DE_SHIFT (5U)
31541 
31543 #define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
31544 #define PWM_DMAEN_CAPTDE_MASK (0xC0U)
31545 #define PWM_DMAEN_CAPTDE_SHIFT (6U)
31546 
31554 #define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
31555 #define PWM_DMAEN_FAND_MASK (0x100U)
31556 #define PWM_DMAEN_FAND_SHIFT (8U)
31557 
31561 #define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
31562 #define PWM_DMAEN_VALDE_MASK (0x200U)
31563 #define PWM_DMAEN_VALDE_SHIFT (9U)
31564 
31568 #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
31569 
31571 /* The count of PWM_DMAEN */
31572 #define PWM_DMAEN_COUNT (4U)
31573 
31576 #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
31577 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
31578 
31582 #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
31583 #define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
31584 #define PWM_TCTRL_TRGFRQ_SHIFT (12U)
31585 
31590 #define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
31591 #define PWM_TCTRL_PWBOT1_MASK (0x4000U)
31592 #define PWM_TCTRL_PWBOT1_SHIFT (14U)
31593 
31597 #define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
31598 #define PWM_TCTRL_PWAOT0_MASK (0x8000U)
31599 #define PWM_TCTRL_PWAOT0_SHIFT (15U)
31600 
31604 #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
31605 
31607 /* The count of PWM_TCTRL */
31608 #define PWM_TCTRL_COUNT (4U)
31609 
31612 #define PWM_DISMAP_DIS0A_MASK (0xFU)
31613 #define PWM_DISMAP_DIS0A_SHIFT (0U)
31614 
31616 #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
31617 #define PWM_DISMAP_DIS1A_MASK (0xFU)
31618 #define PWM_DISMAP_DIS1A_SHIFT (0U)
31619 
31621 #define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
31622 #define PWM_DISMAP_DIS0B_MASK (0xF0U)
31623 #define PWM_DISMAP_DIS0B_SHIFT (4U)
31624 
31626 #define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
31627 #define PWM_DISMAP_DIS1B_MASK (0xF0U)
31628 #define PWM_DISMAP_DIS1B_SHIFT (4U)
31629 
31631 #define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
31632 #define PWM_DISMAP_DIS0X_MASK (0xF00U)
31633 #define PWM_DISMAP_DIS0X_SHIFT (8U)
31634 
31636 #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
31637 #define PWM_DISMAP_DIS1X_MASK (0xF00U)
31638 #define PWM_DISMAP_DIS1X_SHIFT (8U)
31639 
31641 #define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
31642 
31644 /* The count of PWM_DISMAP */
31645 #define PWM_DISMAP_COUNT (4U)
31646 
31647 /* The count of PWM_DISMAP */
31648 #define PWM_DISMAP_COUNT2 (2U)
31649 
31652 #define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
31653 #define PWM_DTCNT0_DTCNT0_SHIFT (0U)
31654 
31656 #define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
31657 
31659 /* The count of PWM_DTCNT0 */
31660 #define PWM_DTCNT0_COUNT (4U)
31661 
31664 #define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
31665 #define PWM_DTCNT1_DTCNT1_SHIFT (0U)
31666 
31668 #define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
31669 
31671 /* The count of PWM_DTCNT1 */
31672 #define PWM_DTCNT1_COUNT (4U)
31673 
31676 #define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
31677 #define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
31678 
31682 #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
31683 #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
31684 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
31685 
31697 #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
31698 #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
31699 #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
31700 
31706 #define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
31707 #define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
31708 #define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
31709 
31715 #define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
31716 #define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
31717 #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
31718 
31725 #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
31726 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
31727 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
31728 
31732 #define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
31733 #define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
31734 #define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
31735 
31737 #define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
31738 #define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
31739 #define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
31740 
31742 #define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
31743 #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
31744 #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
31745 
31747 #define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
31748 
31750 /* The count of PWM_CAPTCTRLA */
31751 #define PWM_CAPTCTRLA_COUNT (4U)
31752 
31755 #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
31756 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
31757 
31759 #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
31760 #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
31761 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
31762 
31764 #define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
31765 
31767 /* The count of PWM_CAPTCOMPA */
31768 #define PWM_CAPTCOMPA_COUNT (4U)
31769 
31772 #define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
31773 #define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
31774 
31778 #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
31779 #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
31780 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
31781 
31793 #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
31794 #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
31795 #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
31796 
31802 #define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
31803 #define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
31804 #define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
31805 
31811 #define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
31812 #define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
31813 #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
31814 
31821 #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
31822 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
31823 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
31824 
31828 #define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
31829 #define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
31830 #define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
31831 
31833 #define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
31834 #define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
31835 #define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
31836 
31838 #define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
31839 #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
31840 #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
31841 
31843 #define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
31844 
31846 /* The count of PWM_CAPTCTRLB */
31847 #define PWM_CAPTCTRLB_COUNT (4U)
31848 
31851 #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
31852 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
31853 
31855 #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
31856 #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
31857 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
31858 
31860 #define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
31861 
31863 /* The count of PWM_CAPTCOMPB */
31864 #define PWM_CAPTCOMPB_COUNT (4U)
31865 
31868 #define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
31869 #define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
31870 
31874 #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
31875 #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
31876 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
31877 
31889 #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
31890 #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
31891 #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
31892 
31898 #define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
31899 #define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
31900 #define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
31901 
31907 #define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
31908 #define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
31909 #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
31910 
31917 #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
31918 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
31919 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
31920 
31924 #define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
31925 #define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
31926 #define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
31927 
31929 #define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
31930 #define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
31931 #define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
31932 
31934 #define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
31935 #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
31936 #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
31937 
31939 #define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
31940 
31942 /* The count of PWM_CAPTCTRLX */
31943 #define PWM_CAPTCTRLX_COUNT (4U)
31944 
31947 #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
31948 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
31949 
31951 #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
31952 #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
31953 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
31954 
31956 #define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
31957 
31959 /* The count of PWM_CAPTCOMPX */
31960 #define PWM_CAPTCOMPX_COUNT (4U)
31961 
31964 #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
31965 #define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
31966 
31968 #define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
31969 
31971 /* The count of PWM_CVAL0 */
31972 #define PWM_CVAL0_COUNT (4U)
31973 
31976 #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
31977 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
31978 
31980 #define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
31981 
31983 /* The count of PWM_CVAL0CYC */
31984 #define PWM_CVAL0CYC_COUNT (4U)
31985 
31988 #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
31989 #define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
31990 
31992 #define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
31993 
31995 /* The count of PWM_CVAL1 */
31996 #define PWM_CVAL1_COUNT (4U)
31997 
32000 #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
32001 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
32002 
32004 #define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
32005 
32007 /* The count of PWM_CVAL1CYC */
32008 #define PWM_CVAL1CYC_COUNT (4U)
32009 
32012 #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
32013 #define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
32014 
32016 #define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
32017 
32019 /* The count of PWM_CVAL2 */
32020 #define PWM_CVAL2_COUNT (4U)
32021 
32024 #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
32025 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
32026 
32028 #define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
32029 
32031 /* The count of PWM_CVAL2CYC */
32032 #define PWM_CVAL2CYC_COUNT (4U)
32033 
32036 #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
32037 #define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
32038 
32040 #define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
32041 
32043 /* The count of PWM_CVAL3 */
32044 #define PWM_CVAL3_COUNT (4U)
32045 
32048 #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
32049 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
32050 
32052 #define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
32053 
32055 /* The count of PWM_CVAL3CYC */
32056 #define PWM_CVAL3CYC_COUNT (4U)
32057 
32060 #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
32061 #define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
32062 
32064 #define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
32065 
32067 /* The count of PWM_CVAL4 */
32068 #define PWM_CVAL4_COUNT (4U)
32069 
32072 #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
32073 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
32074 
32076 #define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
32077 
32079 /* The count of PWM_CVAL4CYC */
32080 #define PWM_CVAL4CYC_COUNT (4U)
32081 
32084 #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
32085 #define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
32086 
32088 #define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
32089 
32091 /* The count of PWM_CVAL5 */
32092 #define PWM_CVAL5_COUNT (4U)
32093 
32096 #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
32097 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
32098 
32100 #define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
32101 
32103 /* The count of PWM_CVAL5CYC */
32104 #define PWM_CVAL5CYC_COUNT (4U)
32105 
32108 #define PWM_OUTEN_PWMX_EN_MASK (0xFU)
32109 #define PWM_OUTEN_PWMX_EN_SHIFT (0U)
32110 
32114 #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
32115 #define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
32116 #define PWM_OUTEN_PWMB_EN_SHIFT (4U)
32117 
32121 #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
32122 #define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
32123 #define PWM_OUTEN_PWMA_EN_SHIFT (8U)
32124 
32128 #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
32129 
32133 #define PWM_MASK_MASKX_MASK (0xFU)
32134 #define PWM_MASK_MASKX_SHIFT (0U)
32135 
32139 #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
32140 #define PWM_MASK_MASKB_MASK (0xF0U)
32141 #define PWM_MASK_MASKB_SHIFT (4U)
32142 
32146 #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
32147 #define PWM_MASK_MASKA_MASK (0xF00U)
32148 #define PWM_MASK_MASKA_SHIFT (8U)
32149 
32153 #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
32154 #define PWM_MASK_UPDATE_MASK_MASK (0xF000U)
32155 #define PWM_MASK_UPDATE_MASK_SHIFT (12U)
32156 
32160 #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
32161 
32165 #define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
32166 #define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
32167 
32171 #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
32172 #define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
32173 #define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
32174 
32178 #define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
32179 #define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
32180 #define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
32181 
32185 #define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
32186 #define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
32187 #define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
32188 
32192 #define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
32193 #define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
32194 #define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
32195 
32199 #define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
32200 #define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
32201 #define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
32202 
32206 #define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
32207 #define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
32208 #define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
32209 
32213 #define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
32214 #define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
32215 #define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
32216 
32220 #define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
32221 
32225 #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
32226 #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
32227 
32233 #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
32234 #define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
32235 #define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
32236 
32242 #define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
32243 #define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
32244 #define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
32245 
32251 #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
32252 #define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
32253 #define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
32254 
32260 #define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
32261 #define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
32262 #define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
32263 
32269 #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
32270 #define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
32271 #define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
32272 
32278 #define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
32279 #define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
32280 #define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
32281 
32287 #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
32288 #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
32289 #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
32290 
32296 #define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
32297 
32301 #define PWM_MCTRL_LDOK_MASK (0xFU)
32302 #define PWM_MCTRL_LDOK_SHIFT (0U)
32303 
32307 #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
32308 #define PWM_MCTRL_CLDOK_MASK (0xF0U)
32309 #define PWM_MCTRL_CLDOK_SHIFT (4U)
32310 
32312 #define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
32313 #define PWM_MCTRL_RUN_MASK (0xF00U)
32314 #define PWM_MCTRL_RUN_SHIFT (8U)
32315 
32319 #define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
32320 #define PWM_MCTRL_IPOL_MASK (0xF000U)
32321 #define PWM_MCTRL_IPOL_SHIFT (12U)
32322 
32326 #define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
32327 
32331 #define PWM_MCTRL2_MONPLL_MASK (0x3U)
32332 #define PWM_MCTRL2_MONPLL_SHIFT (0U)
32333 
32341 #define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
32342 
32346 #define PWM_FCTRL_FIE_MASK (0xFU)
32347 #define PWM_FCTRL_FIE_SHIFT (0U)
32348 
32352 #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
32353 #define PWM_FCTRL_FSAFE_MASK (0xF0U)
32354 #define PWM_FCTRL_FSAFE_SHIFT (4U)
32355 
32364 #define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
32365 #define PWM_FCTRL_FAUTO_MASK (0xF00U)
32366 #define PWM_FCTRL_FAUTO_SHIFT (8U)
32367 
32375 #define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
32376 #define PWM_FCTRL_FLVL_MASK (0xF000U)
32377 #define PWM_FCTRL_FLVL_SHIFT (12U)
32378 
32382 #define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
32383 
32387 #define PWM_FSTS_FFLAG_MASK (0xFU)
32388 #define PWM_FSTS_FFLAG_SHIFT (0U)
32389 
32393 #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
32394 #define PWM_FSTS_FFULL_MASK (0xF0U)
32395 #define PWM_FSTS_FFULL_SHIFT (4U)
32396 
32400 #define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
32401 #define PWM_FSTS_FFPIN_MASK (0xF00U)
32402 #define PWM_FSTS_FFPIN_SHIFT (8U)
32403 
32405 #define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
32406 #define PWM_FSTS_FHALF_MASK (0xF000U)
32407 #define PWM_FSTS_FHALF_SHIFT (12U)
32408 
32412 #define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
32413 
32417 #define PWM_FFILT_FILT_PER_MASK (0xFFU)
32418 #define PWM_FFILT_FILT_PER_SHIFT (0U)
32419 
32421 #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
32422 #define PWM_FFILT_FILT_CNT_MASK (0x700U)
32423 #define PWM_FFILT_FILT_CNT_SHIFT (8U)
32424 
32426 #define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
32427 #define PWM_FFILT_GSTR_MASK (0x8000U)
32428 #define PWM_FFILT_GSTR_SHIFT (15U)
32429 
32433 #define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
32434 
32438 #define PWM_FTST_FTEST_MASK (0x1U)
32439 #define PWM_FTST_FTEST_SHIFT (0U)
32440 
32444 #define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
32445 
32449 #define PWM_FCTRL2_NOCOMB_MASK (0xFU)
32450 #define PWM_FCTRL2_NOCOMB_SHIFT (0U)
32451 
32457 #define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
32458  /* end of group PWM_Register_Masks */
32464 
32465 
32466 /* PWM - Peripheral instance base addresses */
32468 #define PWM1_BASE (0x403DC000u)
32469 
32470 #define PWM1 ((PWM_Type *)PWM1_BASE)
32471 
32472 #define PWM2_BASE (0x403E0000u)
32473 
32474 #define PWM2 ((PWM_Type *)PWM2_BASE)
32475 
32476 #define PWM3_BASE (0x403E4000u)
32477 
32478 #define PWM3 ((PWM_Type *)PWM3_BASE)
32479 
32480 #define PWM4_BASE (0x403E8000u)
32481 
32482 #define PWM4 ((PWM_Type *)PWM4_BASE)
32483 
32484 #define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
32485 
32486 #define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
32487 
32488 #define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
32489 #define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
32490 #define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
32491 #define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
32492 #define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
32493  /* end of group PWM_Peripheral_Access_Layer */
32497 
32498 
32499 /* ----------------------------------------------------------------------------
32500  -- PXP Peripheral Access Layer
32501  ---------------------------------------------------------------------------- */
32502 
32509 typedef struct {
32510  __IO uint32_t CTRL;
32511  __IO uint32_t CTRL_SET;
32512  __IO uint32_t CTRL_CLR;
32513  __IO uint32_t CTRL_TOG;
32514  __IO uint32_t STAT;
32515  __IO uint32_t STAT_SET;
32516  __IO uint32_t STAT_CLR;
32517  __IO uint32_t STAT_TOG;
32518  __IO uint32_t OUT_CTRL;
32519  __IO uint32_t OUT_CTRL_SET;
32520  __IO uint32_t OUT_CTRL_CLR;
32521  __IO uint32_t OUT_CTRL_TOG;
32522  __IO uint32_t OUT_BUF;
32523  uint8_t RESERVED_0[12];
32524  __IO uint32_t OUT_BUF2;
32525  uint8_t RESERVED_1[12];
32526  __IO uint32_t OUT_PITCH;
32527  uint8_t RESERVED_2[12];
32528  __IO uint32_t OUT_LRC;
32529  uint8_t RESERVED_3[12];
32530  __IO uint32_t OUT_PS_ULC;
32531  uint8_t RESERVED_4[12];
32532  __IO uint32_t OUT_PS_LRC;
32533  uint8_t RESERVED_5[12];
32534  __IO uint32_t OUT_AS_ULC;
32535  uint8_t RESERVED_6[12];
32536  __IO uint32_t OUT_AS_LRC;
32537  uint8_t RESERVED_7[12];
32538  __IO uint32_t PS_CTRL;
32539  __IO uint32_t PS_CTRL_SET;
32540  __IO uint32_t PS_CTRL_CLR;
32541  __IO uint32_t PS_CTRL_TOG;
32542  __IO uint32_t PS_BUF;
32543  uint8_t RESERVED_8[12];
32544  __IO uint32_t PS_UBUF;
32545  uint8_t RESERVED_9[12];
32546  __IO uint32_t PS_VBUF;
32547  uint8_t RESERVED_10[12];
32548  __IO uint32_t PS_PITCH;
32549  uint8_t RESERVED_11[12];
32550  __IO uint32_t PS_BACKGROUND;
32551  uint8_t RESERVED_12[12];
32552  __IO uint32_t PS_SCALE;
32553  uint8_t RESERVED_13[12];
32554  __IO uint32_t PS_OFFSET;
32555  uint8_t RESERVED_14[12];
32556  __IO uint32_t PS_CLRKEYLOW;
32557  uint8_t RESERVED_15[12];
32558  __IO uint32_t PS_CLRKEYHIGH;
32559  uint8_t RESERVED_16[12];
32560  __IO uint32_t AS_CTRL;
32561  uint8_t RESERVED_17[12];
32562  __IO uint32_t AS_BUF;
32563  uint8_t RESERVED_18[12];
32564  __IO uint32_t AS_PITCH;
32565  uint8_t RESERVED_19[12];
32566  __IO uint32_t AS_CLRKEYLOW;
32567  uint8_t RESERVED_20[12];
32568  __IO uint32_t AS_CLRKEYHIGH;
32569  uint8_t RESERVED_21[12];
32570  __IO uint32_t CSC1_COEF0;
32571  uint8_t RESERVED_22[12];
32572  __IO uint32_t CSC1_COEF1;
32573  uint8_t RESERVED_23[12];
32574  __IO uint32_t CSC1_COEF2;
32575  uint8_t RESERVED_24[348];
32576  __IO uint32_t POWER;
32577  uint8_t RESERVED_25[220];
32578  __IO uint32_t NEXT;
32579  uint8_t RESERVED_26[60];
32580  __IO uint32_t PORTER_DUFF_CTRL;
32581 } PXP_Type;
32582 
32583 /* ----------------------------------------------------------------------------
32584  -- PXP Register Masks
32585  ---------------------------------------------------------------------------- */
32586 
32594 #define PXP_CTRL_ENABLE_MASK (0x1U)
32595 #define PXP_CTRL_ENABLE_SHIFT (0U)
32596 #define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
32597 #define PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
32598 #define PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
32599 #define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
32600 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
32601 #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
32602 #define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
32603 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
32604 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
32605 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
32606 #define PXP_CTRL_RSVD0_MASK (0xE0U)
32607 #define PXP_CTRL_RSVD0_SHIFT (5U)
32608 #define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)
32609 #define PXP_CTRL_ROTATE_MASK (0x300U)
32610 #define PXP_CTRL_ROTATE_SHIFT (8U)
32611 
32617 #define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
32618 #define PXP_CTRL_HFLIP_MASK (0x400U)
32619 #define PXP_CTRL_HFLIP_SHIFT (10U)
32620 #define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
32621 #define PXP_CTRL_VFLIP_MASK (0x800U)
32622 #define PXP_CTRL_VFLIP_SHIFT (11U)
32623 #define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
32624 #define PXP_CTRL_RSVD1_MASK (0x3FF000U)
32625 #define PXP_CTRL_RSVD1_SHIFT (12U)
32626 #define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)
32627 #define PXP_CTRL_ROT_POS_MASK (0x400000U)
32628 #define PXP_CTRL_ROT_POS_SHIFT (22U)
32629 #define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
32630 #define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
32631 #define PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
32632 
32636 #define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
32637 #define PXP_CTRL_RSVD3_MASK (0xF000000U)
32638 #define PXP_CTRL_RSVD3_SHIFT (24U)
32639 #define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK)
32640 #define PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
32641 #define PXP_CTRL_EN_REPEAT_SHIFT (28U)
32642 #define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
32643 #define PXP_CTRL_RSVD4_MASK (0x20000000U)
32644 #define PXP_CTRL_RSVD4_SHIFT (29U)
32645 #define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)
32646 #define PXP_CTRL_CLKGATE_MASK (0x40000000U)
32647 #define PXP_CTRL_CLKGATE_SHIFT (30U)
32648 #define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
32649 #define PXP_CTRL_SFTRST_MASK (0x80000000U)
32650 #define PXP_CTRL_SFTRST_SHIFT (31U)
32651 #define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
32652 
32656 #define PXP_CTRL_SET_ENABLE_MASK (0x1U)
32657 #define PXP_CTRL_SET_ENABLE_SHIFT (0U)
32658 #define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
32659 #define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
32660 #define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
32661 #define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
32662 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
32663 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
32664 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
32665 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
32666 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
32667 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
32668 #define PXP_CTRL_SET_RSVD0_MASK (0xE0U)
32669 #define PXP_CTRL_SET_RSVD0_SHIFT (5U)
32670 #define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)
32671 #define PXP_CTRL_SET_ROTATE_MASK (0x300U)
32672 #define PXP_CTRL_SET_ROTATE_SHIFT (8U)
32673 
32679 #define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
32680 #define PXP_CTRL_SET_HFLIP_MASK (0x400U)
32681 #define PXP_CTRL_SET_HFLIP_SHIFT (10U)
32682 #define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
32683 #define PXP_CTRL_SET_VFLIP_MASK (0x800U)
32684 #define PXP_CTRL_SET_VFLIP_SHIFT (11U)
32685 #define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
32686 #define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U)
32687 #define PXP_CTRL_SET_RSVD1_SHIFT (12U)
32688 #define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)
32689 #define PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
32690 #define PXP_CTRL_SET_ROT_POS_SHIFT (22U)
32691 #define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
32692 #define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
32693 #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
32694 
32698 #define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
32699 #define PXP_CTRL_SET_RSVD3_MASK (0xF000000U)
32700 #define PXP_CTRL_SET_RSVD3_SHIFT (24U)
32701 #define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK)
32702 #define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
32703 #define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
32704 #define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
32705 #define PXP_CTRL_SET_RSVD4_MASK (0x20000000U)
32706 #define PXP_CTRL_SET_RSVD4_SHIFT (29U)
32707 #define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)
32708 #define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
32709 #define PXP_CTRL_SET_CLKGATE_SHIFT (30U)
32710 #define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
32711 #define PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
32712 #define PXP_CTRL_SET_SFTRST_SHIFT (31U)
32713 #define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
32714 
32718 #define PXP_CTRL_CLR_ENABLE_MASK (0x1U)
32719 #define PXP_CTRL_CLR_ENABLE_SHIFT (0U)
32720 #define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
32721 #define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
32722 #define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
32723 #define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
32724 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
32725 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
32726 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
32727 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
32728 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
32729 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
32730 #define PXP_CTRL_CLR_RSVD0_MASK (0xE0U)
32731 #define PXP_CTRL_CLR_RSVD0_SHIFT (5U)
32732 #define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)
32733 #define PXP_CTRL_CLR_ROTATE_MASK (0x300U)
32734 #define PXP_CTRL_CLR_ROTATE_SHIFT (8U)
32735 
32741 #define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
32742 #define PXP_CTRL_CLR_HFLIP_MASK (0x400U)
32743 #define PXP_CTRL_CLR_HFLIP_SHIFT (10U)
32744 #define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
32745 #define PXP_CTRL_CLR_VFLIP_MASK (0x800U)
32746 #define PXP_CTRL_CLR_VFLIP_SHIFT (11U)
32747 #define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
32748 #define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U)
32749 #define PXP_CTRL_CLR_RSVD1_SHIFT (12U)
32750 #define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)
32751 #define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
32752 #define PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
32753 #define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
32754 #define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
32755 #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
32756 
32760 #define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
32761 #define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U)
32762 #define PXP_CTRL_CLR_RSVD3_SHIFT (24U)
32763 #define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK)
32764 #define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
32765 #define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
32766 #define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
32767 #define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U)
32768 #define PXP_CTRL_CLR_RSVD4_SHIFT (29U)
32769 #define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)
32770 #define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
32771 #define PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
32772 #define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
32773 #define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
32774 #define PXP_CTRL_CLR_SFTRST_SHIFT (31U)
32775 #define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
32776 
32780 #define PXP_CTRL_TOG_ENABLE_MASK (0x1U)
32781 #define PXP_CTRL_TOG_ENABLE_SHIFT (0U)
32782 #define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
32783 #define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
32784 #define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
32785 #define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
32786 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
32787 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
32788 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
32789 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
32790 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
32791 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
32792 #define PXP_CTRL_TOG_RSVD0_MASK (0xE0U)
32793 #define PXP_CTRL_TOG_RSVD0_SHIFT (5U)
32794 #define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)
32795 #define PXP_CTRL_TOG_ROTATE_MASK (0x300U)
32796 #define PXP_CTRL_TOG_ROTATE_SHIFT (8U)
32797 
32803 #define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
32804 #define PXP_CTRL_TOG_HFLIP_MASK (0x400U)
32805 #define PXP_CTRL_TOG_HFLIP_SHIFT (10U)
32806 #define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
32807 #define PXP_CTRL_TOG_VFLIP_MASK (0x800U)
32808 #define PXP_CTRL_TOG_VFLIP_SHIFT (11U)
32809 #define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
32810 #define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U)
32811 #define PXP_CTRL_TOG_RSVD1_SHIFT (12U)
32812 #define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)
32813 #define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
32814 #define PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
32815 #define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
32816 #define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
32817 #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
32818 
32822 #define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
32823 #define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U)
32824 #define PXP_CTRL_TOG_RSVD3_SHIFT (24U)
32825 #define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK)
32826 #define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
32827 #define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
32828 #define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
32829 #define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U)
32830 #define PXP_CTRL_TOG_RSVD4_SHIFT (29U)
32831 #define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)
32832 #define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
32833 #define PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
32834 #define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
32835 #define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
32836 #define PXP_CTRL_TOG_SFTRST_SHIFT (31U)
32837 #define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
32838 
32842 #define PXP_STAT_IRQ_MASK (0x1U)
32843 #define PXP_STAT_IRQ_SHIFT (0U)
32844 #define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
32845 #define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
32846 #define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
32847 #define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
32848 #define PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
32849 #define PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
32850 #define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
32851 #define PXP_STAT_NEXT_IRQ_MASK (0x8U)
32852 #define PXP_STAT_NEXT_IRQ_SHIFT (3U)
32853 #define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
32854 #define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
32855 #define PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
32856 #define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
32857 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
32858 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
32859 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
32860 #define PXP_STAT_RSVD2_MASK (0xFE00U)
32861 #define PXP_STAT_RSVD2_SHIFT (9U)
32862 #define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)
32863 #define PXP_STAT_BLOCKY_MASK (0xFF0000U)
32864 #define PXP_STAT_BLOCKY_SHIFT (16U)
32865 #define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
32866 #define PXP_STAT_BLOCKX_MASK (0xFF000000U)
32867 #define PXP_STAT_BLOCKX_SHIFT (24U)
32868 #define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
32869 
32873 #define PXP_STAT_SET_IRQ_MASK (0x1U)
32874 #define PXP_STAT_SET_IRQ_SHIFT (0U)
32875 #define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
32876 #define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
32877 #define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
32878 #define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
32879 #define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
32880 #define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
32881 #define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
32882 #define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
32883 #define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
32884 #define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
32885 #define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
32886 #define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
32887 #define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
32888 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
32889 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
32890 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
32891 #define PXP_STAT_SET_RSVD2_MASK (0xFE00U)
32892 #define PXP_STAT_SET_RSVD2_SHIFT (9U)
32893 #define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)
32894 #define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
32895 #define PXP_STAT_SET_BLOCKY_SHIFT (16U)
32896 #define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
32897 #define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
32898 #define PXP_STAT_SET_BLOCKX_SHIFT (24U)
32899 #define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
32900 
32904 #define PXP_STAT_CLR_IRQ_MASK (0x1U)
32905 #define PXP_STAT_CLR_IRQ_SHIFT (0U)
32906 #define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
32907 #define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
32908 #define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
32909 #define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
32910 #define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
32911 #define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
32912 #define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
32913 #define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
32914 #define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
32915 #define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
32916 #define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
32917 #define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
32918 #define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
32919 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
32920 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
32921 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
32922 #define PXP_STAT_CLR_RSVD2_MASK (0xFE00U)
32923 #define PXP_STAT_CLR_RSVD2_SHIFT (9U)
32924 #define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)
32925 #define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
32926 #define PXP_STAT_CLR_BLOCKY_SHIFT (16U)
32927 #define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
32928 #define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
32929 #define PXP_STAT_CLR_BLOCKX_SHIFT (24U)
32930 #define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
32931 
32935 #define PXP_STAT_TOG_IRQ_MASK (0x1U)
32936 #define PXP_STAT_TOG_IRQ_SHIFT (0U)
32937 #define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
32938 #define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
32939 #define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
32940 #define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
32941 #define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
32942 #define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
32943 #define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
32944 #define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
32945 #define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
32946 #define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
32947 #define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
32948 #define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
32949 #define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
32950 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
32951 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
32952 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
32953 #define PXP_STAT_TOG_RSVD2_MASK (0xFE00U)
32954 #define PXP_STAT_TOG_RSVD2_SHIFT (9U)
32955 #define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)
32956 #define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
32957 #define PXP_STAT_TOG_BLOCKY_SHIFT (16U)
32958 #define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
32959 #define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
32960 #define PXP_STAT_TOG_BLOCKX_SHIFT (24U)
32961 #define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
32962 
32966 #define PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
32967 #define PXP_OUT_CTRL_FORMAT_SHIFT (0U)
32968 
32987 #define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
32988 #define PXP_OUT_CTRL_RSVD0_MASK (0xE0U)
32989 #define PXP_OUT_CTRL_RSVD0_SHIFT (5U)
32990 #define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)
32991 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
32992 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
32993 
32999 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
33000 #define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U)
33001 #define PXP_OUT_CTRL_RSVD1_SHIFT (10U)
33002 #define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)
33003 #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
33004 #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
33005 #define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
33006 #define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
33007 #define PXP_OUT_CTRL_ALPHA_SHIFT (24U)
33008 #define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
33009 
33013 #define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
33014 #define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
33015 
33034 #define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
33035 #define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U)
33036 #define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U)
33037 #define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)
33038 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
33039 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
33040 
33046 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
33047 #define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U)
33048 #define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U)
33049 #define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)
33050 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
33051 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
33052 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
33053 #define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
33054 #define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
33055 #define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
33056 
33060 #define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
33061 #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
33062 
33081 #define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
33082 #define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U)
33083 #define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U)
33084 #define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)
33085 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
33086 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
33087 
33093 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
33094 #define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U)
33095 #define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U)
33096 #define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)
33097 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
33098 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
33099 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
33100 #define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
33101 #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
33102 #define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
33103 
33107 #define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
33108 #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
33109 
33128 #define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
33129 #define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U)
33130 #define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U)
33131 #define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)
33132 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
33133 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
33134 
33140 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
33141 #define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U)
33142 #define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U)
33143 #define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)
33144 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
33145 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
33146 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
33147 #define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
33148 #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
33149 #define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
33150 
33154 #define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
33155 #define PXP_OUT_BUF_ADDR_SHIFT (0U)
33156 #define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
33157 
33161 #define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
33162 #define PXP_OUT_BUF2_ADDR_SHIFT (0U)
33163 #define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
33164 
33168 #define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
33169 #define PXP_OUT_PITCH_PITCH_SHIFT (0U)
33170 #define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
33171 #define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U)
33172 #define PXP_OUT_PITCH_RSVD_SHIFT (16U)
33173 #define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)
33174 
33178 #define PXP_OUT_LRC_Y_MASK (0x3FFFU)
33179 #define PXP_OUT_LRC_Y_SHIFT (0U)
33180 #define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
33181 #define PXP_OUT_LRC_RSVD0_MASK (0xC000U)
33182 #define PXP_OUT_LRC_RSVD0_SHIFT (14U)
33183 #define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)
33184 #define PXP_OUT_LRC_X_MASK (0x3FFF0000U)
33185 #define PXP_OUT_LRC_X_SHIFT (16U)
33186 #define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
33187 #define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U)
33188 #define PXP_OUT_LRC_RSVD1_SHIFT (30U)
33189 #define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)
33190 
33194 #define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
33195 #define PXP_OUT_PS_ULC_Y_SHIFT (0U)
33196 #define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
33197 #define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U)
33198 #define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U)
33199 #define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)
33200 #define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
33201 #define PXP_OUT_PS_ULC_X_SHIFT (16U)
33202 #define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
33203 #define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U)
33204 #define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U)
33205 #define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)
33206 
33210 #define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
33211 #define PXP_OUT_PS_LRC_Y_SHIFT (0U)
33212 #define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
33213 #define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U)
33214 #define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U)
33215 #define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)
33216 #define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
33217 #define PXP_OUT_PS_LRC_X_SHIFT (16U)
33218 #define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
33219 #define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U)
33220 #define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U)
33221 #define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)
33222 
33226 #define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
33227 #define PXP_OUT_AS_ULC_Y_SHIFT (0U)
33228 #define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
33229 #define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U)
33230 #define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U)
33231 #define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)
33232 #define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
33233 #define PXP_OUT_AS_ULC_X_SHIFT (16U)
33234 #define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
33235 #define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U)
33236 #define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U)
33237 #define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)
33238 
33242 #define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
33243 #define PXP_OUT_AS_LRC_Y_SHIFT (0U)
33244 #define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
33245 #define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U)
33246 #define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U)
33247 #define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)
33248 #define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
33249 #define PXP_OUT_AS_LRC_X_SHIFT (16U)
33250 #define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
33251 #define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U)
33252 #define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U)
33253 #define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)
33254 
33258 #define PXP_PS_CTRL_FORMAT_MASK (0x1FU)
33259 #define PXP_PS_CTRL_FORMAT_SHIFT (0U)
33260 
33277 #define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
33278 #define PXP_PS_CTRL_WB_SWAP_MASK (0x20U)
33279 #define PXP_PS_CTRL_WB_SWAP_SHIFT (5U)
33280 #define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
33281 #define PXP_PS_CTRL_RSVD0_MASK (0xC0U)
33282 #define PXP_PS_CTRL_RSVD0_SHIFT (6U)
33283 #define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)
33284 #define PXP_PS_CTRL_DECY_MASK (0x300U)
33285 #define PXP_PS_CTRL_DECY_SHIFT (8U)
33286 
33292 #define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
33293 #define PXP_PS_CTRL_DECX_MASK (0xC00U)
33294 #define PXP_PS_CTRL_DECX_SHIFT (10U)
33295 
33301 #define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
33302 #define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U)
33303 #define PXP_PS_CTRL_RSVD1_SHIFT (12U)
33304 #define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)
33305 
33309 #define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU)
33310 #define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
33311 
33328 #define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
33329 #define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U)
33330 #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U)
33331 #define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
33332 #define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U)
33333 #define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U)
33334 #define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)
33335 #define PXP_PS_CTRL_SET_DECY_MASK (0x300U)
33336 #define PXP_PS_CTRL_SET_DECY_SHIFT (8U)
33337 
33343 #define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
33344 #define PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
33345 #define PXP_PS_CTRL_SET_DECX_SHIFT (10U)
33346 
33352 #define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
33353 #define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U)
33354 #define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U)
33355 #define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)
33356 
33360 #define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU)
33361 #define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
33362 
33379 #define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
33380 #define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U)
33381 #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U)
33382 #define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
33383 #define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U)
33384 #define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U)
33385 #define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)
33386 #define PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
33387 #define PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
33388 
33394 #define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
33395 #define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
33396 #define PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
33397 
33403 #define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
33404 #define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U)
33405 #define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U)
33406 #define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)
33407 
33411 #define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU)
33412 #define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
33413 
33430 #define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
33431 #define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U)
33432 #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U)
33433 #define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
33434 #define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U)
33435 #define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U)
33436 #define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)
33437 #define PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
33438 #define PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
33439 
33445 #define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
33446 #define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
33447 #define PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
33448 
33454 #define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
33455 #define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U)
33456 #define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U)
33457 #define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)
33458 
33462 #define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
33463 #define PXP_PS_BUF_ADDR_SHIFT (0U)
33464 #define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
33465 
33469 #define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
33470 #define PXP_PS_UBUF_ADDR_SHIFT (0U)
33471 #define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
33472 
33476 #define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
33477 #define PXP_PS_VBUF_ADDR_SHIFT (0U)
33478 #define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
33479 
33483 #define PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
33484 #define PXP_PS_PITCH_PITCH_SHIFT (0U)
33485 #define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
33486 #define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U)
33487 #define PXP_PS_PITCH_RSVD_SHIFT (16U)
33488 #define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)
33489 
33493 #define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
33494 #define PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
33495 #define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
33496 #define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U)
33497 #define PXP_PS_BACKGROUND_RSVD_SHIFT (24U)
33498 #define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK)
33499 
33503 #define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
33504 #define PXP_PS_SCALE_XSCALE_SHIFT (0U)
33505 #define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
33506 #define PXP_PS_SCALE_RSVD1_MASK (0x8000U)
33507 #define PXP_PS_SCALE_RSVD1_SHIFT (15U)
33508 #define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)
33509 #define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
33510 #define PXP_PS_SCALE_YSCALE_SHIFT (16U)
33511 #define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
33512 #define PXP_PS_SCALE_RSVD2_MASK (0x80000000U)
33513 #define PXP_PS_SCALE_RSVD2_SHIFT (31U)
33514 #define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)
33515 
33519 #define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
33520 #define PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
33521 #define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
33522 #define PXP_PS_OFFSET_RSVD1_MASK (0xF000U)
33523 #define PXP_PS_OFFSET_RSVD1_SHIFT (12U)
33524 #define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)
33525 #define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
33526 #define PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
33527 #define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
33528 #define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U)
33529 #define PXP_PS_OFFSET_RSVD2_SHIFT (28U)
33530 #define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)
33531 
33535 #define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
33536 #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
33537 #define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
33538 #define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
33539 #define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U)
33540 #define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK)
33541 
33545 #define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
33546 #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
33547 #define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
33548 #define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
33549 #define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U)
33550 #define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK)
33551 
33555 #define PXP_AS_CTRL_RSVD0_MASK (0x1U)
33556 #define PXP_AS_CTRL_RSVD0_SHIFT (0U)
33557 #define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)
33558 #define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
33559 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
33560 
33567 #define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
33568 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
33569 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
33570 #define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
33571 #define PXP_AS_CTRL_FORMAT_MASK (0xF0U)
33572 #define PXP_AS_CTRL_FORMAT_SHIFT (4U)
33573 
33582 #define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
33583 #define PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
33584 #define PXP_AS_CTRL_ALPHA_SHIFT (8U)
33585 #define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
33586 #define PXP_AS_CTRL_ROP_MASK (0xF0000U)
33587 #define PXP_AS_CTRL_ROP_SHIFT (16U)
33588 
33602 #define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
33603 #define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
33604 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
33605 #define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
33606 #define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U)
33607 #define PXP_AS_CTRL_RSVD1_SHIFT (21U)
33608 #define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)
33609 
33613 #define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
33614 #define PXP_AS_BUF_ADDR_SHIFT (0U)
33615 #define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
33616 
33620 #define PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
33621 #define PXP_AS_PITCH_PITCH_SHIFT (0U)
33622 #define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
33623 #define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U)
33624 #define PXP_AS_PITCH_RSVD_SHIFT (16U)
33625 #define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)
33626 
33630 #define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
33631 #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
33632 #define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
33633 #define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
33634 #define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U)
33635 #define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK)
33636 
33640 #define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
33641 #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
33642 #define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
33643 #define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
33644 #define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)
33645 #define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK)
33646 
33650 #define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
33651 #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
33652 #define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
33653 #define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
33654 #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
33655 #define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
33656 #define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
33657 #define PXP_CSC1_COEF0_C0_SHIFT (18U)
33658 #define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
33659 #define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U)
33660 #define PXP_CSC1_COEF0_RSVD1_SHIFT (29U)
33661 #define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)
33662 #define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
33663 #define PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
33664 #define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
33665 #define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
33666 #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
33667 #define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
33668 
33672 #define PXP_CSC1_COEF1_C4_MASK (0x7FFU)
33673 #define PXP_CSC1_COEF1_C4_SHIFT (0U)
33674 #define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
33675 #define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U)
33676 #define PXP_CSC1_COEF1_RSVD0_SHIFT (11U)
33677 #define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)
33678 #define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
33679 #define PXP_CSC1_COEF1_C1_SHIFT (16U)
33680 #define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
33681 #define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U)
33682 #define PXP_CSC1_COEF1_RSVD1_SHIFT (27U)
33683 #define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)
33684 
33688 #define PXP_CSC1_COEF2_C3_MASK (0x7FFU)
33689 #define PXP_CSC1_COEF2_C3_SHIFT (0U)
33690 #define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
33691 #define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U)
33692 #define PXP_CSC1_COEF2_RSVD0_SHIFT (11U)
33693 #define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)
33694 #define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
33695 #define PXP_CSC1_COEF2_C2_SHIFT (16U)
33696 #define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
33697 #define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U)
33698 #define PXP_CSC1_COEF2_RSVD1_SHIFT (27U)
33699 #define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)
33700 
33704 #define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
33705 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
33706 
33712 #define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
33713 #define PXP_POWER_CTRL_MASK (0xFFFFF000U)
33714 #define PXP_POWER_CTRL_SHIFT (12U)
33715 #define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)
33716 
33720 #define PXP_NEXT_ENABLED_MASK (0x1U)
33721 #define PXP_NEXT_ENABLED_SHIFT (0U)
33722 #define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
33723 #define PXP_NEXT_RSVD_MASK (0x2U)
33724 #define PXP_NEXT_RSVD_SHIFT (1U)
33725 #define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)
33726 #define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
33727 #define PXP_NEXT_POINTER_SHIFT (2U)
33728 #define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
33729 
33733 #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U)
33734 #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U)
33735 #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK)
33736 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
33737 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
33738 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
33739 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
33740 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
33741 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
33742 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
33743 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
33744 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
33745 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
33746 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
33747 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
33748 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
33749 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
33750 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
33751 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
33752 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
33753 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
33754 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
33755 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
33756 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
33757 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
33758 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
33759 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
33760 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
33761 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
33762 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
33763 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
33764 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
33765 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
33766  /* end of group PXP_Register_Masks */
33772 
33773 
33774 /* PXP - Peripheral instance base addresses */
33776 #define PXP_BASE (0x402B4000u)
33777 
33778 #define PXP ((PXP_Type *)PXP_BASE)
33779 
33780 #define PXP_BASE_ADDRS { PXP_BASE }
33781 
33782 #define PXP_BASE_PTRS { PXP }
33783 
33784 #define PXP_IRQ0_IRQS { PXP_IRQn }
33785  /* end of group PXP_Peripheral_Access_Layer */
33789 
33790 
33791 /* ----------------------------------------------------------------------------
33792  -- ROMC Peripheral Access Layer
33793  ---------------------------------------------------------------------------- */
33794 
33801 typedef struct {
33802  uint8_t RESERVED_0[212];
33803  __IO uint32_t ROMPATCHD[8];
33804  __IO uint32_t ROMPATCHCNTL;
33805  uint32_t ROMPATCHENH;
33806  __IO uint32_t ROMPATCHENL;
33807  __IO uint32_t ROMPATCHA[16];
33808  uint8_t RESERVED_1[200];
33809  __IO uint32_t ROMPATCHSR;
33810 } ROMC_Type;
33811 
33812 /* ----------------------------------------------------------------------------
33813  -- ROMC Register Masks
33814  ---------------------------------------------------------------------------- */
33815 
33823 #define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
33824 #define ROMC_ROMPATCHD_DATAX_SHIFT (0U)
33825 #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
33826 
33828 /* The count of ROMC_ROMPATCHD */
33829 #define ROMC_ROMPATCHD_COUNT (8U)
33830 
33833 #define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
33834 #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
33835 
33839 #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
33840 #define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
33841 #define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
33842 
33846 #define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
33847 
33851 #define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
33852 #define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
33853 
33857 #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
33858 
33862 #define ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
33863 #define ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
33864 
33868 #define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
33869 #define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
33870 #define ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
33871 #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
33872 
33874 /* The count of ROMC_ROMPATCHA */
33875 #define ROMC_ROMPATCHA_COUNT (16U)
33876 
33879 #define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
33880 #define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
33881 
33886 #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
33887 #define ROMC_ROMPATCHSR_SW_MASK (0x20000U)
33888 #define ROMC_ROMPATCHSR_SW_SHIFT (17U)
33889 
33893 #define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
33894  /* end of group ROMC_Register_Masks */
33900 
33901 
33902 /* ROMC - Peripheral instance base addresses */
33904 #define ROMC_BASE (0x40180000u)
33905 
33906 #define ROMC ((ROMC_Type *)ROMC_BASE)
33907 
33908 #define ROMC_BASE_ADDRS { ROMC_BASE }
33909 
33910 #define ROMC_BASE_PTRS { ROMC }
33911  /* end of group ROMC_Peripheral_Access_Layer */
33915 
33916 
33917 /* ----------------------------------------------------------------------------
33918  -- RTWDOG Peripheral Access Layer
33919  ---------------------------------------------------------------------------- */
33920 
33927 typedef struct {
33928  __IO uint32_t CS;
33929  __IO uint32_t CNT;
33930  __IO uint32_t TOVAL;
33931  __IO uint32_t WIN;
33932 } RTWDOG_Type;
33933 
33934 /* ----------------------------------------------------------------------------
33935  -- RTWDOG Register Masks
33936  ---------------------------------------------------------------------------- */
33937 
33945 #define RTWDOG_CS_STOP_MASK (0x1U)
33946 #define RTWDOG_CS_STOP_SHIFT (0U)
33947 
33951 #define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
33952 #define RTWDOG_CS_WAIT_MASK (0x2U)
33953 #define RTWDOG_CS_WAIT_SHIFT (1U)
33954 
33958 #define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
33959 #define RTWDOG_CS_DBG_MASK (0x4U)
33960 #define RTWDOG_CS_DBG_SHIFT (2U)
33961 
33965 #define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
33966 #define RTWDOG_CS_TST_MASK (0x18U)
33967 #define RTWDOG_CS_TST_SHIFT (3U)
33968 
33975 #define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
33976 #define RTWDOG_CS_UPDATE_MASK (0x20U)
33977 #define RTWDOG_CS_UPDATE_SHIFT (5U)
33978 
33982 #define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
33983 #define RTWDOG_CS_INT_MASK (0x40U)
33984 #define RTWDOG_CS_INT_SHIFT (6U)
33985 
33989 #define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
33990 #define RTWDOG_CS_EN_MASK (0x80U)
33991 #define RTWDOG_CS_EN_SHIFT (7U)
33992 
33996 #define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
33997 #define RTWDOG_CS_CLK_MASK (0x300U)
33998 #define RTWDOG_CS_CLK_SHIFT (8U)
33999 
34005 #define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
34006 #define RTWDOG_CS_RCS_MASK (0x400U)
34007 #define RTWDOG_CS_RCS_SHIFT (10U)
34008 
34012 #define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
34013 #define RTWDOG_CS_ULK_MASK (0x800U)
34014 #define RTWDOG_CS_ULK_SHIFT (11U)
34015 
34019 #define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
34020 #define RTWDOG_CS_PRES_MASK (0x1000U)
34021 #define RTWDOG_CS_PRES_SHIFT (12U)
34022 
34026 #define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
34027 #define RTWDOG_CS_CMD32EN_MASK (0x2000U)
34028 #define RTWDOG_CS_CMD32EN_SHIFT (13U)
34029 
34033 #define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
34034 #define RTWDOG_CS_FLG_MASK (0x4000U)
34035 #define RTWDOG_CS_FLG_SHIFT (14U)
34036 
34040 #define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
34041 #define RTWDOG_CS_WIN_MASK (0x8000U)
34042 #define RTWDOG_CS_WIN_SHIFT (15U)
34043 
34047 #define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
34048 
34052 #define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
34053 #define RTWDOG_CNT_CNTLOW_SHIFT (0U)
34054 
34056 #define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
34057 #define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
34058 #define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
34059 
34061 #define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
34062 
34066 #define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
34067 #define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
34068 
34070 #define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
34071 #define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
34072 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
34073 
34075 #define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
34076 
34080 #define RTWDOG_WIN_WINLOW_MASK (0xFFU)
34081 #define RTWDOG_WIN_WINLOW_SHIFT (0U)
34082 
34084 #define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
34085 #define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
34086 #define RTWDOG_WIN_WINHIGH_SHIFT (8U)
34087 
34089 #define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
34090  /* end of group RTWDOG_Register_Masks */
34096 
34097 
34098 /* RTWDOG - Peripheral instance base addresses */
34100 #define RTWDOG_BASE (0x400BC000u)
34101 
34102 #define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
34103 
34104 #define RTWDOG_BASE_ADDRS { RTWDOG_BASE }
34105 
34106 #define RTWDOG_BASE_PTRS { RTWDOG }
34107 
34108 #define RTWDOG_IRQS { RTWDOG_IRQn }
34109 /* Extra definition */
34110 #define RTWDOG_UPDATE_KEY (0xD928C520U)
34111 #define RTWDOG_REFRESH_KEY (0xB480A602U)
34112 
34113  /* end of group RTWDOG_Peripheral_Access_Layer */
34117 
34118 
34119 /* ----------------------------------------------------------------------------
34120  -- SEMC Peripheral Access Layer
34121  ---------------------------------------------------------------------------- */
34122 
34129 typedef struct {
34130  __IO uint32_t MCR;
34131  __IO uint32_t IOCR;
34132  __IO uint32_t BMCR0;
34133  __IO uint32_t BMCR1;
34134  __IO uint32_t BR[9];
34135  uint8_t RESERVED_0[4];
34136  __IO uint32_t INTEN;
34137  __IO uint32_t INTR;
34138  __IO uint32_t SDRAMCR0;
34139  __IO uint32_t SDRAMCR1;
34140  __IO uint32_t SDRAMCR2;
34141  __IO uint32_t SDRAMCR3;
34142  __IO uint32_t NANDCR0;
34143  __IO uint32_t NANDCR1;
34144  __IO uint32_t NANDCR2;
34145  __IO uint32_t NANDCR3;
34146  __IO uint32_t NORCR0;
34147  __IO uint32_t NORCR1;
34148  __IO uint32_t NORCR2;
34149  uint32_t NORCR3;
34150  __IO uint32_t SRAMCR0;
34151  __IO uint32_t SRAMCR1;
34152  __IO uint32_t SRAMCR2;
34153  uint32_t SRAMCR3;
34154  __IO uint32_t DBICR0;
34155  __IO uint32_t DBICR1;
34156  uint8_t RESERVED_1[8];
34157  __IO uint32_t IPCR0;
34158  __IO uint32_t IPCR1;
34159  __IO uint32_t IPCR2;
34160  __IO uint32_t IPCMD;
34161  __IO uint32_t IPTXDAT;
34162  uint8_t RESERVED_2[12];
34163  __I uint32_t IPRXDAT;
34164  uint8_t RESERVED_3[12];
34165  __I uint32_t STS0;
34166  uint32_t STS1;
34167  __I uint32_t STS2;
34168  uint32_t STS3;
34169  uint32_t STS4;
34170  uint32_t STS5;
34171  uint32_t STS6;
34172  uint32_t STS7;
34173  uint32_t STS8;
34174  uint32_t STS9;
34175  uint32_t STS10;
34176  uint32_t STS11;
34177  __I uint32_t STS12;
34178  uint32_t STS13;
34179  uint32_t STS14;
34180  uint32_t STS15;
34181 } SEMC_Type;
34182 
34183 /* ----------------------------------------------------------------------------
34184  -- SEMC Register Masks
34185  ---------------------------------------------------------------------------- */
34186 
34194 #define SEMC_MCR_SWRST_MASK (0x1U)
34195 #define SEMC_MCR_SWRST_SHIFT (0U)
34196 
34198 #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
34199 #define SEMC_MCR_MDIS_MASK (0x2U)
34200 #define SEMC_MCR_MDIS_SHIFT (1U)
34201 
34205 #define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
34206 #define SEMC_MCR_DQSMD_MASK (0x4U)
34207 #define SEMC_MCR_DQSMD_SHIFT (2U)
34208 
34212 #define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
34213 #define SEMC_MCR_WPOL0_MASK (0x40U)
34214 #define SEMC_MCR_WPOL0_SHIFT (6U)
34215 
34219 #define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
34220 #define SEMC_MCR_WPOL1_MASK (0x80U)
34221 #define SEMC_MCR_WPOL1_SHIFT (7U)
34222 
34226 #define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
34227 #define SEMC_MCR_CTO_MASK (0xFF0000U)
34228 #define SEMC_MCR_CTO_SHIFT (16U)
34229 
34231 #define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
34232 #define SEMC_MCR_BTO_MASK (0x1F000000U)
34233 #define SEMC_MCR_BTO_SHIFT (24U)
34234 
34239 #define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
34240 
34244 #define SEMC_IOCR_MUX_A8_MASK (0x7U)
34245 #define SEMC_IOCR_MUX_A8_SHIFT (0U)
34246 
34256 #define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
34257 #define SEMC_IOCR_MUX_CSX0_MASK (0x38U)
34258 #define SEMC_IOCR_MUX_CSX0_SHIFT (3U)
34259 
34269 #define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
34270 #define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
34271 #define SEMC_IOCR_MUX_CSX1_SHIFT (6U)
34272 
34282 #define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
34283 #define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
34284 #define SEMC_IOCR_MUX_CSX2_SHIFT (9U)
34285 
34295 #define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
34296 #define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
34297 #define SEMC_IOCR_MUX_CSX3_SHIFT (12U)
34298 
34308 #define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
34309 #define SEMC_IOCR_MUX_RDY_MASK (0x38000U)
34310 #define SEMC_IOCR_MUX_RDY_SHIFT (15U)
34311 
34321 #define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
34322 
34326 #define SEMC_BMCR0_WQOS_MASK (0xFU)
34327 #define SEMC_BMCR0_WQOS_SHIFT (0U)
34328 
34330 #define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
34331 #define SEMC_BMCR0_WAGE_MASK (0xF0U)
34332 #define SEMC_BMCR0_WAGE_SHIFT (4U)
34333 
34335 #define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
34336 #define SEMC_BMCR0_WSH_MASK (0xFF00U)
34337 #define SEMC_BMCR0_WSH_SHIFT (8U)
34338 
34340 #define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
34341 #define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
34342 #define SEMC_BMCR0_WRWS_SHIFT (16U)
34343 
34345 #define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
34346 
34350 #define SEMC_BMCR1_WQOS_MASK (0xFU)
34351 #define SEMC_BMCR1_WQOS_SHIFT (0U)
34352 
34354 #define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
34355 #define SEMC_BMCR1_WAGE_MASK (0xF0U)
34356 #define SEMC_BMCR1_WAGE_SHIFT (4U)
34357 
34359 #define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
34360 #define SEMC_BMCR1_WPH_MASK (0xFF00U)
34361 #define SEMC_BMCR1_WPH_SHIFT (8U)
34362 
34364 #define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
34365 #define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
34366 #define SEMC_BMCR1_WRWS_SHIFT (16U)
34367 
34369 #define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
34370 #define SEMC_BMCR1_WBR_MASK (0xFF000000U)
34371 #define SEMC_BMCR1_WBR_SHIFT (24U)
34372 
34374 #define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
34375 
34379 #define SEMC_BR_VLD_MASK (0x1U)
34380 #define SEMC_BR_VLD_SHIFT (0U)
34381 
34383 #define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
34384 #define SEMC_BR_MS_MASK (0x3EU)
34385 #define SEMC_BR_MS_SHIFT (1U)
34386 
34420 #define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
34421 #define SEMC_BR_BA_MASK (0xFFFFF000U)
34422 #define SEMC_BR_BA_SHIFT (12U)
34423 
34425 #define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
34426 
34428 /* The count of SEMC_BR */
34429 #define SEMC_BR_COUNT (9U)
34430 
34433 #define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
34434 #define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
34435 
34437 #define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
34438 #define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
34439 #define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
34440 
34442 #define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
34443 #define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
34444 #define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
34445 
34447 #define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
34448 #define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
34449 #define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
34450 
34452 #define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
34453 #define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
34454 #define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
34455 
34459 #define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
34460 #define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
34461 #define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
34462 
34466 #define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
34467 
34471 #define SEMC_INTR_IPCMDDONE_MASK (0x1U)
34472 #define SEMC_INTR_IPCMDDONE_SHIFT (0U)
34473 
34475 #define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
34476 #define SEMC_INTR_IPCMDERR_MASK (0x2U)
34477 #define SEMC_INTR_IPCMDERR_SHIFT (1U)
34478 
34480 #define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
34481 #define SEMC_INTR_AXICMDERR_MASK (0x4U)
34482 #define SEMC_INTR_AXICMDERR_SHIFT (2U)
34483 
34485 #define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
34486 #define SEMC_INTR_AXIBUSERR_MASK (0x8U)
34487 #define SEMC_INTR_AXIBUSERR_SHIFT (3U)
34488 
34490 #define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
34491 #define SEMC_INTR_NDPAGEEND_MASK (0x10U)
34492 #define SEMC_INTR_NDPAGEEND_SHIFT (4U)
34493 
34495 #define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
34496 #define SEMC_INTR_NDNOPEND_MASK (0x20U)
34497 #define SEMC_INTR_NDNOPEND_SHIFT (5U)
34498 
34500 #define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
34501 
34505 #define SEMC_SDRAMCR0_PS_MASK (0x1U)
34506 #define SEMC_SDRAMCR0_PS_SHIFT (0U)
34507 
34511 #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
34512 #define SEMC_SDRAMCR0_BL_MASK (0x70U)
34513 #define SEMC_SDRAMCR0_BL_SHIFT (4U)
34514 
34524 #define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
34525 #define SEMC_SDRAMCR0_COL_MASK (0x300U)
34526 #define SEMC_SDRAMCR0_COL_SHIFT (8U)
34527 
34533 #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
34534 #define SEMC_SDRAMCR0_CL_MASK (0xC00U)
34535 #define SEMC_SDRAMCR0_CL_SHIFT (10U)
34536 
34542 #define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
34543 
34547 #define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
34548 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
34549 
34551 #define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
34552 #define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
34553 #define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
34554 
34556 #define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
34557 #define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
34558 #define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
34559 
34561 #define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
34562 #define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
34563 #define SEMC_SDRAMCR1_WRC_SHIFT (13U)
34564 
34566 #define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
34567 #define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
34568 #define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
34569 
34571 #define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
34572 #define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
34573 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
34574 
34576 #define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
34577 
34581 #define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
34582 #define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
34583 
34585 #define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
34586 #define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
34587 #define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
34588 
34590 #define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
34591 #define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
34592 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
34593 
34595 #define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
34596 #define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
34597 #define SEMC_SDRAMCR2_ITO_SHIFT (24U)
34598 
34602 #define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
34603 
34607 #define SEMC_SDRAMCR3_REN_MASK (0x1U)
34608 #define SEMC_SDRAMCR3_REN_SHIFT (0U)
34609 
34611 #define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
34612 #define SEMC_SDRAMCR3_REBL_MASK (0xEU)
34613 #define SEMC_SDRAMCR3_REBL_SHIFT (1U)
34614 
34624 #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
34625 #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
34626 #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
34627 
34631 #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
34632 #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
34633 #define SEMC_SDRAMCR3_RT_SHIFT (16U)
34634 
34638 #define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
34639 #define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
34640 #define SEMC_SDRAMCR3_UT_SHIFT (24U)
34641 
34645 #define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
34646 
34650 #define SEMC_NANDCR0_PS_MASK (0x1U)
34651 #define SEMC_NANDCR0_PS_SHIFT (0U)
34652 
34656 #define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
34657 #define SEMC_NANDCR0_BL_MASK (0x70U)
34658 #define SEMC_NANDCR0_BL_SHIFT (4U)
34659 
34669 #define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
34670 #define SEMC_NANDCR0_EDO_MASK (0x80U)
34671 #define SEMC_NANDCR0_EDO_SHIFT (7U)
34672 
34676 #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
34677 #define SEMC_NANDCR0_COL_MASK (0x700U)
34678 #define SEMC_NANDCR0_COL_SHIFT (8U)
34679 
34689 #define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
34690 
34694 #define SEMC_NANDCR1_CES_MASK (0xFU)
34695 #define SEMC_NANDCR1_CES_SHIFT (0U)
34696 
34698 #define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
34699 #define SEMC_NANDCR1_CEH_MASK (0xF0U)
34700 #define SEMC_NANDCR1_CEH_SHIFT (4U)
34701 
34703 #define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
34704 #define SEMC_NANDCR1_WEL_MASK (0xF00U)
34705 #define SEMC_NANDCR1_WEL_SHIFT (8U)
34706 
34708 #define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
34709 #define SEMC_NANDCR1_WEH_MASK (0xF000U)
34710 #define SEMC_NANDCR1_WEH_SHIFT (12U)
34711 
34713 #define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
34714 #define SEMC_NANDCR1_REL_MASK (0xF0000U)
34715 #define SEMC_NANDCR1_REL_SHIFT (16U)
34716 
34718 #define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
34719 #define SEMC_NANDCR1_REH_MASK (0xF00000U)
34720 #define SEMC_NANDCR1_REH_SHIFT (20U)
34721 
34723 #define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
34724 #define SEMC_NANDCR1_TA_MASK (0xF000000U)
34725 #define SEMC_NANDCR1_TA_SHIFT (24U)
34726 
34728 #define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
34729 #define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
34730 #define SEMC_NANDCR1_CEITV_SHIFT (28U)
34731 
34733 #define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
34734 
34738 #define SEMC_NANDCR2_TWHR_MASK (0x3FU)
34739 #define SEMC_NANDCR2_TWHR_SHIFT (0U)
34740 
34742 #define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
34743 #define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
34744 #define SEMC_NANDCR2_TRHW_SHIFT (6U)
34745 
34747 #define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
34748 #define SEMC_NANDCR2_TADL_MASK (0x3F000U)
34749 #define SEMC_NANDCR2_TADL_SHIFT (12U)
34750 
34752 #define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
34753 #define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
34754 #define SEMC_NANDCR2_TRR_SHIFT (18U)
34755 
34757 #define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
34758 #define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
34759 #define SEMC_NANDCR2_TWB_SHIFT (24U)
34760 
34762 #define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
34763 
34767 #define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
34768 #define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
34769 
34771 #define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
34772 #define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
34773 #define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
34774 
34776 #define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
34777 #define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
34778 #define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
34779 
34781 #define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
34782 
34786 #define SEMC_NORCR0_PS_MASK (0x1U)
34787 #define SEMC_NORCR0_PS_SHIFT (0U)
34788 
34792 #define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
34793 #define SEMC_NORCR0_BL_MASK (0x70U)
34794 #define SEMC_NORCR0_BL_SHIFT (4U)
34795 
34805 #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
34806 #define SEMC_NORCR0_AM_MASK (0x300U)
34807 #define SEMC_NORCR0_AM_SHIFT (8U)
34808 
34814 #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
34815 #define SEMC_NORCR0_ADVP_MASK (0x400U)
34816 #define SEMC_NORCR0_ADVP_SHIFT (10U)
34817 
34821 #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
34822 #define SEMC_NORCR0_COL_MASK (0xF000U)
34823 #define SEMC_NORCR0_COL_SHIFT (12U)
34824 
34842 #define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
34843 
34847 #define SEMC_NORCR1_CES_MASK (0xFU)
34848 #define SEMC_NORCR1_CES_SHIFT (0U)
34849 
34851 #define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
34852 #define SEMC_NORCR1_CEH_MASK (0xF0U)
34853 #define SEMC_NORCR1_CEH_SHIFT (4U)
34854 
34856 #define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
34857 #define SEMC_NORCR1_AS_MASK (0xF00U)
34858 #define SEMC_NORCR1_AS_SHIFT (8U)
34859 
34861 #define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
34862 #define SEMC_NORCR1_AH_MASK (0xF000U)
34863 #define SEMC_NORCR1_AH_SHIFT (12U)
34864 
34866 #define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
34867 #define SEMC_NORCR1_WEL_MASK (0xF0000U)
34868 #define SEMC_NORCR1_WEL_SHIFT (16U)
34869 
34871 #define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
34872 #define SEMC_NORCR1_WEH_MASK (0xF00000U)
34873 #define SEMC_NORCR1_WEH_SHIFT (20U)
34874 
34876 #define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
34877 #define SEMC_NORCR1_REL_MASK (0xF000000U)
34878 #define SEMC_NORCR1_REL_SHIFT (24U)
34879 
34881 #define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
34882 #define SEMC_NORCR1_REH_MASK (0xF0000000U)
34883 #define SEMC_NORCR1_REH_SHIFT (28U)
34884 
34886 #define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
34887 
34891 #define SEMC_NORCR2_WDS_MASK (0xFU)
34892 #define SEMC_NORCR2_WDS_SHIFT (0U)
34893 
34895 #define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)
34896 #define SEMC_NORCR2_WDH_MASK (0xF0U)
34897 #define SEMC_NORCR2_WDH_SHIFT (4U)
34898 
34900 #define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)
34901 #define SEMC_NORCR2_TA_MASK (0xF00U)
34902 #define SEMC_NORCR2_TA_SHIFT (8U)
34903 
34905 #define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
34906 #define SEMC_NORCR2_AWDH_MASK (0xF000U)
34907 #define SEMC_NORCR2_AWDH_SHIFT (12U)
34908 
34910 #define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
34911 #define SEMC_NORCR2_LC_MASK (0xF0000U)
34912 #define SEMC_NORCR2_LC_SHIFT (16U)
34913 
34915 #define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
34916 #define SEMC_NORCR2_RD_MASK (0xF00000U)
34917 #define SEMC_NORCR2_RD_SHIFT (20U)
34918 
34920 #define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
34921 #define SEMC_NORCR2_CEITV_MASK (0xF000000U)
34922 #define SEMC_NORCR2_CEITV_SHIFT (24U)
34923 
34925 #define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
34926 
34930 #define SEMC_SRAMCR0_PS_MASK (0x1U)
34931 #define SEMC_SRAMCR0_PS_SHIFT (0U)
34932 
34936 #define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
34937 #define SEMC_SRAMCR0_BL_MASK (0x70U)
34938 #define SEMC_SRAMCR0_BL_SHIFT (4U)
34939 
34949 #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
34950 #define SEMC_SRAMCR0_AM_MASK (0x300U)
34951 #define SEMC_SRAMCR0_AM_SHIFT (8U)
34952 
34958 #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
34959 #define SEMC_SRAMCR0_ADVP_MASK (0x400U)
34960 #define SEMC_SRAMCR0_ADVP_SHIFT (10U)
34961 
34965 #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
34966 #define SEMC_SRAMCR0_COL_MASK (0xF000U)
34967 #define SEMC_SRAMCR0_COL_SHIFT (12U)
34968 
34986 #define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
34987 
34991 #define SEMC_SRAMCR1_CES_MASK (0xFU)
34992 #define SEMC_SRAMCR1_CES_SHIFT (0U)
34993 
34995 #define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
34996 #define SEMC_SRAMCR1_CEH_MASK (0xF0U)
34997 #define SEMC_SRAMCR1_CEH_SHIFT (4U)
34998 
35000 #define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
35001 #define SEMC_SRAMCR1_AS_MASK (0xF00U)
35002 #define SEMC_SRAMCR1_AS_SHIFT (8U)
35003 
35005 #define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
35006 #define SEMC_SRAMCR1_AH_MASK (0xF000U)
35007 #define SEMC_SRAMCR1_AH_SHIFT (12U)
35008 
35010 #define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
35011 #define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
35012 #define SEMC_SRAMCR1_WEL_SHIFT (16U)
35013 
35015 #define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
35016 #define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
35017 #define SEMC_SRAMCR1_WEH_SHIFT (20U)
35018 
35020 #define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
35021 #define SEMC_SRAMCR1_REL_MASK (0xF000000U)
35022 #define SEMC_SRAMCR1_REL_SHIFT (24U)
35023 
35025 #define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
35026 #define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
35027 #define SEMC_SRAMCR1_REH_SHIFT (28U)
35028 
35030 #define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
35031 
35035 #define SEMC_SRAMCR2_WDS_MASK (0xFU)
35036 #define SEMC_SRAMCR2_WDS_SHIFT (0U)
35037 
35039 #define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
35040 #define SEMC_SRAMCR2_WDH_MASK (0xF0U)
35041 #define SEMC_SRAMCR2_WDH_SHIFT (4U)
35042 
35044 #define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
35045 #define SEMC_SRAMCR2_TA_MASK (0xF00U)
35046 #define SEMC_SRAMCR2_TA_SHIFT (8U)
35047 
35049 #define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
35050 #define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
35051 #define SEMC_SRAMCR2_AWDH_SHIFT (12U)
35052 
35054 #define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
35055 #define SEMC_SRAMCR2_LC_MASK (0xF0000U)
35056 #define SEMC_SRAMCR2_LC_SHIFT (16U)
35057 
35059 #define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
35060 #define SEMC_SRAMCR2_RD_MASK (0xF00000U)
35061 #define SEMC_SRAMCR2_RD_SHIFT (20U)
35062 
35064 #define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
35065 #define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
35066 #define SEMC_SRAMCR2_CEITV_SHIFT (24U)
35067 
35069 #define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
35070 
35074 #define SEMC_DBICR0_PS_MASK (0x1U)
35075 #define SEMC_DBICR0_PS_SHIFT (0U)
35076 
35080 #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
35081 #define SEMC_DBICR0_BL_MASK (0x70U)
35082 #define SEMC_DBICR0_BL_SHIFT (4U)
35083 
35093 #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
35094 #define SEMC_DBICR0_COL_MASK (0xF000U)
35095 #define SEMC_DBICR0_COL_SHIFT (12U)
35096 
35114 #define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
35115 
35119 #define SEMC_DBICR1_CES_MASK (0xFU)
35120 #define SEMC_DBICR1_CES_SHIFT (0U)
35121 
35123 #define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
35124 #define SEMC_DBICR1_CEH_MASK (0xF0U)
35125 #define SEMC_DBICR1_CEH_SHIFT (4U)
35126 
35128 #define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
35129 #define SEMC_DBICR1_WEL_MASK (0xF00U)
35130 #define SEMC_DBICR1_WEL_SHIFT (8U)
35131 
35133 #define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
35134 #define SEMC_DBICR1_WEH_MASK (0xF000U)
35135 #define SEMC_DBICR1_WEH_SHIFT (12U)
35136 
35138 #define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
35139 #define SEMC_DBICR1_REL_MASK (0xF0000U)
35140 #define SEMC_DBICR1_REL_SHIFT (16U)
35141 
35143 #define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
35144 #define SEMC_DBICR1_REH_MASK (0xF00000U)
35145 #define SEMC_DBICR1_REH_SHIFT (20U)
35146 
35148 #define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
35149 #define SEMC_DBICR1_CEITV_MASK (0xF000000U)
35150 #define SEMC_DBICR1_CEITV_SHIFT (24U)
35151 
35153 #define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
35154 #define SEMC_DBICR1_REL2_MASK (0x30000000U)
35155 #define SEMC_DBICR1_REL2_SHIFT (28U)
35156 
35158 #define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK)
35159 #define SEMC_DBICR1_REH2_MASK (0xC0000000U)
35160 #define SEMC_DBICR1_REH2_SHIFT (30U)
35161 
35163 #define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK)
35164 
35168 #define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
35169 #define SEMC_IPCR0_SA_SHIFT (0U)
35170 
35172 #define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
35173 
35177 #define SEMC_IPCR1_DATSZ_MASK (0x7U)
35178 #define SEMC_IPCR1_DATSZ_SHIFT (0U)
35179 
35189 #define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
35190 
35194 #define SEMC_IPCR2_BM0_MASK (0x1U)
35195 #define SEMC_IPCR2_BM0_SHIFT (0U)
35196 
35200 #define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
35201 #define SEMC_IPCR2_BM1_MASK (0x2U)
35202 #define SEMC_IPCR2_BM1_SHIFT (1U)
35203 
35207 #define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
35208 #define SEMC_IPCR2_BM2_MASK (0x4U)
35209 #define SEMC_IPCR2_BM2_SHIFT (2U)
35210 
35214 #define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
35215 #define SEMC_IPCR2_BM3_MASK (0x8U)
35216 #define SEMC_IPCR2_BM3_SHIFT (3U)
35217 
35221 #define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
35222 
35226 #define SEMC_IPCMD_CMD_MASK (0xFFFFU)
35227 #define SEMC_IPCMD_CMD_SHIFT (0U)
35228 #define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
35229 #define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
35230 #define SEMC_IPCMD_KEY_SHIFT (16U)
35231 
35233 #define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
35234 
35238 #define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
35239 #define SEMC_IPTXDAT_DAT_SHIFT (0U)
35240 #define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
35241 
35245 #define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
35246 #define SEMC_IPRXDAT_DAT_SHIFT (0U)
35247 #define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
35248 
35252 #define SEMC_STS0_IDLE_MASK (0x1U)
35253 #define SEMC_STS0_IDLE_SHIFT (0U)
35254 
35256 #define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
35257 #define SEMC_STS0_NARDY_MASK (0x2U)
35258 #define SEMC_STS0_NARDY_SHIFT (1U)
35259 
35263 #define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
35264 
35268 #define SEMC_STS2_NDWRPEND_MASK (0x8U)
35269 #define SEMC_STS2_NDWRPEND_SHIFT (3U)
35270 
35274 #define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
35275 
35279 #define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
35280 #define SEMC_STS12_NDADDR_SHIFT (0U)
35281 
35283 #define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
35284  /* end of group SEMC_Register_Masks */
35290 
35291 
35292 /* SEMC - Peripheral instance base addresses */
35294 #define SEMC_BASE (0x402F0000u)
35295 
35296 #define SEMC ((SEMC_Type *)SEMC_BASE)
35297 
35298 #define SEMC_BASE_ADDRS { SEMC_BASE }
35299 
35300 #define SEMC_BASE_PTRS { SEMC }
35301 
35302 #define SEMC_IRQS { SEMC_IRQn }
35303  /* end of group SEMC_Peripheral_Access_Layer */
35307 
35308 
35309 /* ----------------------------------------------------------------------------
35310  -- SNVS Peripheral Access Layer
35311  ---------------------------------------------------------------------------- */
35312 
35319 typedef struct {
35320  __IO uint32_t HPLR;
35321  __IO uint32_t HPCOMR;
35322  __IO uint32_t HPCR;
35323  __IO uint32_t HPSICR;
35324  __IO uint32_t HPSVCR;
35325  __IO uint32_t HPSR;
35326  __IO uint32_t HPSVSR;
35327  __IO uint32_t HPHACIVR;
35328  __I uint32_t HPHACR;
35329  __IO uint32_t HPRTCMR;
35330  __IO uint32_t HPRTCLR;
35331  __IO uint32_t HPTAMR;
35332  __IO uint32_t HPTALR;
35333  __IO uint32_t LPLR;
35334  __IO uint32_t LPCR;
35335  __IO uint32_t LPMKCR;
35336  __IO uint32_t LPSVCR;
35337  uint8_t RESERVED_0[4];
35338  __IO uint32_t LPTDCR;
35339  __IO uint32_t LPSR;
35340  __IO uint32_t LPSRTCMR;
35341  __IO uint32_t LPSRTCLR;
35342  __IO uint32_t LPTAR;
35343  __I uint32_t LPSMCMR;
35344  __I uint32_t LPSMCLR;
35345  __IO uint32_t LPPGDR;
35346  __IO uint32_t LPGPR0_LEGACY_ALIAS;
35347  __IO uint32_t LPZMKR[8];
35348  uint8_t RESERVED_1[4];
35349  __IO uint32_t LPGPR_ALIAS[4];
35350  uint8_t RESERVED_2[96];
35351  __IO uint32_t LPGPR[8];
35352  uint8_t RESERVED_3[2776];
35353  __I uint32_t HPVIDR1;
35354  __I uint32_t HPVIDR2;
35355 } SNVS_Type;
35356 
35357 /* ----------------------------------------------------------------------------
35358  -- SNVS Register Masks
35359  ---------------------------------------------------------------------------- */
35360 
35368 #define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
35369 #define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
35370 
35374 #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
35375 #define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
35376 #define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
35377 
35381 #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
35382 #define SNVS_HPLR_SRTC_SL_MASK (0x4U)
35383 #define SNVS_HPLR_SRTC_SL_SHIFT (2U)
35384 
35388 #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
35389 #define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
35390 #define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
35391 
35395 #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
35396 #define SNVS_HPLR_MC_SL_MASK (0x10U)
35397 #define SNVS_HPLR_MC_SL_SHIFT (4U)
35398 
35402 #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
35403 #define SNVS_HPLR_GPR_SL_MASK (0x20U)
35404 #define SNVS_HPLR_GPR_SL_SHIFT (5U)
35405 
35409 #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
35410 #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
35411 #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
35412 
35416 #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
35417 #define SNVS_HPLR_LPTDCR_SL_MASK (0x100U)
35418 #define SNVS_HPLR_LPTDCR_SL_SHIFT (8U)
35419 
35423 #define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
35424 #define SNVS_HPLR_MKS_SL_MASK (0x200U)
35425 #define SNVS_HPLR_MKS_SL_SHIFT (9U)
35426 
35430 #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
35431 #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
35432 #define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
35433 
35437 #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
35438 #define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
35439 #define SNVS_HPLR_HPSICR_L_SHIFT (17U)
35440 
35444 #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
35445 #define SNVS_HPLR_HAC_L_MASK (0x40000U)
35446 #define SNVS_HPLR_HAC_L_SHIFT (18U)
35447 
35451 #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
35452 
35456 #define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
35457 #define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
35458 #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
35459 #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
35460 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
35461 
35465 #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
35466 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
35467 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
35468 
35472 #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
35473 #define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
35474 #define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
35475 
35479 #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
35480 #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
35481 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
35482 
35486 #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
35487 #define SNVS_HPCOMR_SW_SV_MASK (0x100U)
35488 #define SNVS_HPCOMR_SW_SV_SHIFT (8U)
35489 #define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
35490 #define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
35491 #define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
35492 #define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
35493 #define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
35494 #define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
35495 #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
35496 #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
35497 #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
35498 
35502 #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
35503 #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
35504 #define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
35505 
35509 #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
35510 #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
35511 #define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
35512 
35516 #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
35517 #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
35518 #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
35519 
35523 #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
35524 #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
35525 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
35526 
35530 #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
35531 #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
35532 #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
35533 #define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
35534 #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
35535 #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
35536 #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
35537 
35541 #define SNVS_HPCR_RTC_EN_MASK (0x1U)
35542 #define SNVS_HPCR_RTC_EN_SHIFT (0U)
35543 
35547 #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
35548 #define SNVS_HPCR_HPTA_EN_MASK (0x2U)
35549 #define SNVS_HPCR_HPTA_EN_SHIFT (1U)
35550 
35554 #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
35555 #define SNVS_HPCR_DIS_PI_MASK (0x4U)
35556 #define SNVS_HPCR_DIS_PI_SHIFT (2U)
35557 
35561 #define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
35562 #define SNVS_HPCR_PI_EN_MASK (0x8U)
35563 #define SNVS_HPCR_PI_EN_SHIFT (3U)
35564 
35568 #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
35569 #define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
35570 #define SNVS_HPCR_PI_FREQ_SHIFT (4U)
35571 
35589 #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
35590 #define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
35591 #define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
35592 
35596 #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
35597 #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
35598 #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
35599 
35609 #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
35610 #define SNVS_HPCR_HP_TS_MASK (0x10000U)
35611 #define SNVS_HPCR_HP_TS_SHIFT (16U)
35612 
35616 #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
35617 #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
35618 #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
35619 #define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
35620 #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
35621 #define SNVS_HPCR_BTN_MASK_SHIFT (27U)
35622 #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
35623 
35627 #define SNVS_HPSICR_SV0_EN_MASK (0x1U)
35628 #define SNVS_HPSICR_SV0_EN_SHIFT (0U)
35629 
35633 #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
35634 #define SNVS_HPSICR_SV1_EN_MASK (0x2U)
35635 #define SNVS_HPSICR_SV1_EN_SHIFT (1U)
35636 
35640 #define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
35641 #define SNVS_HPSICR_SV2_EN_MASK (0x4U)
35642 #define SNVS_HPSICR_SV2_EN_SHIFT (2U)
35643 
35647 #define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
35648 #define SNVS_HPSICR_SV3_EN_MASK (0x8U)
35649 #define SNVS_HPSICR_SV3_EN_SHIFT (3U)
35650 
35654 #define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
35655 #define SNVS_HPSICR_SV4_EN_MASK (0x10U)
35656 #define SNVS_HPSICR_SV4_EN_SHIFT (4U)
35657 
35661 #define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
35662 #define SNVS_HPSICR_SV5_EN_MASK (0x20U)
35663 #define SNVS_HPSICR_SV5_EN_SHIFT (5U)
35664 
35668 #define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
35669 #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
35670 #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
35671 
35675 #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
35676 
35680 #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
35681 #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
35682 
35686 #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
35687 #define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
35688 #define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
35689 
35693 #define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
35694 #define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
35695 #define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
35696 
35700 #define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
35701 #define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
35702 #define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
35703 
35707 #define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
35708 #define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
35709 #define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
35710 
35714 #define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
35715 #define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
35716 #define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
35717 
35722 #define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
35723 #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
35724 #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
35725 
35730 #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
35731 
35735 #define SNVS_HPSR_HPTA_MASK (0x1U)
35736 #define SNVS_HPSR_HPTA_SHIFT (0U)
35737 
35741 #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
35742 #define SNVS_HPSR_PI_MASK (0x2U)
35743 #define SNVS_HPSR_PI_SHIFT (1U)
35744 
35748 #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
35749 #define SNVS_HPSR_LPDIS_MASK (0x10U)
35750 #define SNVS_HPSR_LPDIS_SHIFT (4U)
35751 #define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
35752 #define SNVS_HPSR_BTN_MASK (0x40U)
35753 #define SNVS_HPSR_BTN_SHIFT (6U)
35754 #define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
35755 #define SNVS_HPSR_BI_MASK (0x80U)
35756 #define SNVS_HPSR_BI_SHIFT (7U)
35757 #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
35758 #define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
35759 #define SNVS_HPSR_SSM_STATE_SHIFT (8U)
35760 
35770 #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
35771 #define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)
35772 #define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)
35773 
35779 #define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
35780 #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
35781 #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
35782 #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
35783 #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
35784 #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
35785 
35789 #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
35790 #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
35791 #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
35792 
35796 #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
35797 
35801 #define SNVS_HPSVSR_SV0_MASK (0x1U)
35802 #define SNVS_HPSVSR_SV0_SHIFT (0U)
35803 
35807 #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
35808 #define SNVS_HPSVSR_SV1_MASK (0x2U)
35809 #define SNVS_HPSVSR_SV1_SHIFT (1U)
35810 
35814 #define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
35815 #define SNVS_HPSVSR_SV2_MASK (0x4U)
35816 #define SNVS_HPSVSR_SV2_SHIFT (2U)
35817 
35821 #define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
35822 #define SNVS_HPSVSR_SV3_MASK (0x8U)
35823 #define SNVS_HPSVSR_SV3_SHIFT (3U)
35824 
35828 #define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
35829 #define SNVS_HPSVSR_SV4_MASK (0x10U)
35830 #define SNVS_HPSVSR_SV4_SHIFT (4U)
35831 
35835 #define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
35836 #define SNVS_HPSVSR_SV5_MASK (0x20U)
35837 #define SNVS_HPSVSR_SV5_SHIFT (5U)
35838 
35842 #define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
35843 #define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
35844 #define SNVS_HPSVSR_SW_SV_SHIFT (13U)
35845 #define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
35846 #define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
35847 #define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
35848 #define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
35849 #define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
35850 #define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
35851 #define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
35852 #define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
35853 #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
35854 #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
35855 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
35856 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
35857 
35861 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
35862 #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
35863 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
35864 #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
35865 
35869 #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
35870 #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
35871 #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
35872 
35876 #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
35877 #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
35878 #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
35879 
35883 #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
35884 #define SNVS_HPRTCMR_RTC_SHIFT (0U)
35885 #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
35886 
35890 #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
35891 #define SNVS_HPRTCLR_RTC_SHIFT (0U)
35892 #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
35893 
35897 #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
35898 #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
35899 #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
35900 
35904 #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
35905 #define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
35906 #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
35907 
35911 #define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
35912 #define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
35913 
35917 #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
35918 #define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
35919 #define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
35920 
35924 #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
35925 #define SNVS_LPLR_SRTC_HL_MASK (0x4U)
35926 #define SNVS_LPLR_SRTC_HL_SHIFT (2U)
35927 
35931 #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
35932 #define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
35933 #define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
35934 
35938 #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
35939 #define SNVS_LPLR_MC_HL_MASK (0x10U)
35940 #define SNVS_LPLR_MC_HL_SHIFT (4U)
35941 
35945 #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
35946 #define SNVS_LPLR_GPR_HL_MASK (0x20U)
35947 #define SNVS_LPLR_GPR_HL_SHIFT (5U)
35948 
35952 #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
35953 #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
35954 #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
35955 
35959 #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
35960 #define SNVS_LPLR_LPTDCR_HL_MASK (0x100U)
35961 #define SNVS_LPLR_LPTDCR_HL_SHIFT (8U)
35962 
35966 #define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
35967 #define SNVS_LPLR_MKS_HL_MASK (0x200U)
35968 #define SNVS_LPLR_MKS_HL_SHIFT (9U)
35969 
35973 #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
35974 
35978 #define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
35979 #define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
35980 
35984 #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
35985 #define SNVS_LPCR_LPTA_EN_MASK (0x2U)
35986 #define SNVS_LPCR_LPTA_EN_SHIFT (1U)
35987 
35991 #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
35992 #define SNVS_LPCR_MC_ENV_MASK (0x4U)
35993 #define SNVS_LPCR_MC_ENV_SHIFT (2U)
35994 
35998 #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
35999 #define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
36000 #define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
36001 #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
36002 #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
36003 #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
36004 
36008 #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
36009 #define SNVS_LPCR_DP_EN_MASK (0x20U)
36010 #define SNVS_LPCR_DP_EN_SHIFT (5U)
36011 
36015 #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
36016 #define SNVS_LPCR_TOP_MASK (0x40U)
36017 #define SNVS_LPCR_TOP_SHIFT (6U)
36018 
36022 #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
36023 #define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
36024 #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
36025 #define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
36026 #define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
36027 #define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
36028 
36032 #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
36033 #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
36034 #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
36035 
36045 #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
36046 #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
36047 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
36048 #define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
36049 #define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
36050 #define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
36051 #define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
36052 #define SNVS_LPCR_ON_TIME_MASK (0x300000U)
36053 #define SNVS_LPCR_ON_TIME_SHIFT (20U)
36054 #define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
36055 #define SNVS_LPCR_PK_EN_MASK (0x400000U)
36056 #define SNVS_LPCR_PK_EN_SHIFT (22U)
36057 #define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
36058 #define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
36059 #define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
36060 #define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
36061 #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
36062 #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
36063 #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
36064 
36068 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
36069 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
36070 
36075 #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
36076 #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
36077 #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
36078 
36082 #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
36083 #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
36084 #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
36085 
36089 #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
36090 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
36091 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
36092 
36096 #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
36097 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
36098 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
36099 #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
36100 
36104 #define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
36105 #define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
36106 
36110 #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
36111 #define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
36112 #define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
36113 
36117 #define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
36118 #define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
36119 #define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
36120 
36124 #define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
36125 #define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
36126 #define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
36127 
36131 #define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
36132 #define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
36133 #define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
36134 
36138 #define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
36139 #define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
36140 #define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
36141 
36145 #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
36146 
36150 #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
36151 #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
36152 
36156 #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
36157 #define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
36158 #define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
36159 
36163 #define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
36164 #define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
36165 #define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
36166 
36170 #define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
36171 #define SNVS_LPTDCR_ET1P_MASK (0x800U)
36172 #define SNVS_LPTDCR_ET1P_SHIFT (11U)
36173 
36177 #define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
36178 #define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
36179 #define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
36180 #define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
36181 #define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
36182 #define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
36183 #define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
36184 #define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
36185 #define SNVS_LPTDCR_OSCB_SHIFT (28U)
36186 
36190 #define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
36191 
36195 #define SNVS_LPSR_LPTA_MASK (0x1U)
36196 #define SNVS_LPSR_LPTA_SHIFT (0U)
36197 
36201 #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
36202 #define SNVS_LPSR_SRTCR_MASK (0x2U)
36203 #define SNVS_LPSR_SRTCR_SHIFT (1U)
36204 
36208 #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
36209 #define SNVS_LPSR_MCR_MASK (0x4U)
36210 #define SNVS_LPSR_MCR_SHIFT (2U)
36211 
36215 #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
36216 #define SNVS_LPSR_PGD_MASK (0x8U)
36217 #define SNVS_LPSR_PGD_SHIFT (3U)
36218 #define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
36219 #define SNVS_LPSR_ET1D_MASK (0x200U)
36220 #define SNVS_LPSR_ET1D_SHIFT (9U)
36221 
36225 #define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
36226 #define SNVS_LPSR_ESVD_MASK (0x10000U)
36227 #define SNVS_LPSR_ESVD_SHIFT (16U)
36228 
36232 #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
36233 #define SNVS_LPSR_EO_MASK (0x20000U)
36234 #define SNVS_LPSR_EO_SHIFT (17U)
36235 
36239 #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
36240 #define SNVS_LPSR_SPO_MASK (0x40000U)
36241 #define SNVS_LPSR_SPO_SHIFT (18U)
36242 
36246 #define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
36247 #define SNVS_LPSR_SED_MASK (0x100000U)
36248 #define SNVS_LPSR_SED_SHIFT (20U)
36249 
36253 #define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)
36254 #define SNVS_LPSR_LPNS_MASK (0x40000000U)
36255 #define SNVS_LPSR_LPNS_SHIFT (30U)
36256 
36260 #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
36261 #define SNVS_LPSR_LPS_MASK (0x80000000U)
36262 #define SNVS_LPSR_LPS_SHIFT (31U)
36263 
36267 #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
36268 
36272 #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
36273 #define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
36274 #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
36275 
36279 #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
36280 #define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
36281 #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
36282 
36286 #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
36287 #define SNVS_LPTAR_LPTA_SHIFT (0U)
36288 #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
36289 
36293 #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
36294 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
36295 #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
36296 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
36297 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
36298 #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
36299 
36303 #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
36304 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
36305 #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
36306 
36310 #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
36311 #define SNVS_LPPGDR_PGD_SHIFT (0U)
36312 #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
36313 
36317 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
36318 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
36319 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
36320 
36324 #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
36325 #define SNVS_LPZMKR_ZMK_SHIFT (0U)
36326 #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
36327 
36329 /* The count of SNVS_LPZMKR */
36330 #define SNVS_LPZMKR_COUNT (8U)
36331 
36334 #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
36335 #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
36336 #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
36337 
36339 /* The count of SNVS_LPGPR_ALIAS */
36340 #define SNVS_LPGPR_ALIAS_COUNT (4U)
36341 
36344 #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
36345 #define SNVS_LPGPR_GPR_SHIFT (0U)
36346 #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
36347 
36349 /* The count of SNVS_LPGPR */
36350 #define SNVS_LPGPR_COUNT (8U)
36351 
36354 #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
36355 #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
36356 #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
36357 #define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
36358 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
36359 #define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
36360 #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
36361 #define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
36362 #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
36363 
36367 #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
36368 #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
36369 #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
36370 #define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
36371 #define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
36372 #define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
36373 #define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
36374 #define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
36375 #define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
36376 #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
36377 #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
36378 #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
36379  /* end of group SNVS_Register_Masks */
36385 
36386 
36387 /* SNVS - Peripheral instance base addresses */
36389 #define SNVS_BASE (0x400D4000u)
36390 
36391 #define SNVS ((SNVS_Type *)SNVS_BASE)
36392 
36393 #define SNVS_BASE_ADDRS { SNVS_BASE }
36394 
36395 #define SNVS_BASE_PTRS { SNVS }
36396 
36397 #define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }
36398 #define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
36399 #define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
36400  /* end of group SNVS_Peripheral_Access_Layer */
36404 
36405 
36406 /* ----------------------------------------------------------------------------
36407  -- SPDIF Peripheral Access Layer
36408  ---------------------------------------------------------------------------- */
36409 
36416 typedef struct {
36417  __IO uint32_t SCR;
36418  __IO uint32_t SRCD;
36419  __IO uint32_t SRPC;
36420  __IO uint32_t SIE;
36421  union { /* offset: 0x10 */
36422  __O uint32_t SIC;
36423  __I uint32_t SIS;
36424  };
36425  __I uint32_t SRL;
36426  __I uint32_t SRR;
36427  __I uint32_t SRCSH;
36428  __I uint32_t SRCSL;
36429  __I uint32_t SRU;
36430  __I uint32_t SRQ;
36431  __O uint32_t STL;
36432  __O uint32_t STR;
36433  __IO uint32_t STCSCH;
36434  __IO uint32_t STCSCL;
36435  uint8_t RESERVED_0[8];
36436  __I uint32_t SRFM;
36437  uint8_t RESERVED_1[8];
36438  __IO uint32_t STC;
36439 } SPDIF_Type;
36440 
36441 /* ----------------------------------------------------------------------------
36442  -- SPDIF Register Masks
36443  ---------------------------------------------------------------------------- */
36444 
36452 #define SPDIF_SCR_USRC_SEL_MASK (0x3U)
36453 #define SPDIF_SCR_USRC_SEL_SHIFT (0U)
36454 
36460 #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
36461 #define SPDIF_SCR_TXSEL_MASK (0x1CU)
36462 #define SPDIF_SCR_TXSEL_SHIFT (2U)
36463 
36468 #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
36469 #define SPDIF_SCR_VALCTRL_MASK (0x20U)
36470 #define SPDIF_SCR_VALCTRL_SHIFT (5U)
36471 
36475 #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
36476 #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
36477 #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
36478 #define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
36479 #define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
36480 #define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
36481 #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
36482 #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
36483 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
36484 
36490 #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
36491 #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
36492 #define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
36493 #define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
36494 #define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
36495 #define SPDIF_SCR_LOW_POWER_SHIFT (13U)
36496 #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
36497 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
36498 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
36499 
36505 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
36506 #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
36507 #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
36508 
36512 #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
36513 #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
36514 #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
36515 
36519 #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
36520 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
36521 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
36522 
36528 #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
36529 #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
36530 #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
36531 
36535 #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
36536 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
36537 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
36538 
36542 #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
36543 #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
36544 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
36545 
36549 #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
36550 
36554 #define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
36555 #define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
36556 
36560 #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
36561 
36565 #define SPDIF_SRPC_GAINSEL_MASK (0x38U)
36566 #define SPDIF_SRPC_GAINSEL_SHIFT (3U)
36567 
36576 #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
36577 #define SPDIF_SRPC_LOCK_MASK (0x40U)
36578 #define SPDIF_SRPC_LOCK_SHIFT (6U)
36579 #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
36580 #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
36581 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
36582 
36590 #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
36591 
36595 #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
36596 #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
36597 #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
36598 #define SPDIF_SIE_TXEM_MASK (0x2U)
36599 #define SPDIF_SIE_TXEM_SHIFT (1U)
36600 #define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
36601 #define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
36602 #define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
36603 #define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
36604 #define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
36605 #define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
36606 #define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
36607 #define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
36608 #define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
36609 #define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
36610 #define SPDIF_SIE_UQERR_MASK (0x20U)
36611 #define SPDIF_SIE_UQERR_SHIFT (5U)
36612 #define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
36613 #define SPDIF_SIE_UQSYNC_MASK (0x40U)
36614 #define SPDIF_SIE_UQSYNC_SHIFT (6U)
36615 #define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
36616 #define SPDIF_SIE_QRXOV_MASK (0x80U)
36617 #define SPDIF_SIE_QRXOV_SHIFT (7U)
36618 #define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
36619 #define SPDIF_SIE_QRXFUL_MASK (0x100U)
36620 #define SPDIF_SIE_QRXFUL_SHIFT (8U)
36621 #define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
36622 #define SPDIF_SIE_URXOV_MASK (0x200U)
36623 #define SPDIF_SIE_URXOV_SHIFT (9U)
36624 #define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
36625 #define SPDIF_SIE_URXFUL_MASK (0x400U)
36626 #define SPDIF_SIE_URXFUL_SHIFT (10U)
36627 #define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
36628 #define SPDIF_SIE_BITERR_MASK (0x4000U)
36629 #define SPDIF_SIE_BITERR_SHIFT (14U)
36630 #define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
36631 #define SPDIF_SIE_SYMERR_MASK (0x8000U)
36632 #define SPDIF_SIE_SYMERR_SHIFT (15U)
36633 #define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
36634 #define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
36635 #define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
36636 #define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
36637 #define SPDIF_SIE_CNEW_MASK (0x20000U)
36638 #define SPDIF_SIE_CNEW_SHIFT (17U)
36639 #define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
36640 #define SPDIF_SIE_TXRESYN_MASK (0x40000U)
36641 #define SPDIF_SIE_TXRESYN_SHIFT (18U)
36642 #define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
36643 #define SPDIF_SIE_TXUNOV_MASK (0x80000U)
36644 #define SPDIF_SIE_TXUNOV_SHIFT (19U)
36645 #define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
36646 #define SPDIF_SIE_LOCK_MASK (0x100000U)
36647 #define SPDIF_SIE_LOCK_SHIFT (20U)
36648 #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
36649 
36653 #define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
36654 #define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
36655 #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
36656 #define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
36657 #define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
36658 #define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
36659 #define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
36660 #define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
36661 #define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
36662 #define SPDIF_SIC_UQERR_MASK (0x20U)
36663 #define SPDIF_SIC_UQERR_SHIFT (5U)
36664 #define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
36665 #define SPDIF_SIC_UQSYNC_MASK (0x40U)
36666 #define SPDIF_SIC_UQSYNC_SHIFT (6U)
36667 #define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
36668 #define SPDIF_SIC_QRXOV_MASK (0x80U)
36669 #define SPDIF_SIC_QRXOV_SHIFT (7U)
36670 #define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
36671 #define SPDIF_SIC_URXOV_MASK (0x200U)
36672 #define SPDIF_SIC_URXOV_SHIFT (9U)
36673 #define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
36674 #define SPDIF_SIC_BITERR_MASK (0x4000U)
36675 #define SPDIF_SIC_BITERR_SHIFT (14U)
36676 #define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
36677 #define SPDIF_SIC_SYMERR_MASK (0x8000U)
36678 #define SPDIF_SIC_SYMERR_SHIFT (15U)
36679 #define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
36680 #define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
36681 #define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
36682 #define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
36683 #define SPDIF_SIC_CNEW_MASK (0x20000U)
36684 #define SPDIF_SIC_CNEW_SHIFT (17U)
36685 #define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
36686 #define SPDIF_SIC_TXRESYN_MASK (0x40000U)
36687 #define SPDIF_SIC_TXRESYN_SHIFT (18U)
36688 #define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
36689 #define SPDIF_SIC_TXUNOV_MASK (0x80000U)
36690 #define SPDIF_SIC_TXUNOV_SHIFT (19U)
36691 #define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
36692 #define SPDIF_SIC_LOCK_MASK (0x100000U)
36693 #define SPDIF_SIC_LOCK_SHIFT (20U)
36694 #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
36695 
36699 #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
36700 #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
36701 #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
36702 #define SPDIF_SIS_TXEM_MASK (0x2U)
36703 #define SPDIF_SIS_TXEM_SHIFT (1U)
36704 #define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
36705 #define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
36706 #define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
36707 #define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
36708 #define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
36709 #define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
36710 #define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
36711 #define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
36712 #define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
36713 #define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
36714 #define SPDIF_SIS_UQERR_MASK (0x20U)
36715 #define SPDIF_SIS_UQERR_SHIFT (5U)
36716 #define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
36717 #define SPDIF_SIS_UQSYNC_MASK (0x40U)
36718 #define SPDIF_SIS_UQSYNC_SHIFT (6U)
36719 #define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
36720 #define SPDIF_SIS_QRXOV_MASK (0x80U)
36721 #define SPDIF_SIS_QRXOV_SHIFT (7U)
36722 #define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
36723 #define SPDIF_SIS_QRXFUL_MASK (0x100U)
36724 #define SPDIF_SIS_QRXFUL_SHIFT (8U)
36725 #define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
36726 #define SPDIF_SIS_URXOV_MASK (0x200U)
36727 #define SPDIF_SIS_URXOV_SHIFT (9U)
36728 #define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
36729 #define SPDIF_SIS_URXFUL_MASK (0x400U)
36730 #define SPDIF_SIS_URXFUL_SHIFT (10U)
36731 #define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
36732 #define SPDIF_SIS_BITERR_MASK (0x4000U)
36733 #define SPDIF_SIS_BITERR_SHIFT (14U)
36734 #define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
36735 #define SPDIF_SIS_SYMERR_MASK (0x8000U)
36736 #define SPDIF_SIS_SYMERR_SHIFT (15U)
36737 #define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
36738 #define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
36739 #define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
36740 #define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
36741 #define SPDIF_SIS_CNEW_MASK (0x20000U)
36742 #define SPDIF_SIS_CNEW_SHIFT (17U)
36743 #define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
36744 #define SPDIF_SIS_TXRESYN_MASK (0x40000U)
36745 #define SPDIF_SIS_TXRESYN_SHIFT (18U)
36746 #define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
36747 #define SPDIF_SIS_TXUNOV_MASK (0x80000U)
36748 #define SPDIF_SIS_TXUNOV_SHIFT (19U)
36749 #define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
36750 #define SPDIF_SIS_LOCK_MASK (0x100000U)
36751 #define SPDIF_SIS_LOCK_SHIFT (20U)
36752 #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
36753 
36757 #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
36758 #define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
36759 #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
36760 
36764 #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
36765 #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
36766 #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
36767 
36771 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
36772 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
36773 #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
36774 
36778 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
36779 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
36780 #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
36781 
36785 #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
36786 #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
36787 #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
36788 
36792 #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
36793 #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
36794 #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
36795 
36799 #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
36800 #define SPDIF_STL_TXDATALEFT_SHIFT (0U)
36801 #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
36802 
36806 #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
36807 #define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
36808 #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
36809 
36813 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
36814 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
36815 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
36816 
36820 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
36821 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
36822 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
36823 
36827 #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
36828 #define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
36829 #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
36830 
36834 #define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
36835 #define SPDIF_STC_TXCLK_DF_SHIFT (0U)
36836 
36841 #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
36842 #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
36843 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
36844 
36848 #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
36849 #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
36850 #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
36851 
36857 #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
36858 #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
36859 #define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
36860 
36865 #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
36866  /* end of group SPDIF_Register_Masks */
36872 
36873 
36874 /* SPDIF - Peripheral instance base addresses */
36876 #define SPDIF_BASE (0x40380000u)
36877 
36878 #define SPDIF ((SPDIF_Type *)SPDIF_BASE)
36879 
36880 #define SPDIF_BASE_ADDRS { SPDIF_BASE }
36881 
36882 #define SPDIF_BASE_PTRS { SPDIF }
36883 
36884 #define SPDIF_IRQS { SPDIF_IRQn }
36885  /* end of group SPDIF_Peripheral_Access_Layer */
36889 
36890 
36891 /* ----------------------------------------------------------------------------
36892  -- SRC Peripheral Access Layer
36893  ---------------------------------------------------------------------------- */
36894 
36901 typedef struct {
36902  __IO uint32_t SCR;
36903  __I uint32_t SBMR1;
36904  __IO uint32_t SRSR;
36905  uint8_t RESERVED_0[16];
36906  __I uint32_t SBMR2;
36907  __IO uint32_t GPR[10];
36908 } SRC_Type;
36909 
36910 /* ----------------------------------------------------------------------------
36911  -- SRC Register Masks
36912  ---------------------------------------------------------------------------- */
36913 
36921 #define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
36922 #define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
36923 
36927 #define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
36928 #define SRC_SCR_CORE0_RST_MASK (0x2000U)
36929 #define SRC_SCR_CORE0_RST_SHIFT (13U)
36930 
36934 #define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
36935 #define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
36936 #define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
36937 
36941 #define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
36942 #define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
36943 #define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
36944 
36948 #define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
36949 #define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
36950 #define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
36951 
36955 #define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
36956 
36960 #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
36961 #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
36962 #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
36963 #define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
36964 #define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
36965 #define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
36966 #define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
36967 #define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
36968 #define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
36969 #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
36970 #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
36971 #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
36972 
36976 #define SRC_SRSR_IPP_RESET_B_MASK (0x1U)
36977 #define SRC_SRSR_IPP_RESET_B_SHIFT (0U)
36978 
36982 #define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
36983 #define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
36984 #define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
36985 
36989 #define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
36990 #define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
36991 #define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
36992 
36996 #define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
36997 #define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
36998 #define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
36999 
37003 #define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
37004 #define SRC_SRSR_WDOG_RST_B_MASK (0x10U)
37005 #define SRC_SRSR_WDOG_RST_B_SHIFT (4U)
37006 
37010 #define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
37011 #define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
37012 #define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
37013 
37017 #define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
37018 #define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
37019 #define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
37020 
37024 #define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
37025 #define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
37026 #define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
37027 
37031 #define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
37032 #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
37033 #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
37034 
37038 #define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
37039 
37043 #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
37044 #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
37045 #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
37046 #define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
37047 #define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
37048 #define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
37049 #define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
37050 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
37051 #define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
37052 #define SRC_SBMR2_BMOD_MASK (0x3000000U)
37053 #define SRC_SBMR2_BMOD_SHIFT (24U)
37054 #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
37055 
37059 #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
37060 #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
37061 #define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
37062 #define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
37063 #define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
37064 #define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
37065 
37067 /* The count of SRC_GPR */
37068 #define SRC_GPR_COUNT (10U)
37069 
37070  /* end of group SRC_Register_Masks */
37074 
37075 
37076 /* SRC - Peripheral instance base addresses */
37078 #define SRC_BASE (0x400F8000u)
37079 
37080 #define SRC ((SRC_Type *)SRC_BASE)
37081 
37082 #define SRC_BASE_ADDRS { SRC_BASE }
37083 
37084 #define SRC_BASE_PTRS { SRC }
37085 
37086 #define SRC_IRQS { SRC_IRQn }
37087 /* Backward compatibility */
37088 #define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
37089 #define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
37090 #define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
37091 #define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
37092 #define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
37093 #define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
37094 #define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
37095 #define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
37096 #define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
37097 #define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
37098 #define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
37099 #define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
37100 #define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
37101 #define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
37102 #define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
37103 /* Extra definition */
37104 #define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \
37105  | SRC_SRSR_JTAG_SW_RST_MASK \
37106  | SRC_SRSR_JTAG_RST_B_MASK \
37107  | SRC_SRSR_WDOG_RST_B_MASK \
37108  | SRC_SRSR_IPP_USER_RESET_B_MASK \
37109  | SRC_SRSR_CSU_RESET_B_MASK \
37110  | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \
37111  | SRC_SRSR_IPP_RESET_B_MASK)
37112 
37113  /* end of group SRC_Peripheral_Access_Layer */
37117 
37118 
37119 /* ----------------------------------------------------------------------------
37120  -- TEMPMON Peripheral Access Layer
37121  ---------------------------------------------------------------------------- */
37122 
37129 typedef struct {
37130  uint8_t RESERVED_0[384];
37131  __IO uint32_t TEMPSENSE0;
37132  __IO uint32_t TEMPSENSE0_SET;
37133  __IO uint32_t TEMPSENSE0_CLR;
37134  __IO uint32_t TEMPSENSE0_TOG;
37135  __IO uint32_t TEMPSENSE1;
37136  __IO uint32_t TEMPSENSE1_SET;
37137  __IO uint32_t TEMPSENSE1_CLR;
37138  __IO uint32_t TEMPSENSE1_TOG;
37139  uint8_t RESERVED_1[240];
37140  __IO uint32_t TEMPSENSE2;
37141  __IO uint32_t TEMPSENSE2_SET;
37142  __IO uint32_t TEMPSENSE2_CLR;
37143  __IO uint32_t TEMPSENSE2_TOG;
37144 } TEMPMON_Type;
37145 
37146 /* ----------------------------------------------------------------------------
37147  -- TEMPMON Register Masks
37148  ---------------------------------------------------------------------------- */
37149 
37157 #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
37158 #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
37159 
37163 #define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
37164 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
37165 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
37166 
37170 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
37171 #define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
37172 #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
37173 
37177 #define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
37178 #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
37179 #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
37180 #define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
37181 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
37182 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
37183 #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
37184 
37188 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
37189 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
37190 
37194 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
37195 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
37196 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
37197 
37201 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
37202 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
37203 #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
37204 
37208 #define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
37209 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
37210 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
37211 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
37212 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
37213 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
37214 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
37215 
37219 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
37220 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
37221 
37225 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
37226 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
37227 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
37228 
37232 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
37233 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
37234 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
37235 
37239 #define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
37240 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
37241 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
37242 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
37243 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
37244 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
37245 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
37246 
37250 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
37251 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
37252 
37256 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
37257 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
37258 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
37259 
37263 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
37264 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
37265 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
37266 
37270 #define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
37271 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
37272 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
37273 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
37274 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
37275 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
37276 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
37277 
37281 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
37282 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
37283 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
37284 
37288 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
37289 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
37290 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
37291 
37295 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
37296 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
37297 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
37298 
37302 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
37303 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
37304 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
37305 
37309 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
37310 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
37311 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
37312 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
37313 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
37314 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
37315 
37319 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
37320 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
37321 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
37322 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
37323 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
37324 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
37325 
37329 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
37330 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
37331 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
37332 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
37333 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
37334 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
37335 
37339 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
37340 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
37341 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
37342 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
37343 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
37344 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
37345  /* end of group TEMPMON_Register_Masks */
37351 
37352 
37353 /* TEMPMON - Peripheral instance base addresses */
37355 #define TEMPMON_BASE (0x400D8000u)
37356 
37357 #define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
37358 
37359 #define TEMPMON_BASE_ADDRS { TEMPMON_BASE }
37360 
37361 #define TEMPMON_BASE_PTRS { TEMPMON }
37362  /* end of group TEMPMON_Peripheral_Access_Layer */
37366 
37367 
37368 /* ----------------------------------------------------------------------------
37369  -- TMR Peripheral Access Layer
37370  ---------------------------------------------------------------------------- */
37371 
37378 typedef struct {
37379  struct { /* offset: 0x0, array step: 0x20 */
37380  __IO uint16_t COMP1;
37381  __IO uint16_t COMP2;
37382  __IO uint16_t CAPT;
37383  __IO uint16_t LOAD;
37384  __IO uint16_t HOLD;
37385  __IO uint16_t CNTR;
37386  __IO uint16_t CTRL;
37387  __IO uint16_t SCTRL;
37388  __IO uint16_t CMPLD1;
37389  __IO uint16_t CMPLD2;
37390  __IO uint16_t CSCTRL;
37391  __IO uint16_t FILT;
37392  __IO uint16_t DMA;
37393  uint8_t RESERVED_0[4];
37394  __IO uint16_t ENBL;
37395  } CHANNEL[4];
37396 } TMR_Type;
37397 
37398 /* ----------------------------------------------------------------------------
37399  -- TMR Register Masks
37400  ---------------------------------------------------------------------------- */
37401 
37409 #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
37410 #define TMR_COMP1_COMPARISON_1_SHIFT (0U)
37411 
37413 #define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
37414 
37416 /* The count of TMR_COMP1 */
37417 #define TMR_COMP1_COUNT (4U)
37418 
37421 #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
37422 #define TMR_COMP2_COMPARISON_2_SHIFT (0U)
37423 
37425 #define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
37426 
37428 /* The count of TMR_COMP2 */
37429 #define TMR_COMP2_COUNT (4U)
37430 
37433 #define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
37434 #define TMR_CAPT_CAPTURE_SHIFT (0U)
37435 
37437 #define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
37438 
37440 /* The count of TMR_CAPT */
37441 #define TMR_CAPT_COUNT (4U)
37442 
37445 #define TMR_LOAD_LOAD_MASK (0xFFFFU)
37446 #define TMR_LOAD_LOAD_SHIFT (0U)
37447 
37449 #define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
37450 
37452 /* The count of TMR_LOAD */
37453 #define TMR_LOAD_COUNT (4U)
37454 
37457 #define TMR_HOLD_HOLD_MASK (0xFFFFU)
37458 #define TMR_HOLD_HOLD_SHIFT (0U)
37459 #define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
37460 
37462 /* The count of TMR_HOLD */
37463 #define TMR_HOLD_COUNT (4U)
37464 
37467 #define TMR_CNTR_COUNTER_MASK (0xFFFFU)
37468 #define TMR_CNTR_COUNTER_SHIFT (0U)
37469 #define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
37470 
37472 /* The count of TMR_CNTR */
37473 #define TMR_CNTR_COUNT (4U)
37474 
37477 #define TMR_CTRL_OUTMODE_MASK (0x7U)
37478 #define TMR_CTRL_OUTMODE_SHIFT (0U)
37479 
37489 #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
37490 #define TMR_CTRL_COINIT_MASK (0x8U)
37491 #define TMR_CTRL_COINIT_SHIFT (3U)
37492 
37496 #define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
37497 #define TMR_CTRL_DIR_MASK (0x10U)
37498 #define TMR_CTRL_DIR_SHIFT (4U)
37499 
37503 #define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
37504 #define TMR_CTRL_LENGTH_MASK (0x20U)
37505 #define TMR_CTRL_LENGTH_SHIFT (5U)
37506 
37514 #define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
37515 #define TMR_CTRL_ONCE_MASK (0x40U)
37516 #define TMR_CTRL_ONCE_SHIFT (6U)
37517 
37524 #define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
37525 #define TMR_CTRL_SCS_MASK (0x180U)
37526 #define TMR_CTRL_SCS_SHIFT (7U)
37527 
37533 #define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
37534 #define TMR_CTRL_PCS_MASK (0x1E00U)
37535 #define TMR_CTRL_PCS_SHIFT (9U)
37536 
37554 #define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
37555 #define TMR_CTRL_CM_MASK (0xE000U)
37556 #define TMR_CTRL_CM_SHIFT (13U)
37557 
37570 #define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
37571 
37573 /* The count of TMR_CTRL */
37574 #define TMR_CTRL_COUNT (4U)
37575 
37578 #define TMR_SCTRL_OEN_MASK (0x1U)
37579 #define TMR_SCTRL_OEN_SHIFT (0U)
37580 
37585 #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
37586 #define TMR_SCTRL_OPS_MASK (0x2U)
37587 #define TMR_SCTRL_OPS_SHIFT (1U)
37588 
37592 #define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
37593 #define TMR_SCTRL_FORCE_MASK (0x4U)
37594 #define TMR_SCTRL_FORCE_SHIFT (2U)
37595 
37597 #define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
37598 #define TMR_SCTRL_VAL_MASK (0x8U)
37599 #define TMR_SCTRL_VAL_SHIFT (3U)
37600 
37602 #define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
37603 #define TMR_SCTRL_EEOF_MASK (0x10U)
37604 #define TMR_SCTRL_EEOF_SHIFT (4U)
37605 
37607 #define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
37608 #define TMR_SCTRL_MSTR_MASK (0x20U)
37609 #define TMR_SCTRL_MSTR_SHIFT (5U)
37610 
37612 #define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
37613 #define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
37614 #define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
37615 
37621 #define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
37622 #define TMR_SCTRL_INPUT_MASK (0x100U)
37623 #define TMR_SCTRL_INPUT_SHIFT (8U)
37624 
37626 #define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
37627 #define TMR_SCTRL_IPS_MASK (0x200U)
37628 #define TMR_SCTRL_IPS_SHIFT (9U)
37629 
37631 #define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
37632 #define TMR_SCTRL_IEFIE_MASK (0x400U)
37633 #define TMR_SCTRL_IEFIE_SHIFT (10U)
37634 
37636 #define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
37637 #define TMR_SCTRL_IEF_MASK (0x800U)
37638 #define TMR_SCTRL_IEF_SHIFT (11U)
37639 
37641 #define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
37642 #define TMR_SCTRL_TOFIE_MASK (0x1000U)
37643 #define TMR_SCTRL_TOFIE_SHIFT (12U)
37644 
37646 #define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
37647 #define TMR_SCTRL_TOF_MASK (0x2000U)
37648 #define TMR_SCTRL_TOF_SHIFT (13U)
37649 
37651 #define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
37652 #define TMR_SCTRL_TCFIE_MASK (0x4000U)
37653 #define TMR_SCTRL_TCFIE_SHIFT (14U)
37654 
37656 #define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
37657 #define TMR_SCTRL_TCF_MASK (0x8000U)
37658 #define TMR_SCTRL_TCF_SHIFT (15U)
37659 
37661 #define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
37662 
37664 /* The count of TMR_SCTRL */
37665 #define TMR_SCTRL_COUNT (4U)
37666 
37669 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
37670 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
37671 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
37672 
37674 /* The count of TMR_CMPLD1 */
37675 #define TMR_CMPLD1_COUNT (4U)
37676 
37679 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
37680 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
37681 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
37682 
37684 /* The count of TMR_CMPLD2 */
37685 #define TMR_CMPLD2_COUNT (4U)
37686 
37689 #define TMR_CSCTRL_CL1_MASK (0x3U)
37690 #define TMR_CSCTRL_CL1_SHIFT (0U)
37691 
37697 #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
37698 #define TMR_CSCTRL_CL2_MASK (0xCU)
37699 #define TMR_CSCTRL_CL2_SHIFT (2U)
37700 
37706 #define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
37707 #define TMR_CSCTRL_TCF1_MASK (0x10U)
37708 #define TMR_CSCTRL_TCF1_SHIFT (4U)
37709 
37711 #define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
37712 #define TMR_CSCTRL_TCF2_MASK (0x20U)
37713 #define TMR_CSCTRL_TCF2_SHIFT (5U)
37714 
37716 #define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
37717 #define TMR_CSCTRL_TCF1EN_MASK (0x40U)
37718 #define TMR_CSCTRL_TCF1EN_SHIFT (6U)
37719 
37721 #define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
37722 #define TMR_CSCTRL_TCF2EN_MASK (0x80U)
37723 #define TMR_CSCTRL_TCF2EN_SHIFT (7U)
37724 
37726 #define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
37727 #define TMR_CSCTRL_UP_MASK (0x200U)
37728 #define TMR_CSCTRL_UP_SHIFT (9U)
37729 
37733 #define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
37734 #define TMR_CSCTRL_TCI_MASK (0x400U)
37735 #define TMR_CSCTRL_TCI_SHIFT (10U)
37736 
37740 #define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
37741 #define TMR_CSCTRL_ROC_MASK (0x800U)
37742 #define TMR_CSCTRL_ROC_SHIFT (11U)
37743 
37747 #define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
37748 #define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
37749 #define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
37750 
37754 #define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
37755 #define TMR_CSCTRL_FAULT_MASK (0x2000U)
37756 #define TMR_CSCTRL_FAULT_SHIFT (13U)
37757 
37761 #define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
37762 #define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
37763 #define TMR_CSCTRL_DBG_EN_SHIFT (14U)
37764 
37770 #define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
37771 
37773 /* The count of TMR_CSCTRL */
37774 #define TMR_CSCTRL_COUNT (4U)
37775 
37778 #define TMR_FILT_FILT_PER_MASK (0xFFU)
37779 #define TMR_FILT_FILT_PER_SHIFT (0U)
37780 
37782 #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
37783 #define TMR_FILT_FILT_CNT_MASK (0x700U)
37784 #define TMR_FILT_FILT_CNT_SHIFT (8U)
37785 
37787 #define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
37788 
37790 /* The count of TMR_FILT */
37791 #define TMR_FILT_COUNT (4U)
37792 
37795 #define TMR_DMA_IEFDE_MASK (0x1U)
37796 #define TMR_DMA_IEFDE_SHIFT (0U)
37797 
37799 #define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
37800 #define TMR_DMA_CMPLD1DE_MASK (0x2U)
37801 #define TMR_DMA_CMPLD1DE_SHIFT (1U)
37802 
37804 #define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
37805 #define TMR_DMA_CMPLD2DE_MASK (0x4U)
37806 #define TMR_DMA_CMPLD2DE_SHIFT (2U)
37807 
37809 #define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
37810 
37812 /* The count of TMR_DMA */
37813 #define TMR_DMA_COUNT (4U)
37814 
37817 #define TMR_ENBL_ENBL_MASK (0xFU)
37818 #define TMR_ENBL_ENBL_SHIFT (0U)
37819 
37823 #define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
37824 
37826 /* The count of TMR_ENBL */
37827 #define TMR_ENBL_COUNT (4U)
37828 
37829  /* end of group TMR_Register_Masks */
37833 
37834 
37835 /* TMR - Peripheral instance base addresses */
37837 #define TMR1_BASE (0x401DC000u)
37838 
37839 #define TMR1 ((TMR_Type *)TMR1_BASE)
37840 
37841 #define TMR2_BASE (0x401E0000u)
37842 
37843 #define TMR2 ((TMR_Type *)TMR2_BASE)
37844 
37845 #define TMR3_BASE (0x401E4000u)
37846 
37847 #define TMR3 ((TMR_Type *)TMR3_BASE)
37848 
37849 #define TMR4_BASE (0x401E8000u)
37850 
37851 #define TMR4 ((TMR_Type *)TMR4_BASE)
37852 
37853 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
37854 
37855 #define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
37856 
37857 #define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
37858  /* end of group TMR_Peripheral_Access_Layer */
37862 
37863 
37864 /* ----------------------------------------------------------------------------
37865  -- TRNG Peripheral Access Layer
37866  ---------------------------------------------------------------------------- */
37867 
37874 typedef struct {
37875  __IO uint32_t MCTL;
37876  __IO uint32_t SCMISC;
37877  __IO uint32_t PKRRNG;
37878  union { /* offset: 0xC */
37879  __IO uint32_t PKRMAX;
37880  __I uint32_t PKRSQ;
37881  };
37882  __IO uint32_t SDCTL;
37883  union { /* offset: 0x14 */
37884  __IO uint32_t SBLIM;
37885  __I uint32_t TOTSAM;
37886  };
37887  __IO uint32_t FRQMIN;
37888  union { /* offset: 0x1C */
37889  __I uint32_t FRQCNT;
37890  __IO uint32_t FRQMAX;
37891  };
37892  union { /* offset: 0x20 */
37893  __I uint32_t SCMC;
37894  __IO uint32_t SCML;
37895  };
37896  union { /* offset: 0x24 */
37897  __I uint32_t SCR1C;
37898  __IO uint32_t SCR1L;
37899  };
37900  union { /* offset: 0x28 */
37901  __I uint32_t SCR2C;
37902  __IO uint32_t SCR2L;
37903  };
37904  union { /* offset: 0x2C */
37905  __I uint32_t SCR3C;
37906  __IO uint32_t SCR3L;
37907  };
37908  union { /* offset: 0x30 */
37909  __I uint32_t SCR4C;
37910  __IO uint32_t SCR4L;
37911  };
37912  union { /* offset: 0x34 */
37913  __I uint32_t SCR5C;
37914  __IO uint32_t SCR5L;
37915  };
37916  union { /* offset: 0x38 */
37917  __I uint32_t SCR6PC;
37918  __IO uint32_t SCR6PL;
37919  };
37920  __I uint32_t STATUS;
37921  __I uint32_t ENT[16];
37922  __I uint32_t PKRCNT10;
37923  __I uint32_t PKRCNT32;
37924  __I uint32_t PKRCNT54;
37925  __I uint32_t PKRCNT76;
37926  __I uint32_t PKRCNT98;
37927  __I uint32_t PKRCNTBA;
37928  __I uint32_t PKRCNTDC;
37929  __I uint32_t PKRCNTFE;
37930  __IO uint32_t SEC_CFG;
37931  __IO uint32_t INT_CTRL;
37932  __IO uint32_t INT_MASK;
37933  __I uint32_t INT_STATUS;
37934  uint8_t RESERVED_0[64];
37935  __I uint32_t VID1;
37936  __I uint32_t VID2;
37937 } TRNG_Type;
37938 
37939 /* ----------------------------------------------------------------------------
37940  -- TRNG Register Masks
37941  ---------------------------------------------------------------------------- */
37942 
37950 #define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
37951 #define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
37952 
37958 #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
37959 #define TRNG_MCTL_OSC_DIV_MASK (0xCU)
37960 #define TRNG_MCTL_OSC_DIV_SHIFT (2U)
37961 
37967 #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
37968 #define TRNG_MCTL_UNUSED4_MASK (0x10U)
37969 #define TRNG_MCTL_UNUSED4_SHIFT (4U)
37970 #define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
37971 #define TRNG_MCTL_UNUSED5_MASK (0x20U)
37972 #define TRNG_MCTL_UNUSED5_SHIFT (5U)
37973 #define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
37974 #define TRNG_MCTL_RST_DEF_MASK (0x40U)
37975 #define TRNG_MCTL_RST_DEF_SHIFT (6U)
37976 #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
37977 #define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
37978 #define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
37979 #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
37980 #define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
37981 #define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
37982 #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
37983 #define TRNG_MCTL_FCT_VAL_MASK (0x200U)
37984 #define TRNG_MCTL_FCT_VAL_SHIFT (9U)
37985 #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
37986 #define TRNG_MCTL_ENT_VAL_MASK (0x400U)
37987 #define TRNG_MCTL_ENT_VAL_SHIFT (10U)
37988 #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
37989 #define TRNG_MCTL_TST_OUT_MASK (0x800U)
37990 #define TRNG_MCTL_TST_OUT_SHIFT (11U)
37991 #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
37992 #define TRNG_MCTL_ERR_MASK (0x1000U)
37993 #define TRNG_MCTL_ERR_SHIFT (12U)
37994 #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
37995 #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
37996 #define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
37997 #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
37998 #define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
37999 #define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
38000 #define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
38001 #define TRNG_MCTL_PRGM_MASK (0x10000U)
38002 #define TRNG_MCTL_PRGM_SHIFT (16U)
38003 #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
38004 
38008 #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
38009 #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
38010 #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
38011 #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
38012 #define TRNG_SCMISC_RTY_CT_SHIFT (16U)
38013 #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
38014 
38018 #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
38019 #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
38020 #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
38021 
38025 #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
38026 #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
38027 
38029 #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
38030 
38034 #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
38035 #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
38036 
38038 #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
38039 
38043 #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
38044 #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
38045 #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
38046 #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
38047 #define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
38048 #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
38049 
38053 #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
38054 #define TRNG_SBLIM_SB_LIM_SHIFT (0U)
38055 #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
38056 
38060 #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
38061 #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
38062 #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
38063 
38067 #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
38068 #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
38069 #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
38070 
38074 #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
38075 #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
38076 #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
38077 
38081 #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
38082 #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
38083 #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
38084 
38088 #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
38089 #define TRNG_SCMC_MONO_CT_SHIFT (0U)
38090 #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
38091 
38095 #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
38096 #define TRNG_SCML_MONO_MAX_SHIFT (0U)
38097 #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
38098 #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
38099 #define TRNG_SCML_MONO_RNG_SHIFT (16U)
38100 #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
38101 
38105 #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
38106 #define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
38107 #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
38108 #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
38109 #define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
38110 #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
38111 
38115 #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
38116 #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
38117 #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
38118 #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
38119 #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
38120 #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
38121 
38125 #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
38126 #define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
38127 #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
38128 #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
38129 #define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
38130 #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
38131 
38135 #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
38136 #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
38137 #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
38138 #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
38139 #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
38140 #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
38141 
38145 #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
38146 #define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
38147 #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
38148 #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
38149 #define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
38150 #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
38151 
38155 #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
38156 #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
38157 #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
38158 #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
38159 #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
38160 #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
38161 
38165 #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
38166 #define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
38167 #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
38168 #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
38169 #define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
38170 #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
38171 
38175 #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
38176 #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
38177 #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
38178 #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
38179 #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
38180 #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
38181 
38185 #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
38186 #define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
38187 #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
38188 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
38189 #define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
38190 #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
38191 
38195 #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
38196 #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
38197 #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
38198 #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
38199 #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
38200 #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
38201 
38205 #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
38206 #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
38207 #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
38208 #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
38209 #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
38210 #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
38211 
38215 #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
38216 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
38217 #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
38218 #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
38219 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
38220 #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
38221 
38225 #define TRNG_STATUS_TF1BR0_MASK (0x1U)
38226 #define TRNG_STATUS_TF1BR0_SHIFT (0U)
38227 #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
38228 #define TRNG_STATUS_TF1BR1_MASK (0x2U)
38229 #define TRNG_STATUS_TF1BR1_SHIFT (1U)
38230 #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
38231 #define TRNG_STATUS_TF2BR0_MASK (0x4U)
38232 #define TRNG_STATUS_TF2BR0_SHIFT (2U)
38233 #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
38234 #define TRNG_STATUS_TF2BR1_MASK (0x8U)
38235 #define TRNG_STATUS_TF2BR1_SHIFT (3U)
38236 #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
38237 #define TRNG_STATUS_TF3BR0_MASK (0x10U)
38238 #define TRNG_STATUS_TF3BR0_SHIFT (4U)
38239 #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
38240 #define TRNG_STATUS_TF3BR1_MASK (0x20U)
38241 #define TRNG_STATUS_TF3BR1_SHIFT (5U)
38242 #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
38243 #define TRNG_STATUS_TF4BR0_MASK (0x40U)
38244 #define TRNG_STATUS_TF4BR0_SHIFT (6U)
38245 #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
38246 #define TRNG_STATUS_TF4BR1_MASK (0x80U)
38247 #define TRNG_STATUS_TF4BR1_SHIFT (7U)
38248 #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
38249 #define TRNG_STATUS_TF5BR0_MASK (0x100U)
38250 #define TRNG_STATUS_TF5BR0_SHIFT (8U)
38251 #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
38252 #define TRNG_STATUS_TF5BR1_MASK (0x200U)
38253 #define TRNG_STATUS_TF5BR1_SHIFT (9U)
38254 #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
38255 #define TRNG_STATUS_TF6PBR0_MASK (0x400U)
38256 #define TRNG_STATUS_TF6PBR0_SHIFT (10U)
38257 #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
38258 #define TRNG_STATUS_TF6PBR1_MASK (0x800U)
38259 #define TRNG_STATUS_TF6PBR1_SHIFT (11U)
38260 #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
38261 #define TRNG_STATUS_TFSB_MASK (0x1000U)
38262 #define TRNG_STATUS_TFSB_SHIFT (12U)
38263 #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
38264 #define TRNG_STATUS_TFLR_MASK (0x2000U)
38265 #define TRNG_STATUS_TFLR_SHIFT (13U)
38266 #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
38267 #define TRNG_STATUS_TFP_MASK (0x4000U)
38268 #define TRNG_STATUS_TFP_SHIFT (14U)
38269 #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
38270 #define TRNG_STATUS_TFMB_MASK (0x8000U)
38271 #define TRNG_STATUS_TFMB_SHIFT (15U)
38272 #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
38273 #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
38274 #define TRNG_STATUS_RETRY_CT_SHIFT (16U)
38275 #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
38276 
38280 #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
38281 #define TRNG_ENT_ENT_SHIFT (0U)
38282 #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
38283 
38285 /* The count of TRNG_ENT */
38286 #define TRNG_ENT_COUNT (16U)
38287 
38290 #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
38291 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
38292 #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
38293 #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
38294 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
38295 #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
38296 
38300 #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
38301 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
38302 #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
38303 #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
38304 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
38305 #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
38306 
38310 #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
38311 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
38312 #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
38313 #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
38314 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
38315 #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
38316 
38320 #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
38321 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
38322 #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
38323 #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
38324 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
38325 #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
38326 
38330 #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
38331 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
38332 #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
38333 #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
38334 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
38335 #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
38336 
38340 #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
38341 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
38342 #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
38343 #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
38344 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
38345 #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
38346 
38350 #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
38351 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
38352 #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
38353 #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
38354 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
38355 #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
38356 
38360 #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
38361 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
38362 #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
38363 #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
38364 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
38365 #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
38366 
38370 #define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
38371 #define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
38372 #define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
38373 #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
38374 #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
38375 
38379 #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
38380 #define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
38381 #define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
38382 #define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
38383 
38387 #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
38388 #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
38389 
38393 #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
38394 #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
38395 #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
38396 
38400 #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
38401 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
38402 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
38403 
38407 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
38408 #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
38409 #define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
38410 #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
38411 
38415 #define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
38416 #define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
38417 
38421 #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
38422 #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
38423 #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
38424 
38428 #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
38429 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
38430 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
38431 
38435 #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
38436 
38440 #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
38441 #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
38442 
38446 #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
38447 #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
38448 #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
38449 
38453 #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
38454 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
38455 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
38456 
38460 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
38461 
38465 #define TRNG_VID1_MIN_REV_MASK (0xFFU)
38466 #define TRNG_VID1_MIN_REV_SHIFT (0U)
38467 
38470 #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
38471 #define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
38472 #define TRNG_VID1_MAJ_REV_SHIFT (8U)
38473 
38476 #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
38477 #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
38478 #define TRNG_VID1_IP_ID_SHIFT (16U)
38479 
38482 #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
38483 
38487 #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
38488 #define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
38489 
38492 #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
38493 #define TRNG_VID2_ECO_REV_MASK (0xFF00U)
38494 #define TRNG_VID2_ECO_REV_SHIFT (8U)
38495 
38498 #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
38499 #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
38500 #define TRNG_VID2_INTG_OPT_SHIFT (16U)
38501 
38504 #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
38505 #define TRNG_VID2_ERA_MASK (0xFF000000U)
38506 #define TRNG_VID2_ERA_SHIFT (24U)
38507 
38510 #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
38511  /* end of group TRNG_Register_Masks */
38517 
38518 
38519 /* TRNG - Peripheral instance base addresses */
38521 #define TRNG_BASE (0x400CC000u)
38522 
38523 #define TRNG ((TRNG_Type *)TRNG_BASE)
38524 
38525 #define TRNG_BASE_ADDRS { TRNG_BASE }
38526 
38527 #define TRNG_BASE_PTRS { TRNG }
38528 
38529 #define TRNG_IRQS { TRNG_IRQn }
38530  /* end of group TRNG_Peripheral_Access_Layer */
38534 
38535 
38536 /* ----------------------------------------------------------------------------
38537  -- TSC Peripheral Access Layer
38538  ---------------------------------------------------------------------------- */
38539 
38546 typedef struct {
38547  __IO uint32_t BASIC_SETTING;
38548  uint8_t RESERVED_0[12];
38549  __IO uint32_t PRE_CHARGE_TIME;
38550  uint8_t RESERVED_1[12];
38551  __IO uint32_t FLOW_CONTROL;
38552  uint8_t RESERVED_2[12];
38553  __I uint32_t MEASEURE_VALUE;
38554  uint8_t RESERVED_3[12];
38555  __IO uint32_t INT_EN;
38556  uint8_t RESERVED_4[12];
38557  __IO uint32_t INT_SIG_EN;
38558  uint8_t RESERVED_5[12];
38559  __IO uint32_t INT_STATUS;
38560  uint8_t RESERVED_6[12];
38561  __IO uint32_t DEBUG_MODE;
38562  uint8_t RESERVED_7[12];
38563  __IO uint32_t DEBUG_MODE2;
38564 } TSC_Type;
38565 
38566 /* ----------------------------------------------------------------------------
38567  -- TSC Register Masks
38568  ---------------------------------------------------------------------------- */
38569 
38577 #define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)
38578 #define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)
38579 
38583 #define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
38584 #define TSC_BASIC_SETTING_WIRE_4_5_MASK (0x10U)
38585 #define TSC_BASIC_SETTING_WIRE_4_5_SHIFT (4U)
38586 
38590 #define TSC_BASIC_SETTING_WIRE_4_5(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_WIRE_4_5_SHIFT)) & TSC_BASIC_SETTING_WIRE_4_5_MASK)
38591 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
38592 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
38593 
38595 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
38596 
38600 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
38601 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
38602 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
38603 
38607 #define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)
38608 #define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)
38609 
38611 #define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
38612 #define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)
38613 #define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)
38614 
38618 #define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
38619 #define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)
38620 #define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)
38621 
38625 #define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
38626 #define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)
38627 #define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)
38628 
38632 #define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
38633 #define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)
38634 #define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)
38635 
38639 #define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
38640 
38644 #define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)
38645 #define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)
38646 
38648 #define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
38649 #define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)
38650 #define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)
38651 
38653 #define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
38654 
38658 #define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)
38659 #define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)
38660 
38664 #define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
38665 #define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U)
38666 #define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U)
38667 
38671 #define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
38672 #define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)
38673 #define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)
38674 
38678 #define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
38679 
38683 #define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)
38684 #define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)
38685 
38687 #define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
38688 #define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)
38689 #define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)
38690 
38694 #define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
38695 #define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)
38696 #define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)
38697 
38701 #define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
38702 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)
38703 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)
38704 
38708 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
38709 
38713 #define TSC_INT_STATUS_MEASURE_MASK (0x1U)
38714 #define TSC_INT_STATUS_MEASURE_SHIFT (0U)
38715 
38719 #define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
38720 #define TSC_INT_STATUS_DETECT_MASK (0x10U)
38721 #define TSC_INT_STATUS_DETECT_SHIFT (4U)
38722 
38726 #define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
38727 #define TSC_INT_STATUS_VALID_MASK (0x100U)
38728 #define TSC_INT_STATUS_VALID_SHIFT (8U)
38729 
38733 #define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
38734 #define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)
38735 #define TSC_INT_STATUS_IDLE_SW_SHIFT (12U)
38736 
38740 #define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
38741 
38745 #define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)
38746 #define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)
38747 
38749 #define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
38750 #define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)
38751 #define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)
38752 
38754 #define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
38755 #define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)
38756 #define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)
38757 
38759 #define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
38760 #define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)
38761 #define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)
38762 
38766 #define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
38767 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)
38768 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)
38769 
38773 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
38774 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
38775 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
38776 
38780 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
38781 #define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)
38782 #define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)
38783 
38787 #define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
38788 
38792 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)
38793 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)
38794 
38798 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
38799 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)
38800 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)
38801 
38805 #define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
38806 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)
38807 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)
38808 
38812 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
38813 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)
38814 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)
38815 
38819 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
38820 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)
38821 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)
38822 
38826 #define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
38827 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)
38828 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)
38829 
38833 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
38834 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)
38835 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)
38836 
38840 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
38841 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)
38842 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)
38843 
38847 #define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
38848 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)
38849 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)
38850 
38854 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
38855 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)
38856 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)
38857 
38861 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
38862 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)
38863 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)
38864 
38868 #define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
38869 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)
38870 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)
38871 
38875 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
38876 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)
38877 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)
38878 
38882 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
38883 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)
38884 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)
38885 
38889 #define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
38890 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)
38891 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
38892 
38896 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
38897 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)
38898 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)
38899 
38903 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
38904 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)
38905 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)
38906 
38910 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
38911 #define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)
38912 #define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)
38913 
38922 #define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
38923 #define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)
38924 #define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)
38925 
38929 #define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
38930 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
38931 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
38932 
38936 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
38937 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
38938 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
38939 
38943 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
38944 #define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)
38945 #define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)
38946 
38952 #define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
38953  /* end of group TSC_Register_Masks */
38959 
38960 
38961 /* TSC - Peripheral instance base addresses */
38963 #define TSC_BASE (0x400E0000u)
38964 
38965 #define TSC ((TSC_Type *)TSC_BASE)
38966 
38967 #define TSC_BASE_ADDRS { TSC_BASE }
38968 
38969 #define TSC_BASE_PTRS { TSC }
38970 
38971 #define TSC_IRQS { TSC_DIG_IRQn }
38972 /* Backward compatibility */
38973 #define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_WIRE_4_5_MASK
38974 #define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_WIRE_4_5_SHIFT
38975 #define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_WIRE_4_5(x)
38976 
38977  /* end of group TSC_Peripheral_Access_Layer */
38981 
38982 
38983 /* ----------------------------------------------------------------------------
38984  -- USB Peripheral Access Layer
38985  ---------------------------------------------------------------------------- */
38986 
38993 typedef struct {
38994  __I uint32_t ID;
38995  __I uint32_t HWGENERAL;
38996  __I uint32_t HWHOST;
38997  __I uint32_t HWDEVICE;
38998  __I uint32_t HWTXBUF;
38999  __I uint32_t HWRXBUF;
39000  uint8_t RESERVED_0[104];
39001  __IO uint32_t GPTIMER0LD;
39002  __IO uint32_t GPTIMER0CTRL;
39003  __IO uint32_t GPTIMER1LD;
39004  __IO uint32_t GPTIMER1CTRL;
39005  __IO uint32_t SBUSCFG;
39006  uint8_t RESERVED_1[108];
39007  __I uint8_t CAPLENGTH;
39008  uint8_t RESERVED_2[1];
39009  __I uint16_t HCIVERSION;
39010  __I uint32_t HCSPARAMS;
39011  __I uint32_t HCCPARAMS;
39012  uint8_t RESERVED_3[20];
39013  __I uint16_t DCIVERSION;
39014  uint8_t RESERVED_4[2];
39015  __I uint32_t DCCPARAMS;
39016  uint8_t RESERVED_5[24];
39017  __IO uint32_t USBCMD;
39018  __IO uint32_t USBSTS;
39019  __IO uint32_t USBINTR;
39020  __IO uint32_t FRINDEX;
39021  uint8_t RESERVED_6[4];
39022  union { /* offset: 0x154 */
39023  __IO uint32_t DEVICEADDR;
39024  __IO uint32_t PERIODICLISTBASE;
39025  };
39026  union { /* offset: 0x158 */
39027  __IO uint32_t ASYNCLISTADDR;
39028  __IO uint32_t ENDPTLISTADDR;
39029  };
39030  uint8_t RESERVED_7[4];
39031  __IO uint32_t BURSTSIZE;
39032  __IO uint32_t TXFILLTUNING;
39033  uint8_t RESERVED_8[16];
39034  __IO uint32_t ENDPTNAK;
39035  __IO uint32_t ENDPTNAKEN;
39036  __I uint32_t CONFIGFLAG;
39037  __IO uint32_t PORTSC1;
39038  uint8_t RESERVED_9[28];
39039  __IO uint32_t OTGSC;
39040  __IO uint32_t USBMODE;
39041  __IO uint32_t ENDPTSETUPSTAT;
39042  __IO uint32_t ENDPTPRIME;
39043  __IO uint32_t ENDPTFLUSH;
39044  __I uint32_t ENDPTSTAT;
39045  __IO uint32_t ENDPTCOMPLETE;
39046  __IO uint32_t ENDPTCTRL0;
39047  __IO uint32_t ENDPTCTRL[7];
39048 } USB_Type;
39049 
39050 /* ----------------------------------------------------------------------------
39051  -- USB Register Masks
39052  ---------------------------------------------------------------------------- */
39053 
39061 #define USB_ID_ID_MASK (0x3FU)
39062 #define USB_ID_ID_SHIFT (0U)
39063 #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
39064 #define USB_ID_NID_MASK (0x3F00U)
39065 #define USB_ID_NID_SHIFT (8U)
39066 #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
39067 #define USB_ID_REVISION_MASK (0xFF0000U)
39068 #define USB_ID_REVISION_SHIFT (16U)
39069 #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
39070 
39074 #define USB_HWGENERAL_PHYW_MASK (0x30U)
39075 #define USB_HWGENERAL_PHYW_SHIFT (4U)
39076 
39082 #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
39083 #define USB_HWGENERAL_PHYM_MASK (0x1C0U)
39084 #define USB_HWGENERAL_PHYM_SHIFT (6U)
39085 
39095 #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
39096 #define USB_HWGENERAL_SM_MASK (0x600U)
39097 #define USB_HWGENERAL_SM_SHIFT (9U)
39098 
39104 #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
39105 
39109 #define USB_HWHOST_HC_MASK (0x1U)
39110 #define USB_HWHOST_HC_SHIFT (0U)
39111 
39115 #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
39116 #define USB_HWHOST_NPORT_MASK (0xEU)
39117 #define USB_HWHOST_NPORT_SHIFT (1U)
39118 #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
39119 
39123 #define USB_HWDEVICE_DC_MASK (0x1U)
39124 #define USB_HWDEVICE_DC_SHIFT (0U)
39125 
39129 #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
39130 #define USB_HWDEVICE_DEVEP_MASK (0x3EU)
39131 #define USB_HWDEVICE_DEVEP_SHIFT (1U)
39132 #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
39133 
39137 #define USB_HWTXBUF_TXBURST_MASK (0xFFU)
39138 #define USB_HWTXBUF_TXBURST_SHIFT (0U)
39139 #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
39140 #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
39141 #define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
39142 #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
39143 
39147 #define USB_HWRXBUF_RXBURST_MASK (0xFFU)
39148 #define USB_HWRXBUF_RXBURST_SHIFT (0U)
39149 #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
39150 #define USB_HWRXBUF_RXADD_MASK (0xFF00U)
39151 #define USB_HWRXBUF_RXADD_SHIFT (8U)
39152 #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
39153 
39157 #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
39158 #define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
39159 #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
39160 
39164 #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
39165 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
39166 #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
39167 #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
39168 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
39169 
39173 #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
39174 #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
39175 #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
39176 
39180 #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
39181 #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
39182 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
39183 
39187 #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
39188 
39192 #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
39193 #define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
39194 #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
39195 
39199 #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
39200 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
39201 #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
39202 #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
39203 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
39204 
39208 #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
39209 #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
39210 #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
39211 
39215 #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
39216 #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
39217 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
39218 
39222 #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
39223 
39227 #define USB_SBUSCFG_AHBBRST_MASK (0x7U)
39228 #define USB_SBUSCFG_AHBBRST_SHIFT (0U)
39229 
39239 #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
39240 
39244 #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
39245 #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
39246 #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
39247 
39251 #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
39252 #define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
39253 #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
39254 
39258 #define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
39259 #define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
39260 #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
39261 #define USB_HCSPARAMS_PPC_MASK (0x10U)
39262 #define USB_HCSPARAMS_PPC_SHIFT (4U)
39263 #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
39264 #define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
39265 #define USB_HCSPARAMS_N_PCC_SHIFT (8U)
39266 #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
39267 #define USB_HCSPARAMS_N_CC_MASK (0xF000U)
39268 #define USB_HCSPARAMS_N_CC_SHIFT (12U)
39269 
39273 #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
39274 #define USB_HCSPARAMS_PI_MASK (0x10000U)
39275 #define USB_HCSPARAMS_PI_SHIFT (16U)
39276 #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
39277 #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
39278 #define USB_HCSPARAMS_N_PTT_SHIFT (20U)
39279 #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
39280 #define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
39281 #define USB_HCSPARAMS_N_TT_SHIFT (24U)
39282 #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
39283 
39287 #define USB_HCCPARAMS_ADC_MASK (0x1U)
39288 #define USB_HCCPARAMS_ADC_SHIFT (0U)
39289 #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
39290 #define USB_HCCPARAMS_PFL_MASK (0x2U)
39291 #define USB_HCCPARAMS_PFL_SHIFT (1U)
39292 #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
39293 #define USB_HCCPARAMS_ASP_MASK (0x4U)
39294 #define USB_HCCPARAMS_ASP_SHIFT (2U)
39295 #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
39296 #define USB_HCCPARAMS_IST_MASK (0xF0U)
39297 #define USB_HCCPARAMS_IST_SHIFT (4U)
39298 #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
39299 #define USB_HCCPARAMS_EECP_MASK (0xFF00U)
39300 #define USB_HCCPARAMS_EECP_SHIFT (8U)
39301 #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
39302 
39306 #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
39307 #define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
39308 #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
39309 
39313 #define USB_DCCPARAMS_DEN_MASK (0x1FU)
39314 #define USB_DCCPARAMS_DEN_SHIFT (0U)
39315 #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
39316 #define USB_DCCPARAMS_DC_MASK (0x80U)
39317 #define USB_DCCPARAMS_DC_SHIFT (7U)
39318 #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
39319 #define USB_DCCPARAMS_HC_MASK (0x100U)
39320 #define USB_DCCPARAMS_HC_SHIFT (8U)
39321 #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
39322 
39326 #define USB_USBCMD_RS_MASK (0x1U)
39327 #define USB_USBCMD_RS_SHIFT (0U)
39328 #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
39329 #define USB_USBCMD_RST_MASK (0x2U)
39330 #define USB_USBCMD_RST_SHIFT (1U)
39331 #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
39332 #define USB_USBCMD_FS_1_MASK (0xCU)
39333 #define USB_USBCMD_FS_1_SHIFT (2U)
39334 #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
39335 #define USB_USBCMD_PSE_MASK (0x10U)
39336 #define USB_USBCMD_PSE_SHIFT (4U)
39337 
39341 #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
39342 #define USB_USBCMD_ASE_MASK (0x20U)
39343 #define USB_USBCMD_ASE_SHIFT (5U)
39344 
39348 #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
39349 #define USB_USBCMD_IAA_MASK (0x40U)
39350 #define USB_USBCMD_IAA_SHIFT (6U)
39351 #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
39352 #define USB_USBCMD_ASP_MASK (0x300U)
39353 #define USB_USBCMD_ASP_SHIFT (8U)
39354 #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
39355 #define USB_USBCMD_ASPE_MASK (0x800U)
39356 #define USB_USBCMD_ASPE_SHIFT (11U)
39357 #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
39358 #define USB_USBCMD_ATDTW_MASK (0x1000U)
39359 #define USB_USBCMD_ATDTW_SHIFT (12U)
39360 #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
39361 #define USB_USBCMD_SUTW_MASK (0x2000U)
39362 #define USB_USBCMD_SUTW_SHIFT (13U)
39363 #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
39364 #define USB_USBCMD_FS_2_MASK (0x8000U)
39365 #define USB_USBCMD_FS_2_SHIFT (15U)
39366 
39370 #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
39371 #define USB_USBCMD_ITC_MASK (0xFF0000U)
39372 #define USB_USBCMD_ITC_SHIFT (16U)
39373 
39383 #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
39384 
39388 #define USB_USBSTS_UI_MASK (0x1U)
39389 #define USB_USBSTS_UI_SHIFT (0U)
39390 #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
39391 #define USB_USBSTS_UEI_MASK (0x2U)
39392 #define USB_USBSTS_UEI_SHIFT (1U)
39393 #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
39394 #define USB_USBSTS_PCI_MASK (0x4U)
39395 #define USB_USBSTS_PCI_SHIFT (2U)
39396 #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
39397 #define USB_USBSTS_FRI_MASK (0x8U)
39398 #define USB_USBSTS_FRI_SHIFT (3U)
39399 #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
39400 #define USB_USBSTS_SEI_MASK (0x10U)
39401 #define USB_USBSTS_SEI_SHIFT (4U)
39402 #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
39403 #define USB_USBSTS_AAI_MASK (0x20U)
39404 #define USB_USBSTS_AAI_SHIFT (5U)
39405 #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
39406 #define USB_USBSTS_URI_MASK (0x40U)
39407 #define USB_USBSTS_URI_SHIFT (6U)
39408 #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
39409 #define USB_USBSTS_SRI_MASK (0x80U)
39410 #define USB_USBSTS_SRI_SHIFT (7U)
39411 #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
39412 #define USB_USBSTS_SLI_MASK (0x100U)
39413 #define USB_USBSTS_SLI_SHIFT (8U)
39414 #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
39415 #define USB_USBSTS_ULPII_MASK (0x400U)
39416 #define USB_USBSTS_ULPII_SHIFT (10U)
39417 #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
39418 #define USB_USBSTS_HCH_MASK (0x1000U)
39419 #define USB_USBSTS_HCH_SHIFT (12U)
39420 #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
39421 #define USB_USBSTS_RCL_MASK (0x2000U)
39422 #define USB_USBSTS_RCL_SHIFT (13U)
39423 #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
39424 #define USB_USBSTS_PS_MASK (0x4000U)
39425 #define USB_USBSTS_PS_SHIFT (14U)
39426 #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
39427 #define USB_USBSTS_AS_MASK (0x8000U)
39428 #define USB_USBSTS_AS_SHIFT (15U)
39429 #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
39430 #define USB_USBSTS_NAKI_MASK (0x10000U)
39431 #define USB_USBSTS_NAKI_SHIFT (16U)
39432 #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
39433 #define USB_USBSTS_TI0_MASK (0x1000000U)
39434 #define USB_USBSTS_TI0_SHIFT (24U)
39435 #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
39436 #define USB_USBSTS_TI1_MASK (0x2000000U)
39437 #define USB_USBSTS_TI1_SHIFT (25U)
39438 #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
39439 
39443 #define USB_USBINTR_UE_MASK (0x1U)
39444 #define USB_USBINTR_UE_SHIFT (0U)
39445 #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
39446 #define USB_USBINTR_UEE_MASK (0x2U)
39447 #define USB_USBINTR_UEE_SHIFT (1U)
39448 #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
39449 #define USB_USBINTR_PCE_MASK (0x4U)
39450 #define USB_USBINTR_PCE_SHIFT (2U)
39451 #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
39452 #define USB_USBINTR_FRE_MASK (0x8U)
39453 #define USB_USBINTR_FRE_SHIFT (3U)
39454 #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
39455 #define USB_USBINTR_SEE_MASK (0x10U)
39456 #define USB_USBINTR_SEE_SHIFT (4U)
39457 #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
39458 #define USB_USBINTR_AAE_MASK (0x20U)
39459 #define USB_USBINTR_AAE_SHIFT (5U)
39460 #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
39461 #define USB_USBINTR_URE_MASK (0x40U)
39462 #define USB_USBINTR_URE_SHIFT (6U)
39463 #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
39464 #define USB_USBINTR_SRE_MASK (0x80U)
39465 #define USB_USBINTR_SRE_SHIFT (7U)
39466 #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
39467 #define USB_USBINTR_SLE_MASK (0x100U)
39468 #define USB_USBINTR_SLE_SHIFT (8U)
39469 #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
39470 #define USB_USBINTR_ULPIE_MASK (0x400U)
39471 #define USB_USBINTR_ULPIE_SHIFT (10U)
39472 #define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
39473 #define USB_USBINTR_NAKE_MASK (0x10000U)
39474 #define USB_USBINTR_NAKE_SHIFT (16U)
39475 #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
39476 #define USB_USBINTR_UAIE_MASK (0x40000U)
39477 #define USB_USBINTR_UAIE_SHIFT (18U)
39478 #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
39479 #define USB_USBINTR_UPIE_MASK (0x80000U)
39480 #define USB_USBINTR_UPIE_SHIFT (19U)
39481 #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
39482 #define USB_USBINTR_TIE0_MASK (0x1000000U)
39483 #define USB_USBINTR_TIE0_SHIFT (24U)
39484 #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
39485 #define USB_USBINTR_TIE1_MASK (0x2000000U)
39486 #define USB_USBINTR_TIE1_SHIFT (25U)
39487 #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
39488 
39492 #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
39493 #define USB_FRINDEX_FRINDEX_SHIFT (0U)
39494 
39504 #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
39505 
39509 #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
39510 #define USB_DEVICEADDR_USBADRA_SHIFT (24U)
39511 #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
39512 #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
39513 #define USB_DEVICEADDR_USBADR_SHIFT (25U)
39514 #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
39515 
39519 #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
39520 #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
39521 #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
39522 
39526 #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
39527 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
39528 #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
39529 
39533 #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
39534 #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
39535 #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
39536 
39540 #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
39541 #define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
39542 #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
39543 #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
39544 #define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
39545 #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
39546 
39550 #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
39551 #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
39552 #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
39553 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
39554 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
39555 #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
39556 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
39557 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
39558 #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
39559 
39563 #define USB_ENDPTNAK_EPRN_MASK (0xFFU)
39564 #define USB_ENDPTNAK_EPRN_SHIFT (0U)
39565 #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
39566 #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
39567 #define USB_ENDPTNAK_EPTN_SHIFT (16U)
39568 #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
39569 
39573 #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
39574 #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
39575 #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
39576 #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
39577 #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
39578 #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
39579 
39583 #define USB_CONFIGFLAG_CF_MASK (0x1U)
39584 #define USB_CONFIGFLAG_CF_SHIFT (0U)
39585 
39589 #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
39590 
39594 #define USB_PORTSC1_CCS_MASK (0x1U)
39595 #define USB_PORTSC1_CCS_SHIFT (0U)
39596 #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
39597 #define USB_PORTSC1_CSC_MASK (0x2U)
39598 #define USB_PORTSC1_CSC_SHIFT (1U)
39599 #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
39600 #define USB_PORTSC1_PE_MASK (0x4U)
39601 #define USB_PORTSC1_PE_SHIFT (2U)
39602 #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
39603 #define USB_PORTSC1_PEC_MASK (0x8U)
39604 #define USB_PORTSC1_PEC_SHIFT (3U)
39605 #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
39606 #define USB_PORTSC1_OCA_MASK (0x10U)
39607 #define USB_PORTSC1_OCA_SHIFT (4U)
39608 
39612 #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
39613 #define USB_PORTSC1_OCC_MASK (0x20U)
39614 #define USB_PORTSC1_OCC_SHIFT (5U)
39615 #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
39616 #define USB_PORTSC1_FPR_MASK (0x40U)
39617 #define USB_PORTSC1_FPR_SHIFT (6U)
39618 #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
39619 #define USB_PORTSC1_SUSP_MASK (0x80U)
39620 #define USB_PORTSC1_SUSP_SHIFT (7U)
39621 #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
39622 #define USB_PORTSC1_PR_MASK (0x100U)
39623 #define USB_PORTSC1_PR_SHIFT (8U)
39624 #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
39625 #define USB_PORTSC1_HSP_MASK (0x200U)
39626 #define USB_PORTSC1_HSP_SHIFT (9U)
39627 #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
39628 #define USB_PORTSC1_LS_MASK (0xC00U)
39629 #define USB_PORTSC1_LS_SHIFT (10U)
39630 
39636 #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
39637 #define USB_PORTSC1_PP_MASK (0x1000U)
39638 #define USB_PORTSC1_PP_SHIFT (12U)
39639 #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
39640 #define USB_PORTSC1_PO_MASK (0x2000U)
39641 #define USB_PORTSC1_PO_SHIFT (13U)
39642 #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
39643 #define USB_PORTSC1_PIC_MASK (0xC000U)
39644 #define USB_PORTSC1_PIC_SHIFT (14U)
39645 
39651 #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
39652 #define USB_PORTSC1_PTC_MASK (0xF0000U)
39653 #define USB_PORTSC1_PTC_SHIFT (16U)
39654 
39664 #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
39665 #define USB_PORTSC1_WKCN_MASK (0x100000U)
39666 #define USB_PORTSC1_WKCN_SHIFT (20U)
39667 #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
39668 #define USB_PORTSC1_WKDC_MASK (0x200000U)
39669 #define USB_PORTSC1_WKDC_SHIFT (21U)
39670 #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
39671 #define USB_PORTSC1_WKOC_MASK (0x400000U)
39672 #define USB_PORTSC1_WKOC_SHIFT (22U)
39673 #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
39674 #define USB_PORTSC1_PHCD_MASK (0x800000U)
39675 #define USB_PORTSC1_PHCD_SHIFT (23U)
39676 
39680 #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
39681 #define USB_PORTSC1_PFSC_MASK (0x1000000U)
39682 #define USB_PORTSC1_PFSC_SHIFT (24U)
39683 
39687 #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
39688 #define USB_PORTSC1_PTS_2_MASK (0x2000000U)
39689 #define USB_PORTSC1_PTS_2_SHIFT (25U)
39690 #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
39691 #define USB_PORTSC1_PSPD_MASK (0xC000000U)
39692 #define USB_PORTSC1_PSPD_SHIFT (26U)
39693 
39699 #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
39700 #define USB_PORTSC1_PTW_MASK (0x10000000U)
39701 #define USB_PORTSC1_PTW_SHIFT (28U)
39702 
39706 #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
39707 #define USB_PORTSC1_STS_MASK (0x20000000U)
39708 #define USB_PORTSC1_STS_SHIFT (29U)
39709 #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
39710 #define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
39711 #define USB_PORTSC1_PTS_1_SHIFT (30U)
39712 #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
39713 
39717 #define USB_OTGSC_VD_MASK (0x1U)
39718 #define USB_OTGSC_VD_SHIFT (0U)
39719 #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
39720 #define USB_OTGSC_VC_MASK (0x2U)
39721 #define USB_OTGSC_VC_SHIFT (1U)
39722 #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
39723 #define USB_OTGSC_OT_MASK (0x8U)
39724 #define USB_OTGSC_OT_SHIFT (3U)
39725 #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
39726 #define USB_OTGSC_DP_MASK (0x10U)
39727 #define USB_OTGSC_DP_SHIFT (4U)
39728 #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
39729 #define USB_OTGSC_IDPU_MASK (0x20U)
39730 #define USB_OTGSC_IDPU_SHIFT (5U)
39731 #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
39732 #define USB_OTGSC_ID_MASK (0x100U)
39733 #define USB_OTGSC_ID_SHIFT (8U)
39734 #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
39735 #define USB_OTGSC_AVV_MASK (0x200U)
39736 #define USB_OTGSC_AVV_SHIFT (9U)
39737 #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
39738 #define USB_OTGSC_ASV_MASK (0x400U)
39739 #define USB_OTGSC_ASV_SHIFT (10U)
39740 #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
39741 #define USB_OTGSC_BSV_MASK (0x800U)
39742 #define USB_OTGSC_BSV_SHIFT (11U)
39743 #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
39744 #define USB_OTGSC_BSE_MASK (0x1000U)
39745 #define USB_OTGSC_BSE_SHIFT (12U)
39746 #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
39747 #define USB_OTGSC_TOG_1MS_MASK (0x2000U)
39748 #define USB_OTGSC_TOG_1MS_SHIFT (13U)
39749 #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
39750 #define USB_OTGSC_DPS_MASK (0x4000U)
39751 #define USB_OTGSC_DPS_SHIFT (14U)
39752 #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
39753 #define USB_OTGSC_IDIS_MASK (0x10000U)
39754 #define USB_OTGSC_IDIS_SHIFT (16U)
39755 #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
39756 #define USB_OTGSC_AVVIS_MASK (0x20000U)
39757 #define USB_OTGSC_AVVIS_SHIFT (17U)
39758 #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
39759 #define USB_OTGSC_ASVIS_MASK (0x40000U)
39760 #define USB_OTGSC_ASVIS_SHIFT (18U)
39761 #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
39762 #define USB_OTGSC_BSVIS_MASK (0x80000U)
39763 #define USB_OTGSC_BSVIS_SHIFT (19U)
39764 #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
39765 #define USB_OTGSC_BSEIS_MASK (0x100000U)
39766 #define USB_OTGSC_BSEIS_SHIFT (20U)
39767 #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
39768 #define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
39769 #define USB_OTGSC_STATUS_1MS_SHIFT (21U)
39770 #define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
39771 #define USB_OTGSC_DPIS_MASK (0x400000U)
39772 #define USB_OTGSC_DPIS_SHIFT (22U)
39773 #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
39774 #define USB_OTGSC_IDIE_MASK (0x1000000U)
39775 #define USB_OTGSC_IDIE_SHIFT (24U)
39776 #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
39777 #define USB_OTGSC_AVVIE_MASK (0x2000000U)
39778 #define USB_OTGSC_AVVIE_SHIFT (25U)
39779 #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
39780 #define USB_OTGSC_ASVIE_MASK (0x4000000U)
39781 #define USB_OTGSC_ASVIE_SHIFT (26U)
39782 #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
39783 #define USB_OTGSC_BSVIE_MASK (0x8000000U)
39784 #define USB_OTGSC_BSVIE_SHIFT (27U)
39785 #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
39786 #define USB_OTGSC_BSEIE_MASK (0x10000000U)
39787 #define USB_OTGSC_BSEIE_SHIFT (28U)
39788 #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
39789 #define USB_OTGSC_EN_1MS_MASK (0x20000000U)
39790 #define USB_OTGSC_EN_1MS_SHIFT (29U)
39791 #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
39792 #define USB_OTGSC_DPIE_MASK (0x40000000U)
39793 #define USB_OTGSC_DPIE_SHIFT (30U)
39794 #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
39795 
39799 #define USB_USBMODE_CM_MASK (0x3U)
39800 #define USB_USBMODE_CM_SHIFT (0U)
39801 
39807 #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
39808 #define USB_USBMODE_ES_MASK (0x4U)
39809 #define USB_USBMODE_ES_SHIFT (2U)
39810 
39814 #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
39815 #define USB_USBMODE_SLOM_MASK (0x8U)
39816 #define USB_USBMODE_SLOM_SHIFT (3U)
39817 
39821 #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
39822 #define USB_USBMODE_SDIS_MASK (0x10U)
39823 #define USB_USBMODE_SDIS_SHIFT (4U)
39824 #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
39825 
39829 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
39830 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
39831 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
39832 
39836 #define USB_ENDPTPRIME_PERB_MASK (0xFFU)
39837 #define USB_ENDPTPRIME_PERB_SHIFT (0U)
39838 #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
39839 #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
39840 #define USB_ENDPTPRIME_PETB_SHIFT (16U)
39841 #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
39842 
39846 #define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
39847 #define USB_ENDPTFLUSH_FERB_SHIFT (0U)
39848 #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
39849 #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
39850 #define USB_ENDPTFLUSH_FETB_SHIFT (16U)
39851 #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
39852 
39856 #define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
39857 #define USB_ENDPTSTAT_ERBR_SHIFT (0U)
39858 #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
39859 #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
39860 #define USB_ENDPTSTAT_ETBR_SHIFT (16U)
39861 #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
39862 
39866 #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
39867 #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
39868 #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
39869 #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
39870 #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
39871 #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
39872 
39876 #define USB_ENDPTCTRL0_RXS_MASK (0x1U)
39877 #define USB_ENDPTCTRL0_RXS_SHIFT (0U)
39878 #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
39879 #define USB_ENDPTCTRL0_RXT_MASK (0xCU)
39880 #define USB_ENDPTCTRL0_RXT_SHIFT (2U)
39881 #define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
39882 #define USB_ENDPTCTRL0_RXE_MASK (0x80U)
39883 #define USB_ENDPTCTRL0_RXE_SHIFT (7U)
39884 #define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
39885 #define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
39886 #define USB_ENDPTCTRL0_TXS_SHIFT (16U)
39887 #define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
39888 #define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
39889 #define USB_ENDPTCTRL0_TXT_SHIFT (18U)
39890 #define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
39891 #define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
39892 #define USB_ENDPTCTRL0_TXE_SHIFT (23U)
39893 #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
39894 
39898 #define USB_ENDPTCTRL_RXS_MASK (0x1U)
39899 #define USB_ENDPTCTRL_RXS_SHIFT (0U)
39900 #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
39901 #define USB_ENDPTCTRL_RXD_MASK (0x2U)
39902 #define USB_ENDPTCTRL_RXD_SHIFT (1U)
39903 #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
39904 #define USB_ENDPTCTRL_RXT_MASK (0xCU)
39905 #define USB_ENDPTCTRL_RXT_SHIFT (2U)
39906 #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
39907 #define USB_ENDPTCTRL_RXI_MASK (0x20U)
39908 #define USB_ENDPTCTRL_RXI_SHIFT (5U)
39909 #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
39910 #define USB_ENDPTCTRL_RXR_MASK (0x40U)
39911 #define USB_ENDPTCTRL_RXR_SHIFT (6U)
39912 #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
39913 #define USB_ENDPTCTRL_RXE_MASK (0x80U)
39914 #define USB_ENDPTCTRL_RXE_SHIFT (7U)
39915 #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
39916 #define USB_ENDPTCTRL_TXS_MASK (0x10000U)
39917 #define USB_ENDPTCTRL_TXS_SHIFT (16U)
39918 #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
39919 #define USB_ENDPTCTRL_TXD_MASK (0x20000U)
39920 #define USB_ENDPTCTRL_TXD_SHIFT (17U)
39921 #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
39922 #define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
39923 #define USB_ENDPTCTRL_TXT_SHIFT (18U)
39924 #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
39925 #define USB_ENDPTCTRL_TXI_MASK (0x200000U)
39926 #define USB_ENDPTCTRL_TXI_SHIFT (21U)
39927 #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
39928 #define USB_ENDPTCTRL_TXR_MASK (0x400000U)
39929 #define USB_ENDPTCTRL_TXR_SHIFT (22U)
39930 #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
39931 #define USB_ENDPTCTRL_TXE_MASK (0x800000U)
39932 #define USB_ENDPTCTRL_TXE_SHIFT (23U)
39933 #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
39934 
39936 /* The count of USB_ENDPTCTRL */
39937 #define USB_ENDPTCTRL_COUNT (7U)
39938 
39939  /* end of group USB_Register_Masks */
39943 
39944 
39945 /* USB - Peripheral instance base addresses */
39947 #define USB1_BASE (0x402E0000u)
39948 
39949 #define USB1 ((USB_Type *)USB1_BASE)
39950 
39951 #define USB2_BASE (0x402E0200u)
39952 
39953 #define USB2 ((USB_Type *)USB2_BASE)
39954 
39955 #define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }
39956 
39957 #define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }
39958 
39959 #define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
39960 /* Backward compatibility */
39961 #define GPTIMER0CTL GPTIMER0CTRL
39962 #define GPTIMER1CTL GPTIMER1CTRL
39963 #define USB_SBUSCFG SBUSCFG
39964 #define EPLISTADDR ENDPTLISTADDR
39965 #define EPSETUPSR ENDPTSETUPSTAT
39966 #define EPPRIME ENDPTPRIME
39967 #define EPFLUSH ENDPTFLUSH
39968 #define EPSR ENDPTSTAT
39969 #define EPCOMPLETE ENDPTCOMPLETE
39970 #define EPCR ENDPTCTRL
39971 #define EPCR0 ENDPTCTRL0
39972 #define USBHS_ID_ID_MASK USB_ID_ID_MASK
39973 #define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
39974 #define USBHS_ID_ID(x) USB_ID_ID(x)
39975 #define USBHS_ID_NID_MASK USB_ID_NID_MASK
39976 #define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
39977 #define USBHS_ID_NID(x) USB_ID_NID(x)
39978 #define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
39979 #define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
39980 #define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
39981 #define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
39982 #define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
39983 #define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
39984 #define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
39985 #define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
39986 #define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
39987 #define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
39988 #define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
39989 #define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
39990 #define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
39991 #define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
39992 #define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
39993 #define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
39994 #define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
39995 #define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
39996 #define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
39997 #define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
39998 #define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
39999 #define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
40000 #define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
40001 #define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
40002 #define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
40003 #define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
40004 #define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
40005 #define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
40006 #define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
40007 #define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
40008 #define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
40009 #define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
40010 #define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
40011 #define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
40012 #define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
40013 #define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
40014 #define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
40015 #define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
40016 #define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
40017 #define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
40018 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
40019 #define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
40020 #define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
40021 #define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
40022 #define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
40023 #define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
40024 #define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
40025 #define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
40026 #define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
40027 #define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
40028 #define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
40029 #define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
40030 #define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
40031 #define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
40032 #define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
40033 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
40034 #define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
40035 #define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
40036 #define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
40037 #define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
40038 #define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
40039 #define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
40040 #define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
40041 #define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
40042 #define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
40043 #define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
40044 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
40045 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
40046 #define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
40047 #define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
40048 #define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
40049 #define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
40050 #define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
40051 #define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
40052 #define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
40053 #define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
40054 #define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
40055 #define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
40056 #define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
40057 #define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
40058 #define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
40059 #define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
40060 #define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
40061 #define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
40062 #define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
40063 #define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
40064 #define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
40065 #define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
40066 #define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
40067 #define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
40068 #define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
40069 #define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
40070 #define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
40071 #define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
40072 #define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
40073 #define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
40074 #define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
40075 #define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
40076 #define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
40077 #define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
40078 #define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
40079 #define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
40080 #define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
40081 #define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
40082 #define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
40083 #define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
40084 #define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
40085 #define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
40086 #define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
40087 #define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
40088 #define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
40089 #define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
40090 #define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
40091 #define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
40092 #define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
40093 #define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
40094 #define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
40095 #define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
40096 #define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
40097 #define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
40098 #define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
40099 #define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
40100 #define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
40101 #define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
40102 #define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
40103 #define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
40104 #define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
40105 #define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
40106 #define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
40107 #define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
40108 #define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
40109 #define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
40110 #define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
40111 #define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
40112 #define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
40113 #define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
40114 #define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
40115 #define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
40116 #define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
40117 #define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
40118 #define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
40119 #define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
40120 #define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
40121 #define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
40122 #define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
40123 #define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
40124 #define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
40125 #define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
40126 #define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
40127 #define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
40128 #define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
40129 #define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
40130 #define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
40131 #define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
40132 #define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
40133 #define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
40134 #define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
40135 #define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
40136 #define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
40137 #define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
40138 #define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
40139 #define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
40140 #define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
40141 #define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
40142 #define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
40143 #define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
40144 #define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
40145 #define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
40146 #define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
40147 #define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
40148 #define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
40149 #define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
40150 #define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
40151 #define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
40152 #define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
40153 #define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
40154 #define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
40155 #define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
40156 #define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
40157 #define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
40158 #define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
40159 #define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
40160 #define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
40161 #define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
40162 #define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
40163 #define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
40164 #define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
40165 #define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
40166 #define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
40167 #define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
40168 #define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
40169 #define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
40170 #define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
40171 #define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
40172 #define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
40173 #define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
40174 #define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
40175 #define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
40176 #define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
40177 #define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
40178 #define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
40179 #define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
40180 #define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
40181 #define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
40182 #define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
40183 #define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
40184 #define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
40185 #define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
40186 #define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
40187 #define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
40188 #define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
40189 #define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
40190 #define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
40191 #define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
40192 #define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
40193 #define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
40194 #define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
40195 #define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
40196 #define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
40197 #define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
40198 #define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
40199 #define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
40200 #define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
40201 #define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
40202 #define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
40203 #define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
40204 #define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
40205 #define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
40206 #define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
40207 #define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
40208 #define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
40209 #define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
40210 #define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
40211 #define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
40212 #define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
40213 #define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
40214 #define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
40215 #define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
40216 #define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
40217 #define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
40218 #define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
40219 #define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
40220 #define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
40221 #define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
40222 #define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
40223 #define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
40224 #define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
40225 #define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
40226 #define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
40227 #define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
40228 #define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
40229 #define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
40230 #define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
40231 #define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
40232 #define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
40233 #define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
40234 #define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
40235 #define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
40236 #define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
40237 #define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
40238 #define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
40239 #define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
40240 #define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
40241 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
40242 #define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
40243 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
40244 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
40245 #define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
40246 #define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
40247 #define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
40248 #define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
40249 #define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
40250 #define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
40251 #define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
40252 #define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
40253 #define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
40254 #define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
40255 #define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
40256 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
40257 #define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
40258 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
40259 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
40260 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
40261 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
40262 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
40263 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
40264 #define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
40265 #define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
40266 #define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
40267 #define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
40268 #define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
40269 #define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
40270 #define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
40271 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
40272 #define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
40273 #define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
40274 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
40275 #define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
40276 #define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
40277 #define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
40278 #define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
40279 #define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
40280 #define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
40281 #define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
40282 #define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
40283 #define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
40284 #define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
40285 #define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
40286 #define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
40287 #define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
40288 #define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
40289 #define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
40290 #define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
40291 #define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
40292 #define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
40293 #define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
40294 #define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
40295 #define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
40296 #define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
40297 #define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
40298 #define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
40299 #define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
40300 #define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
40301 #define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
40302 #define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
40303 #define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
40304 #define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
40305 #define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
40306 #define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
40307 #define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
40308 #define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
40309 #define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
40310 #define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
40311 #define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
40312 #define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
40313 #define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
40314 #define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
40315 #define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
40316 #define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
40317 #define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
40318 #define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
40319 #define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
40320 #define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
40321 #define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
40322 #define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
40323 #define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
40324 #define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
40325 #define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
40326 #define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
40327 #define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
40328 #define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
40329 #define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
40330 #define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
40331 #define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
40332 #define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
40333 #define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
40334 #define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
40335 #define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
40336 #define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
40337 #define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
40338 #define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
40339 #define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
40340 #define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
40341 #define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
40342 #define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
40343 #define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
40344 #define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
40345 #define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
40346 #define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
40347 #define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
40348 #define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
40349 #define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
40350 #define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
40351 #define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
40352 #define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
40353 #define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
40354 #define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
40355 #define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
40356 #define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
40357 #define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
40358 #define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
40359 #define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
40360 #define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
40361 #define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
40362 #define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
40363 #define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
40364 #define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
40365 #define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
40366 #define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
40367 #define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
40368 #define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
40369 #define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
40370 #define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
40371 #define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
40372 #define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
40373 #define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
40374 #define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
40375 #define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
40376 #define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
40377 #define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
40378 #define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
40379 #define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
40380 #define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
40381 #define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
40382 #define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
40383 #define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
40384 #define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
40385 #define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
40386 #define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
40387 #define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
40388 #define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
40389 #define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
40390 #define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
40391 #define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
40392 #define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
40393 #define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
40394 #define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
40395 #define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
40396 #define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
40397 #define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
40398 #define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
40399 #define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
40400 #define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
40401 #define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
40402 #define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
40403 #define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
40404 #define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
40405 #define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
40406 #define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
40407 #define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
40408 #define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
40409 #define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
40410 #define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
40411 #define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
40412 #define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
40413 #define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
40414 #define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
40415 #define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
40416 #define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
40417 #define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
40418 #define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
40419 #define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
40420 #define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
40421 #define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
40422 #define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
40423 #define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
40424 #define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
40425 #define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
40426 #define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
40427 #define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
40428 #define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
40429 #define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
40430 #define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
40431 #define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
40432 #define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
40433 #define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
40434 #define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
40435 #define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
40436 #define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
40437 #define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
40438 #define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
40439 #define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
40440 #define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
40441 #define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
40442 #define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
40443 #define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
40444 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
40445 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
40446 #define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
40447 #define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
40448 #define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
40449 #define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
40450 #define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
40451 #define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
40452 #define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
40453 #define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
40454 #define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
40455 #define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
40456 #define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
40457 #define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
40458 #define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
40459 #define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
40460 #define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
40461 #define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
40462 #define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
40463 #define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
40464 #define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
40465 #define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
40466 #define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
40467 #define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
40468 #define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
40469 #define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
40470 #define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
40471 #define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
40472 #define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
40473 #define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
40474 #define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
40475 #define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
40476 #define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
40477 #define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
40478 #define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
40479 #define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
40480 #define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
40481 #define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
40482 #define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
40483 #define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
40484 #define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
40485 #define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
40486 #define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
40487 #define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
40488 #define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
40489 #define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
40490 #define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
40491 #define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
40492 #define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
40493 #define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
40494 #define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
40495 #define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
40496 #define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
40497 #define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
40498 #define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
40499 #define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
40500 #define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
40501 #define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
40502 #define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
40503 #define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
40504 #define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
40505 #define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
40506 #define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
40507 #define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
40508 #define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
40509 #define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
40510 #define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
40511 #define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
40512 #define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
40513 #define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
40514 #define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
40515 #define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
40516 #define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
40517 #define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
40518 #define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
40519 #define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
40520 #define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
40521 #define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
40522 #define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
40523 #define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
40524 #define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
40525 #define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
40526 #define USBHS_Type USB_Type
40527 #define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }
40528 #define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
40529 #define USBHS_IRQHandler USB_OTG1_IRQHandler
40530 
40531  /* end of group USB_Peripheral_Access_Layer */
40535 
40536 
40537 /* ----------------------------------------------------------------------------
40538  -- USBNC Peripheral Access Layer
40539  ---------------------------------------------------------------------------- */
40540 
40547 typedef struct {
40548  uint8_t RESERVED_0[2048];
40549  __IO uint32_t USB_OTGn_CTRL;
40550  uint8_t RESERVED_1[20];
40551  __IO uint32_t USB_OTGn_PHY_CTRL_0;
40552 } USBNC_Type;
40553 
40554 /* ----------------------------------------------------------------------------
40555  -- USBNC Register Masks
40556  ---------------------------------------------------------------------------- */
40557 
40565 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
40566 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
40567 
40571 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
40572 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
40573 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
40574 
40578 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
40579 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
40580 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
40581 
40585 #define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
40586 #define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
40587 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
40588 
40592 #define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
40593 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
40594 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
40595 
40599 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
40600 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
40601 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
40602 
40606 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
40607 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
40608 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
40609 
40613 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
40614 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
40615 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
40616 
40620 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
40621 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
40622 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
40623 
40627 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
40628 #define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
40629 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
40630 
40634 #define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
40635 
40639 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
40640 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
40641 
40645 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
40646  /* end of group USBNC_Register_Masks */
40652 
40653 
40654 /* USBNC - Peripheral instance base addresses */
40656 #define USBNC1_BASE (0x402E0000u)
40657 
40658 #define USBNC1 ((USBNC_Type *)USBNC1_BASE)
40659 
40660 #define USBNC2_BASE (0x402E0004u)
40661 
40662 #define USBNC2 ((USBNC_Type *)USBNC2_BASE)
40663 
40664 #define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }
40665 
40666 #define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }
40667  /* end of group USBNC_Peripheral_Access_Layer */
40671 
40672 
40673 /* ----------------------------------------------------------------------------
40674  -- USBPHY Peripheral Access Layer
40675  ---------------------------------------------------------------------------- */
40676 
40683 typedef struct {
40684  __IO uint32_t PWD;
40685  __IO uint32_t PWD_SET;
40686  __IO uint32_t PWD_CLR;
40687  __IO uint32_t PWD_TOG;
40688  __IO uint32_t TX;
40689  __IO uint32_t TX_SET;
40690  __IO uint32_t TX_CLR;
40691  __IO uint32_t TX_TOG;
40692  __IO uint32_t RX;
40693  __IO uint32_t RX_SET;
40694  __IO uint32_t RX_CLR;
40695  __IO uint32_t RX_TOG;
40696  __IO uint32_t CTRL;
40697  __IO uint32_t CTRL_SET;
40698  __IO uint32_t CTRL_CLR;
40699  __IO uint32_t CTRL_TOG;
40700  __IO uint32_t STATUS;
40701  uint8_t RESERVED_0[12];
40702  __IO uint32_t DEBUGr;
40703  __IO uint32_t DEBUG_SET;
40704  __IO uint32_t DEBUG_CLR;
40705  __IO uint32_t DEBUG_TOG;
40706  __I uint32_t DEBUG0_STATUS;
40707  uint8_t RESERVED_1[12];
40708  __IO uint32_t DEBUG1;
40709  __IO uint32_t DEBUG1_SET;
40710  __IO uint32_t DEBUG1_CLR;
40711  __IO uint32_t DEBUG1_TOG;
40712  __I uint32_t VERSION;
40713 } USBPHY_Type;
40714 
40715 /* ----------------------------------------------------------------------------
40716  -- USBPHY Register Masks
40717  ---------------------------------------------------------------------------- */
40718 
40726 #define USBPHY_PWD_RSVD0_MASK (0x3FFU)
40727 #define USBPHY_PWD_RSVD0_SHIFT (0U)
40728 #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
40729 #define USBPHY_PWD_TXPWDFS_MASK (0x400U)
40730 #define USBPHY_PWD_TXPWDFS_SHIFT (10U)
40731 #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
40732 #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
40733 #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
40734 #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
40735 #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
40736 #define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
40737 #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
40738 #define USBPHY_PWD_RSVD1_MASK (0x1E000U)
40739 #define USBPHY_PWD_RSVD1_SHIFT (13U)
40740 #define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
40741 #define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
40742 #define USBPHY_PWD_RXPWDENV_SHIFT (17U)
40743 #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
40744 #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
40745 #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
40746 #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
40747 #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
40748 #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
40749 #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
40750 #define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
40751 #define USBPHY_PWD_RXPWDRX_SHIFT (20U)
40752 #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
40753 #define USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
40754 #define USBPHY_PWD_RSVD2_SHIFT (21U)
40755 #define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
40756 
40760 #define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
40761 #define USBPHY_PWD_SET_RSVD0_SHIFT (0U)
40762 #define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
40763 #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
40764 #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
40765 #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
40766 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
40767 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
40768 #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
40769 #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
40770 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
40771 #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
40772 #define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
40773 #define USBPHY_PWD_SET_RSVD1_SHIFT (13U)
40774 #define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
40775 #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
40776 #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
40777 #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
40778 #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
40779 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
40780 #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
40781 #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
40782 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
40783 #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
40784 #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
40785 #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
40786 #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
40787 #define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
40788 #define USBPHY_PWD_SET_RSVD2_SHIFT (21U)
40789 #define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
40790 
40794 #define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
40795 #define USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
40796 #define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
40797 #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
40798 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
40799 #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
40800 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
40801 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
40802 #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
40803 #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
40804 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
40805 #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
40806 #define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
40807 #define USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
40808 #define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
40809 #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
40810 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
40811 #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
40812 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
40813 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
40814 #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
40815 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
40816 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
40817 #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
40818 #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
40819 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
40820 #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
40821 #define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
40822 #define USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
40823 #define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
40824 
40828 #define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
40829 #define USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
40830 #define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
40831 #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
40832 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
40833 #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
40834 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
40835 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
40836 #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
40837 #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
40838 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
40839 #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
40840 #define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
40841 #define USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
40842 #define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
40843 #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
40844 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
40845 #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
40846 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
40847 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
40848 #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
40849 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
40850 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
40851 #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
40852 #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
40853 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
40854 #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
40855 #define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
40856 #define USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
40857 #define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
40858 
40862 #define USBPHY_TX_D_CAL_MASK (0xFU)
40863 #define USBPHY_TX_D_CAL_SHIFT (0U)
40864 #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
40865 #define USBPHY_TX_RSVD0_MASK (0xF0U)
40866 #define USBPHY_TX_RSVD0_SHIFT (4U)
40867 #define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
40868 #define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
40869 #define USBPHY_TX_TXCAL45DN_SHIFT (8U)
40870 #define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
40871 #define USBPHY_TX_RSVD1_MASK (0xF000U)
40872 #define USBPHY_TX_RSVD1_SHIFT (12U)
40873 #define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
40874 #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
40875 #define USBPHY_TX_TXCAL45DP_SHIFT (16U)
40876 #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
40877 #define USBPHY_TX_RSVD2_MASK (0x3F00000U)
40878 #define USBPHY_TX_RSVD2_SHIFT (20U)
40879 #define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
40880 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
40881 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
40882 #define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
40883 #define USBPHY_TX_RSVD5_MASK (0xE0000000U)
40884 #define USBPHY_TX_RSVD5_SHIFT (29U)
40885 #define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
40886 
40890 #define USBPHY_TX_SET_D_CAL_MASK (0xFU)
40891 #define USBPHY_TX_SET_D_CAL_SHIFT (0U)
40892 #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
40893 #define USBPHY_TX_SET_RSVD0_MASK (0xF0U)
40894 #define USBPHY_TX_SET_RSVD0_SHIFT (4U)
40895 #define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
40896 #define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
40897 #define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
40898 #define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
40899 #define USBPHY_TX_SET_RSVD1_MASK (0xF000U)
40900 #define USBPHY_TX_SET_RSVD1_SHIFT (12U)
40901 #define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
40902 #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
40903 #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
40904 #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
40905 #define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
40906 #define USBPHY_TX_SET_RSVD2_SHIFT (20U)
40907 #define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
40908 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
40909 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
40910 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
40911 #define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
40912 #define USBPHY_TX_SET_RSVD5_SHIFT (29U)
40913 #define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
40914 
40918 #define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
40919 #define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
40920 #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
40921 #define USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
40922 #define USBPHY_TX_CLR_RSVD0_SHIFT (4U)
40923 #define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
40924 #define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
40925 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
40926 #define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
40927 #define USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
40928 #define USBPHY_TX_CLR_RSVD1_SHIFT (12U)
40929 #define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
40930 #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
40931 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
40932 #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
40933 #define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
40934 #define USBPHY_TX_CLR_RSVD2_SHIFT (20U)
40935 #define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
40936 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
40937 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
40938 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
40939 #define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
40940 #define USBPHY_TX_CLR_RSVD5_SHIFT (29U)
40941 #define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
40942 
40946 #define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
40947 #define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
40948 #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
40949 #define USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
40950 #define USBPHY_TX_TOG_RSVD0_SHIFT (4U)
40951 #define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
40952 #define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
40953 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
40954 #define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
40955 #define USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
40956 #define USBPHY_TX_TOG_RSVD1_SHIFT (12U)
40957 #define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
40958 #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
40959 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
40960 #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
40961 #define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
40962 #define USBPHY_TX_TOG_RSVD2_SHIFT (20U)
40963 #define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
40964 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
40965 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
40966 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
40967 #define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
40968 #define USBPHY_TX_TOG_RSVD5_SHIFT (29U)
40969 #define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
40970 
40974 #define USBPHY_RX_ENVADJ_MASK (0x7U)
40975 #define USBPHY_RX_ENVADJ_SHIFT (0U)
40976 #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
40977 #define USBPHY_RX_RSVD0_MASK (0x8U)
40978 #define USBPHY_RX_RSVD0_SHIFT (3U)
40979 #define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
40980 #define USBPHY_RX_DISCONADJ_MASK (0x70U)
40981 #define USBPHY_RX_DISCONADJ_SHIFT (4U)
40982 #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
40983 #define USBPHY_RX_RSVD1_MASK (0x3FFF80U)
40984 #define USBPHY_RX_RSVD1_SHIFT (7U)
40985 #define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
40986 #define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
40987 #define USBPHY_RX_RXDBYPASS_SHIFT (22U)
40988 #define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
40989 #define USBPHY_RX_RSVD2_MASK (0xFF800000U)
40990 #define USBPHY_RX_RSVD2_SHIFT (23U)
40991 #define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
40992 
40996 #define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
40997 #define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
40998 #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
40999 #define USBPHY_RX_SET_RSVD0_MASK (0x8U)
41000 #define USBPHY_RX_SET_RSVD0_SHIFT (3U)
41001 #define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
41002 #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
41003 #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
41004 #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
41005 #define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
41006 #define USBPHY_RX_SET_RSVD1_SHIFT (7U)
41007 #define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
41008 #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
41009 #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
41010 #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
41011 #define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
41012 #define USBPHY_RX_SET_RSVD2_SHIFT (23U)
41013 #define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
41014 
41018 #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
41019 #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
41020 #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
41021 #define USBPHY_RX_CLR_RSVD0_MASK (0x8U)
41022 #define USBPHY_RX_CLR_RSVD0_SHIFT (3U)
41023 #define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
41024 #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
41025 #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
41026 #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
41027 #define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
41028 #define USBPHY_RX_CLR_RSVD1_SHIFT (7U)
41029 #define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
41030 #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
41031 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
41032 #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
41033 #define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
41034 #define USBPHY_RX_CLR_RSVD2_SHIFT (23U)
41035 #define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
41036 
41040 #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
41041 #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
41042 #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
41043 #define USBPHY_RX_TOG_RSVD0_MASK (0x8U)
41044 #define USBPHY_RX_TOG_RSVD0_SHIFT (3U)
41045 #define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
41046 #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
41047 #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
41048 #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
41049 #define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
41050 #define USBPHY_RX_TOG_RSVD1_SHIFT (7U)
41051 #define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
41052 #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
41053 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
41054 #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
41055 #define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
41056 #define USBPHY_RX_TOG_RSVD2_SHIFT (23U)
41057 #define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
41058 
41062 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
41063 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
41064 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
41065 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
41066 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
41067 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
41068 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
41069 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
41070 #define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
41071 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
41072 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
41073 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
41074 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
41075 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
41076 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
41077 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
41078 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
41079 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
41080 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
41081 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
41082 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
41083 #define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
41084 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
41085 #define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
41086 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
41087 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
41088 #define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
41089 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
41090 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
41091 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
41092 #define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
41093 #define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
41094 #define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
41095 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
41096 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
41097 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
41098 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
41099 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
41100 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
41101 #define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
41102 #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
41103 #define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
41104 #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
41105 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
41106 #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
41107 #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
41108 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
41109 #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
41110 #define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
41111 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
41112 #define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
41113 #define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
41114 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
41115 #define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
41116 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
41117 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
41118 #define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
41119 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
41120 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
41121 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
41122 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
41123 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
41124 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
41125 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
41126 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
41127 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
41128 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
41129 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
41130 #define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
41131 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
41132 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
41133 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
41134 #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
41135 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
41136 #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
41137 #define USBPHY_CTRL_RSVD1_MASK (0x6000000U)
41138 #define USBPHY_CTRL_RSVD1_SHIFT (25U)
41139 #define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
41140 #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
41141 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
41142 #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
41143 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
41144 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
41145 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
41146 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
41147 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
41148 #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
41149 #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
41150 #define USBPHY_CTRL_CLKGATE_SHIFT (30U)
41151 #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
41152 #define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
41153 #define USBPHY_CTRL_SFTRST_SHIFT (31U)
41154 #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
41155 
41159 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
41160 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
41161 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
41162 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
41163 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
41164 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
41165 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
41166 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
41167 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
41168 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
41169 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
41170 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
41171 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
41172 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
41173 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
41174 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
41175 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
41176 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
41177 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
41178 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
41179 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
41180 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
41181 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
41182 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
41183 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
41184 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
41185 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
41186 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
41187 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
41188 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
41189 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
41190 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
41191 #define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
41192 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
41193 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
41194 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
41195 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
41196 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
41197 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
41198 #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
41199 #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
41200 #define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
41201 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
41202 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
41203 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
41204 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
41205 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
41206 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
41207 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
41208 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
41209 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
41210 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
41211 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
41212 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
41213 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
41214 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
41215 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
41216 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
41217 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
41218 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
41219 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
41220 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
41221 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
41222 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
41223 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
41224 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
41225 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
41226 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
41227 #define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
41228 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
41229 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
41230 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
41231 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
41232 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
41233 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
41234 #define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
41235 #define USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
41236 #define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
41237 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
41238 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
41239 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
41240 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
41241 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
41242 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
41243 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
41244 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
41245 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
41246 #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
41247 #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
41248 #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
41249 #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
41250 #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
41251 #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
41252 
41256 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
41257 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
41258 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
41259 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
41260 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
41261 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
41262 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
41263 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
41264 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
41265 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
41266 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
41267 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
41268 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
41269 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
41270 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
41271 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
41272 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
41273 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
41274 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
41275 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
41276 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
41277 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
41278 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
41279 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
41280 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
41281 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
41282 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
41283 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
41284 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
41285 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
41286 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
41287 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
41288 #define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
41289 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
41290 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
41291 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
41292 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
41293 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
41294 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
41295 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
41296 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
41297 #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
41298 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
41299 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
41300 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
41301 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
41302 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
41303 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
41304 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
41305 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
41306 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
41307 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
41308 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
41309 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
41310 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
41311 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
41312 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
41313 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
41314 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
41315 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
41316 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
41317 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
41318 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
41319 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
41320 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
41321 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
41322 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
41323 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
41324 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
41325 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
41326 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
41327 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
41328 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
41329 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
41330 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
41331 #define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
41332 #define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
41333 #define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
41334 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
41335 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
41336 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
41337 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
41338 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
41339 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
41340 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
41341 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
41342 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
41343 #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
41344 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
41345 #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
41346 #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
41347 #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
41348 #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
41349 
41353 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
41354 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
41355 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
41356 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
41357 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
41358 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
41359 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
41360 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
41361 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
41362 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
41363 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
41364 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
41365 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
41366 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
41367 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
41368 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
41369 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
41370 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
41371 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
41372 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
41373 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
41374 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
41375 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
41376 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
41377 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
41378 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
41379 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
41380 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
41381 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
41382 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
41383 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
41384 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
41385 #define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
41386 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
41387 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
41388 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
41389 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
41390 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
41391 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
41392 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
41393 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
41394 #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
41395 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
41396 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
41397 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
41398 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
41399 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
41400 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
41401 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
41402 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
41403 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
41404 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
41405 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
41406 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
41407 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
41408 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
41409 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
41410 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
41411 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
41412 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
41413 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
41414 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
41415 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
41416 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
41417 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
41418 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
41419 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
41420 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
41421 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
41422 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
41423 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
41424 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
41425 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
41426 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
41427 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
41428 #define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
41429 #define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
41430 #define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
41431 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
41432 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
41433 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
41434 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
41435 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
41436 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
41437 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
41438 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
41439 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
41440 #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
41441 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
41442 #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
41443 #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
41444 #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
41445 #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
41446 
41450 #define USBPHY_STATUS_RSVD0_MASK (0x7U)
41451 #define USBPHY_STATUS_RSVD0_SHIFT (0U)
41452 #define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
41453 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
41454 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
41455 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
41456 #define USBPHY_STATUS_RSVD1_MASK (0x30U)
41457 #define USBPHY_STATUS_RSVD1_SHIFT (4U)
41458 #define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
41459 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
41460 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
41461 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
41462 #define USBPHY_STATUS_RSVD2_MASK (0x80U)
41463 #define USBPHY_STATUS_RSVD2_SHIFT (7U)
41464 #define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
41465 #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
41466 #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
41467 #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
41468 #define USBPHY_STATUS_RSVD3_MASK (0x200U)
41469 #define USBPHY_STATUS_RSVD3_SHIFT (9U)
41470 #define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
41471 #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
41472 #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
41473 #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
41474 #define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
41475 #define USBPHY_STATUS_RSVD4_SHIFT (11U)
41476 #define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
41477 
41481 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
41482 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
41483 #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
41484 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
41485 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
41486 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
41487 #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
41488 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
41489 #define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
41490 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
41491 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
41492 #define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
41493 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U)
41494 #define USBPHY_DEBUG_RSVD0_SHIFT (6U)
41495 #define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
41496 #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
41497 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
41498 #define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
41499 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
41500 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
41501 #define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
41502 #define USBPHY_DEBUG_RSVD1_MASK (0xE000U)
41503 #define USBPHY_DEBUG_RSVD1_SHIFT (13U)
41504 #define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
41505 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
41506 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
41507 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
41508 #define USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
41509 #define USBPHY_DEBUG_RSVD2_SHIFT (21U)
41510 #define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
41511 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
41512 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
41513 #define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
41514 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
41515 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
41516 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
41517 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
41518 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
41519 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
41520 #define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
41521 #define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
41522 #define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
41523 #define USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
41524 #define USBPHY_DEBUG_RSVD3_SHIFT (31U)
41525 #define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
41526 
41530 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
41531 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
41532 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
41533 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
41534 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
41535 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
41536 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
41537 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
41538 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
41539 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
41540 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
41541 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
41542 #define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
41543 #define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
41544 #define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
41545 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
41546 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
41547 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
41548 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
41549 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
41550 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
41551 #define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
41552 #define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
41553 #define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
41554 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
41555 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
41556 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
41557 #define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
41558 #define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
41559 #define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
41560 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
41561 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
41562 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
41563 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
41564 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
41565 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
41566 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
41567 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
41568 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
41569 #define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
41570 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
41571 #define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
41572 #define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
41573 #define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
41574 #define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
41575 
41579 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
41580 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
41581 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
41582 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
41583 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
41584 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
41585 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
41586 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
41587 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
41588 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
41589 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
41590 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
41591 #define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
41592 #define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
41593 #define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
41594 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
41595 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
41596 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
41597 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
41598 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
41599 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
41600 #define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
41601 #define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
41602 #define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
41603 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
41604 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
41605 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
41606 #define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
41607 #define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
41608 #define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
41609 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
41610 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
41611 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
41612 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
41613 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
41614 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
41615 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
41616 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
41617 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
41618 #define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
41619 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
41620 #define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
41621 #define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
41622 #define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
41623 #define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
41624 
41628 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
41629 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
41630 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
41631 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
41632 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
41633 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
41634 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
41635 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
41636 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
41637 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
41638 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
41639 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
41640 #define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
41641 #define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
41642 #define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
41643 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
41644 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
41645 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
41646 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
41647 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
41648 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
41649 #define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
41650 #define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
41651 #define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
41652 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
41653 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
41654 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
41655 #define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
41656 #define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
41657 #define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
41658 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
41659 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
41660 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
41661 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
41662 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
41663 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
41664 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
41665 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
41666 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
41667 #define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
41668 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
41669 #define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
41670 #define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
41671 #define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
41672 #define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
41673 
41677 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
41678 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
41679 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
41680 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
41681 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
41682 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
41683 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
41684 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
41685 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
41686 
41690 #define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
41691 #define USBPHY_DEBUG1_RSVD0_SHIFT (0U)
41692 #define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
41693 #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
41694 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
41695 #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
41696 #define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
41697 #define USBPHY_DEBUG1_RSVD1_SHIFT (15U)
41698 #define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
41699 
41703 #define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
41704 #define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
41705 #define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
41706 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
41707 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
41708 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
41709 #define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
41710 #define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
41711 #define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
41712 
41716 #define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
41717 #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
41718 #define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
41719 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
41720 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
41721 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
41722 #define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
41723 #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
41724 #define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
41725 
41729 #define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
41730 #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
41731 #define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
41732 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
41733 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
41734 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
41735 #define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
41736 #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
41737 #define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
41738 
41742 #define USBPHY_VERSION_STEP_MASK (0xFFFFU)
41743 #define USBPHY_VERSION_STEP_SHIFT (0U)
41744 #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
41745 #define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
41746 #define USBPHY_VERSION_MINOR_SHIFT (16U)
41747 #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
41748 #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
41749 #define USBPHY_VERSION_MAJOR_SHIFT (24U)
41750 #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
41751  /* end of group USBPHY_Register_Masks */
41757 
41758 
41759 /* USBPHY - Peripheral instance base addresses */
41761 #define USBPHY1_BASE (0x400D9000u)
41762 
41763 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
41764 
41765 #define USBPHY2_BASE (0x400DA000u)
41766 
41767 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
41768 
41769 #define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
41770 
41771 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
41772 
41773 #define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
41774 /* Backward compatibility */
41775 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
41776 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
41777 #define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
41778 #define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
41779 #define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
41780 #define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
41781 
41782  /* end of group USBPHY_Peripheral_Access_Layer */
41786 
41787 
41788 /* ----------------------------------------------------------------------------
41789  -- USB_ANALOG Peripheral Access Layer
41790  ---------------------------------------------------------------------------- */
41791 
41798 typedef struct {
41799  uint8_t RESERVED_0[416];
41800  struct { /* offset: 0x1A0, array step: 0x60 */
41801  __IO uint32_t VBUS_DETECT;
41802  __IO uint32_t VBUS_DETECT_SET;
41803  __IO uint32_t VBUS_DETECT_CLR;
41804  __IO uint32_t VBUS_DETECT_TOG;
41805  __IO uint32_t CHRG_DETECT;
41806  __IO uint32_t CHRG_DETECT_SET;
41807  __IO uint32_t CHRG_DETECT_CLR;
41808  __IO uint32_t CHRG_DETECT_TOG;
41809  __I uint32_t VBUS_DETECT_STAT;
41810  uint8_t RESERVED_0[12];
41811  __I uint32_t CHRG_DETECT_STAT;
41812  uint8_t RESERVED_1[12];
41813  __IO uint32_t LOOPBACK;
41814  __IO uint32_t LOOPBACK_SET;
41815  __IO uint32_t LOOPBACK_CLR;
41816  __IO uint32_t LOOPBACK_TOG;
41817  __IO uint32_t MISC;
41818  __IO uint32_t MISC_SET;
41819  __IO uint32_t MISC_CLR;
41820  __IO uint32_t MISC_TOG;
41821  } INSTANCE[2];
41822  __I uint32_t DIGPROG;
41823 } USB_ANALOG_Type;
41824 
41825 /* ----------------------------------------------------------------------------
41826  -- USB_ANALOG Register Masks
41827  ---------------------------------------------------------------------------- */
41828 
41836 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
41837 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
41838 
41848 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
41849 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
41850 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
41851 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
41852 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
41853 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
41854 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
41855 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
41856 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
41857 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
41858 
41860 /* The count of USB_ANALOG_VBUS_DETECT */
41861 #define USB_ANALOG_VBUS_DETECT_COUNT (2U)
41862 
41865 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
41866 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
41867 
41877 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
41878 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
41879 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
41880 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
41881 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
41882 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
41883 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
41884 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
41885 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
41886 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
41887 
41889 /* The count of USB_ANALOG_VBUS_DETECT_SET */
41890 #define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)
41891 
41894 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
41895 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
41896 
41906 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
41907 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
41908 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
41909 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
41910 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
41911 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
41912 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
41913 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
41914 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
41915 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
41916 
41918 /* The count of USB_ANALOG_VBUS_DETECT_CLR */
41919 #define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)
41920 
41923 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
41924 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
41925 
41935 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
41936 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
41937 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
41938 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
41939 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
41940 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
41941 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
41942 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
41943 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
41944 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
41945 
41947 /* The count of USB_ANALOG_VBUS_DETECT_TOG */
41948 #define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)
41949 
41952 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
41953 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
41954 
41958 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
41959 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
41960 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
41961 
41965 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
41966 #define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
41967 #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
41968 
41972 #define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
41973 
41975 /* The count of USB_ANALOG_CHRG_DETECT */
41976 #define USB_ANALOG_CHRG_DETECT_COUNT (2U)
41977 
41980 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
41981 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
41982 
41986 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
41987 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
41988 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
41989 
41993 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
41994 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
41995 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
41996 
42000 #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
42001 
42003 /* The count of USB_ANALOG_CHRG_DETECT_SET */
42004 #define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)
42005 
42008 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
42009 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
42010 
42014 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
42015 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
42016 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
42017 
42021 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
42022 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
42023 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
42024 
42028 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
42029 
42031 /* The count of USB_ANALOG_CHRG_DETECT_CLR */
42032 #define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)
42033 
42036 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
42037 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
42038 
42042 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
42043 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
42044 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
42045 
42049 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
42050 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
42051 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
42052 
42056 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
42057 
42059 /* The count of USB_ANALOG_CHRG_DETECT_TOG */
42060 #define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)
42061 
42064 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
42065 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
42066 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
42067 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
42068 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
42069 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
42070 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
42071 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
42072 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
42073 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
42074 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
42075 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
42076 
42078 /* The count of USB_ANALOG_VBUS_DETECT_STAT */
42079 #define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)
42080 
42083 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
42084 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
42085 
42089 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
42090 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
42091 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
42092 
42096 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
42097 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
42098 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
42099 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
42100 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
42101 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
42102 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
42103 
42105 /* The count of USB_ANALOG_CHRG_DETECT_STAT */
42106 #define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)
42107 
42110 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
42111 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
42112 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
42113 
42115 /* The count of USB_ANALOG_LOOPBACK */
42116 #define USB_ANALOG_LOOPBACK_COUNT (2U)
42117 
42120 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
42121 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
42122 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
42123 
42125 /* The count of USB_ANALOG_LOOPBACK_SET */
42126 #define USB_ANALOG_LOOPBACK_SET_COUNT (2U)
42127 
42130 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
42131 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
42132 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
42133 
42135 /* The count of USB_ANALOG_LOOPBACK_CLR */
42136 #define USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
42137 
42140 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
42141 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
42142 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
42143 
42145 /* The count of USB_ANALOG_LOOPBACK_TOG */
42146 #define USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
42147 
42150 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
42151 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
42152 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
42153 #define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
42154 #define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
42155 #define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
42156 #define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
42157 #define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
42158 #define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
42159 
42161 /* The count of USB_ANALOG_MISC */
42162 #define USB_ANALOG_MISC_COUNT (2U)
42163 
42166 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
42167 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
42168 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
42169 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
42170 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
42171 #define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
42172 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
42173 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
42174 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
42175 
42177 /* The count of USB_ANALOG_MISC_SET */
42178 #define USB_ANALOG_MISC_SET_COUNT (2U)
42179 
42182 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
42183 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
42184 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
42185 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
42186 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
42187 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
42188 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
42189 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
42190 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
42191 
42193 /* The count of USB_ANALOG_MISC_CLR */
42194 #define USB_ANALOG_MISC_CLR_COUNT (2U)
42195 
42198 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
42199 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
42200 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
42201 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
42202 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
42203 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
42204 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
42205 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
42206 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
42207 
42209 /* The count of USB_ANALOG_MISC_TOG */
42210 #define USB_ANALOG_MISC_TOG_COUNT (2U)
42211 
42214 #define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
42215 #define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
42216 
42219 #define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
42220  /* end of group USB_ANALOG_Register_Masks */
42226 
42227 
42228 /* USB_ANALOG - Peripheral instance base addresses */
42230 #define USB_ANALOG_BASE (0x400D8000u)
42231 
42232 #define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
42233 
42234 #define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
42235 
42236 #define USB_ANALOG_BASE_PTRS { USB_ANALOG }
42237  /* end of group USB_ANALOG_Peripheral_Access_Layer */
42241 
42242 
42243 /* ----------------------------------------------------------------------------
42244  -- USDHC Peripheral Access Layer
42245  ---------------------------------------------------------------------------- */
42246 
42253 typedef struct {
42254  __IO uint32_t DS_ADDR;
42255  __IO uint32_t BLK_ATT;
42256  __IO uint32_t CMD_ARG;
42257  __IO uint32_t CMD_XFR_TYP;
42258  __I uint32_t CMD_RSP0;
42259  __I uint32_t CMD_RSP1;
42260  __I uint32_t CMD_RSP2;
42261  __I uint32_t CMD_RSP3;
42262  __IO uint32_t DATA_BUFF_ACC_PORT;
42263  __I uint32_t PRES_STATE;
42264  __IO uint32_t PROT_CTRL;
42265  __IO uint32_t SYS_CTRL;
42266  __IO uint32_t INT_STATUS;
42267  __IO uint32_t INT_STATUS_EN;
42268  __IO uint32_t INT_SIGNAL_EN;
42269  __IO uint32_t AUTOCMD12_ERR_STATUS;
42270  __IO uint32_t HOST_CTRL_CAP;
42271  __IO uint32_t WTMK_LVL;
42272  __IO uint32_t MIX_CTRL;
42273  uint8_t RESERVED_0[4];
42274  __O uint32_t FORCE_EVENT;
42275  __I uint32_t ADMA_ERR_STATUS;
42276  __IO uint32_t ADMA_SYS_ADDR;
42277  uint8_t RESERVED_1[4];
42278  __IO uint32_t DLL_CTRL;
42279  __I uint32_t DLL_STATUS;
42280  __IO uint32_t CLK_TUNE_CTRL_STATUS;
42281  uint8_t RESERVED_2[84];
42282  __IO uint32_t VEND_SPEC;
42283  __IO uint32_t MMC_BOOT;
42284  __IO uint32_t VEND_SPEC2;
42285  __IO uint32_t TUNING_CTRL;
42286 } USDHC_Type;
42287 
42288 /* ----------------------------------------------------------------------------
42289  -- USDHC Register Masks
42290  ---------------------------------------------------------------------------- */
42291 
42299 #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
42300 #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
42301 
42303 #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
42304 
42308 #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
42309 #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
42310 
42321 #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
42322 #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
42323 #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
42324 
42330 #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
42331 
42335 #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
42336 #define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
42337 
42339 #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
42340 
42344 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
42345 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
42346 
42352 #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
42353 #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
42354 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
42355 
42359 #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
42360 #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
42361 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
42362 
42366 #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
42367 #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
42368 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
42369 
42373 #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
42374 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
42375 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
42376 
42382 #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
42383 #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
42384 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
42385 
42387 #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
42388 
42392 #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
42393 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
42394 
42396 #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
42397 
42401 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
42402 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
42403 
42405 #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
42406 
42410 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
42411 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
42412 
42414 #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
42415 
42419 #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
42420 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
42421 
42423 #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
42424 
42428 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
42429 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
42430 
42432 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
42433 
42437 #define USDHC_PRES_STATE_CIHB_MASK (0x1U)
42438 #define USDHC_PRES_STATE_CIHB_SHIFT (0U)
42439 
42443 #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
42444 #define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
42445 #define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
42446 
42450 #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
42451 #define USDHC_PRES_STATE_DLA_MASK (0x4U)
42452 #define USDHC_PRES_STATE_DLA_SHIFT (2U)
42453 
42457 #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
42458 #define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
42459 #define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
42460 
42464 #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
42465 #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
42466 #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
42467 
42471 #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
42472 #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
42473 #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
42474 
42478 #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
42479 #define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
42480 #define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
42481 
42485 #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
42486 #define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
42487 #define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
42488 
42492 #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
42493 #define USDHC_PRES_STATE_WTA_MASK (0x100U)
42494 #define USDHC_PRES_STATE_WTA_SHIFT (8U)
42495 
42499 #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
42500 #define USDHC_PRES_STATE_RTA_MASK (0x200U)
42501 #define USDHC_PRES_STATE_RTA_SHIFT (9U)
42502 
42506 #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
42507 #define USDHC_PRES_STATE_BWEN_MASK (0x400U)
42508 #define USDHC_PRES_STATE_BWEN_SHIFT (10U)
42509 
42513 #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
42514 #define USDHC_PRES_STATE_BREN_MASK (0x800U)
42515 #define USDHC_PRES_STATE_BREN_SHIFT (11U)
42516 
42520 #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
42521 #define USDHC_PRES_STATE_RTR_MASK (0x1000U)
42522 #define USDHC_PRES_STATE_RTR_SHIFT (12U)
42523 
42527 #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
42528 #define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
42529 #define USDHC_PRES_STATE_TSCD_SHIFT (15U)
42530 
42534 #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
42535 #define USDHC_PRES_STATE_CINST_MASK (0x10000U)
42536 #define USDHC_PRES_STATE_CINST_SHIFT (16U)
42537 
42541 #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
42542 #define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
42543 #define USDHC_PRES_STATE_CDPL_SHIFT (18U)
42544 
42548 #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
42549 #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
42550 #define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
42551 
42555 #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
42556 #define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
42557 #define USDHC_PRES_STATE_CLSL_SHIFT (23U)
42558 
42560 #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
42561 #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
42562 #define USDHC_PRES_STATE_DLSL_SHIFT (24U)
42563 
42573 #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
42574 
42578 #define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
42579 #define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
42580 
42584 #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
42585 #define USDHC_PROT_CTRL_DTW_MASK (0x6U)
42586 #define USDHC_PROT_CTRL_DTW_SHIFT (1U)
42587 
42593 #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
42594 #define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
42595 #define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
42596 
42600 #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
42601 #define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
42602 #define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
42603 
42609 #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
42610 #define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
42611 #define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
42612 
42616 #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
42617 #define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
42618 #define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
42619 
42623 #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
42624 #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
42625 #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
42626 
42632 #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
42633 #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
42634 #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
42635 
42639 #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
42640 #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
42641 #define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
42642 
42646 #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
42647 #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
42648 #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
42649 
42653 #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
42654 #define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
42655 #define USDHC_PROT_CTRL_IABG_SHIFT (19U)
42656 
42660 #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
42661 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
42662 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
42663 
42665 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
42666 #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
42667 #define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
42668 
42672 #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
42673 #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
42674 #define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
42675 
42679 #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
42680 #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
42681 #define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
42682 
42686 #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
42687 #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
42688 #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
42689 
42694 #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
42695 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
42696 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
42697 
42701 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
42702 
42706 #define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
42707 #define USDHC_SYS_CTRL_DVS_SHIFT (4U)
42708 
42714 #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
42715 #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
42716 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
42717 
42719 #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
42720 #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
42721 #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
42722 
42729 #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
42730 #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
42731 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
42732 
42734 #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
42735 #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
42736 #define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
42737 
42741 #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
42742 #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
42743 #define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
42744 
42748 #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
42749 #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
42750 #define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
42751 
42755 #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
42756 #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
42757 #define USDHC_SYS_CTRL_INITA_SHIFT (27U)
42758 
42760 #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
42761 #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
42762 #define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
42763 
42765 #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
42766 
42770 #define USDHC_INT_STATUS_CC_MASK (0x1U)
42771 #define USDHC_INT_STATUS_CC_SHIFT (0U)
42772 
42776 #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
42777 #define USDHC_INT_STATUS_TC_MASK (0x2U)
42778 #define USDHC_INT_STATUS_TC_SHIFT (1U)
42779 
42783 #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
42784 #define USDHC_INT_STATUS_BGE_MASK (0x4U)
42785 #define USDHC_INT_STATUS_BGE_SHIFT (2U)
42786 
42790 #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
42791 #define USDHC_INT_STATUS_DINT_MASK (0x8U)
42792 #define USDHC_INT_STATUS_DINT_SHIFT (3U)
42793 
42797 #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
42798 #define USDHC_INT_STATUS_BWR_MASK (0x10U)
42799 #define USDHC_INT_STATUS_BWR_SHIFT (4U)
42800 
42804 #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
42805 #define USDHC_INT_STATUS_BRR_MASK (0x20U)
42806 #define USDHC_INT_STATUS_BRR_SHIFT (5U)
42807 
42811 #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
42812 #define USDHC_INT_STATUS_CINS_MASK (0x40U)
42813 #define USDHC_INT_STATUS_CINS_SHIFT (6U)
42814 
42818 #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
42819 #define USDHC_INT_STATUS_CRM_MASK (0x80U)
42820 #define USDHC_INT_STATUS_CRM_SHIFT (7U)
42821 
42825 #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
42826 #define USDHC_INT_STATUS_CINT_MASK (0x100U)
42827 #define USDHC_INT_STATUS_CINT_SHIFT (8U)
42828 
42832 #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
42833 #define USDHC_INT_STATUS_RTE_MASK (0x1000U)
42834 #define USDHC_INT_STATUS_RTE_SHIFT (12U)
42835 
42839 #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
42840 #define USDHC_INT_STATUS_TP_MASK (0x4000U)
42841 #define USDHC_INT_STATUS_TP_SHIFT (14U)
42842 
42844 #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
42845 #define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
42846 #define USDHC_INT_STATUS_CTOE_SHIFT (16U)
42847 
42851 #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
42852 #define USDHC_INT_STATUS_CCE_MASK (0x20000U)
42853 #define USDHC_INT_STATUS_CCE_SHIFT (17U)
42854 
42858 #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
42859 #define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
42860 #define USDHC_INT_STATUS_CEBE_SHIFT (18U)
42861 
42865 #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
42866 #define USDHC_INT_STATUS_CIE_MASK (0x80000U)
42867 #define USDHC_INT_STATUS_CIE_SHIFT (19U)
42868 
42872 #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
42873 #define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
42874 #define USDHC_INT_STATUS_DTOE_SHIFT (20U)
42875 
42879 #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
42880 #define USDHC_INT_STATUS_DCE_MASK (0x200000U)
42881 #define USDHC_INT_STATUS_DCE_SHIFT (21U)
42882 
42886 #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
42887 #define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
42888 #define USDHC_INT_STATUS_DEBE_SHIFT (22U)
42889 
42893 #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
42894 #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
42895 #define USDHC_INT_STATUS_AC12E_SHIFT (24U)
42896 
42900 #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
42901 #define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
42902 #define USDHC_INT_STATUS_TNE_SHIFT (26U)
42903 
42905 #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
42906 #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
42907 #define USDHC_INT_STATUS_DMAE_SHIFT (28U)
42908 
42912 #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
42913 
42917 #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
42918 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
42919 
42923 #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
42924 #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
42925 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
42926 
42930 #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
42931 #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
42932 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
42933 
42937 #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
42938 #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
42939 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
42940 
42944 #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
42945 #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
42946 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
42947 
42951 #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
42952 #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
42953 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
42954 
42958 #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
42959 #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
42960 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
42961 
42965 #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
42966 #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
42967 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
42968 
42972 #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
42973 #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
42974 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
42975 
42979 #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
42980 #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
42981 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
42982 
42986 #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
42987 #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
42988 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
42989 
42993 #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
42994 #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
42995 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
42996 
43000 #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
43001 #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
43002 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
43003 
43007 #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
43008 #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
43009 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
43010 
43014 #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
43015 #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
43016 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
43017 
43021 #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
43022 #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
43023 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
43024 
43028 #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
43029 #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
43030 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
43031 
43035 #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
43036 #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
43037 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
43038 
43042 #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
43043 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
43044 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
43045 
43049 #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
43050 #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
43051 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
43052 
43056 #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
43057 #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
43058 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
43059 
43063 #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
43064 
43068 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
43069 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
43070 
43074 #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
43075 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
43076 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
43077 
43081 #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
43082 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
43083 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
43084 
43088 #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
43089 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
43090 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
43091 
43095 #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
43096 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
43097 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
43098 
43102 #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
43103 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
43104 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
43105 
43109 #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
43110 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
43111 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
43112 
43116 #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
43117 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
43118 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
43119 
43123 #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
43124 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
43125 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
43126 
43130 #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
43131 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
43132 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
43133 
43137 #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
43138 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
43139 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
43140 
43144 #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
43145 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
43146 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
43147 
43151 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
43152 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
43153 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
43154 
43158 #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
43159 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
43160 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
43161 
43165 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
43166 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
43167 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
43168 
43172 #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
43173 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
43174 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
43175 
43179 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
43180 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
43181 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
43182 
43186 #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
43187 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
43188 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
43189 
43193 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
43194 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
43195 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
43196 
43200 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
43201 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
43202 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
43203 
43207 #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
43208 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
43209 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
43210 
43214 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
43215 
43219 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
43220 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
43221 
43225 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
43226 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
43227 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
43228 
43232 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
43233 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
43234 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
43235 
43239 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
43240 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
43241 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
43242 
43246 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
43247 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
43248 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
43249 
43253 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
43254 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
43255 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
43256 
43260 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
43261 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
43262 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
43263 
43265 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
43266 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
43267 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
43268 
43272 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
43273 
43277 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
43278 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
43279 
43281 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
43282 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
43283 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
43284 
43286 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
43287 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
43288 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
43289 
43291 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
43292 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
43293 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
43294 
43296 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
43297 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
43298 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
43299 
43303 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
43304 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
43305 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
43306 
43312 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
43313 #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
43314 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
43315 
43321 #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
43322 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
43323 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
43324 
43328 #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
43329 #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
43330 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
43331 
43335 #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
43336 #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
43337 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
43338 
43342 #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
43343 #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
43344 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
43345 
43349 #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
43350 #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
43351 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
43352 
43356 #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
43357 #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
43358 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
43359 
43363 #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
43364 #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
43365 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
43366 
43370 #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
43371 
43375 #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
43376 #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
43377 
43379 #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
43380 #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
43381 #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
43382 
43384 #define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
43385 #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
43386 #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
43387 
43389 #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
43390 #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
43391 #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
43392 
43394 #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
43395 
43399 #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
43400 #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
43401 
43405 #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
43406 #define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
43407 #define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
43408 
43412 #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
43413 #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
43414 #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
43415 
43419 #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
43420 #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
43421 #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
43422 
43424 #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
43425 #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
43426 #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
43427 
43431 #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
43432 #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
43433 #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
43434 
43438 #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
43439 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
43440 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
43441 
43443 #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
43444 #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
43445 #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
43446 
43448 #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
43449 #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
43450 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
43451 
43455 #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
43456 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
43457 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
43458 
43462 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
43463 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
43464 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
43465 
43469 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
43470 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
43471 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
43472 
43476 #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
43477 
43481 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
43482 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
43483 
43485 #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
43486 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
43487 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
43488 
43490 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
43491 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
43492 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
43493 
43495 #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
43496 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
43497 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
43498 
43500 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
43501 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
43502 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
43503 
43505 #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
43506 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
43507 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
43508 
43510 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
43511 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
43512 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
43513 
43515 #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
43516 #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
43517 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
43518 
43520 #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
43521 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
43522 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
43523 
43525 #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
43526 #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
43527 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
43528 
43530 #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
43531 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
43532 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
43533 
43535 #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
43536 #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
43537 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
43538 
43540 #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
43541 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
43542 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
43543 
43545 #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
43546 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
43547 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
43548 
43550 #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
43551 #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
43552 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
43553 
43555 #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
43556 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
43557 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
43558 
43560 #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
43561 #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
43562 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
43563 
43565 #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
43566 
43570 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
43571 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
43572 
43574 #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
43575 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
43576 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
43577 
43581 #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
43582 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
43583 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
43584 
43588 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
43589 
43593 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
43594 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
43595 
43597 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
43598 
43602 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
43603 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
43604 
43606 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
43607 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
43608 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
43609 
43611 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
43612 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
43613 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
43614 
43616 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
43617 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
43618 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
43619 
43621 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
43622 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
43623 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
43624 
43626 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
43627 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
43628 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
43629 
43631 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
43632 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
43633 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
43634 
43636 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
43637 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
43638 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
43639 
43641 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
43642 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
43643 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
43644 
43646 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
43647 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
43648 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
43649 
43651 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
43652 
43656 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
43657 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
43658 
43660 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
43661 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
43662 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
43663 
43665 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
43666 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
43667 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
43668 
43670 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
43671 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
43672 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
43673 
43675 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
43676 
43680 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
43681 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
43682 
43684 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
43685 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
43686 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
43687 
43689 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
43690 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
43691 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
43692 
43694 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
43695 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
43696 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
43697 
43699 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
43700 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
43701 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
43702 
43704 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
43705 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
43706 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
43707 
43709 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
43710 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
43711 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
43712 
43714 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
43715 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
43716 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
43717 
43719 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
43720 
43724 #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
43725 #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
43726 
43730 #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
43731 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
43732 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
43733 
43737 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
43738 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
43739 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
43740 
43744 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
43745 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
43746 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
43747 
43751 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
43752 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
43753 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
43754 
43758 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
43759 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
43760 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
43761 
43765 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
43766 
43770 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
43771 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
43772 
43784 #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
43785 #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
43786 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
43787 
43791 #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
43792 #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
43793 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
43794 
43798 #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
43799 #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
43800 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
43801 
43805 #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
43806 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
43807 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
43808 
43810 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
43811 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
43812 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
43813 
43817 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
43818 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
43819 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
43820 
43822 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
43823 
43827 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
43828 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
43829 
43833 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
43834 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
43835 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
43836 
43838 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
43839 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
43840 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
43841 
43843 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
43844 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
43845 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
43846 
43850 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
43851 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
43852 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
43853 
43857 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
43858 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)
43859 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)
43860 
43862 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
43863 #define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)
43864 #define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)
43865 
43867 #define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
43868 
43872 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
43873 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
43874 
43876 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
43877 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
43878 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
43879 
43881 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
43882 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
43883 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
43884 
43886 #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
43887 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
43888 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
43889 
43891 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
43892 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
43893 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
43894 
43896 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
43897  /* end of group USDHC_Register_Masks */
43903 
43904 
43905 /* USDHC - Peripheral instance base addresses */
43907 #define USDHC1_BASE (0x402C0000u)
43908 
43909 #define USDHC1 ((USDHC_Type *)USDHC1_BASE)
43910 
43911 #define USDHC2_BASE (0x402C4000u)
43912 
43913 #define USDHC2 ((USDHC_Type *)USDHC2_BASE)
43914 
43915 #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
43916 
43917 #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
43918 
43919 #define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
43920  /* end of group USDHC_Peripheral_Access_Layer */
43924 
43925 
43926 /* ----------------------------------------------------------------------------
43927  -- WDOG Peripheral Access Layer
43928  ---------------------------------------------------------------------------- */
43929 
43936 typedef struct {
43937  __IO uint16_t WCR;
43938  __IO uint16_t WSR;
43939  __I uint16_t WRSR;
43940  __IO uint16_t WICR;
43941  __IO uint16_t WMCR;
43942 } WDOG_Type;
43943 
43944 /* ----------------------------------------------------------------------------
43945  -- WDOG Register Masks
43946  ---------------------------------------------------------------------------- */
43947 
43955 #define WDOG_WCR_WDZST_MASK (0x1U)
43956 #define WDOG_WCR_WDZST_SHIFT (0U)
43957 
43961 #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
43962 #define WDOG_WCR_WDBG_MASK (0x2U)
43963 #define WDOG_WCR_WDBG_SHIFT (1U)
43964 
43968 #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
43969 #define WDOG_WCR_WDE_MASK (0x4U)
43970 #define WDOG_WCR_WDE_SHIFT (2U)
43971 
43975 #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
43976 #define WDOG_WCR_WDT_MASK (0x8U)
43977 #define WDOG_WCR_WDT_SHIFT (3U)
43978 
43982 #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
43983 #define WDOG_WCR_SRS_MASK (0x10U)
43984 #define WDOG_WCR_SRS_SHIFT (4U)
43985 
43989 #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
43990 #define WDOG_WCR_WDA_MASK (0x20U)
43991 #define WDOG_WCR_WDA_SHIFT (5U)
43992 
43996 #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
43997 #define WDOG_WCR_SRE_MASK (0x40U)
43998 #define WDOG_WCR_SRE_SHIFT (6U)
43999 
44003 #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
44004 #define WDOG_WCR_WDW_MASK (0x80U)
44005 #define WDOG_WCR_WDW_SHIFT (7U)
44006 
44010 #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
44011 #define WDOG_WCR_WT_MASK (0xFF00U)
44012 #define WDOG_WCR_WT_SHIFT (8U)
44013 
44020 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
44021 
44025 #define WDOG_WSR_WSR_MASK (0xFFFFU)
44026 #define WDOG_WSR_WSR_SHIFT (0U)
44027 
44031 #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
44032 
44036 #define WDOG_WRSR_SFTW_MASK (0x1U)
44037 #define WDOG_WRSR_SFTW_SHIFT (0U)
44038 
44042 #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
44043 #define WDOG_WRSR_TOUT_MASK (0x2U)
44044 #define WDOG_WRSR_TOUT_SHIFT (1U)
44045 
44049 #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
44050 #define WDOG_WRSR_POR_MASK (0x10U)
44051 #define WDOG_WRSR_POR_SHIFT (4U)
44052 
44056 #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
44057 
44061 #define WDOG_WICR_WICT_MASK (0xFFU)
44062 #define WDOG_WICR_WICT_SHIFT (0U)
44063 
44069 #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
44070 #define WDOG_WICR_WTIS_MASK (0x4000U)
44071 #define WDOG_WICR_WTIS_SHIFT (14U)
44072 
44076 #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
44077 #define WDOG_WICR_WIE_MASK (0x8000U)
44078 #define WDOG_WICR_WIE_SHIFT (15U)
44079 
44083 #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
44084 
44088 #define WDOG_WMCR_PDE_MASK (0x1U)
44089 #define WDOG_WMCR_PDE_SHIFT (0U)
44090 
44094 #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
44095  /* end of group WDOG_Register_Masks */
44101 
44102 
44103 /* WDOG - Peripheral instance base addresses */
44105 #define WDOG1_BASE (0x400B8000u)
44106 
44107 #define WDOG1 ((WDOG_Type *)WDOG1_BASE)
44108 
44109 #define WDOG2_BASE (0x400D0000u)
44110 
44111 #define WDOG2 ((WDOG_Type *)WDOG2_BASE)
44112 
44113 #define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
44114 
44115 #define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
44116 
44117 #define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
44118  /* end of group WDOG_Peripheral_Access_Layer */
44122 
44123 
44124 /* ----------------------------------------------------------------------------
44125  -- XBARA Peripheral Access Layer
44126  ---------------------------------------------------------------------------- */
44127 
44134 typedef struct {
44135  __IO uint16_t SEL0;
44136  __IO uint16_t SEL1;
44137  __IO uint16_t SEL2;
44138  __IO uint16_t SEL3;
44139  __IO uint16_t SEL4;
44140  __IO uint16_t SEL5;
44141  __IO uint16_t SEL6;
44142  __IO uint16_t SEL7;
44143  __IO uint16_t SEL8;
44144  __IO uint16_t SEL9;
44145  __IO uint16_t SEL10;
44146  __IO uint16_t SEL11;
44147  __IO uint16_t SEL12;
44148  __IO uint16_t SEL13;
44149  __IO uint16_t SEL14;
44150  __IO uint16_t SEL15;
44151  __IO uint16_t SEL16;
44152  __IO uint16_t SEL17;
44153  __IO uint16_t SEL18;
44154  __IO uint16_t SEL19;
44155  __IO uint16_t SEL20;
44156  __IO uint16_t SEL21;
44157  __IO uint16_t SEL22;
44158  __IO uint16_t SEL23;
44159  __IO uint16_t SEL24;
44160  __IO uint16_t SEL25;
44161  __IO uint16_t SEL26;
44162  __IO uint16_t SEL27;
44163  __IO uint16_t SEL28;
44164  __IO uint16_t SEL29;
44165  __IO uint16_t SEL30;
44166  __IO uint16_t SEL31;
44167  __IO uint16_t SEL32;
44168  __IO uint16_t SEL33;
44169  __IO uint16_t SEL34;
44170  __IO uint16_t SEL35;
44171  __IO uint16_t SEL36;
44172  __IO uint16_t SEL37;
44173  __IO uint16_t SEL38;
44174  __IO uint16_t SEL39;
44175  __IO uint16_t SEL40;
44176  __IO uint16_t SEL41;
44177  __IO uint16_t SEL42;
44178  __IO uint16_t SEL43;
44179  __IO uint16_t SEL44;
44180  __IO uint16_t SEL45;
44181  __IO uint16_t SEL46;
44182  __IO uint16_t SEL47;
44183  __IO uint16_t SEL48;
44184  __IO uint16_t SEL49;
44185  __IO uint16_t SEL50;
44186  __IO uint16_t SEL51;
44187  __IO uint16_t SEL52;
44188  __IO uint16_t SEL53;
44189  __IO uint16_t SEL54;
44190  __IO uint16_t SEL55;
44191  __IO uint16_t SEL56;
44192  __IO uint16_t SEL57;
44193  __IO uint16_t SEL58;
44194  __IO uint16_t SEL59;
44195  __IO uint16_t SEL60;
44196  __IO uint16_t SEL61;
44197  __IO uint16_t SEL62;
44198  __IO uint16_t SEL63;
44199  __IO uint16_t SEL64;
44200  __IO uint16_t SEL65;
44201  __IO uint16_t CTRL0;
44202  __IO uint16_t CTRL1;
44203 } XBARA_Type;
44204 
44205 /* ----------------------------------------------------------------------------
44206  -- XBARA Register Masks
44207  ---------------------------------------------------------------------------- */
44208 
44216 #define XBARA_SEL0_SEL0_MASK (0x7FU)
44217 #define XBARA_SEL0_SEL0_SHIFT (0U)
44218 #define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
44219 #define XBARA_SEL0_SEL1_MASK (0x7F00U)
44220 #define XBARA_SEL0_SEL1_SHIFT (8U)
44221 #define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
44222 
44226 #define XBARA_SEL1_SEL2_MASK (0x7FU)
44227 #define XBARA_SEL1_SEL2_SHIFT (0U)
44228 #define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
44229 #define XBARA_SEL1_SEL3_MASK (0x7F00U)
44230 #define XBARA_SEL1_SEL3_SHIFT (8U)
44231 #define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
44232 
44236 #define XBARA_SEL2_SEL4_MASK (0x7FU)
44237 #define XBARA_SEL2_SEL4_SHIFT (0U)
44238 #define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
44239 #define XBARA_SEL2_SEL5_MASK (0x7F00U)
44240 #define XBARA_SEL2_SEL5_SHIFT (8U)
44241 #define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
44242 
44246 #define XBARA_SEL3_SEL6_MASK (0x7FU)
44247 #define XBARA_SEL3_SEL6_SHIFT (0U)
44248 #define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
44249 #define XBARA_SEL3_SEL7_MASK (0x7F00U)
44250 #define XBARA_SEL3_SEL7_SHIFT (8U)
44251 #define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
44252 
44256 #define XBARA_SEL4_SEL8_MASK (0x7FU)
44257 #define XBARA_SEL4_SEL8_SHIFT (0U)
44258 #define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
44259 #define XBARA_SEL4_SEL9_MASK (0x7F00U)
44260 #define XBARA_SEL4_SEL9_SHIFT (8U)
44261 #define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
44262 
44266 #define XBARA_SEL5_SEL10_MASK (0x7FU)
44267 #define XBARA_SEL5_SEL10_SHIFT (0U)
44268 #define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
44269 #define XBARA_SEL5_SEL11_MASK (0x7F00U)
44270 #define XBARA_SEL5_SEL11_SHIFT (8U)
44271 #define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
44272 
44276 #define XBARA_SEL6_SEL12_MASK (0x7FU)
44277 #define XBARA_SEL6_SEL12_SHIFT (0U)
44278 #define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
44279 #define XBARA_SEL6_SEL13_MASK (0x7F00U)
44280 #define XBARA_SEL6_SEL13_SHIFT (8U)
44281 #define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
44282 
44286 #define XBARA_SEL7_SEL14_MASK (0x7FU)
44287 #define XBARA_SEL7_SEL14_SHIFT (0U)
44288 #define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
44289 #define XBARA_SEL7_SEL15_MASK (0x7F00U)
44290 #define XBARA_SEL7_SEL15_SHIFT (8U)
44291 #define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
44292 
44296 #define XBARA_SEL8_SEL16_MASK (0x7FU)
44297 #define XBARA_SEL8_SEL16_SHIFT (0U)
44298 #define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
44299 #define XBARA_SEL8_SEL17_MASK (0x7F00U)
44300 #define XBARA_SEL8_SEL17_SHIFT (8U)
44301 #define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
44302 
44306 #define XBARA_SEL9_SEL18_MASK (0x7FU)
44307 #define XBARA_SEL9_SEL18_SHIFT (0U)
44308 #define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
44309 #define XBARA_SEL9_SEL19_MASK (0x7F00U)
44310 #define XBARA_SEL9_SEL19_SHIFT (8U)
44311 #define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
44312 
44316 #define XBARA_SEL10_SEL20_MASK (0x7FU)
44317 #define XBARA_SEL10_SEL20_SHIFT (0U)
44318 #define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
44319 #define XBARA_SEL10_SEL21_MASK (0x7F00U)
44320 #define XBARA_SEL10_SEL21_SHIFT (8U)
44321 #define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
44322 
44326 #define XBARA_SEL11_SEL22_MASK (0x7FU)
44327 #define XBARA_SEL11_SEL22_SHIFT (0U)
44328 #define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
44329 #define XBARA_SEL11_SEL23_MASK (0x7F00U)
44330 #define XBARA_SEL11_SEL23_SHIFT (8U)
44331 #define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
44332 
44336 #define XBARA_SEL12_SEL24_MASK (0x7FU)
44337 #define XBARA_SEL12_SEL24_SHIFT (0U)
44338 #define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
44339 #define XBARA_SEL12_SEL25_MASK (0x7F00U)
44340 #define XBARA_SEL12_SEL25_SHIFT (8U)
44341 #define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
44342 
44346 #define XBARA_SEL13_SEL26_MASK (0x7FU)
44347 #define XBARA_SEL13_SEL26_SHIFT (0U)
44348 #define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
44349 #define XBARA_SEL13_SEL27_MASK (0x7F00U)
44350 #define XBARA_SEL13_SEL27_SHIFT (8U)
44351 #define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
44352 
44356 #define XBARA_SEL14_SEL28_MASK (0x7FU)
44357 #define XBARA_SEL14_SEL28_SHIFT (0U)
44358 #define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
44359 #define XBARA_SEL14_SEL29_MASK (0x7F00U)
44360 #define XBARA_SEL14_SEL29_SHIFT (8U)
44361 #define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
44362 
44366 #define XBARA_SEL15_SEL30_MASK (0x7FU)
44367 #define XBARA_SEL15_SEL30_SHIFT (0U)
44368 #define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
44369 #define XBARA_SEL15_SEL31_MASK (0x7F00U)
44370 #define XBARA_SEL15_SEL31_SHIFT (8U)
44371 #define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
44372 
44376 #define XBARA_SEL16_SEL32_MASK (0x7FU)
44377 #define XBARA_SEL16_SEL32_SHIFT (0U)
44378 #define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
44379 #define XBARA_SEL16_SEL33_MASK (0x7F00U)
44380 #define XBARA_SEL16_SEL33_SHIFT (8U)
44381 #define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
44382 
44386 #define XBARA_SEL17_SEL34_MASK (0x7FU)
44387 #define XBARA_SEL17_SEL34_SHIFT (0U)
44388 #define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
44389 #define XBARA_SEL17_SEL35_MASK (0x7F00U)
44390 #define XBARA_SEL17_SEL35_SHIFT (8U)
44391 #define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
44392 
44396 #define XBARA_SEL18_SEL36_MASK (0x7FU)
44397 #define XBARA_SEL18_SEL36_SHIFT (0U)
44398 #define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
44399 #define XBARA_SEL18_SEL37_MASK (0x7F00U)
44400 #define XBARA_SEL18_SEL37_SHIFT (8U)
44401 #define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
44402 
44406 #define XBARA_SEL19_SEL38_MASK (0x7FU)
44407 #define XBARA_SEL19_SEL38_SHIFT (0U)
44408 #define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
44409 #define XBARA_SEL19_SEL39_MASK (0x7F00U)
44410 #define XBARA_SEL19_SEL39_SHIFT (8U)
44411 #define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
44412 
44416 #define XBARA_SEL20_SEL40_MASK (0x7FU)
44417 #define XBARA_SEL20_SEL40_SHIFT (0U)
44418 #define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
44419 #define XBARA_SEL20_SEL41_MASK (0x7F00U)
44420 #define XBARA_SEL20_SEL41_SHIFT (8U)
44421 #define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
44422 
44426 #define XBARA_SEL21_SEL42_MASK (0x7FU)
44427 #define XBARA_SEL21_SEL42_SHIFT (0U)
44428 #define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
44429 #define XBARA_SEL21_SEL43_MASK (0x7F00U)
44430 #define XBARA_SEL21_SEL43_SHIFT (8U)
44431 #define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
44432 
44436 #define XBARA_SEL22_SEL44_MASK (0x7FU)
44437 #define XBARA_SEL22_SEL44_SHIFT (0U)
44438 #define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
44439 #define XBARA_SEL22_SEL45_MASK (0x7F00U)
44440 #define XBARA_SEL22_SEL45_SHIFT (8U)
44441 #define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
44442 
44446 #define XBARA_SEL23_SEL46_MASK (0x7FU)
44447 #define XBARA_SEL23_SEL46_SHIFT (0U)
44448 #define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
44449 #define XBARA_SEL23_SEL47_MASK (0x7F00U)
44450 #define XBARA_SEL23_SEL47_SHIFT (8U)
44451 #define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
44452 
44456 #define XBARA_SEL24_SEL48_MASK (0x7FU)
44457 #define XBARA_SEL24_SEL48_SHIFT (0U)
44458 #define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
44459 #define XBARA_SEL24_SEL49_MASK (0x7F00U)
44460 #define XBARA_SEL24_SEL49_SHIFT (8U)
44461 #define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
44462 
44466 #define XBARA_SEL25_SEL50_MASK (0x7FU)
44467 #define XBARA_SEL25_SEL50_SHIFT (0U)
44468 #define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
44469 #define XBARA_SEL25_SEL51_MASK (0x7F00U)
44470 #define XBARA_SEL25_SEL51_SHIFT (8U)
44471 #define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
44472 
44476 #define XBARA_SEL26_SEL52_MASK (0x7FU)
44477 #define XBARA_SEL26_SEL52_SHIFT (0U)
44478 #define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
44479 #define XBARA_SEL26_SEL53_MASK (0x7F00U)
44480 #define XBARA_SEL26_SEL53_SHIFT (8U)
44481 #define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
44482 
44486 #define XBARA_SEL27_SEL54_MASK (0x7FU)
44487 #define XBARA_SEL27_SEL54_SHIFT (0U)
44488 #define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
44489 #define XBARA_SEL27_SEL55_MASK (0x7F00U)
44490 #define XBARA_SEL27_SEL55_SHIFT (8U)
44491 #define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
44492 
44496 #define XBARA_SEL28_SEL56_MASK (0x7FU)
44497 #define XBARA_SEL28_SEL56_SHIFT (0U)
44498 #define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
44499 #define XBARA_SEL28_SEL57_MASK (0x7F00U)
44500 #define XBARA_SEL28_SEL57_SHIFT (8U)
44501 #define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
44502 
44506 #define XBARA_SEL29_SEL58_MASK (0x7FU)
44507 #define XBARA_SEL29_SEL58_SHIFT (0U)
44508 #define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
44509 #define XBARA_SEL29_SEL59_MASK (0x7F00U)
44510 #define XBARA_SEL29_SEL59_SHIFT (8U)
44511 #define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
44512 
44516 #define XBARA_SEL30_SEL60_MASK (0x7FU)
44517 #define XBARA_SEL30_SEL60_SHIFT (0U)
44518 #define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
44519 #define XBARA_SEL30_SEL61_MASK (0x7F00U)
44520 #define XBARA_SEL30_SEL61_SHIFT (8U)
44521 #define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
44522 
44526 #define XBARA_SEL31_SEL62_MASK (0x7FU)
44527 #define XBARA_SEL31_SEL62_SHIFT (0U)
44528 #define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
44529 #define XBARA_SEL31_SEL63_MASK (0x7F00U)
44530 #define XBARA_SEL31_SEL63_SHIFT (8U)
44531 #define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
44532 
44536 #define XBARA_SEL32_SEL64_MASK (0x7FU)
44537 #define XBARA_SEL32_SEL64_SHIFT (0U)
44538 #define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
44539 #define XBARA_SEL32_SEL65_MASK (0x7F00U)
44540 #define XBARA_SEL32_SEL65_SHIFT (8U)
44541 #define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
44542 
44546 #define XBARA_SEL33_SEL66_MASK (0x7FU)
44547 #define XBARA_SEL33_SEL66_SHIFT (0U)
44548 #define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
44549 #define XBARA_SEL33_SEL67_MASK (0x7F00U)
44550 #define XBARA_SEL33_SEL67_SHIFT (8U)
44551 #define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
44552 
44556 #define XBARA_SEL34_SEL68_MASK (0x7FU)
44557 #define XBARA_SEL34_SEL68_SHIFT (0U)
44558 #define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
44559 #define XBARA_SEL34_SEL69_MASK (0x7F00U)
44560 #define XBARA_SEL34_SEL69_SHIFT (8U)
44561 #define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
44562 
44566 #define XBARA_SEL35_SEL70_MASK (0x7FU)
44567 #define XBARA_SEL35_SEL70_SHIFT (0U)
44568 #define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
44569 #define XBARA_SEL35_SEL71_MASK (0x7F00U)
44570 #define XBARA_SEL35_SEL71_SHIFT (8U)
44571 #define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
44572 
44576 #define XBARA_SEL36_SEL72_MASK (0x7FU)
44577 #define XBARA_SEL36_SEL72_SHIFT (0U)
44578 #define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
44579 #define XBARA_SEL36_SEL73_MASK (0x7F00U)
44580 #define XBARA_SEL36_SEL73_SHIFT (8U)
44581 #define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
44582 
44586 #define XBARA_SEL37_SEL74_MASK (0x7FU)
44587 #define XBARA_SEL37_SEL74_SHIFT (0U)
44588 #define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
44589 #define XBARA_SEL37_SEL75_MASK (0x7F00U)
44590 #define XBARA_SEL37_SEL75_SHIFT (8U)
44591 #define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
44592 
44596 #define XBARA_SEL38_SEL76_MASK (0x7FU)
44597 #define XBARA_SEL38_SEL76_SHIFT (0U)
44598 #define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
44599 #define XBARA_SEL38_SEL77_MASK (0x7F00U)
44600 #define XBARA_SEL38_SEL77_SHIFT (8U)
44601 #define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
44602 
44606 #define XBARA_SEL39_SEL78_MASK (0x7FU)
44607 #define XBARA_SEL39_SEL78_SHIFT (0U)
44608 #define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
44609 #define XBARA_SEL39_SEL79_MASK (0x7F00U)
44610 #define XBARA_SEL39_SEL79_SHIFT (8U)
44611 #define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
44612 
44616 #define XBARA_SEL40_SEL80_MASK (0x7FU)
44617 #define XBARA_SEL40_SEL80_SHIFT (0U)
44618 #define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
44619 #define XBARA_SEL40_SEL81_MASK (0x7F00U)
44620 #define XBARA_SEL40_SEL81_SHIFT (8U)
44621 #define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
44622 
44626 #define XBARA_SEL41_SEL82_MASK (0x7FU)
44627 #define XBARA_SEL41_SEL82_SHIFT (0U)
44628 #define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
44629 #define XBARA_SEL41_SEL83_MASK (0x7F00U)
44630 #define XBARA_SEL41_SEL83_SHIFT (8U)
44631 #define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
44632 
44636 #define XBARA_SEL42_SEL84_MASK (0x7FU)
44637 #define XBARA_SEL42_SEL84_SHIFT (0U)
44638 #define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
44639 #define XBARA_SEL42_SEL85_MASK (0x7F00U)
44640 #define XBARA_SEL42_SEL85_SHIFT (8U)
44641 #define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
44642 
44646 #define XBARA_SEL43_SEL86_MASK (0x7FU)
44647 #define XBARA_SEL43_SEL86_SHIFT (0U)
44648 #define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
44649 #define XBARA_SEL43_SEL87_MASK (0x7F00U)
44650 #define XBARA_SEL43_SEL87_SHIFT (8U)
44651 #define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
44652 
44656 #define XBARA_SEL44_SEL88_MASK (0x7FU)
44657 #define XBARA_SEL44_SEL88_SHIFT (0U)
44658 #define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
44659 #define XBARA_SEL44_SEL89_MASK (0x7F00U)
44660 #define XBARA_SEL44_SEL89_SHIFT (8U)
44661 #define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
44662 
44666 #define XBARA_SEL45_SEL90_MASK (0x7FU)
44667 #define XBARA_SEL45_SEL90_SHIFT (0U)
44668 #define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
44669 #define XBARA_SEL45_SEL91_MASK (0x7F00U)
44670 #define XBARA_SEL45_SEL91_SHIFT (8U)
44671 #define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
44672 
44676 #define XBARA_SEL46_SEL92_MASK (0x7FU)
44677 #define XBARA_SEL46_SEL92_SHIFT (0U)
44678 #define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
44679 #define XBARA_SEL46_SEL93_MASK (0x7F00U)
44680 #define XBARA_SEL46_SEL93_SHIFT (8U)
44681 #define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
44682 
44686 #define XBARA_SEL47_SEL94_MASK (0x7FU)
44687 #define XBARA_SEL47_SEL94_SHIFT (0U)
44688 #define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
44689 #define XBARA_SEL47_SEL95_MASK (0x7F00U)
44690 #define XBARA_SEL47_SEL95_SHIFT (8U)
44691 #define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
44692 
44696 #define XBARA_SEL48_SEL96_MASK (0x7FU)
44697 #define XBARA_SEL48_SEL96_SHIFT (0U)
44698 #define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
44699 #define XBARA_SEL48_SEL97_MASK (0x7F00U)
44700 #define XBARA_SEL48_SEL97_SHIFT (8U)
44701 #define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
44702 
44706 #define XBARA_SEL49_SEL98_MASK (0x7FU)
44707 #define XBARA_SEL49_SEL98_SHIFT (0U)
44708 #define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
44709 #define XBARA_SEL49_SEL99_MASK (0x7F00U)
44710 #define XBARA_SEL49_SEL99_SHIFT (8U)
44711 #define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
44712 
44716 #define XBARA_SEL50_SEL100_MASK (0x7FU)
44717 #define XBARA_SEL50_SEL100_SHIFT (0U)
44718 #define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
44719 #define XBARA_SEL50_SEL101_MASK (0x7F00U)
44720 #define XBARA_SEL50_SEL101_SHIFT (8U)
44721 #define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
44722 
44726 #define XBARA_SEL51_SEL102_MASK (0x7FU)
44727 #define XBARA_SEL51_SEL102_SHIFT (0U)
44728 #define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
44729 #define XBARA_SEL51_SEL103_MASK (0x7F00U)
44730 #define XBARA_SEL51_SEL103_SHIFT (8U)
44731 #define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
44732 
44736 #define XBARA_SEL52_SEL104_MASK (0x7FU)
44737 #define XBARA_SEL52_SEL104_SHIFT (0U)
44738 #define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
44739 #define XBARA_SEL52_SEL105_MASK (0x7F00U)
44740 #define XBARA_SEL52_SEL105_SHIFT (8U)
44741 #define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
44742 
44746 #define XBARA_SEL53_SEL106_MASK (0x7FU)
44747 #define XBARA_SEL53_SEL106_SHIFT (0U)
44748 #define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
44749 #define XBARA_SEL53_SEL107_MASK (0x7F00U)
44750 #define XBARA_SEL53_SEL107_SHIFT (8U)
44751 #define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
44752 
44756 #define XBARA_SEL54_SEL108_MASK (0x7FU)
44757 #define XBARA_SEL54_SEL108_SHIFT (0U)
44758 #define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
44759 #define XBARA_SEL54_SEL109_MASK (0x7F00U)
44760 #define XBARA_SEL54_SEL109_SHIFT (8U)
44761 #define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
44762 
44766 #define XBARA_SEL55_SEL110_MASK (0x7FU)
44767 #define XBARA_SEL55_SEL110_SHIFT (0U)
44768 #define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
44769 #define XBARA_SEL55_SEL111_MASK (0x7F00U)
44770 #define XBARA_SEL55_SEL111_SHIFT (8U)
44771 #define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
44772 
44776 #define XBARA_SEL56_SEL112_MASK (0x7FU)
44777 #define XBARA_SEL56_SEL112_SHIFT (0U)
44778 #define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
44779 #define XBARA_SEL56_SEL113_MASK (0x7F00U)
44780 #define XBARA_SEL56_SEL113_SHIFT (8U)
44781 #define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
44782 
44786 #define XBARA_SEL57_SEL114_MASK (0x7FU)
44787 #define XBARA_SEL57_SEL114_SHIFT (0U)
44788 #define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
44789 #define XBARA_SEL57_SEL115_MASK (0x7F00U)
44790 #define XBARA_SEL57_SEL115_SHIFT (8U)
44791 #define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
44792 
44796 #define XBARA_SEL58_SEL116_MASK (0x7FU)
44797 #define XBARA_SEL58_SEL116_SHIFT (0U)
44798 #define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
44799 #define XBARA_SEL58_SEL117_MASK (0x7F00U)
44800 #define XBARA_SEL58_SEL117_SHIFT (8U)
44801 #define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
44802 
44806 #define XBARA_SEL59_SEL118_MASK (0x7FU)
44807 #define XBARA_SEL59_SEL118_SHIFT (0U)
44808 #define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
44809 #define XBARA_SEL59_SEL119_MASK (0x7F00U)
44810 #define XBARA_SEL59_SEL119_SHIFT (8U)
44811 #define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
44812 
44816 #define XBARA_SEL60_SEL120_MASK (0x7FU)
44817 #define XBARA_SEL60_SEL120_SHIFT (0U)
44818 #define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
44819 #define XBARA_SEL60_SEL121_MASK (0x7F00U)
44820 #define XBARA_SEL60_SEL121_SHIFT (8U)
44821 #define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
44822 
44826 #define XBARA_SEL61_SEL122_MASK (0x7FU)
44827 #define XBARA_SEL61_SEL122_SHIFT (0U)
44828 #define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
44829 #define XBARA_SEL61_SEL123_MASK (0x7F00U)
44830 #define XBARA_SEL61_SEL123_SHIFT (8U)
44831 #define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
44832 
44836 #define XBARA_SEL62_SEL124_MASK (0x7FU)
44837 #define XBARA_SEL62_SEL124_SHIFT (0U)
44838 #define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
44839 #define XBARA_SEL62_SEL125_MASK (0x7F00U)
44840 #define XBARA_SEL62_SEL125_SHIFT (8U)
44841 #define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
44842 
44846 #define XBARA_SEL63_SEL126_MASK (0x7FU)
44847 #define XBARA_SEL63_SEL126_SHIFT (0U)
44848 #define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
44849 #define XBARA_SEL63_SEL127_MASK (0x7F00U)
44850 #define XBARA_SEL63_SEL127_SHIFT (8U)
44851 #define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
44852 
44856 #define XBARA_SEL64_SEL128_MASK (0x7FU)
44857 #define XBARA_SEL64_SEL128_SHIFT (0U)
44858 #define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
44859 #define XBARA_SEL64_SEL129_MASK (0x7F00U)
44860 #define XBARA_SEL64_SEL129_SHIFT (8U)
44861 #define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
44862 
44866 #define XBARA_SEL65_SEL130_MASK (0x7FU)
44867 #define XBARA_SEL65_SEL130_SHIFT (0U)
44868 #define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
44869 #define XBARA_SEL65_SEL131_MASK (0x7F00U)
44870 #define XBARA_SEL65_SEL131_SHIFT (8U)
44871 #define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
44872 
44876 #define XBARA_CTRL0_DEN0_MASK (0x1U)
44877 #define XBARA_CTRL0_DEN0_SHIFT (0U)
44878 
44882 #define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
44883 #define XBARA_CTRL0_IEN0_MASK (0x2U)
44884 #define XBARA_CTRL0_IEN0_SHIFT (1U)
44885 
44889 #define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
44890 #define XBARA_CTRL0_EDGE0_MASK (0xCU)
44891 #define XBARA_CTRL0_EDGE0_SHIFT (2U)
44892 
44898 #define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
44899 #define XBARA_CTRL0_STS0_MASK (0x10U)
44900 #define XBARA_CTRL0_STS0_SHIFT (4U)
44901 
44905 #define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
44906 #define XBARA_CTRL0_DEN1_MASK (0x100U)
44907 #define XBARA_CTRL0_DEN1_SHIFT (8U)
44908 
44912 #define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
44913 #define XBARA_CTRL0_IEN1_MASK (0x200U)
44914 #define XBARA_CTRL0_IEN1_SHIFT (9U)
44915 
44919 #define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
44920 #define XBARA_CTRL0_EDGE1_MASK (0xC00U)
44921 #define XBARA_CTRL0_EDGE1_SHIFT (10U)
44922 
44928 #define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
44929 #define XBARA_CTRL0_STS1_MASK (0x1000U)
44930 #define XBARA_CTRL0_STS1_SHIFT (12U)
44931 
44935 #define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
44936 
44940 #define XBARA_CTRL1_DEN2_MASK (0x1U)
44941 #define XBARA_CTRL1_DEN2_SHIFT (0U)
44942 
44946 #define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
44947 #define XBARA_CTRL1_IEN2_MASK (0x2U)
44948 #define XBARA_CTRL1_IEN2_SHIFT (1U)
44949 
44953 #define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
44954 #define XBARA_CTRL1_EDGE2_MASK (0xCU)
44955 #define XBARA_CTRL1_EDGE2_SHIFT (2U)
44956 
44962 #define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
44963 #define XBARA_CTRL1_STS2_MASK (0x10U)
44964 #define XBARA_CTRL1_STS2_SHIFT (4U)
44965 
44969 #define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
44970 #define XBARA_CTRL1_DEN3_MASK (0x100U)
44971 #define XBARA_CTRL1_DEN3_SHIFT (8U)
44972 
44976 #define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
44977 #define XBARA_CTRL1_IEN3_MASK (0x200U)
44978 #define XBARA_CTRL1_IEN3_SHIFT (9U)
44979 
44983 #define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
44984 #define XBARA_CTRL1_EDGE3_MASK (0xC00U)
44985 #define XBARA_CTRL1_EDGE3_SHIFT (10U)
44986 
44992 #define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
44993 #define XBARA_CTRL1_STS3_MASK (0x1000U)
44994 #define XBARA_CTRL1_STS3_SHIFT (12U)
44995 
44999 #define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
45000  /* end of group XBARA_Register_Masks */
45006 
45007 
45008 /* XBARA - Peripheral instance base addresses */
45010 #define XBARA1_BASE (0x403BC000u)
45011 
45012 #define XBARA1 ((XBARA_Type *)XBARA1_BASE)
45013 
45014 #define XBARA_BASE_ADDRS { XBARA1_BASE }
45015 
45016 #define XBARA_BASE_PTRS { XBARA1 }
45017  /* end of group XBARA_Peripheral_Access_Layer */
45021 
45022 
45023 /* ----------------------------------------------------------------------------
45024  -- XBARB Peripheral Access Layer
45025  ---------------------------------------------------------------------------- */
45026 
45033 typedef struct {
45034  __IO uint16_t SEL0;
45035  __IO uint16_t SEL1;
45036  __IO uint16_t SEL2;
45037  __IO uint16_t SEL3;
45038  __IO uint16_t SEL4;
45039  __IO uint16_t SEL5;
45040  __IO uint16_t SEL6;
45041  __IO uint16_t SEL7;
45042 } XBARB_Type;
45043 
45044 /* ----------------------------------------------------------------------------
45045  -- XBARB Register Masks
45046  ---------------------------------------------------------------------------- */
45047 
45055 #define XBARB_SEL0_SEL0_MASK (0x3FU)
45056 #define XBARB_SEL0_SEL0_SHIFT (0U)
45057 #define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
45058 #define XBARB_SEL0_SEL1_MASK (0x3F00U)
45059 #define XBARB_SEL0_SEL1_SHIFT (8U)
45060 #define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
45061 
45065 #define XBARB_SEL1_SEL2_MASK (0x3FU)
45066 #define XBARB_SEL1_SEL2_SHIFT (0U)
45067 #define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
45068 #define XBARB_SEL1_SEL3_MASK (0x3F00U)
45069 #define XBARB_SEL1_SEL3_SHIFT (8U)
45070 #define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
45071 
45075 #define XBARB_SEL2_SEL4_MASK (0x3FU)
45076 #define XBARB_SEL2_SEL4_SHIFT (0U)
45077 #define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
45078 #define XBARB_SEL2_SEL5_MASK (0x3F00U)
45079 #define XBARB_SEL2_SEL5_SHIFT (8U)
45080 #define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
45081 
45085 #define XBARB_SEL3_SEL6_MASK (0x3FU)
45086 #define XBARB_SEL3_SEL6_SHIFT (0U)
45087 #define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
45088 #define XBARB_SEL3_SEL7_MASK (0x3F00U)
45089 #define XBARB_SEL3_SEL7_SHIFT (8U)
45090 #define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
45091 
45095 #define XBARB_SEL4_SEL8_MASK (0x3FU)
45096 #define XBARB_SEL4_SEL8_SHIFT (0U)
45097 #define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
45098 #define XBARB_SEL4_SEL9_MASK (0x3F00U)
45099 #define XBARB_SEL4_SEL9_SHIFT (8U)
45100 #define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
45101 
45105 #define XBARB_SEL5_SEL10_MASK (0x3FU)
45106 #define XBARB_SEL5_SEL10_SHIFT (0U)
45107 #define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
45108 #define XBARB_SEL5_SEL11_MASK (0x3F00U)
45109 #define XBARB_SEL5_SEL11_SHIFT (8U)
45110 #define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
45111 
45115 #define XBARB_SEL6_SEL12_MASK (0x3FU)
45116 #define XBARB_SEL6_SEL12_SHIFT (0U)
45117 #define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
45118 #define XBARB_SEL6_SEL13_MASK (0x3F00U)
45119 #define XBARB_SEL6_SEL13_SHIFT (8U)
45120 #define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
45121 
45125 #define XBARB_SEL7_SEL14_MASK (0x3FU)
45126 #define XBARB_SEL7_SEL14_SHIFT (0U)
45127 #define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
45128 #define XBARB_SEL7_SEL15_MASK (0x3F00U)
45129 #define XBARB_SEL7_SEL15_SHIFT (8U)
45130 #define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
45131  /* end of group XBARB_Register_Masks */
45137 
45138 
45139 /* XBARB - Peripheral instance base addresses */
45141 #define XBARB2_BASE (0x403C0000u)
45142 
45143 #define XBARB2 ((XBARB_Type *)XBARB2_BASE)
45144 
45145 #define XBARB3_BASE (0x403C4000u)
45146 
45147 #define XBARB3 ((XBARB_Type *)XBARB3_BASE)
45148 
45149 #define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
45150 
45151 #define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
45152  /* end of group XBARB_Peripheral_Access_Layer */
45156 
45157 
45158 /* ----------------------------------------------------------------------------
45159  -- XTALOSC24M Peripheral Access Layer
45160  ---------------------------------------------------------------------------- */
45161 
45168 typedef struct {
45169  uint8_t RESERVED_0[336];
45170  __IO uint32_t MISC0;
45171  __IO uint32_t MISC0_SET;
45172  __IO uint32_t MISC0_CLR;
45173  __IO uint32_t MISC0_TOG;
45174  uint8_t RESERVED_1[272];
45175  __IO uint32_t LOWPWR_CTRL;
45176  __IO uint32_t LOWPWR_CTRL_SET;
45177  __IO uint32_t LOWPWR_CTRL_CLR;
45178  __IO uint32_t LOWPWR_CTRL_TOG;
45179  uint8_t RESERVED_2[32];
45180  __IO uint32_t OSC_CONFIG0;
45181  __IO uint32_t OSC_CONFIG0_SET;
45182  __IO uint32_t OSC_CONFIG0_CLR;
45183  __IO uint32_t OSC_CONFIG0_TOG;
45184  __IO uint32_t OSC_CONFIG1;
45185  __IO uint32_t OSC_CONFIG1_SET;
45186  __IO uint32_t OSC_CONFIG1_CLR;
45187  __IO uint32_t OSC_CONFIG1_TOG;
45188  __IO uint32_t OSC_CONFIG2;
45189  __IO uint32_t OSC_CONFIG2_SET;
45190  __IO uint32_t OSC_CONFIG2_CLR;
45191  __IO uint32_t OSC_CONFIG2_TOG;
45192 } XTALOSC24M_Type;
45193 
45194 /* ----------------------------------------------------------------------------
45195  -- XTALOSC24M Register Masks
45196  ---------------------------------------------------------------------------- */
45197 
45205 #define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
45206 #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
45207 #define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
45208 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
45209 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
45210 
45214 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
45215 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
45216 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
45217 
45227 #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
45228 #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
45229 #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
45230 #define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
45231 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
45232 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
45233 
45239 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
45240 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
45241 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
45242 
45246 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
45247 #define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
45248 #define XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
45249 
45255 #define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
45256 #define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
45257 #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
45258 #define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
45259 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
45260 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
45261 #define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
45262 #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
45263 #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
45264 
45268 #define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
45269 #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
45270 #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
45271 
45281 #define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
45282 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
45283 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
45284 
45288 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
45289 #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
45290 #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
45291 #define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
45292 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
45293 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
45294 
45298 #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
45299 
45303 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
45304 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
45305 #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
45306 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
45307 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
45308 
45312 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
45313 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
45314 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
45315 
45325 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
45326 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
45327 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
45328 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
45329 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
45330 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
45331 
45337 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
45338 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
45339 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
45340 
45344 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
45345 #define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
45346 #define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
45347 
45353 #define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
45354 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
45355 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
45356 #define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
45357 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
45358 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
45359 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
45360 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
45361 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
45362 
45366 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
45367 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
45368 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
45369 
45379 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
45380 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
45381 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
45382 
45386 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
45387 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
45388 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
45389 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
45390 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
45391 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
45392 
45396 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
45397 
45401 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
45402 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
45403 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
45404 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
45405 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
45406 
45410 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
45411 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
45412 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
45413 
45423 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
45424 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
45425 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
45426 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
45427 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
45428 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
45429 
45435 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
45436 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
45437 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
45438 
45442 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
45443 #define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
45444 #define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
45445 
45451 #define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
45452 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
45453 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
45454 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
45455 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
45456 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
45457 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
45458 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
45459 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
45460 
45464 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
45465 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
45466 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
45467 
45477 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
45478 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
45479 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
45480 
45484 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
45485 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
45486 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
45487 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
45488 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
45489 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
45490 
45494 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
45495 
45499 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
45500 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
45501 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
45502 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
45503 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
45504 
45508 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
45509 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
45510 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
45511 
45521 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
45522 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
45523 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
45524 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
45525 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
45526 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
45527 
45533 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
45534 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
45535 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
45536 
45540 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
45541 #define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
45542 #define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
45543 
45549 #define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
45550 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
45551 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
45552 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
45553 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
45554 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
45555 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
45556 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
45557 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
45558 
45562 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
45563 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
45564 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
45565 
45575 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
45576 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
45577 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
45578 
45582 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
45583 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
45584 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
45585 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
45586 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
45587 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
45588 
45592 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
45593 
45597 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
45598 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
45599 
45603 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
45604 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
45605 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
45606 
45610 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
45611 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
45612 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
45613 
45617 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
45618 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
45619 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
45620 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
45621 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
45622 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
45623 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
45624 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
45625 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
45626 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
45627 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
45628 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
45629 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
45630 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
45631 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
45632 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
45633 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
45634 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
45635 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
45636 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
45637 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
45638 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
45639 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
45640 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
45641 
45647 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
45648 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
45649 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
45650 
45654 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
45655 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
45656 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
45657 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
45658 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
45659 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
45660 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
45661 
45665 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
45666 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
45667 
45671 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
45672 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
45673 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
45674 
45678 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
45679 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
45680 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
45681 
45685 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
45686 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
45687 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
45688 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
45689 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
45690 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
45691 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
45692 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
45693 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
45694 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
45695 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
45696 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
45697 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
45698 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
45699 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
45700 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
45701 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
45702 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
45703 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
45704 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
45705 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
45706 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
45707 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
45708 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
45709 
45715 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
45716 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
45717 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
45718 
45722 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
45723 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
45724 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
45725 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
45726 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
45727 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
45728 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
45729 
45733 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
45734 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
45735 
45739 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
45740 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
45741 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
45742 
45746 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
45747 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
45748 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
45749 
45753 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
45754 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
45755 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
45756 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
45757 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
45758 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
45759 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
45760 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
45761 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
45762 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
45763 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
45764 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
45765 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
45766 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
45767 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
45768 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
45769 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
45770 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
45771 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
45772 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
45773 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
45774 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
45775 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
45776 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
45777 
45783 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
45784 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
45785 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
45786 
45790 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
45791 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
45792 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
45793 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
45794 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
45795 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
45796 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
45797 
45801 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
45802 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
45803 
45807 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
45808 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
45809 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
45810 
45814 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
45815 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
45816 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
45817 
45821 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
45822 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
45823 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
45824 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
45825 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
45826 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
45827 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
45828 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
45829 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
45830 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
45831 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
45832 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
45833 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
45834 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
45835 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
45836 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
45837 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
45838 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
45839 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
45840 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
45841 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
45842 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
45843 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
45844 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
45845 
45851 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
45852 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
45853 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
45854 
45858 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
45859 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
45860 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
45861 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
45862 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
45863 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
45864 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
45865 
45869 #define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
45870 #define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
45871 #define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
45872 #define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
45873 #define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
45874 #define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
45875 #define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
45876 #define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
45877 #define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
45878 #define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
45879 #define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
45880 #define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
45881 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
45882 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
45883 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
45884 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
45885 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
45886 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
45887 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
45888 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
45889 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
45890 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
45891 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
45892 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
45893 
45897 #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
45898 #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
45899 #define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
45900 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
45901 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
45902 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
45903 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
45904 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
45905 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
45906 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
45907 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
45908 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
45909 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
45910 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
45911 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
45912 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
45913 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
45914 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
45915 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
45916 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
45917 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
45918 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
45919 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
45920 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
45921 
45925 #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
45926 #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
45927 #define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
45928 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
45929 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
45930 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
45931 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
45932 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
45933 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
45934 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
45935 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
45936 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
45937 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
45938 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
45939 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
45940 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
45941 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
45942 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
45943 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
45944 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
45945 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
45946 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
45947 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
45948 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
45949 
45953 #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
45954 #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
45955 #define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
45956 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
45957 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
45958 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
45959 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
45960 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
45961 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
45962 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
45963 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
45964 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
45965 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
45966 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
45967 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
45968 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
45969 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
45970 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
45971 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
45972 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
45973 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
45974 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
45975 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
45976 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
45977 
45981 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
45982 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
45983 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
45984 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
45985 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
45986 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
45987 
45991 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
45992 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
45993 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
45994 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
45995 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
45996 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
45997 
46001 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
46002 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
46003 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
46004 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
46005 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
46006 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
46007 
46011 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
46012 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
46013 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
46014 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
46015 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
46016 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
46017 
46021 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
46022 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
46023 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
46024 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
46025 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
46026 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
46027 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
46028 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
46029 #define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
46030 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
46031 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
46032 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
46033 
46037 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
46038 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
46039 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
46040 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
46041 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
46042 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
46043 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
46044 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
46045 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
46046 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
46047 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
46048 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
46049 
46053 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
46054 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
46055 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
46056 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
46057 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
46058 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
46059 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
46060 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
46061 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
46062 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
46063 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
46064 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
46065 
46069 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
46070 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
46071 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
46072 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
46073 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
46074 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
46075 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
46076 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
46077 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
46078 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
46079 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
46080 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)
46081  /* end of group XTALOSC24M_Register_Masks */
46087 
46088 
46089 /* XTALOSC24M - Peripheral instance base addresses */
46091 #define XTALOSC24M_BASE (0x400D8000u)
46092 
46093 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
46094 
46095 #define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
46096 
46097 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
46098  /* end of group XTALOSC24M_Peripheral_Access_Layer */
46102 
46103 
46104 /*
46105 ** End of section using anonymous unions
46106 */
46107 
46108 #if defined(__ARMCC_VERSION)
46109  #if (__ARMCC_VERSION >= 6010050)
46110  #pragma clang diagnostic pop
46111  #else
46112  #pragma pop
46113  #endif
46114 #elif defined(__CWCC__)
46115  #pragma pop
46116 #elif defined(__GNUC__)
46117  /* leave anonymous unions enabled */
46118 #elif defined(__IAR_SYSTEMS_ICC__)
46119  #pragma language=default
46120 #else
46121  #error Not supported compiler type
46122 #endif
46123  /* end of group Peripheral_access_layer */
46127 
46128 
46129 /* ----------------------------------------------------------------------------
46130  -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
46131  ---------------------------------------------------------------------------- */
46132 
46138 #if defined(__ARMCC_VERSION)
46139  #if (__ARMCC_VERSION >= 6010050)
46140  #pragma clang system_header
46141  #endif
46142 #elif defined(__IAR_SYSTEMS_ICC__)
46143  #pragma system_include
46144 #endif
46145 
46152 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
46153 
46159 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
46160  /* end of group Bit_Field_Generic_Macros */
46164 
46165 
46166 /* ----------------------------------------------------------------------------
46167  -- SDK Compatibility
46168  ---------------------------------------------------------------------------- */
46169 
46175 /* No SDK compatibility issues. */
46176  /* end of group SDK_Compatibility_Symbols */
46180 
46181 
46182 #endif /* _MIMXRT1052_H_ */
46183 
kDmaRequestMuxFlexSPITx
@ kDmaRequestMuxFlexSPITx
Definition: MIMXRT1052.h:334
kXBARB2_InputAdcEtcXbar0Coco0
@ kXBARB2_InputAdcEtcXbar0Coco0
Definition: MIMXRT1052.h:1001
TEMPMON_Type
Definition: MIMXRT1052.h:37129
ACMP1_IRQn
@ ACMP1_IRQn
Definition: MIMXRT1052.h:217
USDHC_Type::CMD_RSP1
__I uint32_t CMD_RSP1
Definition: MIMXRT1052.h:42259
IOMUXC_GPR_Type::GPR1
__IO uint32_t GPR1
Definition: MIMXRT1052.h:20859
R
#define R
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:5104
TMR_Type::@317::ENBL
__IO uint16_t ENBL
Definition: MIMXRT1052.h:37394
USDHC_Type::MMC_BOOT
__IO uint32_t MMC_BOOT
Definition: MIMXRT1052.h:42283
PMU_Type::REG_CORE
__IO uint32_t REG_CORE
Definition: MIMXRT1052.h:28681
CCM_ANALOG_Type::PLL_ENET_TOG
__IO uint32_t PLL_ENET_TOG
Definition: MIMXRT1052.h:6114
NotAvail_IRQn
@ NotAvail_IRQn
Definition: MIMXRT1052.h:80
kXBARA1_InputIomuxXbarInout09
@ kXBARA1_InputIomuxXbarInout09
Definition: MIMXRT1052.h:884
kXBARA1_OutputFlexpwm4ExtSync0
@ kXBARA1_OutputFlexpwm4ExtSync0
Definition: MIMXRT1052.h:1142
Reserved78_IRQn
@ Reserved78_IRQn
Definition: MIMXRT1052.h:156
DCP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:10271
PXP_Type::PS_PITCH
__IO uint32_t PS_PITCH
Definition: MIMXRT1052.h:32548
ENET_Type::RCR
__IO uint32_t RCR
Definition: MIMXRT1052.h:15619
LPI2C2_IRQn
@ LPI2C2_IRQn
Definition: MIMXRT1052.h:123
SNVS_Type::LPPGDR
__IO uint32_t LPPGDR
Definition: MIMXRT1052.h:35345
HardFault_IRQn
@ HardFault_IRQn
Definition: MIMXRT1052.h:84
DCP_Type::CH2OPTS_TOG
__IO uint32_t CH2OPTS_TOG
Definition: MIMXRT1052.h:10341
USBPHY_Type::DEBUG0_STATUS
__I uint32_t DEBUG0_STATUS
Definition: MIMXRT1052.h:40706
LPSPI_Type::CR
__IO uint32_t CR
Definition: MIMXRT1052.h:26148
ROMC_Type::ROMPATCHCNTL
__IO uint32_t ROMPATCHCNTL
Definition: MIMXRT1052.h:33804
TRNG_Type::FRQMIN
__IO uint32_t FRQMIN
Definition: MIMXRT1052.h:37887
kDmaRequestMuxFlexPWM1ValueSub3
@ kDmaRequestMuxFlexPWM1ValueSub3
Definition: MIMXRT1052.h:344
kXBARA1_OutputEwmEwmIn
@ kXBARA1_OutputEwmEwmIn
Definition: MIMXRT1052.h:1185
PXP_Type::PORTER_DUFF_CTRL
__IO uint32_t PORTER_DUFF_CTRL
Definition: MIMXRT1052.h:32580
ENET_Type::ATSTMP
__I uint32_t ATSTMP
Definition: MIMXRT1052.h:15716
CCM_ANALOG_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1052.h:6126
OCOTP_Type::CFG4
__IO uint32_t CFG4
Definition: MIMXRT1052.h:27732
WDOG_Type::WCR
__IO uint16_t WCR
Definition: MIMXRT1052.h:43937
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1052.h:608
kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT
Definition: MIMXRT1052.h:818
CAN_Type::RX15MASK
__IO uint32_t RX15MASK
Definition: MIMXRT1052.h:3319
PWM_Type::@314::TCTRL
__IO uint16_t TCTRL
Definition: MIMXRT1052.h:30866
kXBARB2_InputDmaDone2
@ kXBARB2_InputDmaDone2
Definition: MIMXRT1052.h:1015
USBPHY_Type::DEBUG1_SET
__IO uint32_t DEBUG1_SET
Definition: MIMXRT1052.h:40709
kDmaRequestMuxFlexPWM3ValueSub2
@ kDmaRequestMuxFlexPWM3ValueSub2
Definition: MIMXRT1052.h:351
kXBARB3_OutputAoi2In12
@ kXBARB3_OutputAoi2In12
Definition: MIMXRT1052.h:1242
kXBARB3_InputLogicLow
@ kXBARB3_InputLogicLow
Definition: MIMXRT1052.h:1021
AIPSTZ_Type::OPACR4
__IO uint32_t OPACR4
Definition: MIMXRT1052.h:2084
DCP_Type::CONTEXT
__IO uint32_t CONTEXT
Definition: MIMXRT1052.h:10286
kXBARA1_OutputIomuxXbarInout18
@ kXBARA1_OutputIomuxXbarInout18
Definition: MIMXRT1052.h:1101
CCM_ANALOG_Type::MISC2
__IO uint32_t MISC2
Definition: MIMXRT1052.h:6132
PWM_Type::DTSRCSEL
__IO uint16_t DTSRCSEL
Definition: MIMXRT1052.h:30893
TSC_Type::INT_EN
__IO uint32_t INT_EN
Definition: MIMXRT1052.h:38555
GPIO1_INT1_IRQn
@ GPIO1_INT1_IRQn
Definition: MIMXRT1052.h:167
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1052.h:693
LPI2C4_IRQn
@ LPI2C4_IRQn
Definition: MIMXRT1052.h:125
OCOTP_Type::SRK0
__IO uint32_t SRK0
Definition: MIMXRT1052.h:27754
FLEXIO_Type::SHIFTERR
__IO uint32_t SHIFTERR
Definition: MIMXRT1052.h:17372
BEE_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:3011
DMA9_DMA25_IRQn
@ DMA9_DMA25_IRQn
Definition: MIMXRT1052.h:103
kXBARA1_OutputRESERVED24
@ kXBARA1_OutputRESERVED24
Definition: MIMXRT1052.h:1107
ENET_Type::RSEM
__IO uint32_t RSEM
Definition: MIMXRT1052.h:15642
LPI2C_Type::SCFGR1
__IO uint32_t SCFGR1
Definition: MIMXRT1052.h:25124
ENC_Type::LPOS
__IO uint16_t LPOS
Definition: MIMXRT1052.h:15147
kXBARA1_InputIomuxXbarInout15
@ kXBARA1_InputIomuxXbarInout15
Definition: MIMXRT1052.h:890
kDmaRequestMuxFlexPWM2CaptureSub2
@ kDmaRequestMuxFlexPWM2CaptureSub2
Definition: MIMXRT1052.h:396
DCP_Type::CH0SEMA
__IO uint32_t CH0SEMA
Definition: MIMXRT1052.h:10308
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1052.h:548
USB_ANALOG_Type::@342::LOOPBACK_SET
__IO uint32_t LOOPBACK_SET
Definition: MIMXRT1052.h:41814
kDmaRequestMuxLPI2C3
@ kDmaRequestMuxLPI2C3
Definition: MIMXRT1052.h:324
USB_Type::GPTIMER1CTRL
__IO uint32_t GPTIMER1CTRL
Definition: MIMXRT1052.h:39004
kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:822
DMA_Type::DCHPRI31
__IO uint8_t DCHPRI31
Definition: MIMXRT1052.h:11999
system_MIMXRT1052.h
USDHC_Type::CMD_XFR_TYP
__IO uint32_t CMD_XFR_TYP
Definition: MIMXRT1052.h:42257
PWM_Type::@314::CVAL5CYC
__I uint16_t CVAL5CYC
Definition: MIMXRT1052.h:30887
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: MIMXRT1052.h:83
PXP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:32513
XTALOSC24M_Type::LOWPWR_CTRL_CLR
__IO uint32_t LOWPWR_CTRL_CLR
Definition: MIMXRT1052.h:45177
kXBARA1_OutputFlexpwm1Fault1
@ kXBARA1_OutputFlexpwm1Fault1
Definition: MIMXRT1052.h:1119
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1052.h:619
USBPHY_Type
Definition: MIMXRT1052.h:40683
OCOTP_Type::SW_GP20
__IO uint32_t SW_GP20
Definition: MIMXRT1052.h:27786
kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
Definition: MIMXRT1052.h:752
FLEXRAM_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1052.h:17944
CCM_ANALOG_Type::PLL_ENET_SET
__IO uint32_t PLL_ENET_SET
Definition: MIMXRT1052.h:6112
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
DMA4_DMA20_IRQn
@ DMA4_DMA20_IRQn
Definition: MIMXRT1052.h:98
XBARA_Type::SEL22
__IO uint16_t SEL22
Definition: MIMXRT1052.h:44157
SPDIF_Type::SRQ
__I uint32_t SRQ
Definition: MIMXRT1052.h:36430
SEMC_Type::SDRAMCR3
__IO uint32_t SDRAMCR3
Definition: MIMXRT1052.h:34141
USBPHY_Type::TX
__IO uint32_t TX
Definition: MIMXRT1052.h:40688
kDmaRequestMuxQTIMER1CaptTimer3
@ kDmaRequestMuxQTIMER1CaptTimer3
Definition: MIMXRT1052.h:356
kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT
Definition: MIMXRT1052.h:814
kIOMUXC_LPSPI4_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI4_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:791
PWM_Type::@314::DTCNT1
__IO uint16_t DTCNT1
Definition: MIMXRT1052.h:30869
XBARA_Type::SEL52
__IO uint16_t SEL52
Definition: MIMXRT1052.h:44187
kXBARB2_InputRESERVED4
@ kXBARB2_InputRESERVED4
Definition: MIMXRT1052.h:967
ENET_Type::IEEE_T_1COL
__I uint32_t IEEE_T_1COL
Definition: MIMXRT1052.h:15674
kXBARB3_OutputAoi2In04
@ kXBARB3_OutputAoi2In04
Definition: MIMXRT1052.h:1234
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
Definition: MIMXRT1052.h:526
XBARA_Type::SEL17
__IO uint16_t SEL17
Definition: MIMXRT1052.h:44152
SPDIF_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1052.h:36417
LPI2C_Type::MCFGR0
__IO uint32_t MCFGR0
Definition: MIMXRT1052.h:25102
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1052.h:626
PWM_Type::@314::DMAEN
__IO uint16_t DMAEN
Definition: MIMXRT1052.h:30865
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
Definition: MIMXRT1052.h:659
kXBARB3_InputFlexpwm3Pwm1OutTrig01
@ kXBARB3_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1052.h:1049
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1052.h:621
USB_Type::DCIVERSION
__I uint16_t DCIVERSION
Definition: MIMXRT1052.h:39013
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1052.h:630
kXBARA1_InputQtimer3Tmr2Output
@ kXBARA1_InputQtimer3Tmr2Output
Definition: MIMXRT1052.h:909
I2S_Type::TCR4
__IO uint32_t TCR4
Definition: MIMXRT1052.h:19874
kIOMUXC_XBAR1_IN19_SELECT_INPUT
@ kIOMUXC_XBAR1_IN19_SELECT_INPUT
Definition: MIMXRT1052.h:869
kXBARA1_OutputEnc4Trigger
@ kXBARA1_OutputEnc4Trigger
Definition: MIMXRT1052.h:1168
DCP_Type::CHANNELCTRL
__IO uint32_t CHANNELCTRL
Definition: MIMXRT1052.h:10278
kXBARB3_InputEnc3PosMatch
@ kXBARB3_InputEnc3PosMatch
Definition: MIMXRT1052.h:1069
LPI2C_Type::MDMR
__IO uint32_t MDMR
Definition: MIMXRT1052.h:25107
SEMC_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:34130
USB_ANALOG_Type::@342::CHRG_DETECT_TOG
__IO uint32_t CHRG_DETECT_TOG
Definition: MIMXRT1052.h:41808
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
@ kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
Definition: MIMXRT1052.h:740
TSC_Type::DEBUG_MODE
__IO uint32_t DEBUG_MODE
Definition: MIMXRT1052.h:38561
DMA_Type::DCHPRI23
__IO uint8_t DCHPRI23
Definition: MIMXRT1052.h:11991
GPIO2_Combined_16_31_IRQn
@ GPIO2_Combined_16_31_IRQn
Definition: MIMXRT1052.h:177
ADC_ETC_IRQ2_IRQn
@ ADC_ETC_IRQ2_IRQn
Definition: MIMXRT1052.h:214
DCDC_IRQn
@ DCDC_IRQn
Definition: MIMXRT1052.h:163
TMR_Type::@317::COMP2
__IO uint16_t COMP2
Definition: MIMXRT1052.h:37381
kXBARA1_OutputEnc4Index
@ kXBARA1_OutputEnc4Index
Definition: MIMXRT1052.h:1166
CMP_Type::DACCR
__IO uint8_t DACCR
Definition: MIMXRT1052.h:8546
DCP_Type::CH3STAT
__IO uint32_t CH3STAT
Definition: MIMXRT1052.h:10346
kXBARB2_InputAdcEtcXbar1Coco1
@ kXBARB2_InputAdcEtcXbar1Coco1
Definition: MIMXRT1052.h:1006
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1052.h:457
XTALOSC24M_Type::OSC_CONFIG0_SET
__IO uint32_t OSC_CONFIG0_SET
Definition: MIMXRT1052.h:45181
LCDIF_Type::BM_ERROR_STAT
__IO uint32_t BM_ERROR_STAT
Definition: MIMXRT1052.h:23549
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:415
kIOMUXC_XBAR1_IN18_SELECT_INPUT
@ kIOMUXC_XBAR1_IN18_SELECT_INPUT
Definition: MIMXRT1052.h:860
DMA_Type::DCHPRI8
__IO uint8_t DCHPRI8
Definition: MIMXRT1052.h:11982
kXBARA1_InputIomuxXbarInout06
@ kXBARA1_InputIomuxXbarInout06
Definition: MIMXRT1052.h:881
ENC_Type::UPOS
__IO uint16_t UPOS
Definition: MIMXRT1052.h:15146
PWM_Type::@314::OCTRL
__IO uint16_t OCTRL
Definition: MIMXRT1052.h:30862
kXBARB2_InputLogicLow
@ kXBARB2_InputLogicLow
Definition: MIMXRT1052.h:963
kXBARA1_InputIomuxXbarIn20
@ kXBARA1_InputIomuxXbarIn20
Definition: MIMXRT1052.h:895
DMA_Type::@304::DLAST_SGA
__IO uint32_t DLAST_SGA
Definition: MIMXRT1052.h:12020
TRNG_Type::@328::SCR2L
__IO uint32_t SCR2L
Definition: MIMXRT1052.h:37902
kXBARA1_OutputQtimer4Tmr2Input
@ kXBARA1_OutputQtimer4Tmr2Input
Definition: MIMXRT1052.h:1183
kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:420
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1052.h:501
USB_Type::HWTXBUF
__I uint32_t HWTXBUF
Definition: MIMXRT1052.h:38998
ENET_Type::ATINC
__IO uint32_t ATINC
Definition: MIMXRT1052.h:15715
kXBARB2_OutputAoi1In08
@ kXBARB2_OutputAoi1In08
Definition: MIMXRT1052.h:1222
PXP_Type::PS_CTRL
__IO uint32_t PS_CTRL
Definition: MIMXRT1052.h:32538
USB_OTG2_IRQn
@ USB_OTG2_IRQn
Definition: MIMXRT1052.h:206
SNVS_Type::HPSVSR
__IO uint32_t HPSVSR
Definition: MIMXRT1052.h:35326
kXBARB3_InputEnc2PosMatch
@ kXBARB3_InputEnc2PosMatch
Definition: MIMXRT1052.h:1068
SAI2_IRQn
@ SAI2_IRQn
Definition: MIMXRT1052.h:151
ADC_ETC_Type::@301::TRIGn_CHAIN_3_2
__IO uint32_t TRIGn_CHAIN_3_2
Definition: MIMXRT1052.h:1626
kIOMUXC_USDHC2_CLK_SELECT_INPUT
@ kIOMUXC_USDHC2_CLK_SELECT_INPUT
Definition: MIMXRT1052.h:839
TEMPMON_Type::TEMPSENSE1_SET
__IO uint32_t TEMPSENSE1_SET
Definition: MIMXRT1052.h:37136
TMR_Type::@317::DMA
__IO uint16_t DMA
Definition: MIMXRT1052.h:37392
LPI2C_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:25098
BEE_Type::CTR_NONCE1_W1
__O uint32_t CTR_NONCE1_W1
Definition: MIMXRT1052.h:3024
kXBARA1_InputFlexpwm4Pwm3OutTrig01
@ kXBARA1_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1052.h:929
kIOMUXC_XBAR1_IN25_SELECT_INPUT
@ kIOMUXC_XBAR1_IN25_SELECT_INPUT
Definition: MIMXRT1052.h:868
kXBARB3_InputFlexpwm2Pwm2OutTrig01
@ kXBARB3_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1052.h:1046
USDHC_Type::HOST_CTRL_CAP
__IO uint32_t HOST_CTRL_CAP
Definition: MIMXRT1052.h:42270
kXBARA1_InputAdcEtcXbar1Coco0
@ kXBARA1_InputAdcEtcXbar1Coco0
Definition: MIMXRT1052.h:959
kXBARA1_InputIomuxXbarInout18
@ kXBARA1_InputIomuxXbarInout18
Definition: MIMXRT1052.h:893
_iomuxc_sw_pad_ctl_pad
_iomuxc_sw_pad_ctl_pad
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Definition: MIMXRT1052.h:580
ENET_Type::RMON_R_P_GTE2048
__I uint32_t RMON_R_P_GTE2048
Definition: MIMXRT1052.h:15700
kDmaRequestMuxLPUART4Rx
@ kDmaRequestMuxLPUART4Rx
Definition: MIMXRT1052.h:370
_iomuxc_select_input
_iomuxc_select_input
Enumeration for the IOMUXC select input.
Definition: MIMXRT1052.h:715
TEMPMON_Type::TEMPSENSE1_TOG
__IO uint32_t TEMPSENSE1_TOG
Definition: MIMXRT1052.h:37138
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1052.h:442
DCP_Type::CH1STAT_CLR
__IO uint32_t CH1STAT_CLR
Definition: MIMXRT1052.h:10324
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14
Definition: MIMXRT1052.h:545
OCOTP_Type::SW_STICKY
__IO uint32_t SW_STICKY
Definition: MIMXRT1052.h:27711
SEMC_Type::DBICR0
__IO uint32_t DBICR0
Definition: MIMXRT1052.h:34154
OCOTP_Type::SRK3
__IO uint32_t SRK3
Definition: MIMXRT1052.h:27760
TSC_Type::DEBUG_MODE2
__IO uint32_t DEBUG_MODE2
Definition: MIMXRT1052.h:38563
CCM_Type::CSR
__I uint32_t CSR
Definition: MIMXRT1052.h:4157
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1052.h:486
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1052.h:648
kXBARA1_InputIomuxXbarInout17
@ kXBARA1_InputIomuxXbarInout17
Definition: MIMXRT1052.h:892
kDmaRequestMuxACMP3
@ kDmaRequestMuxACMP3
Definition: MIMXRT1052.h:332
OCOTP_Type::MEM0
__IO uint32_t MEM0
Definition: MIMXRT1052.h:27738
CAN_Type::@303::WORD1
__IO uint32_t WORD1
Definition: MIMXRT1052.h:3340
GPIO1_INT4_IRQn
@ GPIO1_INT4_IRQn
Definition: MIMXRT1052.h:170
USDHC_Type::VEND_SPEC
__IO uint32_t VEND_SPEC
Definition: MIMXRT1052.h:42282
kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT
Definition: MIMXRT1052.h:757
kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:820
USBPHY_Type::PWD_TOG
__IO uint32_t PWD_TOG
Definition: MIMXRT1052.h:40687
PWM_Type::@314::CAPTCTRLB
__IO uint16_t CAPTCTRLB
Definition: MIMXRT1052.h:30872
TEMPMON_Type::TEMPSENSE1_CLR
__IO uint32_t TEMPSENSE1_CLR
Definition: MIMXRT1052.h:37137
kIOMUXC_CSI_DATA03_SELECT_INPUT
@ kIOMUXC_CSI_DATA03_SELECT_INPUT
Definition: MIMXRT1052.h:721
USB_OTG1_IRQn
@ USB_OTG1_IRQn
Definition: MIMXRT1052.h:207
XBARA_Type::SEL13
__IO uint16_t SEL13
Definition: MIMXRT1052.h:44148
kXBARA1_InputFlexpwm1Pwm1OutTrig01
@ kXBARA1_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1052.h:915
CSU_Type
Definition: MIMXRT1052.h:9469
ADC_ETC_Type::@301::TRIGn_CHAIN_7_6
__IO uint32_t TRIGn_CHAIN_7_6
Definition: MIMXRT1052.h:1628
TRNG_Type::VID2
__I uint32_t VID2
Definition: MIMXRT1052.h:37936
PWM_Type::@314::CVAL0
__I uint16_t CVAL0
Definition: MIMXRT1052.h:30876
ENET_Type::IEEE_T_OCTETS_OK
__I uint32_t IEEE_T_OCTETS_OK
Definition: MIMXRT1052.h:15683
ENET_Type::ATCOR
__IO uint32_t ATCOR
Definition: MIMXRT1052.h:15714
kXBARB3_InputQtimer4Tmr1Output
@ kXBARB3_InputQtimer4Tmr1Output
Definition: MIMXRT1052.h:1038
PMU_Type::REG_3P0_CLR
__IO uint32_t REG_3P0_CLR
Definition: MIMXRT1052.h:28675
PWM3_FAULT_IRQn
@ PWM3_FAULT_IRQn
Definition: MIMXRT1052.h:240
CSI_Type::CSICR19
__IO uint32_t CSICR19
Definition: MIMXRT1052.h:8808
OCOTP_Type::TIMING2
__IO uint32_t TIMING2
Definition: MIMXRT1052.h:27720
kXBARB3_InputAdcEtcXbar1Coco0
@ kXBARB3_InputAdcEtcXbar1Coco0
Definition: MIMXRT1052.h:1063
BEE_Type::REGION1_BOT
__IO uint32_t REGION1_BOT
Definition: MIMXRT1052.h:3028
CCM_ANALOG_Type::PLL_SYS_SET
__IO uint32_t PLL_SYS_SET
Definition: MIMXRT1052.h:6086
CCM_2_IRQn
@ CCM_2_IRQn
Definition: MIMXRT1052.h:190
LPSPI_Type::SR
__IO uint32_t SR
Definition: MIMXRT1052.h:26149
ENET_Type::RMON_T_FRAG
__I uint32_t RMON_T_FRAG
Definition: MIMXRT1052.h:15661
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1052.h:642
kXBARB3_InputAdcEtcXbar1Coco2
@ kXBARB3_InputAdcEtcXbar1Coco2
Definition: MIMXRT1052.h:1065
kIOMUXC_LPSPI4_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI4_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:794
DMA_Type::@304::CSR
__IO uint16_t CSR
Definition: MIMXRT1052.h:12021
ENC_Type::POSD
__IO uint16_t POSD
Definition: MIMXRT1052.h:15142
USDHC_Type::CMD_ARG
__IO uint32_t CMD_ARG
Definition: MIMXRT1052.h:42256
USB_Type::HCCPARAMS
__I uint32_t HCCPARAMS
Definition: MIMXRT1052.h:39011
kDmaRequestMuxSai2Rx
@ kDmaRequestMuxSai2Rx
Definition: MIMXRT1052.h:327
kXBARB3_InputQtimer4Tmr0Output
@ kXBARB3_InputQtimer4Tmr0Output
Definition: MIMXRT1052.h:1037
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1052.h:607
LCDIF_Type::CTRL2_CLR
__IO uint32_t CTRL2_CLR
Definition: MIMXRT1052.h:23529
DCDC_Type::REG2
__IO uint32_t REG2
Definition: MIMXRT1052.h:10087
ENET_Type::RMON_T_COL
__I uint32_t RMON_T_COL
Definition: MIMXRT1052.h:15663
USBPHY_Type::DEBUGr
__IO uint32_t DEBUGr
Definition: MIMXRT1052.h:40702
PXP_Type::STAT_CLR
__IO uint32_t STAT_CLR
Definition: MIMXRT1052.h:32516
OCOTP_Type::ANA0
__IO uint32_t ANA0
Definition: MIMXRT1052.h:27748
ENET_Type::IEEE_T_FDXFC
__I uint32_t IEEE_T_FDXFC
Definition: MIMXRT1052.h:15682
PWM2_3_IRQn
@ PWM2_3_IRQn
Definition: MIMXRT1052.h:234
ENET_Type::GALR
__IO uint32_t GALR
Definition: MIMXRT1052.h:15633
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1052.h:602
kXBARB2_InputFlexpwm3Pwm4OutTrig01
@ kXBARB2_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1052.h:994
XBAR1_IRQ_0_1_IRQn
@ XBAR1_IRQ_0_1_IRQn
Definition: MIMXRT1052.h:210
SPDIF_Type
Definition: MIMXRT1052.h:36416
SPDIF_Type::STCSCL
__IO uint32_t STCSCL
Definition: MIMXRT1052.h:36434
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1052.h:612
FLEXSPI_Type::INTEN
__IO uint32_t INTEN
Definition: MIMXRT1052.h:18094
BusFault_IRQn
@ BusFault_IRQn
Definition: MIMXRT1052.h:86
CCM_ANALOG_Type::PLL_VIDEO_CLR
__IO uint32_t PLL_VIDEO_CLR
Definition: MIMXRT1052.h:6105
__I
#define __I
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:234
DCP_Type::CH3OPTS_TOG
__IO uint32_t CH3OPTS_TOG
Definition: MIMXRT1052.h:10353
PMU_EVENT_IRQn
@ PMU_EVENT_IRQn
Definition: MIMXRT1052.h:155
XBARA_Type::SEL49
__IO uint16_t SEL49
Definition: MIMXRT1052.h:44184
ADC_ETC_Type
Definition: MIMXRT1052.h:1617
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1052.h:592
USB_ANALOG_Type::@342::LOOPBACK_TOG
__IO uint32_t LOOPBACK_TOG
Definition: MIMXRT1052.h:41816
BEE_Type::REGION1_TOP
__IO uint32_t REGION1_TOP
Definition: MIMXRT1052.h:3027
SEMC_Type::SRAMCR3
uint32_t SRAMCR3
Definition: MIMXRT1052.h:34153
PMU_Type::REG_2P5_TOG
__IO uint32_t REG_2P5_TOG
Definition: MIMXRT1052.h:28680
I2S_Type::RCSR
__IO uint32_t RCSR
Definition: MIMXRT1052.h:19882
kDmaRequestMuxQTIMER1CaptTimer1
@ kDmaRequestMuxQTIMER1CaptTimer1
Definition: MIMXRT1052.h:354
kXBARA1_OutputFlexpwm3ExtSync0
@ kXBARA1_OutputFlexpwm3ExtSync0
Definition: MIMXRT1052.h:1135
kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
Definition: MIMXRT1052.h:747
kIOMUXC_XBAR1_IN04_SELECT_INPUT
@ kIOMUXC_XBAR1_IN04_SELECT_INPUT
Definition: MIMXRT1052.h:853
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1052.h:559
SEMC_Type::SRAMCR0
__IO uint32_t SRAMCR0
Definition: MIMXRT1052.h:34150
XBARA_Type::CTRL1
__IO uint16_t CTRL1
Definition: MIMXRT1052.h:44202
CCM_ANALOG_Type::PLL_AUDIO
__IO uint32_t PLL_AUDIO
Definition: MIMXRT1052.h:6095
kXBARA1_OutputIomuxXbarInout04
@ kXBARA1_OutputIomuxXbarInout04
Definition: MIMXRT1052.h:1087
CTI0_ERROR_IRQn
@ CTI0_ERROR_IRQn
Definition: MIMXRT1052.h:111
GPT_Type::PR
__IO uint32_t PR
Definition: MIMXRT1052.h:19579
CCM_Type::CDHIPR
__I uint32_t CDHIPR
Definition: MIMXRT1052.h:4172
OCOTP_Type::CFG2
__IO uint32_t CFG2
Definition: MIMXRT1052.h:27728
SPDIF_Type::STCSCH
__IO uint32_t STCSCH
Definition: MIMXRT1052.h:36433
PWM_Type::@314::INIT
__IO uint16_t INIT
Definition: MIMXRT1052.h:30846
TMR_Type::@317::SCTRL
__IO uint16_t SCTRL
Definition: MIMXRT1052.h:37387
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1052.h:461
DCP_Type::CH3OPTS_CLR
__IO uint32_t CH3OPTS_CLR
Definition: MIMXRT1052.h:10352
LCDIF_Type::LUT0_DATA
__IO uint32_t LUT0_DATA
Definition: MIMXRT1052.h:23582
ENET_Type::RMON_T_CRC_ALIGN
__I uint32_t RMON_T_CRC_ALIGN
Definition: MIMXRT1052.h:15658
DMA_Type::DCHPRI4
__IO uint8_t DCHPRI4
Definition: MIMXRT1052.h:11978
kDmaRequestMuxLPSPI4Rx
@ kDmaRequestMuxLPSPI4Rx
Definition: MIMXRT1052.h:379
DMA_Type::DCHPRI11
__IO uint8_t DCHPRI11
Definition: MIMXRT1052.h:11979
ENET_Type::RSFL
__IO uint32_t RSFL
Definition: MIMXRT1052.h:15641
DMA_Type::DCHPRI18
__IO uint8_t DCHPRI18
Definition: MIMXRT1052.h:11988
PXP_Type::PS_CTRL_CLR
__IO uint32_t PS_CTRL_CLR
Definition: MIMXRT1052.h:32540
kDmaRequestMuxXBAR1Request3
@ kDmaRequestMuxXBAR1Request3
Definition: MIMXRT1052.h:393
kXBARA1_OutputIomuxXbarInout14
@ kXBARA1_OutputIomuxXbarInout14
Definition: MIMXRT1052.h:1097
CCM_Type
Definition: MIMXRT1052.h:4154
kXBARB3_InputFlexpwm3Pwm4OutTrig01
@ kXBARB3_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1052.h:1052
PWM_Type::@314::FRACVAL3
__IO uint16_t FRACVAL3
Definition: MIMXRT1052.h:30855
PGC_Type::CPU_CTRL
__IO uint32_t CPU_CTRL
Definition: MIMXRT1052.h:28379
USBPHY_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1052.h:40712
USDHC_Type::CMD_RSP0
__I uint32_t CMD_RSP0
Definition: MIMXRT1052.h:42258
PWM_Type::@314::CVAL4CYC
__I uint16_t CVAL4CYC
Definition: MIMXRT1052.h:30885
DMA_Type::DCHPRI2
__IO uint8_t DCHPRI2
Definition: MIMXRT1052.h:11972
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13
Definition: MIMXRT1052.h:671
DMA_Type::DCHPRI19
__IO uint8_t DCHPRI19
Definition: MIMXRT1052.h:11987
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1052.h:448
ENC_Type::CTRL2
__IO uint16_t CTRL2
Definition: MIMXRT1052.h:15154
SNVS_Type::HPCOMR
__IO uint32_t HPCOMR
Definition: MIMXRT1052.h:35321
SPDIF_Type::SRL
__I uint32_t SRL
Definition: MIMXRT1052.h:36425
DCP_Type::CH2OPTS_CLR
__IO uint32_t CH2OPTS_CLR
Definition: MIMXRT1052.h:10340
DCP_Type::CH3STAT_TOG
__IO uint32_t CH3STAT_TOG
Definition: MIMXRT1052.h:10349
I2S_Type
Definition: MIMXRT1052.h:19867
ENET_Type::RMON_R_OCTETS
__I uint32_t RMON_R_OCTETS
Definition: MIMXRT1052.h:15701
kXBARA1_InputAdcEtcXbar0Coco3
@ kXBARA1_InputAdcEtcXbar0Coco3
Definition: MIMXRT1052.h:958
CAN_Type::IMASK2
__IO uint32_t IMASK2
Definition: MIMXRT1052.h:3322
SNVS_Type::HPTALR
__IO uint32_t HPTALR
Definition: MIMXRT1052.h:35332
LPI2C_Type::MSR
__IO uint32_t MSR
Definition: MIMXRT1052.h:25099
kXBARA1_InputAoi1Out0
@ kXBARA1_InputAoi1Out0
Definition: MIMXRT1052.h:947
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1052.h:620
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1052.h:485
FLEXSPI_Type::IPTXFSTS
__I uint32_t IPTXFSTS
Definition: MIMXRT1052.h:18120
SPDIF_Type::SRU
__I uint32_t SRU
Definition: MIMXRT1052.h:36429
kDmaRequestMuxLPUART5Rx
@ kDmaRequestMuxLPUART5Rx
Definition: MIMXRT1052.h:315
IOMUXC_SNVS_GPR_Type::GPR2
uint32_t GPR2
Definition: MIMXRT1052.h:23306
XBARB_Type::SEL0
__IO uint16_t SEL0
Definition: MIMXRT1052.h:45034
XBARA_Type::SEL10
__IO uint16_t SEL10
Definition: MIMXRT1052.h:44145
kXBARB3_OutputAoi2In03
@ kXBARB3_OutputAoi2In03
Definition: MIMXRT1052.h:1233
GPIO1_Combined_0_15_IRQn
@ GPIO1_Combined_0_15_IRQn
Definition: MIMXRT1052.h:174
PXP_Type::PS_VBUF
__IO uint32_t PS_VBUF
Definition: MIMXRT1052.h:32546
FLEXIO1_IRQn
@ FLEXIO1_IRQn
Definition: MIMXRT1052.h:184
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
@ kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
Definition: MIMXRT1052.h:739
kXBARB2_InputQtimer4Tmr2Output
@ kXBARB2_InputQtimer4Tmr2Output
Definition: MIMXRT1052.h:981
LPI2C_Type::SAMR
__IO uint32_t SAMR
Definition: MIMXRT1052.h:25127
SNVS_Type::LPSRTCMR
__IO uint32_t LPSRTCMR
Definition: MIMXRT1052.h:35340
kXBARB2_InputFlexpwm3Pwm1OutTrig01
@ kXBARB2_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1052.h:991
LCDIF_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:23521
USDHC_Type::WTMK_LVL
__IO uint32_t WTMK_LVL
Definition: MIMXRT1052.h:42271
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
Definition: MIMXRT1052.h:753
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07
Definition: MIMXRT1052.h:665
DMA_ERROR_IRQn
@ DMA_ERROR_IRQn
Definition: MIMXRT1052.h:110
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1052.h:657
TEMP_PANIC_IRQn
@ TEMP_PANIC_IRQn
Definition: MIMXRT1052.h:158
PXP_Type::OUT_AS_ULC
__IO uint32_t OUT_AS_ULC
Definition: MIMXRT1052.h:32534
OCOTP_Type::SJC_RESP0
__IO uint32_t SJC_RESP0
Definition: MIMXRT1052.h:27770
kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
@ kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
Definition: MIMXRT1052.h:731
TRNG_Type::INT_MASK
__IO uint32_t INT_MASK
Definition: MIMXRT1052.h:37932
kXBARB3_InputDmaDone7
@ kXBARB3_InputDmaDone7
Definition: MIMXRT1052.h:1078
OCOTP_Type::CFG5
__IO uint32_t CFG5
Definition: MIMXRT1052.h:27734
kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT
Definition: MIMXRT1052.h:817
ENC_Type::LPOSH
__I uint16_t LPOSH
Definition: MIMXRT1052.h:15149
CCM_Type::CSCDR2
__IO uint32_t CSCDR2
Definition: MIMXRT1052.h:4169
PXP_Type::PS_UBUF
__IO uint32_t PS_UBUF
Definition: MIMXRT1052.h:32544
kDmaRequestMuxQTIMER2CaptTimer0
@ kDmaRequestMuxQTIMER2CaptTimer0
Definition: MIMXRT1052.h:410
DMA_Type::@304::@307::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
Definition: MIMXRT1052.h:12018
LCDIF_Type::PIGEONCTRL1
__IO uint32_t PIGEONCTRL1
Definition: MIMXRT1052.h:23561
FLEXSPI_Type::AHBCR
__IO uint32_t AHBCR
Definition: MIMXRT1052.h:18093
kDmaRequestMuxEnetTimer1
@ kDmaRequestMuxEnetTimer1
Definition: MIMXRT1052.h:391
kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:418
DMA_Type::DCHPRI9
__IO uint8_t DCHPRI9
Definition: MIMXRT1052.h:11981
ENC_Type::UPOSH
__I uint16_t UPOSH
Definition: MIMXRT1052.h:15148
kIOMUXC_USDHC2_DATA0_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:842
kIOMUXC_LPSPI4_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI4_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:792
kXBARA1_OutputEnc2Index
@ kXBARA1_OutputEnc2Index
Definition: MIMXRT1052.h:1156
ENET_Type::IEEE_T_CSERR
__I uint32_t IEEE_T_CSERR
Definition: MIMXRT1052.h:15680
PWM4_FAULT_IRQn
@ PWM4_FAULT_IRQn
Definition: MIMXRT1052.h:245
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
Definition: MIMXRT1052.h:658
kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:419
DCP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:10273
kIOMUXC_CSI_DATA05_SELECT_INPUT
@ kIOMUXC_CSI_DATA05_SELECT_INPUT
Definition: MIMXRT1052.h:723
kXBARB3_OutputAoi2In02
@ kXBARB3_OutputAoi2In02
Definition: MIMXRT1052.h:1232
GPIO1_Combined_16_31_IRQn
@ GPIO1_Combined_16_31_IRQn
Definition: MIMXRT1052.h:175
PXP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:32511
CSU_IRQn
@ CSU_IRQn
Definition: MIMXRT1052.h:143
kXBARA1_OutputDmaChMuxReq31
@ kXBARA1_OutputDmaChMuxReq31
Definition: MIMXRT1052.h:1084
PMU_Type::MISC1_CLR
__IO uint32_t MISC1_CLR
Definition: MIMXRT1052.h:28691
OCOTP_Type::SJC_RESP1
__IO uint32_t SJC_RESP1
Definition: MIMXRT1052.h:27772
LCDIF_Type::PIGEONCTRL2_SET
__IO uint32_t PIGEONCTRL2_SET
Definition: MIMXRT1052.h:23566
kXBARA1_OutputFlexpwm1ExtSync1
@ kXBARA1_OutputFlexpwm1ExtSync1
Definition: MIMXRT1052.h:1114
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1052.h:589
XBARA_Type::SEL27
__IO uint16_t SEL27
Definition: MIMXRT1052.h:44162
ACMP3_IRQn
@ ACMP3_IRQn
Definition: MIMXRT1052.h:219
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
Definition: MIMXRT1052.h:687
kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT
Definition: MIMXRT1052.h:815
CTI1_ERROR_IRQn
@ CTI1_ERROR_IRQn
Definition: MIMXRT1052.h:112
I2S_Type::RCR3
__IO uint32_t RCR3
Definition: MIMXRT1052.h:19885
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1052.h:494
CMP_Type::CR0
__IO uint8_t CR0
Definition: MIMXRT1052.h:8542
kXBARB2_InputDmaDone5
@ kXBARB2_InputDmaDone5
Definition: MIMXRT1052.h:1018
kXBARA1_InputRESERVED31
@ kXBARA1_InputRESERVED31
Definition: MIMXRT1052.h:906
kXBARB2_InputDmaDone7
@ kXBARB2_InputDmaDone7
Definition: MIMXRT1052.h:1020
PWM_Type::@314::CVAL3
__I uint16_t CVAL3
Definition: MIMXRT1052.h:30882
kXBARA1_InputAdcEtcXbar0Coco1
@ kXBARA1_InputAdcEtcXbar0Coco1
Definition: MIMXRT1052.h:956
kXBARB3_OutputAoi2In13
@ kXBARB3_OutputAoi2In13
Definition: MIMXRT1052.h:1243
CCM_Type::CSCDR1
__IO uint32_t CSCDR1
Definition: MIMXRT1052.h:4164
DMA_Type::ERQ
__IO uint32_t ERQ
Definition: MIMXRT1052.h:11951
LPI2C_Type::MCCR0
__IO uint32_t MCCR0
Definition: MIMXRT1052.h:25109
kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
Definition: MIMXRT1052.h:749
LPI2C_Type::SASR
__I uint32_t SASR
Definition: MIMXRT1052.h:25129
kXBARA1_InputIomuxXbarIn02
@ kXBARA1_InputIomuxXbarIn02
Definition: MIMXRT1052.h:877
kXBARB3_InputAdcEtcXbar1Coco1
@ kXBARB3_InputAdcEtcXbar1Coco1
Definition: MIMXRT1052.h:1064
WDOG1_IRQn
@ WDOG1_IRQn
Definition: MIMXRT1052.h:186
CCM_ANALOG_Type::MISC1_CLR
__IO uint32_t MISC1_CLR
Definition: MIMXRT1052.h:6130
kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT
@ kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:765
SEMC_Type::IPCR1
__IO uint32_t IPCR1
Definition: MIMXRT1052.h:34158
ENET_Type::RAEM
__IO uint32_t RAEM
Definition: MIMXRT1052.h:15643
TSC_Type::INT_SIG_EN
__IO uint32_t INT_SIG_EN
Definition: MIMXRT1052.h:38557
ENET_Type::IEEE_T_MCOL
__I uint32_t IEEE_T_MCOL
Definition: MIMXRT1052.h:15675
kIOMUXC_LPSPI3_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI3_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:788
kDmaRequestMuxFlexPWM4CaptureSub3
@ kDmaRequestMuxFlexPWM4CaptureSub3
Definition: MIMXRT1052.h:405
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1052.h:616
CAN_Type::IFLAG2
__IO uint32_t IFLAG2
Definition: MIMXRT1052.h:3324
SEMC_Type::STS2
__I uint32_t STS2
Definition: MIMXRT1052.h:34167
CCM_Type::CS1CDR
__IO uint32_t CS1CDR
Definition: MIMXRT1052.h:4165
USB_Type::ENDPTSTAT
__I uint32_t ENDPTSTAT
Definition: MIMXRT1052.h:39044
kXBARA1_OutputQtimer2Tmr2Input
@ kXBARA1_OutputQtimer2Tmr2Input
Definition: MIMXRT1052.h:1175
ENET_Type::RMON_R_PACKETS
__I uint32_t RMON_R_PACKETS
Definition: MIMXRT1052.h:15685
kXBARA1_OutputFlexpwm3Fault0
@ kXBARA1_OutputFlexpwm3Fault0
Definition: MIMXRT1052.h:1139
WDOG_Type::WMCR
__IO uint16_t WMCR
Definition: MIMXRT1052.h:43941
PWM_Type::@314::CAPTCOMPB
__IO uint16_t CAPTCOMPB
Definition: MIMXRT1052.h:30873
GPIO_Type::GDIR
__IO uint32_t GDIR
Definition: MIMXRT1052.h:19127
USB_Type::OTGSC
__IO uint32_t OTGSC
Definition: MIMXRT1052.h:39039
kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT
@ kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:767
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1052.h:549
kXBARB2_InputAcmp1Out
@ kXBARB2_InputAcmp1Out
Definition: MIMXRT1052.h:969
PXP_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1052.h:32514
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1052.h:553
CSU_Type::HPCONTROL0
__IO uint32_t HPCONTROL0
Definition: MIMXRT1052.h:9476
kXBARB2_InputFlexpwm1Pwm1OutTrig01
@ kXBARB2_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1052.h:983
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1052.h:441
CCM_ANALOG_Type::MISC2_TOG
__IO uint32_t MISC2_TOG
Definition: MIMXRT1052.h:6135
kIOMUXC_CSI_DATA08_SELECT_INPUT
@ kIOMUXC_CSI_DATA08_SELECT_INPUT
Definition: MIMXRT1052.h:726
DCP_Type::STAT_SET
__IO uint32_t STAT_SET
Definition: MIMXRT1052.h:10275
XBARA_Type::SEL24
__IO uint16_t SEL24
Definition: MIMXRT1052.h:44159
LPSPI_Type::TDR
__O uint32_t TDR
Definition: MIMXRT1052.h:26163
USDHC_Type::PROT_CTRL
__IO uint32_t PROT_CTRL
Definition: MIMXRT1052.h:42264
ENET_Type::MSCR
__IO uint32_t MSCR
Definition: MIMXRT1052.h:15615
LPSPI_Type::FSR
__I uint32_t FSR
Definition: MIMXRT1052.h:26161
XBARA_Type::SEL8
__IO uint16_t SEL8
Definition: MIMXRT1052.h:44143
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1052.h:513
kXBARB3_InputAcmp4Out
@ kXBARB3_InputAcmp4Out
Definition: MIMXRT1052.h:1030
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1052.h:504
kDmaRequestMuxLPSPI4Tx
@ kDmaRequestMuxLPSPI4Tx
Definition: MIMXRT1052.h:380
kXBARA1_OutputEnc2PhaseAInput
@ kXBARA1_OutputEnc2PhaseAInput
Definition: MIMXRT1052.h:1154
SEMC_Type::STS8
uint32_t STS8
Definition: MIMXRT1052.h:34173
CCM_Type::CCGR6
__IO uint32_t CCGR6
Definition: MIMXRT1052.h:4185
USDHC_Type::ADMA_ERR_STATUS
__I uint32_t ADMA_ERR_STATUS
Definition: MIMXRT1052.h:42275
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1052.h:552
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1052.h:459
CAN_Type::@303::WORD0
__IO uint32_t WORD0
Definition: MIMXRT1052.h:3339
DCP_Type::CH2STAT
__IO uint32_t CH2STAT
Definition: MIMXRT1052.h:10334
DMA_Type::EEI
__IO uint32_t EEI
Definition: MIMXRT1052.h:11953
IOMUXC_GPR_Type
Definition: MIMXRT1052.h:20857
kDmaRequestMuxFlexPWM3CaptureSub2
@ kDmaRequestMuxFlexPWM3CaptureSub2
Definition: MIMXRT1052.h:347
kXBARB3_OutputAoi2In05
@ kXBARB3_OutputAoi2In05
Definition: MIMXRT1052.h:1235
ACMP2_IRQn
@ ACMP2_IRQn
Definition: MIMXRT1052.h:218
kXBARA1_OutputFlexpwm1ExtSync0
@ kXBARA1_OutputFlexpwm1ExtSync0
Definition: MIMXRT1052.h:1113
kXBARA1_InputAoi2Out1
@ kXBARA1_InputAoi2Out1
Definition: MIMXRT1052.h:952
TEMPMON_Type::TEMPSENSE2
__IO uint32_t TEMPSENSE2
Definition: MIMXRT1052.h:37140
ENC_Type::REVH
__I uint16_t REVH
Definition: MIMXRT1052.h:15145
kDmaRequestMuxLPUART2Rx
@ kDmaRequestMuxLPUART2Rx
Definition: MIMXRT1052.h:368
ADC_Type::GC
__IO uint32_t GC
Definition: MIMXRT1052.h:1301
CCM_ANALOG_Type::PLL_SYS_SS
__IO uint32_t PLL_SYS_SS
Definition: MIMXRT1052.h:6089
kXBARA1_InputIomuxXbarInout14
@ kXBARA1_InputIomuxXbarInout14
Definition: MIMXRT1052.h:889
kXBARB2_InputPitTrigger1
@ kXBARB2_InputPitTrigger1
Definition: MIMXRT1052.h:1000
IOMUXC_GPR_Type::GPR17
__IO uint32_t GPR17
Definition: MIMXRT1052.h:20875
CCM_ANALOG_Type::MISC1_TOG
__IO uint32_t MISC1_TOG
Definition: MIMXRT1052.h:6131
kXBARA1_InputLogicHigh
@ kXBARA1_InputLogicHigh
Definition: MIMXRT1052.h:876
kXBARB3_InputFlexpwm2Pwm3OutTrig01
@ kXBARB3_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1052.h:1047
PWM_Type::OUTEN
__IO uint16_t OUTEN
Definition: MIMXRT1052.h:30890
FLEXIO_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:17367
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1052.h:491
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1052.h:611
kXBARB3_InputRESERVED11
@ kXBARB3_InputRESERVED11
Definition: MIMXRT1052.h:1032
DMA_Type::DCHPRI24
__IO uint8_t DCHPRI24
Definition: MIMXRT1052.h:11998
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
Definition: MIMXRT1052.h:533
GPIO_Type::EDGE_SEL
__IO uint32_t EDGE_SEL
Definition: MIMXRT1052.h:19133
LCDIF_Type::PIGEONCTRL2_TOG
__IO uint32_t PIGEONCTRL2_TOG
Definition: MIMXRT1052.h:23568
OCOTP_Type::SCS_CLR
__IO uint32_t SCS_CLR
Definition: MIMXRT1052.h:27715
TSC_DIG_IRQn
@ TSC_DIG_IRQn
Definition: MIMXRT1052.h:134
kIOMUXC_XBAR1_IN14_SELECT_INPUT
@ kIOMUXC_XBAR1_IN14_SELECT_INPUT
Definition: MIMXRT1052.h:865
DMA_Type::DCHPRI26
__IO uint8_t DCHPRI26
Definition: MIMXRT1052.h:11996
kIOMUXC_ENET_MDIO_SELECT_INPUT
@ kIOMUXC_ENET_MDIO_SELECT_INPUT
Definition: MIMXRT1052.h:732
XTALOSC24M_Type::OSC_CONFIG1
__IO uint32_t OSC_CONFIG1
Definition: MIMXRT1052.h:45184
TEMPMON_Type::TEMPSENSE0_CLR
__IO uint32_t TEMPSENSE0_CLR
Definition: MIMXRT1052.h:37133
_xbar_input_signal
_xbar_input_signal
Definition: MIMXRT1052.h:873
PWM_Type::@314::CVAL3CYC
__I uint16_t CVAL3CYC
Definition: MIMXRT1052.h:30883
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
Definition: MIMXRT1052.h:543
DCP_Type::CH1STAT
__IO uint32_t CH1STAT
Definition: MIMXRT1052.h:10322
CCM_ANALOG_Type::PLL_VIDEO_TOG
__IO uint32_t PLL_VIDEO_TOG
Definition: MIMXRT1052.h:6106
USB_Type::ENDPTFLUSH
__IO uint32_t ENDPTFLUSH
Definition: MIMXRT1052.h:39043
CCM_Type::CCGR5
__IO uint32_t CCGR5
Definition: MIMXRT1052.h:4184
kXBARA1_InputIomuxXbarIn03
@ kXBARA1_InputIomuxXbarIn03
Definition: MIMXRT1052.h:878
CCM_Type::CBCDR
__IO uint32_t CBCDR
Definition: MIMXRT1052.h:4160
kXBARA1_InputQtimer4Tmr3Output
@ kXBARA1_InputQtimer4Tmr3Output
Definition: MIMXRT1052.h:914
KPP_Type::KPCR
__IO uint16_t KPCR
Definition: MIMXRT1052.h:23378
CAN_Type::DBG1
__I uint32_t DBG1
Definition: MIMXRT1052.h:3333
CAN_Type::TIMER
__IO uint32_t TIMER
Definition: MIMXRT1052.h:3315
CAN_Type::IMASK1
__IO uint32_t IMASK1
Definition: MIMXRT1052.h:3323
kXBARB2_InputFlexpwm3Pwm3OutTrig01
@ kXBARB2_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1052.h:993
LCDIF_Type::@312::PIGEON_1
__IO uint32_t PIGEON_1
Definition: MIMXRT1052.h:23573
PIT_Type::LTMR64H
__I uint32_t LTMR64H
Definition: MIMXRT1052.h:28512
kIOMUXC_ENET_RXERR_SELECT_INPUT
@ kIOMUXC_ENET_RXERR_SELECT_INPUT
Definition: MIMXRT1052.h:736
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1052.h:464
CCM_ANALOG_Type::PLL_ENET_CLR
__IO uint32_t PLL_ENET_CLR
Definition: MIMXRT1052.h:6113
TMR_Type::@317::CMPLD2
__IO uint16_t CMPLD2
Definition: MIMXRT1052.h:37389
WDOG_Type::WRSR
__I uint16_t WRSR
Definition: MIMXRT1052.h:43939
PXP_Type::AS_BUF
__IO uint32_t AS_BUF
Definition: MIMXRT1052.h:32562
_xbar_output_signal
_xbar_output_signal
Definition: MIMXRT1052.h:1081
TRNG_Type::@330::SCR3C
__I uint32_t SCR3C
Definition: MIMXRT1052.h:37905
kXBARA1_InputDmaDone6
@ kXBARA1_InputDmaDone6
Definition: MIMXRT1052.h:945
PIT_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:28510
PXP_Type::OUT_CTRL_TOG
__IO uint32_t OUT_CTRL_TOG
Definition: MIMXRT1052.h:32521
SEMC_Type::NORCR2
__IO uint32_t NORCR2
Definition: MIMXRT1052.h:34148
PMU_Type::REG_2P5_SET
__IO uint32_t REG_2P5_SET
Definition: MIMXRT1052.h:28678
LPI2C_Type::MCFGR1
__IO uint32_t MCFGR1
Definition: MIMXRT1052.h:25103
CCM_ANALOG_Type::MISC2_CLR
__IO uint32_t MISC2_CLR
Definition: MIMXRT1052.h:6134
XBARA_Type::SEL56
__IO uint16_t SEL56
Definition: MIMXRT1052.h:44191
kXBARA1_OutputLpuart8TrgInput
@ kXBARA1_OutputLpuart8TrgInput
Definition: MIMXRT1052.h:1209
kDmaRequestMuxADC1
@ kDmaRequestMuxADC1
Definition: MIMXRT1052.h:330
kXBARA1_OutputFlexpwm1Exta1
@ kXBARA1_OutputFlexpwm1Exta1
Definition: MIMXRT1052.h:1110
kIOMUXC_CSI_DATA09_SELECT_INPUT
@ kIOMUXC_CSI_DATA09_SELECT_INPUT
Definition: MIMXRT1052.h:727
LCDIF_Type::CUR_BUF
__IO uint32_t CUR_BUF
Definition: MIMXRT1052.h:23533
kXBARB3_InputPitTrigger1
@ kXBARB3_InputPitTrigger1
Definition: MIMXRT1052.h:1058
IOMUXC_GPR_Type::GPR15
uint32_t GPR15
Definition: MIMXRT1052.h:20873
CAN_Type::RXMGMASK
__IO uint32_t RXMGMASK
Definition: MIMXRT1052.h:3317
DCP_Type::CH1STAT_SET
__IO uint32_t CH1STAT_SET
Definition: MIMXRT1052.h:10323
OCOTP_Type::DATA
__IO uint32_t DATA
Definition: MIMXRT1052.h:27705
GPT1_IRQn
@ GPT1_IRQn
Definition: MIMXRT1052.h:194
LPUART_Type::MATCH
__IO uint32_t MATCH
Definition: MIMXRT1052.h:26780
SNVS_HP_WRAPPER_IRQn
@ SNVS_HP_WRAPPER_IRQn
Definition: MIMXRT1052.h:140
FLEXSPI_Type
Definition: MIMXRT1052.h:18089
kXBARB2_OutputAoi1In12
@ kXBARB2_OutputAoi1In12
Definition: MIMXRT1052.h:1226
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:358
XBARA_Type::SEL60
__IO uint16_t SEL60
Definition: MIMXRT1052.h:44195
kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
Definition: MIMXRT1052.h:756
FLEXIO_Type::TIMIEN
__IO uint32_t TIMIEN
Definition: MIMXRT1052.h:17377
XTALOSC24M_Type::OSC_CONFIG1_SET
__IO uint32_t OSC_CONFIG1_SET
Definition: MIMXRT1052.h:45185
DCP_Type::CH1OPTS
__IO uint32_t CH1OPTS
Definition: MIMXRT1052.h:10326
GPIO_Type::DR
__IO uint32_t DR
Definition: MIMXRT1052.h:19126
RTWDOG_Type::TOVAL
__IO uint32_t TOVAL
Definition: MIMXRT1052.h:33930
PMU_Type::REG_1P1_SET
__IO uint32_t REG_1P1_SET
Definition: MIMXRT1052.h:28670
DCP_Type::CH0STAT_SET
__IO uint32_t CH0STAT_SET
Definition: MIMXRT1052.h:10311
Reserved144_IRQn
@ Reserved144_IRQn
Definition: MIMXRT1052.h:222
XBARA_Type::SEL26
__IO uint16_t SEL26
Definition: MIMXRT1052.h:44161
kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
Definition: MIMXRT1052.h:742
IOMUXC_GPR_Type::GPR8
__IO uint32_t GPR8
Definition: MIMXRT1052.h:20866
kXBARA1_OutputFlexpwm234Exta0
@ kXBARA1_OutputFlexpwm234Exta0
Definition: MIMXRT1052.h:1123
DMA_Type::DCHPRI1
__IO uint8_t DCHPRI1
Definition: MIMXRT1052.h:11973
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1052.h:637
DMA_Type::DCHPRI22
__IO uint8_t DCHPRI22
Definition: MIMXRT1052.h:11992
ADC_ETC_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:1618
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1052.h:595
XBARA_Type::SEL15
__IO uint16_t SEL15
Definition: MIMXRT1052.h:44150
USDHC_Type::DATA_BUFF_ACC_PORT
__IO uint32_t DATA_BUFF_ACC_PORT
Definition: MIMXRT1052.h:42262
kXBARB3_OutputAoi2In08
@ kXBARB3_OutputAoi2In08
Definition: MIMXRT1052.h:1238
kDmaRequestMuxLCDIF
@ kDmaRequestMuxLCDIF
Definition: MIMXRT1052.h:376
TRNG_Type::SDCTL
__IO uint32_t SDCTL
Definition: MIMXRT1052.h:37882
kDmaRequestMuxLPSPI3Tx
@ kDmaRequestMuxLPSPI3Tx
Definition: MIMXRT1052.h:322
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
Definition: MIMXRT1052.h:531
kXBARA1_OutputQtimer1Tmr2Input
@ kXBARA1_OutputQtimer1Tmr2Input
Definition: MIMXRT1052.h:1171
SNVS_Type::LPTDCR
__IO uint32_t LPTDCR
Definition: MIMXRT1052.h:35338
DMA_Type::@304::DADDR
__IO uint32_t DADDR
Definition: MIMXRT1052.h:12014
kDmaRequestMuxFlexPWM4ValueSub3
@ kDmaRequestMuxFlexPWM4ValueSub3
Definition: MIMXRT1052.h:409
IOMUXC_GPR_Type::GPR12
__IO uint32_t GPR12
Definition: MIMXRT1052.h:20870
kDmaRequestMuxQTIMER2CaptTimer1
@ kDmaRequestMuxQTIMER2CaptTimer1
Definition: MIMXRT1052.h:411
TRNG_Type::@336::SCR6PL
__IO uint32_t SCR6PL
Definition: MIMXRT1052.h:37918
TRNG_Type::@318::PKRMAX
__IO uint32_t PKRMAX
Definition: MIMXRT1052.h:37879
LPI2C_Type::MCCR1
__IO uint32_t MCCR1
Definition: MIMXRT1052.h:25111
ENET_Type::RMON_T_OCTETS
__I uint32_t RMON_T_OCTETS
Definition: MIMXRT1052.h:15671
kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT
@ kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT
Definition: MIMXRT1052.h:761
ENET_Type::@311::TCCR
__IO uint32_t TCCR
Definition: MIMXRT1052.h:15721
IOMUXC_GPR_Type::GPR11
__IO uint32_t GPR11
Definition: MIMXRT1052.h:20869
ROMC_Type::ROMPATCHSR
__IO uint32_t ROMPATCHSR
Definition: MIMXRT1052.h:33809
FLEXSPI_Type::LUTKEY
__IO uint32_t LUTKEY
Definition: MIMXRT1052.h:18096
ENET_Type::RXIC
__IO uint32_t RXIC
Definition: MIMXRT1052.h:15628
USDHC_Type::CMD_RSP2
__I uint32_t CMD_RSP2
Definition: MIMXRT1052.h:42260
kXBARB2_InputAdcEtcXbar0Coco1
@ kXBARB2_InputAdcEtcXbar0Coco1
Definition: MIMXRT1052.h:1002
kIOMUXC_USDHC2_DATA4_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA4_SELECT_INPUT
Definition: MIMXRT1052.h:846
CCM_ANALOG_Type::PLL_SYS_DENOM
__IO uint32_t PLL_SYS_DENOM
Definition: MIMXRT1052.h:6093
CAN_Type::ESR1
__IO uint32_t ESR1
Definition: MIMXRT1052.h:3321
USB_Type::PORTSC1
__IO uint32_t PORTSC1
Definition: MIMXRT1052.h:39037
TMR_Type::@317::LOAD
__IO uint16_t LOAD
Definition: MIMXRT1052.h:37383
IOMUXC_SNVS_Type
Definition: MIMXRT1052.h:22795
CAN_Type
Definition: MIMXRT1052.h:3312
ENET_Type::ATOFF
__IO uint32_t ATOFF
Definition: MIMXRT1052.h:15712
USBPHY_Type::DEBUG1_TOG
__IO uint32_t DEBUG1_TOG
Definition: MIMXRT1052.h:40711
OCOTP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:27702
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1052.h:474
OCOTP_Type::MEM4
__IO uint32_t MEM4
Definition: MIMXRT1052.h:27746
XBARA_Type::SEL57
__IO uint16_t SEL57
Definition: MIMXRT1052.h:44192
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
Definition: MIMXRT1052.h:677
ENET_Type::RMON_T_P65TO127
__I uint32_t RMON_T_P65TO127
Definition: MIMXRT1052.h:15665
USB_ANALOG_Type::@342::VBUS_DETECT_STAT
__I uint32_t VBUS_DETECT_STAT
Definition: MIMXRT1052.h:41809
TMR_Type::@317::CMPLD1
__IO uint16_t CMPLD1
Definition: MIMXRT1052.h:37388
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1052.h:487
GPT_Type
Definition: MIMXRT1052.h:19577
SNVS_Type::HPCR
__IO uint32_t HPCR
Definition: MIMXRT1052.h:35322
USDHC_Type::INT_STATUS_EN
__IO uint32_t INT_STATUS_EN
Definition: MIMXRT1052.h:42267
USB_ANALOG_Type::@342::MISC_TOG
__IO uint32_t MISC_TOG
Definition: MIMXRT1052.h:41820
kIOMUXC_LPSPI3_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI3_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:790
DCP_Type::CHANNELCTRL_TOG
__IO uint32_t CHANNELCTRL_TOG
Definition: MIMXRT1052.h:10281
CCM_ANALOG_Type::PLL_ARM_TOG
__IO uint32_t PLL_ARM_TOG
Definition: MIMXRT1052.h:6076
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:91
CCM_ANALOG_Type::MISC1
__IO uint32_t MISC1
Definition: MIMXRT1052.h:6128
PGC_Type::CPU_SR
__IO uint32_t CPU_SR
Definition: MIMXRT1052.h:28382
kIOMUXC_SAI2_MCLK2_SELECT_INPUT
@ kIOMUXC_SAI2_MCLK2_SELECT_INPUT
Definition: MIMXRT1052.h:828
kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:826
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1052.h:500
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
Definition: MIMXRT1052.h:518
kXBARA1_InputIomuxXbarInout08
@ kXBARA1_InputIomuxXbarInout08
Definition: MIMXRT1052.h:883
PWM_Type::@314::CVAL0CYC
__I uint16_t CVAL0CYC
Definition: MIMXRT1052.h:30877
xbar_output_signal_t
enum _xbar_output_signal xbar_output_signal_t
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1052.h:656
BEE_IRQn
@ BEE_IRQn
Definition: MIMXRT1052.h:149
LPI2C_Type::MDER
__IO uint32_t MDER
Definition: MIMXRT1052.h:25101
ENET_Type::OPD
__IO uint32_t OPD
Definition: MIMXRT1052.h:15625
OCOTP_Type::SW_GP21
__IO uint32_t SW_GP21
Definition: MIMXRT1052.h:27788
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1052.h:627
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1052.h:550
SEMC_Type::SRAMCR1
__IO uint32_t SRAMCR1
Definition: MIMXRT1052.h:34151
ENC_Type::LMOD
__IO uint16_t LMOD
Definition: MIMXRT1052.h:15156
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1052.h:503
DMA7_DMA23_IRQn
@ DMA7_DMA23_IRQn
Definition: MIMXRT1052.h:101
kIOMUXC_USDHC2_DATA5_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA5_SELECT_INPUT
Definition: MIMXRT1052.h:847
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14
Definition: MIMXRT1052.h:529
SEMC_Type::IPRXDAT
__I uint32_t IPRXDAT
Definition: MIMXRT1052.h:34163
GPT_Type::IR
__IO uint32_t IR
Definition: MIMXRT1052.h:19581
TSC_Type::PRE_CHARGE_TIME
__IO uint32_t PRE_CHARGE_TIME
Definition: MIMXRT1052.h:38549
PXP_Type::PS_CTRL_SET
__IO uint32_t PS_CTRL_SET
Definition: MIMXRT1052.h:32539
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1052.h:652
DMA_Type::@304::@305::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
Definition: MIMXRT1052.h:12011
DMA0_DMA16_IRQn
@ DMA0_DMA16_IRQn
Definition: MIMXRT1052.h:94
SEMC_IRQn
@ SEMC_IRQn
Definition: MIMXRT1052.h:203
XBARA_Type::SEL61
__IO uint16_t SEL61
Definition: MIMXRT1052.h:44196
DMA_Type::DCHPRI17
__IO uint8_t DCHPRI17
Definition: MIMXRT1052.h:11989
CCM_Type::CBCMR
__IO uint32_t CBCMR
Definition: MIMXRT1052.h:4161
kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT
@ kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:766
kIOMUXC_USDHC2_CD_B_SELECT_INPUT
@ kIOMUXC_USDHC2_CD_B_SELECT_INPUT
Definition: MIMXRT1052.h:840
PXP_Type::STAT_SET
__IO uint32_t STAT_SET
Definition: MIMXRT1052.h:32515
kXBARB2_OutputAoi1In07
@ kXBARB2_OutputAoi1In07
Definition: MIMXRT1052.h:1221
kDmaRequestMuxFlexIO1Request0Request1
@ kDmaRequestMuxFlexIO1Request0Request1
Definition: MIMXRT1052.h:308
kXBARB3_InputFlexpwm4Pwm1OutTrig01
@ kXBARB3_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1052.h:1053
kXBARB3_InputDmaDone5
@ kXBARB3_InputDmaDone5
Definition: MIMXRT1052.h:1076
kXBARB2_InputEnc4PosMatch
@ kXBARB2_InputEnc4PosMatch
Definition: MIMXRT1052.h:1012
WDOG_Type::WSR
__IO uint16_t WSR
Definition: MIMXRT1052.h:43938
LCDIF_Type::LUT1_DATA
__IO uint32_t LUT1_DATA
Definition: MIMXRT1052.h:23586
PMU_Type::MISC1_TOG
__IO uint32_t MISC1_TOG
Definition: MIMXRT1052.h:28692
kXBARA1_OutputFlexio1TriggerIn1
@ kXBARA1_OutputFlexio1TriggerIn1
Definition: MIMXRT1052.h:1211
kXBARB3_InputFlexpwm2Pwm1OutTrig01
@ kXBARB3_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1052.h:1045
ENET_Type::TDAR
__IO uint32_t TDAR
Definition: MIMXRT1052.h:15610
kXBARB2_InputAdcEtcXbar1Coco0
@ kXBARB2_InputAdcEtcXbar1Coco0
Definition: MIMXRT1052.h:1005
LCDIF_Type::LUT0_ADDR
__IO uint32_t LUT0_ADDR
Definition: MIMXRT1052.h:23580
kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:823
XTALOSC24M_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1052.h:45173
ENET_Type::ATPER
__IO uint32_t ATPER
Definition: MIMXRT1052.h:15713
kXBARB3_OutputAoi2In10
@ kXBARB3_OutputAoi2In10
Definition: MIMXRT1052.h:1240
GPC_Type::CNTR
__IO uint32_t CNTR
Definition: MIMXRT1052.h:18997
FLEXSPI_Type::IPRXFSTS
__I uint32_t IPRXFSTS
Definition: MIMXRT1052.h:18119
USB_Type::ID
__I uint32_t ID
Definition: MIMXRT1052.h:38994
OCOTP_Type::SCS_SET
__IO uint32_t SCS_SET
Definition: MIMXRT1052.h:27714
FLEXSPI_Type::IPRXFCR
__IO uint32_t IPRXFCR
Definition: MIMXRT1052.h:18111
OCOTP_Type::MEM3
__IO uint32_t MEM3
Definition: MIMXRT1052.h:27744
kXBARB2_InputPitTrigger0
@ kXBARB2_InputPitTrigger0
Definition: MIMXRT1052.h:999
LPSPI_Type::CFGR0
__IO uint32_t CFGR0
Definition: MIMXRT1052.h:26152
IOMUXC_GPR_Type::GPR23
__IO uint32_t GPR23
Definition: MIMXRT1052.h:20881
kXBARB3_InputFlexpwm1Pwm4OutTrig01
@ kXBARB3_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1052.h:1044
CAN_Type::@303::ID
__IO uint32_t ID
Definition: MIMXRT1052.h:3338
kIOMUXC_USDHC2_DATA2_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:844
SNVS_Type::HPVIDR1
__I uint32_t HPVIDR1
Definition: MIMXRT1052.h:35353
DCP_Type::CH1SEMA
__IO uint32_t CH1SEMA
Definition: MIMXRT1052.h:10320
TRNG_Type::PKRRNG
__IO uint32_t PKRRNG
Definition: MIMXRT1052.h:37877
LPI2C_Type::MTDR
__O uint32_t MTDR
Definition: MIMXRT1052.h:25115
PGC_Type::MEGA_PUPSCR
__IO uint32_t MEGA_PUPSCR
Definition: MIMXRT1052.h:28375
CCM_ANALOG_Type::PLL_ARM
__IO uint32_t PLL_ARM
Definition: MIMXRT1052.h:6073
PMU_Type::MISC2_SET
__IO uint32_t MISC2_SET
Definition: MIMXRT1052.h:28694
CCM_ANALOG_Type::PFD_528_SET
__IO uint32_t PFD_528_SET
Definition: MIMXRT1052.h:6120
SEMC_Type::INTEN
__IO uint32_t INTEN
Definition: MIMXRT1052.h:34136
XBARB_Type::SEL3
__IO uint16_t SEL3
Definition: MIMXRT1052.h:45037
USBPHY_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:40696
kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:364
FLEXSPI_Type::STS2
__I uint32_t STS2
Definition: MIMXRT1052.h:18117
OCOTP_Type::CFG0
__IO uint32_t CFG0
Definition: MIMXRT1052.h:27724
kXBARA1_OutputIomuxXbarInout15
@ kXBARA1_OutputIomuxXbarInout15
Definition: MIMXRT1052.h:1098
TRNG_Type
Definition: MIMXRT1052.h:37874
XBARA_Type::SEL6
__IO uint16_t SEL6
Definition: MIMXRT1052.h:44141
ENC_Type::LCOMP
__IO uint16_t LCOMP
Definition: MIMXRT1052.h:15158
kIOMUXC_LPUART3_CTS_B_SELECT_INPUT
@ kIOMUXC_LPUART3_CTS_B_SELECT_INPUT
Definition: MIMXRT1052.h:797
ENET_Type::IAUR
__IO uint32_t IAUR
Definition: MIMXRT1052.h:15630
kDmaRequestMuxFlexIO2Request0Request1
@ kDmaRequestMuxFlexIO2Request0Request1
Definition: MIMXRT1052.h:309
CAN_Type::CTRL2
__IO uint32_t CTRL2
Definition: MIMXRT1052.h:3326
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04
Definition: MIMXRT1052.h:519
DMA13_DMA29_IRQn
@ DMA13_DMA29_IRQn
Definition: MIMXRT1052.h:107
PMU_Type::REG_2P5
__IO uint32_t REG_2P5
Definition: MIMXRT1052.h:28677
LCDIF_Type::TRANSFER_COUNT
__IO uint32_t TRANSFER_COUNT
Definition: MIMXRT1052.h:23531
DCP_Type::CH0STAT
__IO uint32_t CH0STAT
Definition: MIMXRT1052.h:10310
XBARA_Type::SEL4
__IO uint16_t SEL4
Definition: MIMXRT1052.h:44139
EWM_Type::CTRL
__IO uint8_t CTRL
Definition: MIMXRT1052.h:17247
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
Definition: MIMXRT1052.h:668
DMA_Type::DCHPRI30
__IO uint8_t DCHPRI30
Definition: MIMXRT1052.h:12000
USB_ANALOG_Type
Definition: MIMXRT1052.h:41798
DCP_Type::STAT_TOG
__IO uint32_t STAT_TOG
Definition: MIMXRT1052.h:10277
kXBARA1_OutputFlexpwm1234Fault3
@ kXBARA1_OutputFlexpwm1234Fault3
Definition: MIMXRT1052.h:1121
EWM_Type::SERV
__O uint8_t SERV
Definition: MIMXRT1052.h:17248
kDmaRequestMuxSai1Tx
@ kDmaRequestMuxSai1Tx
Definition: MIMXRT1052.h:326
LPUART1_IRQn
@ LPUART1_IRQn
Definition: MIMXRT1052.h:114
FLEXSPI_Type::IPCR0
__IO uint32_t IPCR0
Definition: MIMXRT1052.h:18106
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
Definition: MIMXRT1052.h:516
kDmaRequestMuxFlexSPIRx
@ kDmaRequestMuxFlexSPIRx
Definition: MIMXRT1052.h:333
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1052.h:493
kDmaRequestMuxSai2Tx
@ kDmaRequestMuxSai2Tx
Definition: MIMXRT1052.h:328
kIOMUXC_XBAR1_IN21_SELECT_INPUT
@ kIOMUXC_XBAR1_IN21_SELECT_INPUT
Definition: MIMXRT1052.h:870
ENET_Type::MMFR
__IO uint32_t MMFR
Definition: MIMXRT1052.h:15614
kXBARA1_OutputDmaChMuxReq94
@ kXBARA1_OutputDmaChMuxReq94
Definition: MIMXRT1052.h:1085
kXBARA1_OutputFlexpwm2ExtSync2
@ kXBARA1_OutputFlexpwm2ExtSync2
Definition: MIMXRT1052.h:1129
PWM4_2_IRQn
@ PWM4_2_IRQn
Definition: MIMXRT1052.h:243
SEMC_Type::NORCR1
__IO uint32_t NORCR1
Definition: MIMXRT1052.h:34147
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1052.h:644
SPDIF_Type::SRCSH
__I uint32_t SRCSH
Definition: MIMXRT1052.h:36427
kIOMUXC_XBAR1_IN20_SELECT_INPUT
@ kIOMUXC_XBAR1_IN20_SELECT_INPUT
Definition: MIMXRT1052.h:861
CCM_Type::CSCDR3
__IO uint32_t CSCDR3
Definition: MIMXRT1052.h:4170
DCP_Type::DBGDATA
__I uint32_t DBGDATA
Definition: MIMXRT1052.h:10357
USBPHY_Type::TX_TOG
__IO uint32_t TX_TOG
Definition: MIMXRT1052.h:40691
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1052.h:444
ENC3_IRQn
@ ENC3_IRQn
Definition: MIMXRT1052.h:225
kXBARB3_InputAdcEtcXbar0Coco3
@ kXBARB3_InputAdcEtcXbar0Coco3
Definition: MIMXRT1052.h:1062
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
Definition: MIMXRT1052.h:675
SPDIF_Type::STC
__IO uint32_t STC
Definition: MIMXRT1052.h:36438
DMA8_DMA24_IRQn
@ DMA8_DMA24_IRQn
Definition: MIMXRT1052.h:102
CCM_ANALOG_Type::PLL_AUDIO_DENOM
__IO uint32_t PLL_AUDIO_DENOM
Definition: MIMXRT1052.h:6101
PWM3_1_IRQn
@ PWM3_1_IRQn
Definition: MIMXRT1052.h:237
USB_Type::GPTIMER1LD
__IO uint32_t GPTIMER1LD
Definition: MIMXRT1052.h:39003
kXBARA1_OutputIomuxXbarInout06
@ kXBARA1_OutputIomuxXbarInout06
Definition: MIMXRT1052.h:1089
kXBARA1_OutputAdcEtcXbar1Trig2
@ kXBARA1_OutputAdcEtcXbar1Trig2
Definition: MIMXRT1052.h:1192
XTALOSC24M_Type::OSC_CONFIG2
__IO uint32_t OSC_CONFIG2
Definition: MIMXRT1052.h:45188
ADC_Type::OFS
__IO uint32_t OFS
Definition: MIMXRT1052.h:1304
XBARA_Type::SEL42
__IO uint16_t SEL42
Definition: MIMXRT1052.h:44177
SEMC_Type::DBICR1
__IO uint32_t DBICR1
Definition: MIMXRT1052.h:34155
LCDIF_Type::PIGEONCTRL0_TOG
__IO uint32_t PIGEONCTRL0_TOG
Definition: MIMXRT1052.h:23560
ENET_Type::TIPG
__IO uint32_t TIPG
Definition: MIMXRT1052.h:15648
ENET_Type::TSEM
__IO uint32_t TSEM
Definition: MIMXRT1052.h:15645
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
Definition: MIMXRT1052.h:669
ENET_Type::IEEE_T_FRAME_OK
__I uint32_t IEEE_T_FRAME_OK
Definition: MIMXRT1052.h:15673
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:417
CSI_Type::CSIDMASA_FB2
__IO uint32_t CSIDMASA_FB2
Definition: MIMXRT1052.h:8803
TRNG_Type::@326::SCR1C
__I uint32_t SCR1C
Definition: MIMXRT1052.h:37897
kXBARB3_InputQtimer4Tmr2Output
@ kXBARB3_InputQtimer4Tmr2Output
Definition: MIMXRT1052.h:1039
kXBARA1_OutputLpuart6TrgInput
@ kXBARA1_OutputLpuart6TrgInput
Definition: MIMXRT1052.h:1207
kXBARB2_InputFlexpwm1Pwm3OutTrig01
@ kXBARB2_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1052.h:985
CSI_Type::CSIFBUF_PARA
__IO uint32_t CSIFBUF_PARA
Definition: MIMXRT1052.h:8804
kIOMUXC_LPUART3_TX_SELECT_INPUT
@ kIOMUXC_LPUART3_TX_SELECT_INPUT
Definition: MIMXRT1052.h:799
LCDIF_Type::CTRL2_SET
__IO uint32_t CTRL2_SET
Definition: MIMXRT1052.h:23528
USBPHY_Type::PWD
__IO uint32_t PWD
Definition: MIMXRT1052.h:40684
kDmaRequestMuxFlexPWM2ValueSub2
@ kDmaRequestMuxFlexPWM2ValueSub2
Definition: MIMXRT1052.h:400
kXBARA1_InputIomuxXbarIn25
@ kXBARA1_InputIomuxXbarIn25
Definition: MIMXRT1052.h:900
kXBARB3_InputRESERVED10
@ kXBARB3_InputRESERVED10
Definition: MIMXRT1052.h:1031
PendSV_IRQn
@ PendSV_IRQn
Definition: MIMXRT1052.h:90
kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT
Definition: MIMXRT1052.h:759
USBNC_Type::USB_OTGn_CTRL
__IO uint32_t USB_OTGn_CTRL
Definition: MIMXRT1052.h:40549
LCDIF_Type::VDCTRL0_CLR
__IO uint32_t VDCTRL0_CLR
Definition: MIMXRT1052.h:23539
PWM_Type::@314::CVAL1CYC
__I uint16_t CVAL1CYC
Definition: MIMXRT1052.h:30879
ADC_Type::CV
__IO uint32_t CV
Definition: MIMXRT1052.h:1303
DMA_Type::@304::DOFF
__IO uint16_t DOFF
Definition: MIMXRT1052.h:12015
kDmaRequestMuxADC2
@ kDmaRequestMuxADC2
Definition: MIMXRT1052.h:387
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10
Definition: MIMXRT1052.h:684
USB_Type
Definition: MIMXRT1052.h:38993
USB_Type::TXFILLTUNING
__IO uint32_t TXFILLTUNING
Definition: MIMXRT1052.h:39032
GPIO1_INT2_IRQn
@ GPIO1_INT2_IRQn
Definition: MIMXRT1052.h:168
CCM_Type::CCGR1
__IO uint32_t CCGR1
Definition: MIMXRT1052.h:4180
kDmaRequestMuxLPUART2Tx
@ kDmaRequestMuxLPUART2Tx
Definition: MIMXRT1052.h:367
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1052.h:638
kDmaRequestMuxFlexPWM1CaptureSub2
@ kDmaRequestMuxFlexPWM1CaptureSub2
Definition: MIMXRT1052.h:339
DCP_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1052.h:10361
PWM1_0_IRQn
@ PWM1_0_IRQn
Definition: MIMXRT1052.h:196
kXBARA1_InputFlexpwm2Pwm1OutTrig01
@ kXBARA1_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1052.h:919
ENET_Type::RMON_T_P64
__I uint32_t RMON_T_P64
Definition: MIMXRT1052.h:15664
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1052.h:456
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1052.h:468
DMA_Type
Definition: MIMXRT1052.h:11947
CAN_Type::RX14MASK
__IO uint32_t RX14MASK
Definition: MIMXRT1052.h:3318
ENET_Type::RMON_T_MC_PKT
__I uint32_t RMON_T_MC_PKT
Definition: MIMXRT1052.h:15657
CSI_Type::CSICR2
__IO uint32_t CSICR2
Definition: MIMXRT1052.h:8793
USDHC_Type
Definition: MIMXRT1052.h:42253
OCOTP_Type::GP3
__IO uint32_t GP3
Definition: MIMXRT1052.h:27778
PIT_Type::@313::LDVAL
__IO uint32_t LDVAL
Definition: MIMXRT1052.h:28516
CCM_ANALOG_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1052.h:6125
PMU_Type::MISC1
__IO uint32_t MISC1
Definition: MIMXRT1052.h:28689
SNVS_Type::HPHACR
__I uint32_t HPHACR
Definition: MIMXRT1052.h:35328
ENET_Type::RMON_R_RESVD_0
uint32_t RMON_R_RESVD_0
Definition: MIMXRT1052.h:15693
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:357
FLEXIO_Type::SHIFTSIEN
__IO uint32_t SHIFTSIEN
Definition: MIMXRT1052.h:17375
ENET_Type::TXIC
__IO uint32_t TXIC
Definition: MIMXRT1052.h:15626
kXBARB3_InputQtimer3Tmr3Output
@ kXBARB3_InputQtimer3Tmr3Output
Definition: MIMXRT1052.h:1036
TRNG_Type::PKRCNT32
__I uint32_t PKRCNT32
Definition: MIMXRT1052.h:37923
SEMC_Type::NANDCR3
__IO uint32_t NANDCR3
Definition: MIMXRT1052.h:34145
kXBARA1_OutputAdcEtcXbar0Trig0
@ kXBARA1_OutputAdcEtcXbar0Trig0
Definition: MIMXRT1052.h:1186
AIPSTZ_Type::OPACR
__IO uint32_t OPACR
Definition: MIMXRT1052.h:2080
SEMC_Type::STS7
uint32_t STS7
Definition: MIMXRT1052.h:34172
SNVS_Type::LPTAR
__IO uint32_t LPTAR
Definition: MIMXRT1052.h:35342
ENET_Type::RMON_R_FRAG
__I uint32_t RMON_R_FRAG
Definition: MIMXRT1052.h:15691
kXBARA1_OutputFlexpwm3ExtSync2
@ kXBARA1_OutputFlexpwm3ExtSync2
Definition: MIMXRT1052.h:1137
kXBARA1_OutputEnc3Trigger
@ kXBARA1_OutputEnc3Trigger
Definition: MIMXRT1052.h:1163
TMR_Type::@317::CAPT
__IO uint16_t CAPT
Definition: MIMXRT1052.h:37382
LPUART_Type::FIFO
__IO uint32_t FIFO
Definition: MIMXRT1052.h:26782
ADC_ETC_Type::DMA_CTRL
__IO uint32_t DMA_CTRL
Definition: MIMXRT1052.h:1621
kIOMUXC_ENET_RXEN_SELECT_INPUT
@ kIOMUXC_ENET_RXEN_SELECT_INPUT
Definition: MIMXRT1052.h:735
DMA6_DMA22_IRQn
@ DMA6_DMA22_IRQn
Definition: MIMXRT1052.h:100
kXBARA1_InputIomuxXbarInout05
@ kXBARA1_InputIomuxXbarInout05
Definition: MIMXRT1052.h:880
CMP_Type::MUXCR
__IO uint8_t MUXCR
Definition: MIMXRT1052.h:8547
kIOMUXC_SPDIF_IN_SELECT_INPUT
@ kIOMUXC_SPDIF_IN_SELECT_INPUT
Definition: MIMXRT1052.h:834
kXBARA1_OutputEnc3PhaseBInput
@ kXBARA1_OutputEnc3PhaseBInput
Definition: MIMXRT1052.h:1160
USDHC2_IRQn
@ USDHC2_IRQn
Definition: MIMXRT1052.h:205
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1052.h:495
GPIO1_INT3_IRQn
@ GPIO1_INT3_IRQn
Definition: MIMXRT1052.h:169
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:421
SEMC_Type::STS10
uint32_t STS10
Definition: MIMXRT1052.h:34175
PWM_Type::FSTS
__IO uint16_t FSTS
Definition: MIMXRT1052.h:30897
PXP_Type::NEXT
__IO uint32_t NEXT
Definition: MIMXRT1052.h:32578
XBARA_Type::CTRL0
__IO uint16_t CTRL0
Definition: MIMXRT1052.h:44201
TRNG_Type::PKRCNTBA
__I uint32_t PKRCNTBA
Definition: MIMXRT1052.h:37927
ENET_Type::MIBC
__IO uint32_t MIBC
Definition: MIMXRT1052.h:15617
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07
Definition: MIMXRT1052.h:538
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1052.h:460
CSI_Type::CSIDMASA_FB1
__IO uint32_t CSIDMASA_FB1
Definition: MIMXRT1052.h:8802
DCP_Type::KEY
__IO uint32_t KEY
Definition: MIMXRT1052.h:10288
CCM_ANALOG_Type::PLL_USB1_SET
__IO uint32_t PLL_USB1_SET
Definition: MIMXRT1052.h:6078
kDmaRequestMuxLPI2C1
@ kDmaRequestMuxLPI2C1
Definition: MIMXRT1052.h:323
Reserved123_IRQn
@ Reserved123_IRQn
Definition: MIMXRT1052.h:201
XBARA_Type::SEL14
__IO uint16_t SEL14
Definition: MIMXRT1052.h:44149
XBARA_Type::SEL18
__IO uint16_t SEL18
Definition: MIMXRT1052.h:44153
LPI2C1_IRQn
@ LPI2C1_IRQn
Definition: MIMXRT1052.h:122
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1052.h:488
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
Definition: MIMXRT1052.h:674
kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:824
EWM_Type::CMPH
__IO uint8_t CMPH
Definition: MIMXRT1052.h:17250
kDmaRequestMuxQTIMER1CaptTimer2
@ kDmaRequestMuxQTIMER1CaptTimer2
Definition: MIMXRT1052.h:355
XTALOSC24M_Type::LOWPWR_CTRL_TOG
__IO uint32_t LOWPWR_CTRL_TOG
Definition: MIMXRT1052.h:45178
USB_Type::HWDEVICE
__I uint32_t HWDEVICE
Definition: MIMXRT1052.h:38997
kDmaRequestMuxACMP2
@ kDmaRequestMuxACMP2
Definition: MIMXRT1052.h:388
TRNG_Type::@332::SCR4L
__IO uint32_t SCR4L
Definition: MIMXRT1052.h:37910
XTALOSC24M_Type::LOWPWR_CTRL_SET
__IO uint32_t LOWPWR_CTRL_SET
Definition: MIMXRT1052.h:45176
kXBARA1_InputIomuxXbarIn21
@ kXBARA1_InputIomuxXbarIn21
Definition: MIMXRT1052.h:896
SPDIF_Type::SRCD
__IO uint32_t SRCD
Definition: MIMXRT1052.h:36418
ENET_Type::MRBR
__IO uint32_t MRBR
Definition: MIMXRT1052.h:15639
kXBARB3_OutputAoi2In14
@ kXBARB3_OutputAoi2In14
Definition: MIMXRT1052.h:1244
kXBARB3_OutputAoi2In09
@ kXBARB3_OutputAoi2In09
Definition: MIMXRT1052.h:1239
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08
Definition: MIMXRT1052.h:666
LCDIF_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:23520
DMA2_DMA18_IRQn
@ DMA2_DMA18_IRQn
Definition: MIMXRT1052.h:96
CCM_ANALOG_Type::PLL_ARM_CLR
__IO uint32_t PLL_ARM_CLR
Definition: MIMXRT1052.h:6075
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1052.h:646
PWM_Type::@314::CVAL5
__I uint16_t CVAL5
Definition: MIMXRT1052.h:30886
TRNG_Type::@322::FRQMAX
__IO uint32_t FRQMAX
Definition: MIMXRT1052.h:37890
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1052.h:628
ENET_Type::RMON_R_UNDERSIZE
__I uint32_t RMON_R_UNDERSIZE
Definition: MIMXRT1052.h:15689
GPIO5_Combined_16_31_IRQn
@ GPIO5_Combined_16_31_IRQn
Definition: MIMXRT1052.h:183
kXBARA1_OutputIomuxXbarInout10
@ kXBARA1_OutputIomuxXbarInout10
Definition: MIMXRT1052.h:1093
DCP_Type::DBGSELECT
__IO uint32_t DBGSELECT
Definition: MIMXRT1052.h:10355
GPIO3_Combined_16_31_IRQn
@ GPIO3_Combined_16_31_IRQn
Definition: MIMXRT1052.h:179
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE
__IO uint32_t SW_PAD_CTL_PAD_TEST_MODE
Definition: MIMXRT1052.h:22799
kXBARA1_OutputFlexpwm1Fault0
@ kXBARA1_OutputFlexpwm1Fault0
Definition: MIMXRT1052.h:1118
LCDIF_Type::LUT_CTRL
__IO uint32_t LUT_CTRL
Definition: MIMXRT1052.h:23578
OCOTP_Type::SW_GP22
__IO uint32_t SW_GP22
Definition: MIMXRT1052.h:27790
kXBARA1_OutputFlexpwm2ExtSync0
@ kXBARA1_OutputFlexpwm2ExtSync0
Definition: MIMXRT1052.h:1127
SEMC_Type::STS3
uint32_t STS3
Definition: MIMXRT1052.h:34168
LCDIF_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:23519
ENC_Type::UCOMP
__IO uint16_t UCOMP
Definition: MIMXRT1052.h:15157
kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT
@ kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:769
kXBARA1_OutputQtimer4Tmr0Input
@ kXBARA1_OutputQtimer4Tmr0Input
Definition: MIMXRT1052.h:1181
kDmaRequestMuxFlexPWM4ValueSub0
@ kDmaRequestMuxFlexPWM4ValueSub0
Definition: MIMXRT1052.h:406
kXBARB2_InputQtimer4Tmr1Output
@ kXBARB2_InputQtimer4Tmr1Output
Definition: MIMXRT1052.h:980
DCP_Type::PACKET3
__I uint32_t PACKET3
Definition: MIMXRT1052.h:10298
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1052.h:594
RTWDOG_IRQn
@ RTWDOG_IRQn
Definition: MIMXRT1052.h:187
PMU_Type::REG_1P1
__IO uint32_t REG_1P1
Definition: MIMXRT1052.h:28669
Reserved87_IRQn
@ Reserved87_IRQn
Definition: MIMXRT1052.h:165
OCOTP_Type::LOCK
__IO uint32_t LOCK
Definition: MIMXRT1052.h:27722
kXBARB2_InputFlexpwm3Pwm2OutTrig01
@ kXBARB2_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1052.h:992
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1052.h:632
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
Definition: MIMXRT1052.h:676
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1052.h:452
PXP_Type::CSC1_COEF2
__IO uint32_t CSC1_COEF2
Definition: MIMXRT1052.h:32574
FLEXSPI_Type::STS0
__I uint32_t STS0
Definition: MIMXRT1052.h:18115
CCM_Type::CISR
__IO uint32_t CISR
Definition: MIMXRT1052.h:4175
DMA_Type::DCHPRI21
__IO uint8_t DCHPRI21
Definition: MIMXRT1052.h:11993
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1052.h:704
LCDIF_Type::PIGEONCTRL0_SET
__IO uint32_t PIGEONCTRL0_SET
Definition: MIMXRT1052.h:23558
CCM_ANALOG_Type::PLL_USB1
__IO uint32_t PLL_USB1
Definition: MIMXRT1052.h:6077
kXBARA1_OutputFlexpwm4ExtSync3
@ kXBARA1_OutputFlexpwm4ExtSync3
Definition: MIMXRT1052.h:1145
PWM_Type::@314::CAPTCOMPA
__IO uint16_t CAPTCOMPA
Definition: MIMXRT1052.h:30871
CCM_ANALOG_Type::PLL_USB1_CLR
__IO uint32_t PLL_USB1_CLR
Definition: MIMXRT1052.h:6079
PXP_Type::PS_CTRL_TOG
__IO uint32_t PS_CTRL_TOG
Definition: MIMXRT1052.h:32541
kXBARA1_OutputFlexpwm234Exta2
@ kXBARA1_OutputFlexpwm234Exta2
Definition: MIMXRT1052.h:1125
CCM_ANALOG_Type::PLL_VIDEO_DENOM
__IO uint32_t PLL_VIDEO_DENOM
Definition: MIMXRT1052.h:6109
AIPSTZ_Type
Definition: MIMXRT1052.h:2077
kDmaRequestMuxFlexPWM3CaptureSub3
@ kDmaRequestMuxFlexPWM3CaptureSub3
Definition: MIMXRT1052.h:348
LPI2C_Type::SSR
__IO uint32_t SSR
Definition: MIMXRT1052.h:25120
kXBARA1_OutputRESERVED25
@ kXBARA1_OutputRESERVED25
Definition: MIMXRT1052.h:1108
kIOMUXC_LPSPI2_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI2_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:786
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1052.h:481
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1052.h:561
kIOMUXC_LPUART8_RX_SELECT_INPUT
@ kIOMUXC_LPUART8_RX_SELECT_INPUT
Definition: MIMXRT1052.h:808
kXBARA1_InputAcmp4Out
@ kXBARA1_InputAcmp4Out
Definition: MIMXRT1052.h:904
kXBARA1_OutputLpuart3TrgInput
@ kXBARA1_OutputLpuart3TrgInput
Definition: MIMXRT1052.h:1204
kIOMUXC_XBAR1_IN15_SELECT_INPUT
@ kIOMUXC_XBAR1_IN15_SELECT_INPUT
Definition: MIMXRT1052.h:866
SPDIF_Type::@315::SIC
__O uint32_t SIC
Definition: MIMXRT1052.h:36422
BEE_Type::CTR_NONCE0_W0
__O uint32_t CTR_NONCE0_W0
Definition: MIMXRT1052.h:3019
kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
Definition: MIMXRT1052.h:743
kXBARA1_OutputAdcEtcXbar1Trig1
@ kXBARA1_OutputAdcEtcXbar1Trig1
Definition: MIMXRT1052.h:1191
CCM_Type::CMEOR
__IO uint32_t CMEOR
Definition: MIMXRT1052.h:4187
TRNG_Type::INT_STATUS
__I uint32_t INT_STATUS
Definition: MIMXRT1052.h:37933
kXBARB2_InputAdcEtcXbar0Coco3
@ kXBARB2_InputAdcEtcXbar0Coco3
Definition: MIMXRT1052.h:1004
I2S_Type::RCR1
__IO uint32_t RCR1
Definition: MIMXRT1052.h:19883
ENET_Type::TACC
__IO uint32_t TACC
Definition: MIMXRT1052.h:15651
OCOTP_Type::CFG1
__IO uint32_t CFG1
Definition: MIMXRT1052.h:27726
CCM_ANALOG_Type::PLL_USB2_CLR
__IO uint32_t PLL_USB2_CLR
Definition: MIMXRT1052.h:6083
LCDIF_Type::PIGEONCTRL2
__IO uint32_t PIGEONCTRL2
Definition: MIMXRT1052.h:23565
PIT_Type
Definition: MIMXRT1052.h:28509
kXBARB2_InputAdcEtcXbar1Coco3
@ kXBARB2_InputAdcEtcXbar1Coco3
Definition: MIMXRT1052.h:1008
LPI2C_Type::MFCR
__IO uint32_t MFCR
Definition: MIMXRT1052.h:25113
kXBARA1_OutputIomuxXbarInout13
@ kXBARA1_OutputIomuxXbarInout13
Definition: MIMXRT1052.h:1096
OCOTP_Type::MAC1
__IO uint32_t MAC1
Definition: MIMXRT1052.h:27776
CCM_ANALOG_Type::PFD_480_SET
__IO uint32_t PFD_480_SET
Definition: MIMXRT1052.h:6116
PWM_Type::@314::VAL4
__IO uint16_t VAL4
Definition: MIMXRT1052.h:30858
I2S_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:19869
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1052.h:478
ENC_Type::WTR
__IO uint16_t WTR
Definition: MIMXRT1052.h:15141
UsageFault_IRQn
@ UsageFault_IRQn
Definition: MIMXRT1052.h:87
LPSPI2_IRQn
@ LPSPI2_IRQn
Definition: MIMXRT1052.h:127
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1052.h:593
PWM_Type::@314::CAPTCOMPX
__IO uint16_t CAPTCOMPX
Definition: MIMXRT1052.h:30875
SEMC_Type::SDRAMCR0
__IO uint32_t SDRAMCR0
Definition: MIMXRT1052.h:34138
kXBARB2_InputRESERVED3
@ kXBARB2_InputRESERVED3
Definition: MIMXRT1052.h:966
kXBARA1_OutputEnc3PhaseAInput
@ kXBARA1_OutputEnc3PhaseAInput
Definition: MIMXRT1052.h:1159
ADC_Type
Definition: MIMXRT1052.h:1296
SEMC_Type::BMCR1
__IO uint32_t BMCR1
Definition: MIMXRT1052.h:34133
LCDIF_Type::VDCTRL0_SET
__IO uint32_t VDCTRL0_SET
Definition: MIMXRT1052.h:23538
kIOMUXC_ENET1_RXDATA_SELECT_INPUT
@ kIOMUXC_ENET1_RXDATA_SELECT_INPUT
Definition: MIMXRT1052.h:734
kXBARB3_InputEnc4PosMatch
@ kXBARB3_InputEnc4PosMatch
Definition: MIMXRT1052.h:1070
kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT
Definition: MIMXRT1052.h:758
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1052.h:631
kXBARA1_OutputAcmp3Sample
@ kXBARA1_OutputAcmp3Sample
Definition: MIMXRT1052.h:1105
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1052.h:586
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1052.h:590
kXBARA1_OutputEnc1PhaseBInput
@ kXBARA1_OutputEnc1PhaseBInput
Definition: MIMXRT1052.h:1150
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1052.h:633
IOMUXC_GPR_Type::GPR13
__IO uint32_t GPR13
Definition: MIMXRT1052.h:20871
SEMC_Type::STS6
uint32_t STS6
Definition: MIMXRT1052.h:34171
ENET_Type::IEEE_T_LCOL
__I uint32_t IEEE_T_LCOL
Definition: MIMXRT1052.h:15677
kXBARB3_InputAcmp1Out
@ kXBARB3_InputAcmp1Out
Definition: MIMXRT1052.h:1027
kXBARB3_InputFlexpwm1Pwm3OutTrig01
@ kXBARB3_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1052.h:1043
USDHC_Type::VEND_SPEC2
__IO uint32_t VEND_SPEC2
Definition: MIMXRT1052.h:42284
LPI2C_Type::SRDR
__I uint32_t SRDR
Definition: MIMXRT1052.h:25134
LPI2C3_IRQn
@ LPI2C3_IRQn
Definition: MIMXRT1052.h:124
kXBARA1_OutputFlexpwm1ExtSync2
@ kXBARA1_OutputFlexpwm1ExtSync2
Definition: MIMXRT1052.h:1115
ENET_Type::PAUR
__IO uint32_t PAUR
Definition: MIMXRT1052.h:15624
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1052.h:563
IOMUXC_GPR_Type::GPR25
__IO uint32_t GPR25
Definition: MIMXRT1052.h:20883
kXBARB2_InputFlexpwm2Pwm4OutTrig01
@ kXBARB2_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1052.h:990
kXBARB3_InputAdcEtcXbar0Coco2
@ kXBARB3_InputAdcEtcXbar0Coco2
Definition: MIMXRT1052.h:1061
DCP_Type::CH3OPTS_SET
__IO uint32_t CH3OPTS_SET
Definition: MIMXRT1052.h:10351
IOMUXC_GPR_Type::GPR0
uint32_t GPR0
Definition: MIMXRT1052.h:20858
kXBARA1_OutputEnc4Home
@ kXBARA1_OutputEnc4Home
Definition: MIMXRT1052.h:1167
kXBARA1_OutputFlexpwm1Exta2
@ kXBARA1_OutputFlexpwm1Exta2
Definition: MIMXRT1052.h:1111
LPUART_Type::DATA
__IO uint32_t DATA
Definition: MIMXRT1052.h:26779
ENET_Type::IEEE_R_DROP
__I uint32_t IEEE_R_DROP
Definition: MIMXRT1052.h:15702
GPT2_IRQn
@ GPT2_IRQn
Definition: MIMXRT1052.h:195
kXBARA1_OutputLpspi4TrgInput
@ kXBARA1_OutputLpspi4TrgInput
Definition: MIMXRT1052.h:1201
CCM_ANALOG_Type::PFD_480
__IO uint32_t PFD_480
Definition: MIMXRT1052.h:6115
CSI_Type
Definition: MIMXRT1052.h:8791
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1052.h:643
PMU_Type::MISC1_SET
__IO uint32_t MISC1_SET
Definition: MIMXRT1052.h:28690
DCP_Type::CH3CMDPTR
__IO uint32_t CH3CMDPTR
Definition: MIMXRT1052.h:10342
kIOMUXC_LPUART7_RX_SELECT_INPUT
@ kIOMUXC_LPUART7_RX_SELECT_INPUT
Definition: MIMXRT1052.h:806
kXBARA1_InputFlexpwm3Pwm1OutTrig01
@ kXBARA1_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1052.h:923
PXP_Type::OUT_AS_LRC
__IO uint32_t OUT_AS_LRC
Definition: MIMXRT1052.h:32536
LPSPI_Type::DER
__IO uint32_t DER
Definition: MIMXRT1052.h:26151
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07
Definition: MIMXRT1052.h:522
kDmaRequestMuxFlexPWM1CaptureSub3
@ kDmaRequestMuxFlexPWM1CaptureSub3
Definition: MIMXRT1052.h:340
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1052.h:610
kXBARA1_OutputFlexpwm4ExtSync2
@ kXBARA1_OutputFlexpwm4ExtSync2
Definition: MIMXRT1052.h:1144
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1052.h:601
IOMUXC_GPR_Type::GPR5
__IO uint32_t GPR5
Definition: MIMXRT1052.h:20863
CCM_ANALOG_Type::PLL_USB1_TOG
__IO uint32_t PLL_USB1_TOG
Definition: MIMXRT1052.h:6080
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1052.h:458
kDmaRequestMuxXBAR1Request2
@ kDmaRequestMuxXBAR1Request2
Definition: MIMXRT1052.h:392
AOI_Type::@302::BFCRT23
__IO uint16_t BFCRT23
Definition: MIMXRT1052.h:2804
LPI2C_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:25096
kXBARB2_InputQtimer4Tmr3Output
@ kXBARB2_InputQtimer4Tmr3Output
Definition: MIMXRT1052.h:982
ENET_Type::RMON_T_P1024TO2047
__I uint32_t RMON_T_P1024TO2047
Definition: MIMXRT1052.h:15669
kXBARA1_OutputQtimer3Tmr0Input
@ kXBARA1_OutputQtimer3Tmr0Input
Definition: MIMXRT1052.h:1177
PWM1_3_IRQn
@ PWM1_3_IRQn
Definition: MIMXRT1052.h:199
TRNG_Type::@334::SCR5C
__I uint32_t SCR5C
Definition: MIMXRT1052.h:37913
kXBARA1_OutputFlexpwm3ExtSync1
@ kXBARA1_OutputFlexpwm3ExtSync1
Definition: MIMXRT1052.h:1136
SEMC_Type::NANDCR0
__IO uint32_t NANDCR0
Definition: MIMXRT1052.h:34142
IOMUXC_GPR_Type::GPR9
uint32_t GPR9
Definition: MIMXRT1052.h:20867
kXBARA1_InputQtimer4Tmr0Output
@ kXBARA1_InputQtimer4Tmr0Output
Definition: MIMXRT1052.h:911
XBARA_Type::SEL35
__IO uint16_t SEL35
Definition: MIMXRT1052.h:44170
LCDIF_Type::@312::PIGEON_0
__IO uint32_t PIGEON_0
Definition: MIMXRT1052.h:23571
PXP_Type::OUT_PS_LRC
__IO uint32_t OUT_PS_LRC
Definition: MIMXRT1052.h:32532
CAN1_IRQn
@ CAN1_IRQn
Definition: MIMXRT1052.h:130
kDmaRequestMuxACMP1
@ kDmaRequestMuxACMP1
Definition: MIMXRT1052.h:331
OCOTP_Type::MEM1
__IO uint32_t MEM1
Definition: MIMXRT1052.h:27740
CCM_ANALOG_Type::PLL_VIDEO_NUM
__IO uint32_t PLL_VIDEO_NUM
Definition: MIMXRT1052.h:6107
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1052.h:510
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:416
LPSPI_Type::TCR
__IO uint32_t TCR
Definition: MIMXRT1052.h:26162
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1052.h:505
ENET_Type::IEEE_T_MACERR
__I uint32_t IEEE_T_MACERR
Definition: MIMXRT1052.h:15679
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1052.h:547
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1052.h:482
TRNG_Type::PKRCNTDC
__I uint32_t PKRCNTDC
Definition: MIMXRT1052.h:37928
CCM_Type::CCSR
__IO uint32_t CCSR
Definition: MIMXRT1052.h:4158
kIOMUXC_LPSPI2_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI2_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:783
kXBARA1_OutputFlexpwm4ExtSync1
@ kXBARA1_OutputFlexpwm4ExtSync1
Definition: MIMXRT1052.h:1143
CCM_ANALOG_Type::PLL_VIDEO
__IO uint32_t PLL_VIDEO
Definition: MIMXRT1052.h:6103
CSI_IRQn
@ CSI_IRQn
Definition: MIMXRT1052.h:137
USB_Type::USBSTS
__IO uint32_t USBSTS
Definition: MIMXRT1052.h:39018
LCDIF_Type::VDCTRL2
__IO uint32_t VDCTRL2
Definition: MIMXRT1052.h:23543
LPI2C_Type::SDER
__IO uint32_t SDER
Definition: MIMXRT1052.h:25122
kIOMUXC_XBAR1_IN16_SELECT_INPUT
@ kIOMUXC_XBAR1_IN16_SELECT_INPUT
Definition: MIMXRT1052.h:867
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ
__IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ
Definition: MIMXRT1052.h:22797
GPT_Type::CNT
__I uint32_t CNT
Definition: MIMXRT1052.h:19584
DMA_Type::DCHPRI13
__IO uint8_t DCHPRI13
Definition: MIMXRT1052.h:11985
kIOMUXC_XBAR1_IN07_SELECT_INPUT
@ kIOMUXC_XBAR1_IN07_SELECT_INPUT
Definition: MIMXRT1052.h:856
ENET_Type::RMON_R_P64
__I uint32_t RMON_R_P64
Definition: MIMXRT1052.h:15694
kXBARA1_InputAoi2Out3
@ kXBARA1_InputAoi2Out3
Definition: MIMXRT1052.h:954
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
Definition: MIMXRT1052.h:686
ENET_Type::RMON_R_CRC_ALIGN
__I uint32_t RMON_R_CRC_ALIGN
Definition: MIMXRT1052.h:15688
SEMC_Type::STS1
uint32_t STS1
Definition: MIMXRT1052.h:34166
XBARA_Type::SEL39
__IO uint16_t SEL39
Definition: MIMXRT1052.h:44174
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1052.h:483
PWM4_1_IRQn
@ PWM4_1_IRQn
Definition: MIMXRT1052.h:242
PWM_Type::@314::CAPTCTRLA
__IO uint16_t CAPTCTRLA
Definition: MIMXRT1052.h:30870
CCM_ANALOG_Type::PLL_AUDIO_TOG
__IO uint32_t PLL_AUDIO_TOG
Definition: MIMXRT1052.h:6098
kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT
@ kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:768
FLEXSPI_Type::LUTCR
__IO uint32_t LUTCR
Definition: MIMXRT1052.h:18097
ADC_Type::CFG
__IO uint32_t CFG
Definition: MIMXRT1052.h:1300
kIOMUXC_USDHC1_WP_SELECT_INPUT
@ kIOMUXC_USDHC1_WP_SELECT_INPUT
Definition: MIMXRT1052.h:838
TSC_Type::FLOW_CONTROL
__IO uint32_t FLOW_CONTROL
Definition: MIMXRT1052.h:38551
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1052.h:625
PWM4_3_IRQn
@ PWM4_3_IRQn
Definition: MIMXRT1052.h:244
PWM_Type::@314::VAL3
__IO uint16_t VAL3
Definition: MIMXRT1052.h:30856
I2S_Type::RCR4
__IO uint32_t RCR4
Definition: MIMXRT1052.h:19886
kDmaRequestMuxFlexPWM1CaptureSub0
@ kDmaRequestMuxFlexPWM1CaptureSub0
Definition: MIMXRT1052.h:337
kDmaRequestMuxLPSPI1Rx
@ kDmaRequestMuxLPSPI1Rx
Definition: MIMXRT1052.h:319
ENET_Type::IEEE_R_FDXFC
__I uint32_t IEEE_R_FDXFC
Definition: MIMXRT1052.h:15707
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1052.h:446
GPIO_Type::PSR
__I uint32_t PSR
Definition: MIMXRT1052.h:19128
kXBARA1_OutputFlexpwm4ExtForce
@ kXBARA1_OutputFlexpwm4ExtForce
Definition: MIMXRT1052.h:1148
kDmaRequestMuxLPUART7Rx
@ kDmaRequestMuxLPUART7Rx
Definition: MIMXRT1052.h:317
ENET_Type::RMON_T_BC_PKT
__I uint32_t RMON_T_BC_PKT
Definition: MIMXRT1052.h:15656
kXBARB3_InputRESERVED3
@ kXBARB3_InputRESERVED3
Definition: MIMXRT1052.h:1024
CCM_ANALOG_Type::PLL_SYS
__IO uint32_t PLL_SYS
Definition: MIMXRT1052.h:6085
LPI2C_Type::MFSR
__I uint32_t MFSR
Definition: MIMXRT1052.h:25114
DCP_Type
Definition: MIMXRT1052.h:10269
kDmaRequestMuxFlexPWM1ValueSub2
@ kDmaRequestMuxFlexPWM1ValueSub2
Definition: MIMXRT1052.h:343
XBARB_Type::SEL5
__IO uint16_t SEL5
Definition: MIMXRT1052.h:45039
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
Definition: MIMXRT1052.h:660
ENC_Type::UMOD
__IO uint16_t UMOD
Definition: MIMXRT1052.h:15155
DMA_Type::CERQ
__O uint8_t CERQ
Definition: MIMXRT1052.h:11956
CSI_Type::CSIIMAG_PARA
__IO uint32_t CSIIMAG_PARA
Definition: MIMXRT1052.h:8805
OCOTP_Type::SRK2
__IO uint32_t SRK2
Definition: MIMXRT1052.h:27758
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1052.h:707
IOMUXC_GPR_Type::GPR4
__IO uint32_t GPR4
Definition: MIMXRT1052.h:20862
IOMUXC_GPR_Type::GPR18
__IO uint32_t GPR18
Definition: MIMXRT1052.h:20876
ADC1_IRQn
@ ADC1_IRQn
Definition: MIMXRT1052.h:161
PXP_Type::PS_CLRKEYLOW
__IO uint32_t PS_CLRKEYLOW
Definition: MIMXRT1052.h:32556
TRNG_Type::@326::SCR1L
__IO uint32_t SCR1L
Definition: MIMXRT1052.h:37898
CSI_Type::CSISR
__IO uint32_t CSISR
Definition: MIMXRT1052.h:8798
kXBARB3_InputRESERVED4
@ kXBARB3_InputRESERVED4
Definition: MIMXRT1052.h:1025
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1052.h:484
XBARA_Type::SEL1
__IO uint16_t SEL1
Definition: MIMXRT1052.h:44136
kXBARA1_OutputLpuart1TrgInput
@ kXBARA1_OutputLpuart1TrgInput
Definition: MIMXRT1052.h:1202
OCOTP_Type::GP1
__IO uint32_t GP1
Definition: MIMXRT1052.h:27780
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1052.h:690
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1052.h:462
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1052.h:695
kXBARB3_InputFlexpwm2Pwm4OutTrig01
@ kXBARB3_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1052.h:1048
TRNG_Type::@320::SBLIM
__IO uint32_t SBLIM
Definition: MIMXRT1052.h:37884
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1052.h:445
LCDIF_Type::LUT1_ADDR
__IO uint32_t LUT1_ADDR
Definition: MIMXRT1052.h:23584
kDmaRequestMuxFlexPWM4ValueSub1
@ kDmaRequestMuxFlexPWM4ValueSub1
Definition: MIMXRT1052.h:407
kXBARA1_OutputFlexpwm3ExtForce
@ kXBARA1_OutputFlexpwm3ExtForce
Definition: MIMXRT1052.h:1141
TMR_Type::@317::CNTR
__IO uint16_t CNTR
Definition: MIMXRT1052.h:37385
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1052.h:641
LCDIF_Type::CRC_STAT
__IO uint32_t CRC_STAT
Definition: MIMXRT1052.h:23551
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1052.h:506
XBARA_Type::SEL21
__IO uint16_t SEL21
Definition: MIMXRT1052.h:44156
kIOMUXC_USDHC2_DATA6_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA6_SELECT_INPUT
Definition: MIMXRT1052.h:848
USB_Type::CAPLENGTH
__I uint8_t CAPLENGTH
Definition: MIMXRT1052.h:39007
kXBARB2_InputRESERVED10
@ kXBARB2_InputRESERVED10
Definition: MIMXRT1052.h:973
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1052.h:467
kXBARA1_OutputIomuxXbarInout08
@ kXBARA1_OutputIomuxXbarInout08
Definition: MIMXRT1052.h:1091
CCM_ANALOG_Type::PFD_528_CLR
__IO uint32_t PFD_528_CLR
Definition: MIMXRT1052.h:6121
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1052.h:604
DCP_Type::PACKET5
__I uint32_t PACKET5
Definition: MIMXRT1052.h:10302
kDmaRequestMuxEnetTimer0
@ kDmaRequestMuxEnetTimer0
Definition: MIMXRT1052.h:390
kXBARA1_OutputLpspi2TrgInput
@ kXBARA1_OutputLpspi2TrgInput
Definition: MIMXRT1052.h:1199
kXBARB2_OutputAoi1In10
@ kXBARB2_OutputAoi1In10
Definition: MIMXRT1052.h:1224
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1052.h:560
USB_Type::SBUSCFG
__IO uint32_t SBUSCFG
Definition: MIMXRT1052.h:39005
DCP_Type::CH2STAT_SET
__IO uint32_t CH2STAT_SET
Definition: MIMXRT1052.h:10335
XBARA_Type::SEL28
__IO uint16_t SEL28
Definition: MIMXRT1052.h:44163
PWM_Type::MCTRL2
__IO uint16_t MCTRL2
Definition: MIMXRT1052.h:30895
DCDC_Type::REG1
__IO uint32_t REG1
Definition: MIMXRT1052.h:10086
kDmaRequestMuxFlexPWM3ValueSub3
@ kDmaRequestMuxFlexPWM3ValueSub3
Definition: MIMXRT1052.h:352
DMA_Type::DCHPRI3
__IO uint8_t DCHPRI3
Definition: MIMXRT1052.h:11971
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1052.h:509
kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:362
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1052.h:614
kXBARA1_InputFlexpwm2Pwm4OutTrig01
@ kXBARA1_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1052.h:922
GPC_IRQn
@ GPC_IRQn
Definition: MIMXRT1052.h:191
USDHC_Type::AUTOCMD12_ERR_STATUS
__IO uint32_t AUTOCMD12_ERR_STATUS
Definition: MIMXRT1052.h:42269
SEMC_Type
Definition: MIMXRT1052.h:34129
AOI_Type
Definition: MIMXRT1052.h:2801
CSI_Type::CSIDMASA_STATFIFO
__IO uint32_t CSIDMASA_STATFIFO
Definition: MIMXRT1052.h:8800
kXBARB2_OutputAoi1In02
@ kXBARB2_OutputAoi1In02
Definition: MIMXRT1052.h:1216
SPDIF_Type::SRPC
__IO uint32_t SRPC
Definition: MIMXRT1052.h:36419
ENET_Type::IALR
__IO uint32_t IALR
Definition: MIMXRT1052.h:15631
ADC_ETC_IRQ1_IRQn
@ ADC_ETC_IRQ1_IRQn
Definition: MIMXRT1052.h:213
ENET_Type::RMON_T_P512TO1023
__I uint32_t RMON_T_P512TO1023
Definition: MIMXRT1052.h:15668
kIOMUXC_LPUART5_TX_SELECT_INPUT
@ kIOMUXC_LPUART5_TX_SELECT_INPUT
Definition: MIMXRT1052.h:803
SEMC_Type::STS12
__I uint32_t STS12
Definition: MIMXRT1052.h:34177
XTALOSC24M_Type
Definition: MIMXRT1052.h:45168
kXBARA1_OutputAdcEtcXbar1Trig3
@ kXBARA1_OutputAdcEtcXbar1Trig3
Definition: MIMXRT1052.h:1193
IOMUXC_GPR_Type::GPR20
__IO uint32_t GPR20
Definition: MIMXRT1052.h:20878
kXBARA1_InputAoi1Out2
@ kXBARA1_InputAoi1Out2
Definition: MIMXRT1052.h:949
PMU_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1052.h:28688
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1052.h:703
kXBARA1_OutputLpuart7TrgInput
@ kXBARA1_OutputLpuart7TrgInput
Definition: MIMXRT1052.h:1208
TRNG_IRQn
@ TRNG_IRQn
Definition: MIMXRT1052.h:147
kIOMUXC_XBAR1_IN17_SELECT_INPUT
@ kIOMUXC_XBAR1_IN17_SELECT_INPUT
Definition: MIMXRT1052.h:859
SNVS_Type::HPTAMR
__IO uint32_t HPTAMR
Definition: MIMXRT1052.h:35331
PWM_Type::@314::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1052.h:30848
GPIO_Type::IMR
__IO uint32_t IMR
Definition: MIMXRT1052.h:19131
SEMC_Type::NORCR3
uint32_t NORCR3
Definition: MIMXRT1052.h:34149
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1052.h:591
GPT_Type::SR
__IO uint32_t SR
Definition: MIMXRT1052.h:19580
kXBARA1_InputDmaDone7
@ kXBARA1_InputDmaDone7
Definition: MIMXRT1052.h:946
ENC_Type::REV
__IO uint16_t REV
Definition: MIMXRT1052.h:15144
kDmaRequestMuxLPUART1Rx
@ kDmaRequestMuxLPUART1Rx
Definition: MIMXRT1052.h:311
kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT
@ kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:764
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1052.h:585
SEMC_Type::BMCR0
__IO uint32_t BMCR0
Definition: MIMXRT1052.h:34132
PWM3_0_IRQn
@ PWM3_0_IRQn
Definition: MIMXRT1052.h:236
ENET_Type::ECR
__IO uint32_t ECR
Definition: MIMXRT1052.h:15612
ENET_Type::EIMR
__IO uint32_t EIMR
Definition: MIMXRT1052.h:15607
kXBARA1_InputPitTrigger0
@ kXBARA1_InputPitTrigger0
Definition: MIMXRT1052.h:931
USB_Type::HCSPARAMS
__I uint32_t HCSPARAMS
Definition: MIMXRT1052.h:39010
kXBARA1_OutputEnc1PhaseAInput
@ kXBARA1_OutputEnc1PhaseAInput
Definition: MIMXRT1052.h:1149
XBARA_Type::SEL23
__IO uint16_t SEL23
Definition: MIMXRT1052.h:44158
GPIO2_Combined_0_15_IRQn
@ GPIO2_Combined_0_15_IRQn
Definition: MIMXRT1052.h:176
PWM_Type::@314::CVAL4
__I uint16_t CVAL4
Definition: MIMXRT1052.h:30884
FLEXIO_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:17368
kXBARA1_InputIomuxXbarInout16
@ kXBARA1_InputIomuxXbarInout16
Definition: MIMXRT1052.h:891
kXBARB2_InputAdcEtcXbar0Coco2
@ kXBARB2_InputAdcEtcXbar0Coco2
Definition: MIMXRT1052.h:1003
LCDIF_Type
Definition: MIMXRT1052.h:23518
USBPHY_Type::RX_TOG
__IO uint32_t RX_TOG
Definition: MIMXRT1052.h:40695
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1052.h:471
kDmaRequestMuxLPUART3Rx
@ kDmaRequestMuxLPUART3Rx
Definition: MIMXRT1052.h:313
USDHC_Type::ADMA_SYS_ADDR
__IO uint32_t ADMA_SYS_ADDR
Definition: MIMXRT1052.h:42276
SEMC_Type::STS15
uint32_t STS15
Definition: MIMXRT1052.h:34180
kXBARA1_InputAoi2Out2
@ kXBARA1_InputAoi2Out2
Definition: MIMXRT1052.h:953
_iomuxc_sw_mux_ctl_pad
_iomuxc_sw_mux_ctl_pad
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Definition: MIMXRT1052.h:437
ROMC_Type
Definition: MIMXRT1052.h:33801
kXBARB2_InputFlexpwm2Pwm1OutTrig01
@ kXBARB2_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1052.h:987
USDHC1_IRQn
@ USDHC1_IRQn
Definition: MIMXRT1052.h:204
kXBARA1_InputIomuxXbarInout11
@ kXBARA1_InputIomuxXbarInout11
Definition: MIMXRT1052.h:886
LPUART3_IRQn
@ LPUART3_IRQn
Definition: MIMXRT1052.h:116
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
Definition: MIMXRT1052.h:670
AIPSTZ_Type::OPACR3
__IO uint32_t OPACR3
Definition: MIMXRT1052.h:2083
GPR_IRQ_IRQn
@ GPR_IRQ_IRQn
Definition: MIMXRT1052.h:135
LCDIF_Type::CTRL2_TOG
__IO uint32_t CTRL2_TOG
Definition: MIMXRT1052.h:23530
CCM_Type::CLPCR
__IO uint32_t CLPCR
Definition: MIMXRT1052.h:4174
USB_ANALOG_Type::@342::LOOPBACK_CLR
__IO uint32_t LOOPBACK_CLR
Definition: MIMXRT1052.h:41815
OCOTP_Type::ANA1
__IO uint32_t ANA1
Definition: MIMXRT1052.h:27750
FLEXIO_Type
Definition: MIMXRT1052.h:17366
SRC_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1052.h:36902
kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT
@ kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:763
USB_ANALOG_Type::@342::CHRG_DETECT_SET
__IO uint32_t CHRG_DETECT_SET
Definition: MIMXRT1052.h:41806
I2S_Type::TCR5
__IO uint32_t TCR5
Definition: MIMXRT1052.h:19875
ENET_Type::RACC
__IO uint32_t RACC
Definition: MIMXRT1052.h:15652
PIT_Type::LTMR64L
__I uint32_t LTMR64L
Definition: MIMXRT1052.h:28513
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10
Definition: MIMXRT1052.h:541
PMU_Type::REG_3P0_SET
__IO uint32_t REG_3P0_SET
Definition: MIMXRT1052.h:28674
kXBARB2_InputRESERVED5
@ kXBARB2_InputRESERVED5
Definition: MIMXRT1052.h:968
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1052.h:512
kXBARB2_OutputAoi1In01
@ kXBARB2_OutputAoi1In01
Definition: MIMXRT1052.h:1215
XTALOSC24M_Type::OSC_CONFIG2_CLR
__IO uint32_t OSC_CONFIG2_CLR
Definition: MIMXRT1052.h:45190
OCOTP_Type::SRK7
__IO uint32_t SRK7
Definition: MIMXRT1052.h:27768
XBARA_Type::SEL50
__IO uint16_t SEL50
Definition: MIMXRT1052.h:44185
kXBARA1_OutputQtimer2Tmr1Input
@ kXBARA1_OutputQtimer2Tmr1Input
Definition: MIMXRT1052.h:1174
USBPHY_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:40698
FLEXIO_Type::SHIFTSTAT
__IO uint32_t SHIFTSTAT
Definition: MIMXRT1052.h:17371
CCM_ANALOG_Type::PLL_USB2_SET
__IO uint32_t PLL_USB2_SET
Definition: MIMXRT1052.h:6082
FLEXRAM_Type::INT_SIG_EN
__IO uint32_t INT_SIG_EN
Definition: MIMXRT1052.h:17946
kXBARA1_OutputAcmp1Sample
@ kXBARA1_OutputAcmp1Sample
Definition: MIMXRT1052.h:1103
XBAR1_IRQ_2_3_IRQn
@ XBAR1_IRQ_2_3_IRQn
Definition: MIMXRT1052.h:211
kXBARA1_OutputIomuxXbarInout09
@ kXBARA1_OutputIomuxXbarInout09
Definition: MIMXRT1052.h:1092
ENET_1588_Timer_IRQn
@ ENET_1588_Timer_IRQn
Definition: MIMXRT1052.h:209
kXBARB2_OutputAoi1In11
@ kXBARB2_OutputAoi1In11
Definition: MIMXRT1052.h:1225
SEMC_Type::IPCR0
__IO uint32_t IPCR0
Definition: MIMXRT1052.h:34157
ENC_Type::UINIT
__IO uint16_t UINIT
Definition: MIMXRT1052.h:15150
kXBARB3_InputPitTrigger0
@ kXBARB3_InputPitTrigger0
Definition: MIMXRT1052.h:1057
USBPHY_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:40699
kXBARA1_InputAdcEtcXbar1Coco1
@ kXBARA1_InputAdcEtcXbar1Coco1
Definition: MIMXRT1052.h:960
kXBARA1_OutputFlexpwm1ExtClk
@ kXBARA1_OutputFlexpwm1ExtClk
Definition: MIMXRT1052.h:1117
SNVS_Type::LPCR
__IO uint32_t LPCR
Definition: MIMXRT1052.h:35334
USBPHY_Type::DEBUG1_CLR
__IO uint32_t DEBUG1_CLR
Definition: MIMXRT1052.h:40710
TSC_Type::BASIC_SETTING
__IO uint32_t BASIC_SETTING
Definition: MIMXRT1052.h:38547
kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:832
OCOTP_Type::CFG6
__IO uint32_t CFG6
Definition: MIMXRT1052.h:27736
CCM_Type::CDCDR
__IO uint32_t CDCDR
Definition: MIMXRT1052.h:4167
kXBARA1_OutputFlexpwm2ExtForce
@ kXBARA1_OutputFlexpwm2ExtForce
Definition: MIMXRT1052.h:1134
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1052.h:624
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:825
kXBARA1_OutputFlexpwm3ExtSync3
@ kXBARA1_OutputFlexpwm3ExtSync3
Definition: MIMXRT1052.h:1138
USBNC_Type
Definition: MIMXRT1052.h:40547
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1052.h:599
DMA_Type::DCHPRI25
__IO uint8_t DCHPRI25
Definition: MIMXRT1052.h:11997
kXBARB2_InputEnc2PosMatch
@ kXBARB2_InputEnc2PosMatch
Definition: MIMXRT1052.h:1010
FLEXSPI_Type::IPCR1
__IO uint32_t IPCR1
Definition: MIMXRT1052.h:18107
XBARA_Type::SEL55
__IO uint16_t SEL55
Definition: MIMXRT1052.h:44190
ENET_Type::RAFL
__IO uint32_t RAFL
Definition: MIMXRT1052.h:15644
CCM_Type::CIMR
__IO uint32_t CIMR
Definition: MIMXRT1052.h:4176
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
Definition: MIMXRT1052.h:517
XBARA_Type::SEL20
__IO uint16_t SEL20
Definition: MIMXRT1052.h:44155
SRC_IRQn
@ SRC_IRQn
Definition: MIMXRT1052.h:192
kXBARA1_InputAdcEtcXbar1Coco3
@ kXBARA1_InputAdcEtcXbar1Coco3
Definition: MIMXRT1052.h:962
USBNC_Type::USB_OTGn_PHY_CTRL_0
__IO uint32_t USB_OTGn_PHY_CTRL_0
Definition: MIMXRT1052.h:40551
ADC2_IRQn
@ ADC2_IRQn
Definition: MIMXRT1052.h:162
ADC_ETC_Type::@301::TRIGn_RESULT_7_6
__I uint32_t TRIGn_RESULT_7_6
Definition: MIMXRT1052.h:1632
USB_ANALOG_Type::@342::MISC_CLR
__IO uint32_t MISC_CLR
Definition: MIMXRT1052.h:41819
SNVS_Type::LPLR
__IO uint32_t LPLR
Definition: MIMXRT1052.h:35333
ENET_Type::TCR
__IO uint32_t TCR
Definition: MIMXRT1052.h:15621
LCDIF_Type::@312::PIGEON_2
__IO uint32_t PIGEON_2
Definition: MIMXRT1052.h:23575
kXBARA1_OutputEnc2PhaseBInput
@ kXBARA1_OutputEnc2PhaseBInput
Definition: MIMXRT1052.h:1155
XBARA_Type::SEL48
__IO uint16_t SEL48
Definition: MIMXRT1052.h:44183
CCM_ANALOG_Type::PLL_AUDIO_NUM
__IO uint32_t PLL_AUDIO_NUM
Definition: MIMXRT1052.h:6099
kXBARA1_OutputFlexpwm1ExtForce
@ kXBARA1_OutputFlexpwm1ExtForce
Definition: MIMXRT1052.h:1122
USB_Type::@338::DEVICEADDR
__IO uint32_t DEVICEADDR
Definition: MIMXRT1052.h:39023
kXBARB3_InputAcmp2Out
@ kXBARB3_InputAcmp2Out
Definition: MIMXRT1052.h:1028
SNVS_Type::HPSVCR
__IO uint32_t HPSVCR
Definition: MIMXRT1052.h:35324
TRNG_Type::PKRCNT76
__I uint32_t PKRCNT76
Definition: MIMXRT1052.h:37925
IRQn_Type
enum IRQn IRQn_Type
LCDIF_Type::NEXT_BUF
__IO uint32_t NEXT_BUF
Definition: MIMXRT1052.h:23535
kDmaRequestMuxLPSPI3Rx
@ kDmaRequestMuxLPSPI3Rx
Definition: MIMXRT1052.h:321
GPIO_Type::DR_CLEAR
__O uint32_t DR_CLEAR
Definition: MIMXRT1052.h:19136
kXBARA1_OutputFlexpwm2ExtSync3
@ kXBARA1_OutputFlexpwm2ExtSync3
Definition: MIMXRT1052.h:1130
DCP_Type::CH2STAT_CLR
__IO uint32_t CH2STAT_CLR
Definition: MIMXRT1052.h:10336
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF
__IO uint32_t SW_PAD_CTL_PAD_ONOFF
Definition: MIMXRT1052.h:22801
CCM_Type::CS2CDR
__IO uint32_t CS2CDR
Definition: MIMXRT1052.h:4166
DMA_Type::DCHPRI16
__IO uint8_t DCHPRI16
Definition: MIMXRT1052.h:11990
TRNG_Type::SEC_CFG
__IO uint32_t SEC_CFG
Definition: MIMXRT1052.h:37930
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1052.h:507
ENET_Type::RMON_T_DROP
uint32_t RMON_T_DROP
Definition: MIMXRT1052.h:15654
Reserved68_IRQn
@ Reserved68_IRQn
Definition: MIMXRT1052.h:146
LCDIF_Type::CTRL1_SET
__IO uint32_t CTRL1_SET
Definition: MIMXRT1052.h:23524
kIOMUXC_USDHC2_CMD_SELECT_INPUT
@ kIOMUXC_USDHC2_CMD_SELECT_INPUT
Definition: MIMXRT1052.h:841
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1052.h:473
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1052.h:603
kIOMUXC_LPI2C2_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C2_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:774
SEMC_Type::IPCMD
__IO uint32_t IPCMD
Definition: MIMXRT1052.h:34160
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1052.h:454
ENET_Type::RMON_T_P_GTE2048
__I uint32_t RMON_T_P_GTE2048
Definition: MIMXRT1052.h:15670
OCOTP_Type::SW_GP1
__IO uint32_t SW_GP1
Definition: MIMXRT1052.h:27784
SRC_Type
Definition: MIMXRT1052.h:36901
SPDIF_IRQn
@ SPDIF_IRQn
Definition: MIMXRT1052.h:154
SNVS_Type::HPRTCLR
__IO uint32_t HPRTCLR
Definition: MIMXRT1052.h:35330
kXBARA1_OutputFlexpwm1ExtSync3
@ kXBARA1_OutputFlexpwm1ExtSync3
Definition: MIMXRT1052.h:1116
DMA_Type::DCHPRI0
__IO uint8_t DCHPRI0
Definition: MIMXRT1052.h:11974
kIOMUXC_LPUART6_RX_SELECT_INPUT
@ kIOMUXC_LPUART6_RX_SELECT_INPUT
Definition: MIMXRT1052.h:804
LCDIF_IRQn
@ LCDIF_IRQn
Definition: MIMXRT1052.h:136
LPUART_Type::GLOBAL
__IO uint32_t GLOBAL
Definition: MIMXRT1052.h:26774
CCM_ANALOG_Type::MISC2_SET
__IO uint32_t MISC2_SET
Definition: MIMXRT1052.h:6133
kXBARB2_InputAcmp2Out
@ kXBARB2_InputAcmp2Out
Definition: MIMXRT1052.h:970
kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:833
kIOMUXC_USDHC2_WP_SELECT_INPUT
@ kIOMUXC_USDHC2_WP_SELECT_INPUT
Definition: MIMXRT1052.h:850
kDmaRequestMuxQTIMER2CaptTimer2
@ kDmaRequestMuxQTIMER2CaptTimer2
Definition: MIMXRT1052.h:412
LPUART_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:26778
DCP_Type::CH0OPTS_TOG
__IO uint32_t CH0OPTS_TOG
Definition: MIMXRT1052.h:10317
iomuxc_select_input_t
enum _iomuxc_select_input iomuxc_select_input_t
Enumeration for the IOMUXC select input.
BEE_Type::ADDR_OFFSET1
__IO uint32_t ADDR_OFFSET1
Definition: MIMXRT1052.h:3013
SNVS_Type::HPRTCMR
__IO uint32_t HPRTCMR
Definition: MIMXRT1052.h:35329
TRNG_Type::PKRCNT10
__I uint32_t PKRCNT10
Definition: MIMXRT1052.h:37922
CCM_1_IRQn
@ CCM_1_IRQn
Definition: MIMXRT1052.h:189
DMA_Type::CR
__IO uint32_t CR
Definition: MIMXRT1052.h:11948
BEE_Type::CTR_NONCE1_W0
__O uint32_t CTR_NONCE1_W0
Definition: MIMXRT1052.h:3023
PGC_Type::MEGA_SR
__IO uint32_t MEGA_SR
Definition: MIMXRT1052.h:28377
RTWDOG_Type::CNT
__IO uint32_t CNT
Definition: MIMXRT1052.h:33929
kXBARB2_InputAcmp3Out
@ kXBARB2_InputAcmp3Out
Definition: MIMXRT1052.h:971
PXP_Type::POWER
__IO uint32_t POWER
Definition: MIMXRT1052.h:32576
FLEXSPI_Type::FLSHCR4
__IO uint32_t FLSHCR4
Definition: MIMXRT1052.h:18104
DCP_Type::PACKET6
__I uint32_t PACKET6
Definition: MIMXRT1052.h:10304
XTALOSC24M_Type::OSC_CONFIG1_TOG
__IO uint32_t OSC_CONFIG1_TOG
Definition: MIMXRT1052.h:45187
LCDIF_Type::PIGEONCTRL0_CLR
__IO uint32_t PIGEONCTRL0_CLR
Definition: MIMXRT1052.h:23559
USB_Type::USBINTR
__IO uint32_t USBINTR
Definition: MIMXRT1052.h:39019
Reserved115_IRQn
@ Reserved115_IRQn
Definition: MIMXRT1052.h:193
TRNG_Type::PKRCNTFE
__I uint32_t PKRCNTFE
Definition: MIMXRT1052.h:37929
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15
Definition: MIMXRT1052.h:530
kDmaRequestMuxACMP4
@ kDmaRequestMuxACMP4
Definition: MIMXRT1052.h:389
BEE_Type
Definition: MIMXRT1052.h:3010
XBARA_Type::SEL53
__IO uint16_t SEL53
Definition: MIMXRT1052.h:44188
USB_ANALOG_Type::@342::MISC_SET
__IO uint32_t MISC_SET
Definition: MIMXRT1052.h:41818
LPI2C_Type::STAR
__IO uint32_t STAR
Definition: MIMXRT1052.h:25130
kXBARA1_InputEnc2PosMatch
@ kXBARA1_InputEnc2PosMatch
Definition: MIMXRT1052.h:936
kXBARB2_InputEnc3PosMatch
@ kXBARB2_InputEnc3PosMatch
Definition: MIMXRT1052.h:1011
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05
Definition: MIMXRT1052.h:663
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06
Definition: MIMXRT1052.h:537
kIOMUXC_SAI1_MCLK2_SELECT_INPUT
@ kIOMUXC_SAI1_MCLK2_SELECT_INPUT
Definition: MIMXRT1052.h:819
kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
Definition: MIMXRT1052.h:744
XBARA_Type::SEL62
__IO uint16_t SEL62
Definition: MIMXRT1052.h:44197
kXBARA1_InputAoi1Out1
@ kXBARA1_InputAoi1Out1
Definition: MIMXRT1052.h:948
LCDIF_Type::CTRL2
__IO uint32_t CTRL2
Definition: MIMXRT1052.h:23527
kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT
@ kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:830
DCP_Type::CAPABILITY0
__IO uint32_t CAPABILITY0
Definition: MIMXRT1052.h:10282
DMA_Type::@304::@309::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
Definition: MIMXRT1052.h:12023
DCP_Type::CHANNELCTRL_SET
__IO uint32_t CHANNELCTRL_SET
Definition: MIMXRT1052.h:10279
CCM_ANALOG_Type::PFD_480_CLR
__IO uint32_t PFD_480_CLR
Definition: MIMXRT1052.h:6117
CORE_IRQn
@ CORE_IRQn
Definition: MIMXRT1052.h:113
ENET_Type
Definition: MIMXRT1052.h:15604
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11
Definition: MIMXRT1052.h:542
kIOMUXC_XBAR1_IN05_SELECT_INPUT
@ kIOMUXC_XBAR1_IN05_SELECT_INPUT
Definition: MIMXRT1052.h:854
LPI2C_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1052.h:25119
CSI_Type::CSICR18
__IO uint32_t CSICR18
Definition: MIMXRT1052.h:8807
GPIO4_Combined_0_15_IRQn
@ GPIO4_Combined_0_15_IRQn
Definition: MIMXRT1052.h:180
OCOTP_Type::READ_CTRL
__IO uint32_t READ_CTRL
Definition: MIMXRT1052.h:27707
kXBARA1_OutputEnc2Home
@ kXBARA1_OutputEnc2Home
Definition: MIMXRT1052.h:1157
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09
Definition: MIMXRT1052.h:667
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:359
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1052.h:701
DMA3_DMA19_IRQn
@ DMA3_DMA19_IRQn
Definition: MIMXRT1052.h:97
XBARA_Type::SEL47
__IO uint16_t SEL47
Definition: MIMXRT1052.h:44182
DCP_Type::KEYDATA
__IO uint32_t KEYDATA
Definition: MIMXRT1052.h:10290
GPC_Type::ISR5
__I uint32_t ISR5
Definition: MIMXRT1052.h:19003
DMA_Type::@304::SLAST
__IO uint32_t SLAST
Definition: MIMXRT1052.h:12013
kIOMUXC_LPI2C4_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C4_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:777
kIOMUXC_LPSPI1_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI1_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:781
OCOTP_Type::SRK5
__IO uint32_t SRK5
Definition: MIMXRT1052.h:27764
kIOMUXC_XBAR1_IN24_SELECT_INPUT
@ kIOMUXC_XBAR1_IN24_SELECT_INPUT
Definition: MIMXRT1052.h:864
DMA_Type::DCHPRI28
__IO uint8_t DCHPRI28
Definition: MIMXRT1052.h:12002
kXBARB3_InputAdcEtcXbar0Coco0
@ kXBARB3_InputAdcEtcXbar0Coco0
Definition: MIMXRT1052.h:1059
GPC_Type
Definition: MIMXRT1052.h:18996
XBARB_Type::SEL4
__IO uint16_t SEL4
Definition: MIMXRT1052.h:45038
PXP_Type::PS_SCALE
__IO uint32_t PS_SCALE
Definition: MIMXRT1052.h:32552
SPDIF_Type::SIE
__IO uint32_t SIE
Definition: MIMXRT1052.h:36420
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1052.h:584
kXBARA1_InputAdcEtcXbar0Coco2
@ kXBARA1_InputAdcEtcXbar0Coco2
Definition: MIMXRT1052.h:957
FLEXRAM_Type::TCM_CTRL
__IO uint32_t TCM_CTRL
Definition: MIMXRT1052.h:17942
LPSPI_Type::FCR
__IO uint32_t FCR
Definition: MIMXRT1052.h:26160
DMA_Type::ERR
__IO uint32_t ERR
Definition: MIMXRT1052.h:11965
DCP_Type::PACKET0
__I uint32_t PACKET0
Definition: MIMXRT1052.h:10292
kDmaRequestMuxQTIMER2CaptTimer3
@ kDmaRequestMuxQTIMER2CaptTimer3
Definition: MIMXRT1052.h:413
FLEXIO_Type::SHIFTSDEN
__IO uint32_t SHIFTSDEN
Definition: MIMXRT1052.h:17379
PGC_Type::CPU_PUPSCR
__IO uint32_t CPU_PUPSCR
Definition: MIMXRT1052.h:28380
USBPHY_Type::DEBUG_SET
__IO uint32_t DEBUG_SET
Definition: MIMXRT1052.h:40703
kDmaRequestMuxFlexPWM2CaptureSub1
@ kDmaRequestMuxFlexPWM2CaptureSub1
Definition: MIMXRT1052.h:395
PWM_Type::@314::VAL1
__IO uint16_t VAL1
Definition: MIMXRT1052.h:30852
BEE_Type::CTR_NONCE0_W1
__O uint32_t CTR_NONCE0_W1
Definition: MIMXRT1052.h:3020
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15
Definition: MIMXRT1052.h:546
kIOMUXC_LPI2C2_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C2_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:773
kXBARB2_OutputAoi1In00
@ kXBARB2_OutputAoi1In00
Definition: MIMXRT1052.h:1214
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
Definition: MIMXRT1052.h:534
iomuxc_sw_pad_ctl_pad_t
enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
kXBARA1_InputAoi2Out0
@ kXBARA1_InputAoi2Out0
Definition: MIMXRT1052.h:951
PWM1_FAULT_IRQn
@ PWM1_FAULT_IRQn
Definition: MIMXRT1052.h:200
CAN_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:3313
LCDIF_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:23522
CCM_Type::CCGR0
__IO uint32_t CCGR0
Definition: MIMXRT1052.h:4179
ADC_ETC_Type::@301::TRIGn_RESULT_1_0
__I uint32_t TRIGn_RESULT_1_0
Definition: MIMXRT1052.h:1629
kXBARA1_OutputEnc3Index
@ kXBARA1_OutputEnc3Index
Definition: MIMXRT1052.h:1161
PMU_Type::REG_1P1_CLR
__IO uint32_t REG_1P1_CLR
Definition: MIMXRT1052.h:28671
FLEXIO_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:17369
kXBARB2_InputDmaDone4
@ kXBARB2_InputDmaDone4
Definition: MIMXRT1052.h:1017
kXBARA1_InputFlexpwm3Pwm3OutTrig01
@ kXBARA1_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1052.h:925
USDHC_Type::SYS_CTRL
__IO uint32_t SYS_CTRL
Definition: MIMXRT1052.h:42265
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1052.h:558
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1052.h:450
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1052.h:490
PIT_Type::@313::TCTRL
__IO uint32_t TCTRL
Definition: MIMXRT1052.h:28518
PWM2_1_IRQn
@ PWM2_1_IRQn
Definition: MIMXRT1052.h:232
FLEXRAM_Type::INT_STAT_EN
__IO uint32_t INT_STAT_EN
Definition: MIMXRT1052.h:17945
kDmaRequestMuxPxp
@ kDmaRequestMuxPxp
Definition: MIMXRT1052.h:375
kXBARA1_OutputLpspi3TrgInput
@ kXBARA1_OutputLpspi3TrgInput
Definition: MIMXRT1052.h:1200
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09
Definition: MIMXRT1052.h:524
LPI2C_Type::SIER
__IO uint32_t SIER
Definition: MIMXRT1052.h:25121
kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:361
kXBARB3_OutputAoi2In01
@ kXBARB3_OutputAoi2In01
Definition: MIMXRT1052.h:1231
kIOMUXC_CSI_DATA07_SELECT_INPUT
@ kIOMUXC_CSI_DATA07_SELECT_INPUT
Definition: MIMXRT1052.h:725
USB_ANALOG_Type::@342::CHRG_DETECT_CLR
__IO uint32_t CHRG_DETECT_CLR
Definition: MIMXRT1052.h:41807
IOMUXC_GPR_Type::GPR14
__IO uint32_t GPR14
Definition: MIMXRT1052.h:20872
DMA1_DMA17_IRQn
@ DMA1_DMA17_IRQn
Definition: MIMXRT1052.h:95
XBARA_Type::SEL2
__IO uint16_t SEL2
Definition: MIMXRT1052.h:44137
ENET_Type::RDAR
__IO uint32_t RDAR
Definition: MIMXRT1052.h:15609
TEMPMON_Type::TEMPSENSE2_TOG
__IO uint32_t TEMPSENSE2_TOG
Definition: MIMXRT1052.h:37143
DMA_Type::@304::@305::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
Definition: MIMXRT1052.h:12010
kXBARB2_OutputAoi1In13
@ kXBARB2_OutputAoi1In13
Definition: MIMXRT1052.h:1227
LPUART_Type::BAUD
__IO uint32_t BAUD
Definition: MIMXRT1052.h:26776
kDmaRequestMuxADC_ETC
@ kDmaRequestMuxADC_ETC
Definition: MIMXRT1052.h:329
TRNG_Type::@330::SCR3L
__IO uint32_t SCR3L
Definition: MIMXRT1052.h:37906
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1052.h:451
kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT
@ kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:770
LPUART4_IRQn
@ LPUART4_IRQn
Definition: MIMXRT1052.h:117
kXBARA1_OutputFlexio2TriggerIn0
@ kXBARA1_OutputFlexio2TriggerIn0
Definition: MIMXRT1052.h:1212
PXP_Type
Definition: MIMXRT1052.h:32509
kXBARB2_InputEnc1PosMatch
@ kXBARB2_InputEnc1PosMatch
Definition: MIMXRT1052.h:1009
kDmaRequestMuxLPUART8Rx
@ kDmaRequestMuxLPUART8Rx
Definition: MIMXRT1052.h:374
kXBARA1_OutputEnc1Home
@ kXBARA1_OutputEnc1Home
Definition: MIMXRT1052.h:1152
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ
__IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ
Definition: MIMXRT1052.h:22803
kXBARB3_InputFlexpwm4Pwm4OutTrig01
@ kXBARB3_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1052.h:1056
XBARA_Type::SEL37
__IO uint16_t SEL37
Definition: MIMXRT1052.h:44172
kXBARA1_OutputAcmp2Sample
@ kXBARA1_OutputAcmp2Sample
Definition: MIMXRT1052.h:1104
kXBARB3_InputQtimer3Tmr1Output
@ kXBARB3_InputQtimer3Tmr1Output
Definition: MIMXRT1052.h:1034
XBARA_Type::SEL5
__IO uint16_t SEL5
Definition: MIMXRT1052.h:44140
DMA_Type::INT
__IO uint32_t INT
Definition: MIMXRT1052.h:11963
kXBARA1_InputIomuxXbarIn23
@ kXBARA1_InputIomuxXbarIn23
Definition: MIMXRT1052.h:898
KPP_Type::KPDR
__IO uint16_t KPDR
Definition: MIMXRT1052.h:23381
kXBARA1_OutputQtimer4Tmr3Input
@ kXBARA1_OutputQtimer4Tmr3Input
Definition: MIMXRT1052.h:1184
SNVS_HP_WRAPPER_TZ_IRQn
@ SNVS_HP_WRAPPER_TZ_IRQn
Definition: MIMXRT1052.h:141
XBARA_Type::SEL36
__IO uint16_t SEL36
Definition: MIMXRT1052.h:44171
PGC_Type::MEGA_CTRL
__IO uint32_t MEGA_CTRL
Definition: MIMXRT1052.h:28374
kXBARA1_InputDmaDone0
@ kXBARA1_InputDmaDone0
Definition: MIMXRT1052.h:939
kXBARA1_InputFlexpwm1Pwm3OutTrig01
@ kXBARA1_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1052.h:917
kXBARB2_OutputAoi1In03
@ kXBARB2_OutputAoi1In03
Definition: MIMXRT1052.h:1217
kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT
Definition: MIMXRT1052.h:816
kXBARB2_InputDmaDone6
@ kXBARB2_InputDmaDone6
Definition: MIMXRT1052.h:1019
kXBARB3_OutputAoi2In15
@ kXBARB3_OutputAoi2In15
Definition: MIMXRT1052.h:1245
FLEXSPI_Type::MCR1
__IO uint32_t MCR1
Definition: MIMXRT1052.h:18091
SNVS_Type::HPSICR
__IO uint32_t HPSICR
Definition: MIMXRT1052.h:35323
PWM_Type::@314::VAL5
__IO uint16_t VAL5
Definition: MIMXRT1052.h:30860
kDmaRequestMuxFlexPWM4CaptureSub2
@ kDmaRequestMuxFlexPWM4CaptureSub2
Definition: MIMXRT1052.h:404
kDmaRequestMuxFlexPWM2ValueSub0
@ kDmaRequestMuxFlexPWM2ValueSub0
Definition: MIMXRT1052.h:398
TSC_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1052.h:38559
ENET_Type::RMON_T_JAB
__I uint32_t RMON_T_JAB
Definition: MIMXRT1052.h:15662
AOI_Type::@302::BFCRT01
__IO uint16_t BFCRT01
Definition: MIMXRT1052.h:2803
EWM_Type::CMPL
__IO uint8_t CMPL
Definition: MIMXRT1052.h:17249
FLEXSPI_Type::AHBSPNDSTS
__I uint32_t AHBSPNDSTS
Definition: MIMXRT1052.h:18118
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1052.h:588
LPI2C_Type::SCFGR2
__IO uint32_t SCFGR2
Definition: MIMXRT1052.h:25125
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: MIMXRT1052.h:89
XBARA_Type::SEL19
__IO uint16_t SEL19
Definition: MIMXRT1052.h:44154
kDmaRequestMuxXBAR1Request0
@ kDmaRequestMuxXBAR1Request0
Definition: MIMXRT1052.h:335
USB_ANALOG_Type::@342::LOOPBACK
__IO uint32_t LOOPBACK
Definition: MIMXRT1052.h:41813
kDmaRequestMuxLPI2C2
@ kDmaRequestMuxLPI2C2
Definition: MIMXRT1052.h:381
kXBARA1_InputRESERVED30
@ kXBARA1_InputRESERVED30
Definition: MIMXRT1052.h:905
USB_Type::ENDPTPRIME
__IO uint32_t ENDPTPRIME
Definition: MIMXRT1052.h:39042
DMA_Type::SERQ
__O uint8_t SERQ
Definition: MIMXRT1052.h:11957
OCOTP_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1052.h:27718
kXBARA1_OutputFlexpwm1234Fault2
@ kXBARA1_OutputFlexpwm1234Fault2
Definition: MIMXRT1052.h:1120
kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT
@ kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:762
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1052.h:706
kDmaRequestMuxFlexIO2Request2Request3
@ kDmaRequestMuxFlexIO2Request2Request3
Definition: MIMXRT1052.h:366
kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT
Definition: MIMXRT1052.h:811
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1052.h:622
SEMC_Type::STS5
uint32_t STS5
Definition: MIMXRT1052.h:34170
ENET_Type::ATCR
__IO uint32_t ATCR
Definition: MIMXRT1052.h:15710
kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT
Definition: MIMXRT1052.h:760
USB_Type::ENDPTCTRL0
__IO uint32_t ENDPTCTRL0
Definition: MIMXRT1052.h:39046
CCM_Type::CCGR3
__IO uint32_t CCGR3
Definition: MIMXRT1052.h:4182
ADC_ETC_Type::DONE2_ERR_IRQ
__IO uint32_t DONE2_ERR_IRQ
Definition: MIMXRT1052.h:1620
kDmaRequestMuxLPSPI1Tx
@ kDmaRequestMuxLPSPI1Tx
Definition: MIMXRT1052.h:320
DMA_Type::SSRT
__O uint8_t SSRT
Definition: MIMXRT1052.h:11959
FLEXIO_Type::TIMSTAT
__IO uint32_t TIMSTAT
Definition: MIMXRT1052.h:17373
kIOMUXC_USB_OTG2_OC_SELECT_INPUT
@ kIOMUXC_USB_OTG2_OC_SELECT_INPUT
Definition: MIMXRT1052.h:835
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1052.h:449
PGC_Type::MEGA_PDNSCR
__IO uint32_t MEGA_PDNSCR
Definition: MIMXRT1052.h:28376
ADC_Type::CAL
__IO uint32_t CAL
Definition: MIMXRT1052.h:1305
LPUART8_IRQn
@ LPUART8_IRQn
Definition: MIMXRT1052.h:121
XBARA_Type::SEL65
__IO uint16_t SEL65
Definition: MIMXRT1052.h:44200
PMU_Type::REG_3P0
__IO uint32_t REG_3P0
Definition: MIMXRT1052.h:28673
kXBARB3_InputEnc1PosMatch
@ kXBARB3_InputEnc1PosMatch
Definition: MIMXRT1052.h:1067
kXBARB2_InputFlexpwm4Pwm2OutTrig01
@ kXBARB2_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1052.h:996
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1052.h:479
DCP_Type::CH3OPTS
__IO uint32_t CH3OPTS
Definition: MIMXRT1052.h:10350
kDmaRequestMuxFlexPWM2ValueSub1
@ kDmaRequestMuxFlexPWM2ValueSub1
Definition: MIMXRT1052.h:399
CSI_Type::CSICR3
__IO uint32_t CSICR3
Definition: MIMXRT1052.h:8794
kXBARA1_InputFlexpwm4Pwm1OutTrig01
@ kXBARA1_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1052.h:927
PWM_Type::FFILT
__IO uint16_t FFILT
Definition: MIMXRT1052.h:30898
kXBARB3_InputFlexpwm4Pwm2OutTrig01
@ kXBARB3_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1052.h:1054
kDmaRequestMuxSpdifTx
@ kDmaRequestMuxSpdifTx
Definition: MIMXRT1052.h:386
DMA_Type::@304::ATTR
__IO uint16_t ATTR
Definition: MIMXRT1052.h:12007
kXBARA1_OutputQtimer3Tmr2Input
@ kXBARA1_OutputQtimer3Tmr2Input
Definition: MIMXRT1052.h:1179
DMA_Type::CERR
__O uint8_t CERR
Definition: MIMXRT1052.h:11960
kIOMUXC_LPI2C3_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C3_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:776
CAN_Type::RXFGMASK
__IO uint32_t RXFGMASK
Definition: MIMXRT1052.h:3330
PIT_IRQn
@ PIT_IRQn
Definition: MIMXRT1052.h:216
PWM_Type::@314::CVAL2
__I uint16_t CVAL2
Definition: MIMXRT1052.h:30880
EWM_Type::CLKCTRL
__IO uint8_t CLKCTRL
Definition: MIMXRT1052.h:17251
CCM_ANALOG_Type::PFD_480_TOG
__IO uint32_t PFD_480_TOG
Definition: MIMXRT1052.h:6118
ENET_Type::RMON_R_P65TO127
__I uint32_t RMON_R_P65TO127
Definition: MIMXRT1052.h:15695
USBPHY_Type::DEBUG1
__IO uint32_t DEBUG1
Definition: MIMXRT1052.h:40708
USB_Type::HWHOST
__I uint32_t HWHOST
Definition: MIMXRT1052.h:38996
DCP_Type::CHANNELCTRL_CLR
__IO uint32_t CHANNELCTRL_CLR
Definition: MIMXRT1052.h:10280
kXBARB2_InputFlexpwm2Pwm3OutTrig01
@ kXBARB2_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1052.h:989
TMR2_IRQn
@ TMR2_IRQn
Definition: MIMXRT1052.h:228
OCOTP_Type::READ_FUSE_DATA
__IO uint32_t READ_FUSE_DATA
Definition: MIMXRT1052.h:27709
LPSPI4_IRQn
@ LPSPI4_IRQn
Definition: MIMXRT1052.h:129
I2S_Type::TCSR
__IO uint32_t TCSR
Definition: MIMXRT1052.h:19870
IOMUXC_SNVS_GPR_Type::GPR1
uint32_t GPR1
Definition: MIMXRT1052.h:23305
XBARA_Type::SEL45
__IO uint16_t SEL45
Definition: MIMXRT1052.h:44180
TMR3_IRQn
@ TMR3_IRQn
Definition: MIMXRT1052.h:229
kXBARB3_InputQtimer3Tmr0Output
@ kXBARB3_InputQtimer3Tmr0Output
Definition: MIMXRT1052.h:1033
DMA_Type::DCHPRI29
__IO uint8_t DCHPRI29
Definition: MIMXRT1052.h:12001
DMA15_DMA31_IRQn
@ DMA15_DMA31_IRQn
Definition: MIMXRT1052.h:109
SNVS_Type::LPSMCMR
__I uint32_t LPSMCMR
Definition: MIMXRT1052.h:35343
LPI2C_Type
Definition: MIMXRT1052.h:25094
LPUART5_IRQn
@ LPUART5_IRQn
Definition: MIMXRT1052.h:118
kXBARA1_OutputQtimer1Tmr1Input
@ kXBARA1_OutputQtimer1Tmr1Input
Definition: MIMXRT1052.h:1170
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1052.h:654
PWM_Type::@314::STS
__IO uint16_t STS
Definition: MIMXRT1052.h:30863
ROMC_Type::ROMPATCHENH
uint32_t ROMPATCHENH
Definition: MIMXRT1052.h:33805
CCM_Type::CCGR4
__IO uint32_t CCGR4
Definition: MIMXRT1052.h:4183
GPIO1_INT6_IRQn
@ GPIO1_INT6_IRQn
Definition: MIMXRT1052.h:172
DMA_Type::DCHPRI14
__IO uint8_t DCHPRI14
Definition: MIMXRT1052.h:11984
kIOMUXC_LPUART6_TX_SELECT_INPUT
@ kIOMUXC_LPUART6_TX_SELECT_INPUT
Definition: MIMXRT1052.h:805
kDmaRequestMuxFlexPWM2CaptureSub0
@ kDmaRequestMuxFlexPWM2CaptureSub0
Definition: MIMXRT1052.h:394
kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:831
kXBARB2_InputRESERVED11
@ kXBARB2_InputRESERVED11
Definition: MIMXRT1052.h:974
kIOMUXC_LPSPI2_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI2_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:784
LPUART6_IRQn
@ LPUART6_IRQn
Definition: MIMXRT1052.h:119
kXBARA1_OutputFlexpwm2Fault1
@ kXBARA1_OutputFlexpwm2Fault1
Definition: MIMXRT1052.h:1133
kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
Definition: MIMXRT1052.h:754
CCM_ANALOG_Type::PLL_USB2
__IO uint32_t PLL_USB2
Definition: MIMXRT1052.h:6081
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1052.h:699
kIOMUXC_CSI_HSYNC_SELECT_INPUT
@ kIOMUXC_CSI_HSYNC_SELECT_INPUT
Definition: MIMXRT1052.h:728
OCOTP_Type::TIMING
__IO uint32_t TIMING
Definition: MIMXRT1052.h:27703
SEMC_Type::IOCR
__IO uint32_t IOCR
Definition: MIMXRT1052.h:34131
kXBARB3_InputDmaDone6
@ kXBARB3_InputDmaDone6
Definition: MIMXRT1052.h:1077
ENET_Type::RMON_R_P512TO1023
__I uint32_t RMON_R_P512TO1023
Definition: MIMXRT1052.h:15698
PWM_Type::@314::INTEN
__IO uint16_t INTEN
Definition: MIMXRT1052.h:30864
CAN_Type::ECR
__IO uint32_t ECR
Definition: MIMXRT1052.h:3320
CCM_Type::CCOSR
__IO uint32_t CCOSR
Definition: MIMXRT1052.h:4177
XBARA_Type::SEL11
__IO uint16_t SEL11
Definition: MIMXRT1052.h:44146
FLEXSPI_Type::INTR
__IO uint32_t INTR
Definition: MIMXRT1052.h:18095
I2S_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:19868
kXBARA1_InputFlexpwm4Pwm2OutTrig01
@ kXBARA1_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1052.h:928
TEMPMON_Type::TEMPSENSE0_SET
__IO uint32_t TEMPSENSE0_SET
Definition: MIMXRT1052.h:37132
ADC_ETC_Type::@301::TRIGn_CHAIN_1_0
__IO uint32_t TRIGn_CHAIN_1_0
Definition: MIMXRT1052.h:1625
PXP_Type::OUT_CTRL_SET
__IO uint32_t OUT_CTRL_SET
Definition: MIMXRT1052.h:32519
kXBARA1_OutputFlexpwm4Fault0
@ kXBARA1_OutputFlexpwm4Fault0
Definition: MIMXRT1052.h:1146
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP
__IO uint32_t SW_MUX_CTL_PAD_WAKEUP
Definition: MIMXRT1052.h:22796
kXBARA1_InputQtimer4Tmr2Output
@ kXBARA1_InputQtimer4Tmr2Output
Definition: MIMXRT1052.h:913
FLEXSPI_Type::MCR2
__IO uint32_t MCR2
Definition: MIMXRT1052.h:18092
PMU_Type::MISC2
__IO uint32_t MISC2
Definition: MIMXRT1052.h:28693
PXP_Type::PS_BACKGROUND
__IO uint32_t PS_BACKGROUND
Definition: MIMXRT1052.h:32550
I2S_Type::RCR5
__IO uint32_t RCR5
Definition: MIMXRT1052.h:19887
kXBARA1_InputAoi1Out3
@ kXBARA1_InputAoi1Out3
Definition: MIMXRT1052.h:950
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05
Definition: MIMXRT1052.h:520
DMA_Type::@304::SADDR
__IO uint32_t SADDR
Definition: MIMXRT1052.h:12005
DCP_Type::CH3STAT_CLR
__IO uint32_t CH3STAT_CLR
Definition: MIMXRT1052.h:10348
kXBARB3_InputAdcEtcXbar0Coco1
@ kXBARB3_InputAdcEtcXbar0Coco1
Definition: MIMXRT1052.h:1060
DCP_Type::CH2OPTS
__IO uint32_t CH2OPTS
Definition: MIMXRT1052.h:10338
USB_Type::@338::PERIODICLISTBASE
__IO uint32_t PERIODICLISTBASE
Definition: MIMXRT1052.h:39024
kIOMUXC_XBAR1_IN09_SELECT_INPUT
@ kIOMUXC_XBAR1_IN09_SELECT_INPUT
Definition: MIMXRT1052.h:858
ADC_ETC_Type::@301::TRIGn_CHAIN_5_4
__IO uint32_t TRIGn_CHAIN_5_4
Definition: MIMXRT1052.h:1627
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14
Definition: MIMXRT1052.h:688
DCP_Type::PACKET4
__I uint32_t PACKET4
Definition: MIMXRT1052.h:10300
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1052.h:618
FLEXIO_Type::PIN
__I uint32_t PIN
Definition: MIMXRT1052.h:17370
LPI2C_Type::MCFGR2
__IO uint32_t MCFGR2
Definition: MIMXRT1052.h:25104
LCDIF_Type::PIGEONCTRL1_SET
__IO uint32_t PIGEONCTRL1_SET
Definition: MIMXRT1052.h:23562
USB_Type::ENDPTSETUPSTAT
__IO uint32_t ENDPTSETUPSTAT
Definition: MIMXRT1052.h:39041
IOMUXC_SNVS_GPR_Type
Definition: MIMXRT1052.h:23303
kXBARA1_OutputEnc3Home
@ kXBARA1_OutputEnc3Home
Definition: MIMXRT1052.h:1162
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1052.h:466
USB_ANALOG_Type::@342::VBUS_DETECT_CLR
__IO uint32_t VBUS_DETECT_CLR
Definition: MIMXRT1052.h:41803
SPDIF_Type::SRFM
__I uint32_t SRFM
Definition: MIMXRT1052.h:36436
kXBARA1_OutputLpuart5TrgInput
@ kXBARA1_OutputLpuart5TrgInput
Definition: MIMXRT1052.h:1206
XBARB_Type::SEL7
__IO uint16_t SEL7
Definition: MIMXRT1052.h:45041
ENET_Type::RMON_T_UNDERSIZE
__I uint32_t RMON_T_UNDERSIZE
Definition: MIMXRT1052.h:15659
SEMC_Type::IPTXDAT
__IO uint32_t IPTXDAT
Definition: MIMXRT1052.h:34161
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
Definition: MIMXRT1052.h:527
SEMC_Type::SDRAMCR2
__IO uint32_t SDRAMCR2
Definition: MIMXRT1052.h:34140
PWM_Type::@314::DTCNT0
__IO uint16_t DTCNT0
Definition: MIMXRT1052.h:30868
CCM_ANALOG_Type::PLL_AUDIO_SET
__IO uint32_t PLL_AUDIO_SET
Definition: MIMXRT1052.h:6096
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15
Definition: MIMXRT1052.h:689
DCP_Type::CH2STAT_TOG
__IO uint32_t CH2STAT_TOG
Definition: MIMXRT1052.h:10337
GPIO1_INT7_IRQn
@ GPIO1_INT7_IRQn
Definition: MIMXRT1052.h:173
ENET_Type::IEEE_R_FRAME_OK
__I uint32_t IEEE_R_FRAME_OK
Definition: MIMXRT1052.h:15703
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1052.h:470
WDOG_Type
Definition: MIMXRT1052.h:43936
ADC_Type::GS
__IO uint32_t GS
Definition: MIMXRT1052.h:1302
kXBARA1_OutputLpi2c2TrgInput
@ kXBARA1_OutputLpi2c2TrgInput
Definition: MIMXRT1052.h:1195
kXBARB3_InputFlexpwm4Pwm3OutTrig01
@ kXBARB3_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1052.h:1055
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04
Definition: MIMXRT1052.h:535
kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
Definition: MIMXRT1052.h:755
OCOTP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:27699
PMU_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1052.h:28687
LCDIF_Type::CTRL1
__IO uint32_t CTRL1
Definition: MIMXRT1052.h:23523
kXBARA1_OutputQtimer4Tmr1Input
@ kXBARA1_OutputQtimer4Tmr1Input
Definition: MIMXRT1052.h:1182
kXBARA1_OutputDmaChMuxReq30
@ kXBARA1_OutputDmaChMuxReq30
Definition: MIMXRT1052.h:1083
kIOMUXC_NMI_SELECT_INPUT
@ kIOMUXC_NMI_SELECT_INPUT
Definition: MIMXRT1052.h:810
FLEXSPI_IRQn
@ FLEXSPI_IRQn
Definition: MIMXRT1052.h:202
DMA_Type::@304::@309::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
Definition: MIMXRT1052.h:12024
IOMUXC_GPR_Type::GPR6
__IO uint32_t GPR6
Definition: MIMXRT1052.h:20864
kDmaRequestMuxFlexPWM3ValueSub0
@ kDmaRequestMuxFlexPWM3ValueSub0
Definition: MIMXRT1052.h:349
DCDC_Type::REG3
__IO uint32_t REG3
Definition: MIMXRT1052.h:10088
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ
Definition: MIMXRT1052.h:22798
kXBARA1_InputFlexpwm2Pwm3OutTrig01
@ kXBARA1_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1052.h:921
PWM3_2_IRQn
@ PWM3_2_IRQn
Definition: MIMXRT1052.h:238
kXBARB3_InputFlexpwm1Pwm1OutTrig01
@ kXBARB3_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1052.h:1041
XBARA_Type::SEL3
__IO uint16_t SEL3
Definition: MIMXRT1052.h:44138
ADC_ETC_IRQ0_IRQn
@ ADC_ETC_IRQ0_IRQn
Definition: MIMXRT1052.h:212
CSI_Type::CSIRXCNT
__IO uint32_t CSIRXCNT
Definition: MIMXRT1052.h:8797
PWM4_0_IRQn
@ PWM4_0_IRQn
Definition: MIMXRT1052.h:241
kXBARA1_InputFlexpwm2Pwm2OutTrig01
@ kXBARA1_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1052.h:920
kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT
@ kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT
Definition: MIMXRT1052.h:718
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:363
ENC2_IRQn
@ ENC2_IRQn
Definition: MIMXRT1052.h:224
kXBARA1_OutputQtimer3Tmr1Input
@ kXBARA1_OutputQtimer3Tmr1Input
Definition: MIMXRT1052.h:1178
LCDIF_Type::PIGEONCTRL1_CLR
__IO uint32_t PIGEONCTRL1_CLR
Definition: MIMXRT1052.h:23563
kDmaRequestMuxFlexPWM4CaptureSub0
@ kDmaRequestMuxFlexPWM4CaptureSub0
Definition: MIMXRT1052.h:402
kXBARA1_OutputLpuart2TrgInput
@ kXBARA1_OutputLpuart2TrgInput
Definition: MIMXRT1052.h:1203
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1052.h:613
TMR4_IRQn
@ TMR4_IRQn
Definition: MIMXRT1052.h:230
kDmaRequestMuxSai3Tx
@ kDmaRequestMuxSai3Tx
Definition: MIMXRT1052.h:384
CSU_Type::SA
__IO uint32_t SA
Definition: MIMXRT1052.h:9474
kXBARA1_InputDmaDone2
@ kXBARA1_InputDmaDone2
Definition: MIMXRT1052.h:941
BEE_Type::STATUS
__IO uint32_t STATUS
Definition: MIMXRT1052.h:3018
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
Definition: MIMXRT1052.h:525
CMP_Type::CR1
__IO uint8_t CR1
Definition: MIMXRT1052.h:8543
DMA12_DMA28_IRQn
@ DMA12_DMA28_IRQn
Definition: MIMXRT1052.h:106
PIT_Type::@313::TFLG
__IO uint32_t TFLG
Definition: MIMXRT1052.h:28519
LCDIF_Type::VDCTRL0
__IO uint32_t VDCTRL0
Definition: MIMXRT1052.h:23537
kIOMUXC_CCM_PMIC_READY_SELECT_INPUT
@ kIOMUXC_CCM_PMIC_READY_SELECT_INPUT
Definition: MIMXRT1052.h:719
kIOMUXC_XBAR1_IN23_SELECT_INPUT
@ kIOMUXC_XBAR1_IN23_SELECT_INPUT
Definition: MIMXRT1052.h:863
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1052.h:465
kIOMUXC_LPUART5_RX_SELECT_INPUT
@ kIOMUXC_LPUART5_RX_SELECT_INPUT
Definition: MIMXRT1052.h:802
XBARA_Type::SEL54
__IO uint16_t SEL54
Definition: MIMXRT1052.h:44189
kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT
Definition: MIMXRT1052.h:813
kIOMUXC_XBAR1_IN06_SELECT_INPUT
@ kIOMUXC_XBAR1_IN06_SELECT_INPUT
Definition: MIMXRT1052.h:855
kXBARB2_InputDmaDone3
@ kXBARB2_InputDmaDone3
Definition: MIMXRT1052.h:1016
kXBARA1_InputAcmp3Out
@ kXBARA1_InputAcmp3Out
Definition: MIMXRT1052.h:903
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13
Definition: MIMXRT1052.h:528
IOMUXC_SNVS_GPR_Type::GPR3
__IO uint32_t GPR3
Definition: MIMXRT1052.h:23307
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1052.h:691
CCM_Type::CCR
__IO uint32_t CCR
Definition: MIMXRT1052.h:4155
GPC_Type::IMR5
__IO uint32_t IMR5
Definition: MIMXRT1052.h:19002
XBARA_Type::SEL51
__IO uint16_t SEL51
Definition: MIMXRT1052.h:44186
kXBARA1_OutputLpspi1TrgInput
@ kXBARA1_OutputLpspi1TrgInput
Definition: MIMXRT1052.h:1198
PWM_Type::@314::FRACVAL2
__IO uint16_t FRACVAL2
Definition: MIMXRT1052.h:30853
PMU_Type::MISC2_TOG
__IO uint32_t MISC2_TOG
Definition: MIMXRT1052.h:28696
PWM_Type::@314::VAL0
__IO uint16_t VAL0
Definition: MIMXRT1052.h:30850
ENET_Type::FTRL
__IO uint32_t FTRL
Definition: MIMXRT1052.h:15649
TEMPMON_Type::TEMPSENSE0
__IO uint32_t TEMPSENSE0
Definition: MIMXRT1052.h:37131
kXBARA1_InputEnc4PosMatch
@ kXBARA1_InputEnc4PosMatch
Definition: MIMXRT1052.h:938
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1052.h:597
kXBARB3_OutputAoi2In07
@ kXBARB3_OutputAoi2In07
Definition: MIMXRT1052.h:1237
CCM_ANALOG_Type::PLL_VIDEO_SET
__IO uint32_t PLL_VIDEO_SET
Definition: MIMXRT1052.h:6104
kXBARB2_InputQtimer3Tmr3Output
@ kXBARB2_InputQtimer3Tmr3Output
Definition: MIMXRT1052.h:978
PWM2_2_IRQn
@ PWM2_2_IRQn
Definition: MIMXRT1052.h:233
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1052.h:551
IOMUXC_GPR_Type::GPR16
__IO uint32_t GPR16
Definition: MIMXRT1052.h:20874
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1052.h:492
SPDIF_Type::@315::SIS
__I uint32_t SIS
Definition: MIMXRT1052.h:36423
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP
__IO uint32_t SW_PAD_CTL_PAD_WAKEUP
Definition: MIMXRT1052.h:22802
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1052.h:562
kXBARA1_InputEnc3PosMatch
@ kXBARA1_InputEnc3PosMatch
Definition: MIMXRT1052.h:937
PWM2_FAULT_IRQn
@ PWM2_FAULT_IRQn
Definition: MIMXRT1052.h:235
SPDIF_Type::STR
__O uint32_t STR
Definition: MIMXRT1052.h:36432
SPDIF_Type::SRCSL
__I uint32_t SRCSL
Definition: MIMXRT1052.h:36428
SEMC_Type::NANDCR2
__IO uint32_t NANDCR2
Definition: MIMXRT1052.h:34144
kDmaRequestMuxCSI
@ kDmaRequestMuxCSI
Definition: MIMXRT1052.h:318
ENET_Type::RMON_R_JAB
__I uint32_t RMON_R_JAB
Definition: MIMXRT1052.h:15692
Reserved143_IRQn
@ Reserved143_IRQn
Definition: MIMXRT1052.h:221
IOMUXC_GPR_Type::GPR22
__IO uint32_t GPR22
Definition: MIMXRT1052.h:20880
XBARA_Type::SEL12
__IO uint16_t SEL12
Definition: MIMXRT1052.h:44147
PWM_Type::@314::VAL2
__IO uint16_t VAL2
Definition: MIMXRT1052.h:30854
PWM_Type::MASK
__IO uint16_t MASK
Definition: MIMXRT1052.h:30891
PXP_Type::OUT_BUF2
__IO uint32_t OUT_BUF2
Definition: MIMXRT1052.h:32524
ADC_ETC_Type::@301::TRIGn_COUNTER
__IO uint32_t TRIGn_COUNTER
Definition: MIMXRT1052.h:1624
FLEXIO_Type::SHIFTEIEN
__IO uint32_t SHIFTEIEN
Definition: MIMXRT1052.h:17376
DCP_Type::CH0OPTS_SET
__IO uint32_t CH0OPTS_SET
Definition: MIMXRT1052.h:10315
ENET_Type::IEEE_T_DEF
__I uint32_t IEEE_T_DEF
Definition: MIMXRT1052.h:15676
CCM_ANALOG_Type::PLL_SYS_TOG
__IO uint32_t PLL_SYS_TOG
Definition: MIMXRT1052.h:6088
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:414
kDmaRequestMuxFlexPWM3ValueSub1
@ kDmaRequestMuxFlexPWM3ValueSub1
Definition: MIMXRT1052.h:350
PWM_Type::@314::FRCTRL
__IO uint16_t FRCTRL
Definition: MIMXRT1052.h:30861
FLEXRAM_Type
Definition: MIMXRT1052.h:17941
kXBARA1_OutputFlexio1TriggerIn0
@ kXBARA1_OutputFlexio1TriggerIn0
Definition: MIMXRT1052.h:1210
LPSPI_Type::RDR
__I uint32_t RDR
Definition: MIMXRT1052.h:26166
kXBARB2_InputDmaDone1
@ kXBARB2_InputDmaDone1
Definition: MIMXRT1052.h:1014
AIPSTZ_Type::OPACR1
__IO uint32_t OPACR1
Definition: MIMXRT1052.h:2081
CCM_ANALOG_Type
Definition: MIMXRT1052.h:6072
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1052.h:511
PMU_Type::REG_CORE_TOG
__IO uint32_t REG_CORE_TOG
Definition: MIMXRT1052.h:28684
DMA_Type::@304::@305::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
Definition: MIMXRT1052.h:12009
kDmaRequestMuxXBAR1Request1
@ kDmaRequestMuxXBAR1Request1
Definition: MIMXRT1052.h:336
CAN_Type::IFLAG1
__IO uint32_t IFLAG1
Definition: MIMXRT1052.h:3325
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1052.h:636
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
Definition: MIMXRT1052.h:741
PXP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:32510
kXBARA1_InputIomuxXbarInout12
@ kXBARA1_InputIomuxXbarInout12
Definition: MIMXRT1052.h:887
SVCall_IRQn
@ SVCall_IRQn
Definition: MIMXRT1052.h:88
kXBARA1_OutputIomuxXbarInout11
@ kXBARA1_OutputIomuxXbarInout11
Definition: MIMXRT1052.h:1094
USB_PHY2_IRQn
@ USB_PHY2_IRQn
Definition: MIMXRT1052.h:160
IOMUXC_GPR_Type::GPR10
__IO uint32_t GPR10
Definition: MIMXRT1052.h:20868
OCOTP_Type::SRK_REVOKE
__IO uint32_t SRK_REVOKE
Definition: MIMXRT1052.h:27798
CSU_Type::HP0
__IO uint32_t HP0
Definition: MIMXRT1052.h:9472
PWM_Type::@314::FRACVAL1
__IO uint16_t FRACVAL1
Definition: MIMXRT1052.h:30851
LPSPI_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:26145
kXBARA1_OutputQtimer2Tmr0Input
@ kXBARA1_OutputQtimer2Tmr0Input
Definition: MIMXRT1052.h:1173
LCDIF_Type::VDCTRL3
__IO uint32_t VDCTRL3
Definition: MIMXRT1052.h:23545
OCOTP_Type::SCS_TOG
__IO uint32_t SCS_TOG
Definition: MIMXRT1052.h:27716
kIOMUXC_CSI_DATA02_SELECT_INPUT
@ kIOMUXC_CSI_DATA02_SELECT_INPUT
Definition: MIMXRT1052.h:720
BEE_Type::AES_KEY0_W1
__IO uint32_t AES_KEY0_W1
Definition: MIMXRT1052.h:3015
RTWDOG_Type::WIN
__IO uint32_t WIN
Definition: MIMXRT1052.h:33931
OCOTP_Type::CFG3
__IO uint32_t CFG3
Definition: MIMXRT1052.h:27730
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1052.h:477
SEMC_Type::INTR
__IO uint32_t INTR
Definition: MIMXRT1052.h:34137
SEMC_Type::SRAMCR2
__IO uint32_t SRAMCR2
Definition: MIMXRT1052.h:34152
kXBARB3_InputDmaDone1
@ kXBARB3_InputDmaDone1
Definition: MIMXRT1052.h:1072
XBARB_Type::SEL6
__IO uint16_t SEL6
Definition: MIMXRT1052.h:45040
LCDIF_Type::CTRL1_CLR
__IO uint32_t CTRL1_CLR
Definition: MIMXRT1052.h:23525
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1052.h:443
kXBARA1_InputDmaDone3
@ kXBARA1_InputDmaDone3
Definition: MIMXRT1052.h:942
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04
Definition: MIMXRT1052.h:678
kXBARA1_OutputIomuxXbarInout07
@ kXBARA1_OutputIomuxXbarInout07
Definition: MIMXRT1052.h:1090
PWM_Type::@314::FRACVAL5
__IO uint16_t FRACVAL5
Definition: MIMXRT1052.h:30859
USB_Type::FRINDEX
__IO uint32_t FRINDEX
Definition: MIMXRT1052.h:39020
ENET_Type::GAUR
__IO uint32_t GAUR
Definition: MIMXRT1052.h:15632
DCP_Type::CH1OPTS_SET
__IO uint32_t CH1OPTS_SET
Definition: MIMXRT1052.h:10327
PXP_Type::OUT_PITCH
__IO uint32_t OUT_PITCH
Definition: MIMXRT1052.h:32526
kXBARA1_OutputEnc4PhaseBInput
@ kXBARA1_OutputEnc4PhaseBInput
Definition: MIMXRT1052.h:1165
SNVS_Type::HPSR
__IO uint32_t HPSR
Definition: MIMXRT1052.h:35325
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:360
IOMUXC_GPR_Type::GPR24
__IO uint32_t GPR24
Definition: MIMXRT1052.h:20882
kXBARA1_InputFlexpwm1Pwm2OutTrig01
@ kXBARA1_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1052.h:916
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1052.h:502
LPSPI_Type::IER
__IO uint32_t IER
Definition: MIMXRT1052.h:26150
kIOMUXC_USDHC2_DATA7_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA7_SELECT_INPUT
Definition: MIMXRT1052.h:849
LCDIF_Type::VDCTRL4
__IO uint32_t VDCTRL4
Definition: MIMXRT1052.h:23547
kXBARA1_InputDmaDone4
@ kXBARA1_InputDmaDone4
Definition: MIMXRT1052.h:943
kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
Definition: MIMXRT1052.h:751
PXP_IRQn
@ PXP_IRQn
Definition: MIMXRT1052.h:138
SEMC_Type::STS0
__I uint32_t STS0
Definition: MIMXRT1052.h:34165
DCP_Type::CH0CMDPTR
__IO uint32_t CH0CMDPTR
Definition: MIMXRT1052.h:10306
kXBARB3_InputRESERVED5
@ kXBARB3_InputRESERVED5
Definition: MIMXRT1052.h:1026
kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT
Definition: MIMXRT1052.h:812
SNVS_Type::LPGPR0_LEGACY_ALIAS
__IO uint32_t LPGPR0_LEGACY_ALIAS
Definition: MIMXRT1052.h:35346
GPIO1_INT0_IRQn
@ GPIO1_INT0_IRQn
Definition: MIMXRT1052.h:166
kXBARB2_InputQtimer3Tmr1Output
@ kXBARB2_InputQtimer3Tmr1Output
Definition: MIMXRT1052.h:976
CCM_ANALOG_Type::PLL_ARM_SET
__IO uint32_t PLL_ARM_SET
Definition: MIMXRT1052.h:6074
ADC_ETC_Type::DONE0_1_IRQ
__IO uint32_t DONE0_1_IRQ
Definition: MIMXRT1052.h:1619
SAI3_TX_IRQn
@ SAI3_TX_IRQn
Definition: MIMXRT1052.h:153
USB_Type::ENDPTNAK
__IO uint32_t ENDPTNAK
Definition: MIMXRT1052.h:39034
kDmaRequestMuxFlexPWM2ValueSub3
@ kDmaRequestMuxFlexPWM2ValueSub3
Definition: MIMXRT1052.h:401
XBARA_Type::SEL59
__IO uint16_t SEL59
Definition: MIMXRT1052.h:44194
kDmaRequestMuxSai3Rx
@ kDmaRequestMuxSai3Rx
Definition: MIMXRT1052.h:383
ENET_Type::RMON_T_P256TO511
__I uint32_t RMON_T_P256TO511
Definition: MIMXRT1052.h:15667
kXBARB2_OutputAoi1In06
@ kXBARB2_OutputAoi1In06
Definition: MIMXRT1052.h:1220
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1052.h:463
DCP_IRQn
@ DCP_IRQn
Definition: MIMXRT1052.h:144
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1052.h:499
TEMPMON_Type::TEMPSENSE1
__IO uint32_t TEMPSENSE1
Definition: MIMXRT1052.h:37135
ENET_Type::IEEE_R_ALIGN
__I uint32_t IEEE_R_ALIGN
Definition: MIMXRT1052.h:15705
kXBARA1_OutputFlexio2TriggerIn1
@ kXBARA1_OutputFlexio2TriggerIn1
Definition: MIMXRT1052.h:1213
LPI2C_Type::MIER
__IO uint32_t MIER
Definition: MIMXRT1052.h:25100
CCM_ANALOG_Type::PLL_AUDIO_CLR
__IO uint32_t PLL_AUDIO_CLR
Definition: MIMXRT1052.h:6097
DCDC_Type
Definition: MIMXRT1052.h:10084
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1052.h:455
CAN_Type::@303::CS
__IO uint32_t CS
Definition: MIMXRT1052.h:3337
kXBARA1_InputLogicLow
@ kXBARA1_InputLogicLow
Definition: MIMXRT1052.h:875
kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
Definition: MIMXRT1052.h:750
kXBARB2_InputFlexpwm1Pwm4OutTrig01
@ kXBARB2_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1052.h:986
PWM2_0_IRQn
@ PWM2_0_IRQn
Definition: MIMXRT1052.h:231
kXBARB3_InputQtimer4Tmr3Output
@ kXBARB3_InputQtimer4Tmr3Output
Definition: MIMXRT1052.h:1040
GPIO5_Combined_0_15_IRQn
@ GPIO5_Combined_0_15_IRQn
Definition: MIMXRT1052.h:182
__O
#define __O
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:236
CCM_ANALOG_Type::MISC1_SET
__IO uint32_t MISC1_SET
Definition: MIMXRT1052.h:6129
kIOMUXC_LPSPI1_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI1_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:780
kXBARB3_OutputAoi2In11
@ kXBARB3_OutputAoi2In11
Definition: MIMXRT1052.h:1241
kXBARB2_InputAdcEtcXbar1Coco2
@ kXBARB2_InputAdcEtcXbar1Coco2
Definition: MIMXRT1052.h:1007
DCP_Type::CH2CMDPTR
__IO uint32_t CH2CMDPTR
Definition: MIMXRT1052.h:10330
LPUART_Type::WATER
__IO uint32_t WATER
Definition: MIMXRT1052.h:26783
USBPHY_Type::TX_SET
__IO uint32_t TX_SET
Definition: MIMXRT1052.h:40689
XBARA_Type::SEL9
__IO uint16_t SEL9
Definition: MIMXRT1052.h:44144
TMR_Type::@317::CSCTRL
__IO uint16_t CSCTRL
Definition: MIMXRT1052.h:37390
SEMC_Type::STS11
uint32_t STS11
Definition: MIMXRT1052.h:34176
TRNG_Type::VID1
__I uint32_t VID1
Definition: MIMXRT1052.h:37935
kXBARB3_InputQtimer3Tmr2Output
@ kXBARB3_InputQtimer3Tmr2Output
Definition: MIMXRT1052.h:1035
kIOMUXC_LPUART2_RX_SELECT_INPUT
@ kIOMUXC_LPUART2_RX_SELECT_INPUT
Definition: MIMXRT1052.h:795
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
Definition: MIMXRT1052.h:532
PXP_Type::PS_CLRKEYHIGH
__IO uint32_t PS_CLRKEYHIGH
Definition: MIMXRT1052.h:32558
kXBARB2_InputFlexpwm4Pwm4OutTrig01
@ kXBARB2_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1052.h:998
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1052.h:649
XBARA_Type::SEL33
__IO uint16_t SEL33
Definition: MIMXRT1052.h:44168
PXP_Type::OUT_PS_ULC
__IO uint32_t OUT_PS_ULC
Definition: MIMXRT1052.h:32530
kIOMUXC_ENET_TXCLK_SELECT_INPUT
@ kIOMUXC_ENET_TXCLK_SELECT_INPUT
Definition: MIMXRT1052.h:738
CAN_Type::DBG2
__I uint32_t DBG2
Definition: MIMXRT1052.h:3334
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1052.h:447
kXBARA1_OutputIomuxXbarInout12
@ kXBARA1_OutputIomuxXbarInout12
Definition: MIMXRT1052.h:1095
kXBARA1_InputAdcEtcXbar1Coco2
@ kXBARA1_InputAdcEtcXbar1Coco2
Definition: MIMXRT1052.h:961
XTALOSC24M_Type::OSC_CONFIG0
__IO uint32_t OSC_CONFIG0
Definition: MIMXRT1052.h:45180
USB_ANALOG_Type::@342::MISC
__IO uint32_t MISC
Definition: MIMXRT1052.h:41817
AIPSTZ_Type::MPR
__IO uint32_t MPR
Definition: MIMXRT1052.h:2078
USB_ANALOG_Type::@342::VBUS_DETECT_TOG
__IO uint32_t VBUS_DETECT_TOG
Definition: MIMXRT1052.h:41804
PXP_Type::STAT_TOG
__IO uint32_t STAT_TOG
Definition: MIMXRT1052.h:32517
kIOMUXC_XBAR1_IN03_SELECT_INPUT
@ kIOMUXC_XBAR1_IN03_SELECT_INPUT
Definition: MIMXRT1052.h:852
kXBARA1_InputFlexpwm1Pwm4OutTrig01
@ kXBARA1_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1052.h:918
USBPHY_Type::PWD_SET
__IO uint32_t PWD_SET
Definition: MIMXRT1052.h:40685
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1052.h:651
kXBARB3_InputFlexpwm3Pwm3OutTrig01
@ kXBARB3_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1052.h:1051
LPSPI_Type
Definition: MIMXRT1052.h:26144
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition: MIMXRT1052.h:304
PXP_Type::OUT_CTRL_CLR
__IO uint32_t OUT_CTRL_CLR
Definition: MIMXRT1052.h:32520
USB_ANALOG_Type::DIGPROG
__I uint32_t DIGPROG
Definition: MIMXRT1052.h:41822
kXBARA1_OutputFlexpwm3Fault1
@ kXBARA1_OutputFlexpwm3Fault1
Definition: MIMXRT1052.h:1140
kXBARA1_InputDmaDone1
@ kXBARA1_InputDmaDone1
Definition: MIMXRT1052.h:940
PXP_Type::CSC1_COEF1
__IO uint32_t CSC1_COEF1
Definition: MIMXRT1052.h:32572
ENC_Type::LINIT
__IO uint16_t LINIT
Definition: MIMXRT1052.h:15151
XTALOSC24M_Type::OSC_CONFIG0_TOG
__IO uint32_t OSC_CONFIG0_TOG
Definition: MIMXRT1052.h:45183
DMA_Type::DCHPRI15
__IO uint8_t DCHPRI15
Definition: MIMXRT1052.h:11983
CCM_ANALOG_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1052.h:6124
DMA_Type::EARS
__IO uint32_t EARS
Definition: MIMXRT1052.h:11969
kXBARA1_OutputQtimer2Tmr3Input
@ kXBARA1_OutputQtimer2Tmr3Input
Definition: MIMXRT1052.h:1176
kDmaRequestMuxSpdifRx
@ kDmaRequestMuxSpdifRx
Definition: MIMXRT1052.h:385
IOMUXC_SNVS_GPR_Type::GPR0
uint32_t GPR0
Definition: MIMXRT1052.h:23304
ENET_Type::TDSR
__IO uint32_t TDSR
Definition: MIMXRT1052.h:15638
kXBARA1_OutputIomuxXbarInout19
@ kXBARA1_OutputIomuxXbarInout19
Definition: MIMXRT1052.h:1102
GPIO1_INT5_IRQn
@ GPIO1_INT5_IRQn
Definition: MIMXRT1052.h:171
kXBARA1_OutputLpi2c4TrgInput
@ kXBARA1_OutputLpi2c4TrgInput
Definition: MIMXRT1052.h:1197
kXBARA1_InputIomuxXbarInout13
@ kXBARA1_InputIomuxXbarInout13
Definition: MIMXRT1052.h:888
ENET_Type::ATVR
__IO uint32_t ATVR
Definition: MIMXRT1052.h:15711
CCM_ANALOG_Type::PLL_SYS_NUM
__IO uint32_t PLL_SYS_NUM
Definition: MIMXRT1052.h:6091
kXBARB2_OutputAoi1In09
@ kXBARB2_OutputAoi1In09
Definition: MIMXRT1052.h:1223
XBARA_Type::SEL16
__IO uint16_t SEL16
Definition: MIMXRT1052.h:44151
kXBARA1_OutputQtimer1Tmr3Input
@ kXBARA1_OutputQtimer1Tmr3Input
Definition: MIMXRT1052.h:1172
kXBARB3_InputRESERVED2
@ kXBARB3_InputRESERVED2
Definition: MIMXRT1052.h:1023
LPSPI_Type::CFGR1
__IO uint32_t CFGR1
Definition: MIMXRT1052.h:26153
CSI_Type::CSIDMATS_STATFIFO
__IO uint32_t CSIDMATS_STATFIFO
Definition: MIMXRT1052.h:8801
kXBARB3_InputDmaDone2
@ kXBARB3_InputDmaDone2
Definition: MIMXRT1052.h:1073
ENC_Type::POSDH
__I uint16_t POSDH
Definition: MIMXRT1052.h:15143
DCP_Type::PACKET2
__I uint32_t PACKET2
Definition: MIMXRT1052.h:10296
LCDIF_Type::PIGEONCTRL0
__IO uint32_t PIGEONCTRL0
Definition: MIMXRT1052.h:23557
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1052.h:700
XBARA_Type::SEL25
__IO uint16_t SEL25
Definition: MIMXRT1052.h:44160
kDmaRequestMuxLPUART8Tx
@ kDmaRequestMuxLPUART8Tx
Definition: MIMXRT1052.h:373
ENET_Type::IEEE_T_DROP
uint32_t IEEE_T_DROP
Definition: MIMXRT1052.h:15672
PWM_Type::FTST
__IO uint16_t FTST
Definition: MIMXRT1052.h:30899
CAN_Type::CRCR
__I uint32_t CRCR
Definition: MIMXRT1052.h:3329
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1052.h:692
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1052.h:564
ENET_IRQn
@ ENET_IRQn
Definition: MIMXRT1052.h:208
kXBARA1_InputQtimer3Tmr0Output
@ kXBARA1_InputQtimer3Tmr0Output
Definition: MIMXRT1052.h:907
kIOMUXC_LPSPI1_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI1_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:782
BEE_Type::CTR_NONCE0_W2
__O uint32_t CTR_NONCE0_W2
Definition: MIMXRT1052.h:3021
LPSPI_Type::DMR0
__IO uint32_t DMR0
Definition: MIMXRT1052.h:26155
kXBARB3_InputFlexpwm3Pwm2OutTrig01
@ kXBARB3_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1052.h:1050
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1052.h:476
SJC_IRQn
@ SJC_IRQn
Definition: MIMXRT1052.h:148
kDmaRequestMuxLPUART7Tx
@ kDmaRequestMuxLPUART7Tx
Definition: MIMXRT1052.h:316
DCP_Type::CH1STAT_TOG
__IO uint32_t CH1STAT_TOG
Definition: MIMXRT1052.h:10325
LCDIF_Type::STAT
__I uint32_t STAT
Definition: MIMXRT1052.h:23553
LPSPI1_IRQn
@ LPSPI1_IRQn
Definition: MIMXRT1052.h:126
kXBARB3_InputDmaDone4
@ kXBARB3_InputDmaDone4
Definition: MIMXRT1052.h:1075
TRNG_Type::STATUS
__I uint32_t STATUS
Definition: MIMXRT1052.h:37920
USBPHY_Type::RX_SET
__IO uint32_t RX_SET
Definition: MIMXRT1052.h:40693
TRNG_Type::@332::SCR4C
__I uint32_t SCR4C
Definition: MIMXRT1052.h:37909
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1052.h:698
DMA_Type::DCHPRI10
__IO uint8_t DCHPRI10
Definition: MIMXRT1052.h:11980
USBPHY_Type::PWD_CLR
__IO uint32_t PWD_CLR
Definition: MIMXRT1052.h:40686
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1052.h:653
XTALOSC24M_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1052.h:45171
CCM_ANALOG_Type::PLL_USB2_TOG
__IO uint32_t PLL_USB2_TOG
Definition: MIMXRT1052.h:6084
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1052.h:600
SEMC_Type::STS14
uint32_t STS14
Definition: MIMXRT1052.h:34179
DCP_Type::PAGETABLE
__IO uint32_t PAGETABLE
Definition: MIMXRT1052.h:10359
kDmaRequestMuxLPUART5Tx
@ kDmaRequestMuxLPUART5Tx
Definition: MIMXRT1052.h:314
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08
Definition: MIMXRT1052.h:539
CAN_Type::RXFIR
__I uint32_t RXFIR
Definition: MIMXRT1052.h:3331
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1052.h:609
XBARB_Type::SEL2
__IO uint16_t SEL2
Definition: MIMXRT1052.h:45036
ENET_Type::IEEE_R_CRC
__I uint32_t IEEE_R_CRC
Definition: MIMXRT1052.h:15704
USBPHY_Type::DEBUG_CLR
__IO uint32_t DEBUG_CLR
Definition: MIMXRT1052.h:40704
XBARA_Type::SEL64
__IO uint16_t SEL64
Definition: MIMXRT1052.h:44199
kXBARB3_InputLogicHigh
@ kXBARB3_InputLogicHigh
Definition: MIMXRT1052.h:1022
kXBARA1_InputFlexpwm4Pwm4OutTrig01
@ kXBARA1_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1052.h:930
PWM_Type
Definition: MIMXRT1052.h:30843
SEMC_Type::NORCR0
__IO uint32_t NORCR0
Definition: MIMXRT1052.h:34146
kXBARB3_OutputAoi2In00
@ kXBARB3_OutputAoi2In00
Definition: MIMXRT1052.h:1230
ENC_Type::TST
__IO uint16_t TST
Definition: MIMXRT1052.h:15153
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1052.h:514
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1052.h:645
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1052.h:508
DCP_Type::CH2OPTS_SET
__IO uint32_t CH2OPTS_SET
Definition: MIMXRT1052.h:10339
kXBARA1_OutputAdcEtcXbar0Trig3
@ kXBARA1_OutputAdcEtcXbar0Trig3
Definition: MIMXRT1052.h:1189
PMU_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1052.h:28685
ENET_Type::PALR
__IO uint32_t PALR
Definition: MIMXRT1052.h:15623
PMU_Type
Definition: MIMXRT1052.h:28667
USDHC_Type::CLK_TUNE_CTRL_STATUS
__IO uint32_t CLK_TUNE_CTRL_STATUS
Definition: MIMXRT1052.h:42280
XBARB_Type::SEL1
__IO uint16_t SEL1
Definition: MIMXRT1052.h:45035
kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
Definition: MIMXRT1052.h:748
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04
Definition: MIMXRT1052.h:662
DMA_Type::ES
__I uint32_t ES
Definition: MIMXRT1052.h:11949
SNVS_Type::LPSRTCLR
__IO uint32_t LPSRTCLR
Definition: MIMXRT1052.h:35341
SRC_Type::SBMR1
__I uint32_t SBMR1
Definition: MIMXRT1052.h:36903
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1052.h:623
DMA_Type::HRS
__I uint32_t HRS
Definition: MIMXRT1052.h:11967
TEMPMON_Type::TEMPSENSE2_SET
__IO uint32_t TEMPSENSE2_SET
Definition: MIMXRT1052.h:37141
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: MIMXRT1052.h:85
CSI_Type::CSISTATFIFO
__I uint32_t CSISTATFIFO
Definition: MIMXRT1052.h:8795
kXBARA1_OutputFlexpwm1Exta3
@ kXBARA1_OutputFlexpwm1Exta3
Definition: MIMXRT1052.h:1112
EWM_Type::CLKPRESCALER
__IO uint8_t CLKPRESCALER
Definition: MIMXRT1052.h:17252
KPP_IRQn
@ KPP_IRQn
Definition: MIMXRT1052.h:133
ENET_Type::EIR
__IO uint32_t EIR
Definition: MIMXRT1052.h:15606
CSI_Type::CSIRFIFO
__I uint32_t CSIRFIFO
Definition: MIMXRT1052.h:8796
ENET_Type::RMON_R_P1024TO2047
__I uint32_t RMON_R_P1024TO2047
Definition: MIMXRT1052.h:15699
ENET_Type::RMON_T_P128TO255
__I uint32_t RMON_T_P128TO255
Definition: MIMXRT1052.h:15666
ADC_ETC_Type::@301::TRIGn_RESULT_3_2
__I uint32_t TRIGn_RESULT_3_2
Definition: MIMXRT1052.h:1630
XTALOSC24M_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1052.h:45172
USB_Type::USBCMD
__IO uint32_t USBCMD
Definition: MIMXRT1052.h:39017
kIOMUXC_CSI_DATA04_SELECT_INPUT
@ kIOMUXC_CSI_DATA04_SELECT_INPUT
Definition: MIMXRT1052.h:722
DMA_Type::DCHPRI5
__IO uint8_t DCHPRI5
Definition: MIMXRT1052.h:11977
kDmaRequestMuxFlexPWM3CaptureSub0
@ kDmaRequestMuxFlexPWM3CaptureSub0
Definition: MIMXRT1052.h:345
LCDIF_Type::VDCTRL0_TOG
__IO uint32_t VDCTRL0_TOG
Definition: MIMXRT1052.h:23540
CCM_Type::CCGR2
__IO uint32_t CCGR2
Definition: MIMXRT1052.h:4181
ENET_Type::RMON_R_MC_PKT
__I uint32_t RMON_R_MC_PKT
Definition: MIMXRT1052.h:15687
OCOTP_Type::SCS
__IO uint32_t SCS
Definition: MIMXRT1052.h:27713
XTALOSC24M_Type::OSC_CONFIG1_CLR
__IO uint32_t OSC_CONFIG1_CLR
Definition: MIMXRT1052.h:45186
LPUART_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:26773
kIOMUXC_XBAR1_IN08_SELECT_INPUT
@ kIOMUXC_XBAR1_IN08_SELECT_INPUT
Definition: MIMXRT1052.h:857
kXBARB2_OutputAoi1In04
@ kXBARB2_OutputAoi1In04
Definition: MIMXRT1052.h:1218
kIOMUXC_CSI_PIXCLK_SELECT_INPUT
@ kIOMUXC_CSI_PIXCLK_SELECT_INPUT
Definition: MIMXRT1052.h:729
USB_Type::CONFIGFLAG
__I uint32_t CONFIGFLAG
Definition: MIMXRT1052.h:39036
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
Definition: MIMXRT1052.h:515
DCP_Type::CAPABILITY1
__I uint32_t CAPABILITY1
Definition: MIMXRT1052.h:10284
OCOTP_Type::MISC_CONF1
__IO uint32_t MISC_CONF1
Definition: MIMXRT1052.h:27796
PXP_Type::CSC1_COEF0
__IO uint32_t CSC1_COEF0
Definition: MIMXRT1052.h:32570
PIT_Type::@313::CVAL
__I uint32_t CVAL
Definition: MIMXRT1052.h:28517
XBARA_Type::SEL58
__IO uint16_t SEL58
Definition: MIMXRT1052.h:44193
RTWDOG_Type
Definition: MIMXRT1052.h:33927
OCOTP_Type::SRK1
__IO uint32_t SRK1
Definition: MIMXRT1052.h:27756
SEMC_Type::IPCR2
__IO uint32_t IPCR2
Definition: MIMXRT1052.h:34159
GPIO_Type::DR_SET
__O uint32_t DR_SET
Definition: MIMXRT1052.h:19135
LPSPI3_IRQn
@ LPSPI3_IRQn
Definition: MIMXRT1052.h:128
BEE_Type::ADDR_OFFSET0
__IO uint32_t ADDR_OFFSET0
Definition: MIMXRT1052.h:3012
PGC_Type
Definition: MIMXRT1052.h:28372
GPIO_Type::DR_TOGGLE
__O uint32_t DR_TOGGLE
Definition: MIMXRT1052.h:19137
kIOMUXC_XBAR1_IN22_SELECT_INPUT
@ kIOMUXC_XBAR1_IN22_SELECT_INPUT
Definition: MIMXRT1052.h:862
TRNG_Type::PKRCNT98
__I uint32_t PKRCNT98
Definition: MIMXRT1052.h:37926
PXP_Type::OUT_LRC
__IO uint32_t OUT_LRC
Definition: MIMXRT1052.h:32528
kXBARB2_InputDmaDone0
@ kXBARB2_InputDmaDone0
Definition: MIMXRT1052.h:1013
LPSPI_Type::CCR
__IO uint32_t CCR
Definition: MIMXRT1052.h:26158
ENET_Type::RMON_R_P128TO255
__I uint32_t RMON_R_P128TO255
Definition: MIMXRT1052.h:15696
kXBARA1_InputAcmp2Out
@ kXBARA1_InputAcmp2Out
Definition: MIMXRT1052.h:902
kIOMUXC_XBAR1_IN02_SELECT_INPUT
@ kIOMUXC_XBAR1_IN02_SELECT_INPUT
Definition: MIMXRT1052.h:851
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1052.h:629
kXBARA1_OutputAdcEtcXbar0Trig1
@ kXBARA1_OutputAdcEtcXbar0Trig1
Definition: MIMXRT1052.h:1187
LPI2C_Type::MCFGR3
__IO uint32_t MCFGR3
Definition: MIMXRT1052.h:25105
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1052.h:639
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1052.h:655
TRNG_Type::SCMISC
__IO uint32_t SCMISC
Definition: MIMXRT1052.h:37876
kXBARA1_InputIomuxXbarInout19
@ kXBARA1_InputIomuxXbarInout19
Definition: MIMXRT1052.h:894
XBARA_Type::SEL29
__IO uint16_t SEL29
Definition: MIMXRT1052.h:44164
USB_Type::HWGENERAL
__I uint32_t HWGENERAL
Definition: MIMXRT1052.h:38995
DCP_Type::PACKET1
__I uint32_t PACKET1
Definition: MIMXRT1052.h:10294
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15
Definition: MIMXRT1052.h:673
kIOMUXC_USDHC2_DATA1_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:843
SNVS_Type::HPLR
__IO uint32_t HPLR
Definition: MIMXRT1052.h:35320
kXBARA1_InputQtimer3Tmr3Output
@ kXBARA1_InputQtimer3Tmr3Output
Definition: MIMXRT1052.h:910
OCOTP_Type
Definition: MIMXRT1052.h:27698
DMA_Type::DCHPRI27
__IO uint8_t DCHPRI27
Definition: MIMXRT1052.h:11995
SEMC_Type::STS9
uint32_t STS9
Definition: MIMXRT1052.h:34174
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09
Definition: MIMXRT1052.h:540
LPSPI_Type::DMR1
__IO uint32_t DMR1
Definition: MIMXRT1052.h:26156
BEE_Type::AES_KEY0_W2
__IO uint32_t AES_KEY0_W2
Definition: MIMXRT1052.h:3016
KPP_Type::KDDR
__IO uint16_t KDDR
Definition: MIMXRT1052.h:23380
kIOMUXC_LPI2C3_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C3_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:775
USB_Type::BURSTSIZE
__IO uint32_t BURSTSIZE
Definition: MIMXRT1052.h:39031
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14
Definition: MIMXRT1052.h:672
USBPHY_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:40697
XBARA_Type::SEL40
__IO uint16_t SEL40
Definition: MIMXRT1052.h:44175
DCP_VMI_IRQn
@ DCP_VMI_IRQn
Definition: MIMXRT1052.h:145
USBPHY_Type::RX_CLR
__IO uint32_t RX_CLR
Definition: MIMXRT1052.h:40694
DMA5_DMA21_IRQn
@ DMA5_DMA21_IRQn
Definition: MIMXRT1052.h:99
OCOTP_Type::SW_GP23
__IO uint32_t SW_GP23
Definition: MIMXRT1052.h:27792
ENET_Type::@311::TCSR
__IO uint32_t TCSR
Definition: MIMXRT1052.h:15720
PXP_Type::PS_OFFSET
__IO uint32_t PS_OFFSET
Definition: MIMXRT1052.h:32554
USDHC_Type::MIX_CTRL
__IO uint32_t MIX_CTRL
Definition: MIMXRT1052.h:42272
OCOTP_Type::MISC_CONF0
__IO uint32_t MISC_CONF0
Definition: MIMXRT1052.h:27794
iomuxc_sw_mux_ctl_pad_t
enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
ENC_Type::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1052.h:15139
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1052.h:705
ROMC_Type::ROMPATCHENL
__IO uint32_t ROMPATCHENL
Definition: MIMXRT1052.h:33806
SEMC_Type::SDRAMCR1
__IO uint32_t SDRAMCR1
Definition: MIMXRT1052.h:34139
kDmaRequestMuxFlexIO1Request2Request3
@ kDmaRequestMuxFlexIO1Request2Request3
Definition: MIMXRT1052.h:365
OCOTP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:27701
USB_Type::@340::ASYNCLISTADDR
__IO uint32_t ASYNCLISTADDR
Definition: MIMXRT1052.h:39027
I2S_Type::TCR2
__IO uint32_t TCR2
Definition: MIMXRT1052.h:19872
kIOMUXC_LPSPI2_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI2_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:785
CCM_ANALOG_Type::PFD_528_TOG
__IO uint32_t PFD_528_TOG
Definition: MIMXRT1052.h:6122
XTALOSC24M_Type::OSC_CONFIG2_TOG
__IO uint32_t OSC_CONFIG2_TOG
Definition: MIMXRT1052.h:45191
SAI1_IRQn
@ SAI1_IRQn
Definition: MIMXRT1052.h:150
CAN_Type::GFWR
__IO uint32_t GFWR
Definition: MIMXRT1052.h:3345
ENET_Type::RMON_R_OVERSIZE
__I uint32_t RMON_R_OVERSIZE
Definition: MIMXRT1052.h:15690
DCP_Type::STAT_CLR
__IO uint32_t STAT_CLR
Definition: MIMXRT1052.h:10276
PWM_Type::SWCOUT
__IO uint16_t SWCOUT
Definition: MIMXRT1052.h:30892
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1052.h:497
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1052.h:496
ADC_Type::HS
__I uint32_t HS
Definition: MIMXRT1052.h:1298
kXBARA1_InputIomuxXbarInout10
@ kXBARA1_InputIomuxXbarInout10
Definition: MIMXRT1052.h:885
OCOTP_Type::ANA2
__IO uint32_t ANA2
Definition: MIMXRT1052.h:27752
SEMC_Type::STS13
uint32_t STS13
Definition: MIMXRT1052.h:34178
CSI_Type::CSICR1
__IO uint32_t CSICR1
Definition: MIMXRT1052.h:8792
kIOMUXC_CSI_VSYNC_SELECT_INPUT
@ kIOMUXC_CSI_VSYNC_SELECT_INPUT
Definition: MIMXRT1052.h:730
SNVS_Type::LPSR
__IO uint32_t LPSR
Definition: MIMXRT1052.h:35339
ENET_Type::TFWR
__IO uint32_t TFWR
Definition: MIMXRT1052.h:15635
XBARA_Type::SEL46
__IO uint16_t SEL46
Definition: MIMXRT1052.h:44181
SNVS_LP_WRAPPER_IRQn
@ SNVS_LP_WRAPPER_IRQn
Definition: MIMXRT1052.h:142
LPUART7_IRQn
@ LPUART7_IRQn
Definition: MIMXRT1052.h:120
DMAMUX_Type
Definition: MIMXRT1052.h:15060
kXBARA1_InputEnc1PosMatch
@ kXBARA1_InputEnc1PosMatch
Definition: MIMXRT1052.h:935
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06
Definition: MIMXRT1052.h:664
USB_Type::DCCPARAMS
__I uint32_t DCCPARAMS
Definition: MIMXRT1052.h:39015
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1052.h:635
TRNG_Type::@318::PKRSQ
__I uint32_t PKRSQ
Definition: MIMXRT1052.h:37880
USDHC_Type::CMD_RSP3
__I uint32_t CMD_RSP3
Definition: MIMXRT1052.h:42261
USDHC_Type::FORCE_EVENT
__O uint32_t FORCE_EVENT
Definition: MIMXRT1052.h:42274
USB_ANALOG_Type::@342::CHRG_DETECT_STAT
__I uint32_t CHRG_DETECT_STAT
Definition: MIMXRT1052.h:41811
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1052.h:650
kXBARA1_OutputFlexpwm2Fault0
@ kXBARA1_OutputFlexpwm2Fault0
Definition: MIMXRT1052.h:1132
kXBARA1_OutputFlexpwm2ExtSync1
@ kXBARA1_OutputFlexpwm2ExtSync1
Definition: MIMXRT1052.h:1128
LPUART_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:26772
USB_Type::@340::ENDPTLISTADDR
__IO uint32_t ENDPTLISTADDR
Definition: MIMXRT1052.h:39028
DMA_Type::@304::@307::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
Definition: MIMXRT1052.h:12017
DMA_Type::@304::SOFF
__IO uint16_t SOFF
Definition: MIMXRT1052.h:12006
kXBARA1_OutputAdcEtcXbar0Trig2
@ kXBARA1_OutputAdcEtcXbar0Trig2
Definition: MIMXRT1052.h:1188
DCP_Type::CH0OPTS_CLR
__IO uint32_t CH0OPTS_CLR
Definition: MIMXRT1052.h:10316
LPI2C_Type::STDR
__O uint32_t STDR
Definition: MIMXRT1052.h:25132
XBARA_Type::SEL32
__IO uint16_t SEL32
Definition: MIMXRT1052.h:44167
kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
Definition: MIMXRT1052.h:745
TRNG_Type::@334::SCR5L
__IO uint32_t SCR5L
Definition: MIMXRT1052.h:37914
USB_Type::HWRXBUF
__I uint32_t HWRXBUF
Definition: MIMXRT1052.h:38999
kXBARB2_OutputAoi1In14
@ kXBARB2_OutputAoi1In14
Definition: MIMXRT1052.h:1228
PXP_Type::OUT_CTRL
__IO uint32_t OUT_CTRL
Definition: MIMXRT1052.h:32518
kIOMUXC_LPI2C1_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C1_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:771
ENET_Type::RMON_R_BC_PKT
__I uint32_t RMON_R_BC_PKT
Definition: MIMXRT1052.h:15686
kDmaRequestMuxLPUART6Tx
@ kDmaRequestMuxLPUART6Tx
Definition: MIMXRT1052.h:371
ENET_Type::IEEE_R_MACERR
__I uint32_t IEEE_R_MACERR
Definition: MIMXRT1052.h:15706
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1052.h:556
kIOMUXC_CSI_DATA06_SELECT_INPUT
@ kIOMUXC_CSI_DATA06_SELECT_INPUT
Definition: MIMXRT1052.h:724
PMU_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1052.h:28686
LPUART_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1052.h:26777
TRNG_Type::MCTL
__IO uint32_t MCTL
Definition: MIMXRT1052.h:37875
SPDIF_Type::STL
__O uint32_t STL
Definition: MIMXRT1052.h:36431
CCM_ANALOG_Type::PLL_ENET
__IO uint32_t PLL_ENET
Definition: MIMXRT1052.h:6111
PWM_Type::@314::CTRL2
__IO uint16_t CTRL2
Definition: MIMXRT1052.h:30847
FLEXSPI_Type::IPTXFCR
__IO uint32_t IPTXFCR
Definition: MIMXRT1052.h:18112
USB_Type::GPTIMER0LD
__IO uint32_t GPTIMER0LD
Definition: MIMXRT1052.h:39001
USB_Type::GPTIMER0CTRL
__IO uint32_t GPTIMER0CTRL
Definition: MIMXRT1052.h:39002
kDmaRequestMuxLPUART1Tx
@ kDmaRequestMuxLPUART1Tx
Definition: MIMXRT1052.h:310
PWM_Type::@314::CVAL1
__I uint16_t CVAL1
Definition: MIMXRT1052.h:30878
USBPHY_Type::DEBUG_TOG
__IO uint32_t DEBUG_TOG
Definition: MIMXRT1052.h:40705
FLEXSPI_Type::MCR0
__IO uint32_t MCR0
Definition: MIMXRT1052.h:18090
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1052.h:554
kDmaRequestMuxFlexPWM3CaptureSub1
@ kDmaRequestMuxFlexPWM3CaptureSub1
Definition: MIMXRT1052.h:346
ENC_Type
Definition: MIMXRT1052.h:15138
XBARB_Type
Definition: MIMXRT1052.h:45033
ENET_Type::RMON_T_PACKETS
__I uint32_t RMON_T_PACKETS
Definition: MIMXRT1052.h:15655
DMA10_DMA26_IRQn
@ DMA10_DMA26_IRQn
Definition: MIMXRT1052.h:104
XBARA_Type::SEL0
__IO uint16_t SEL0
Definition: MIMXRT1052.h:44135
kDmaRequestMuxFlexPWM1CaptureSub1
@ kDmaRequestMuxFlexPWM1CaptureSub1
Definition: MIMXRT1052.h:338
kXBARB2_OutputAoi1In15
@ kXBARB2_OutputAoi1In15
Definition: MIMXRT1052.h:1229
kXBARB2_InputAcmp4Out
@ kXBARB2_InputAcmp4Out
Definition: MIMXRT1052.h:972
TMR_Type
Definition: MIMXRT1052.h:37378
GPIO_Type
Definition: MIMXRT1052.h:19125
kXBARA1_InputPitTrigger3
@ kXBARA1_InputPitTrigger3
Definition: MIMXRT1052.h:934
USDHC_Type::BLK_ATT
__IO uint32_t BLK_ATT
Definition: MIMXRT1052.h:42255
kXBARA1_InputQtimer4Tmr1Output
@ kXBARA1_InputQtimer4Tmr1Output
Definition: MIMXRT1052.h:912
DMA14_DMA30_IRQn
@ DMA14_DMA30_IRQn
Definition: MIMXRT1052.h:108
ENC4_IRQn
@ ENC4_IRQn
Definition: MIMXRT1052.h:226
USBPHY_Type::TX_CLR
__IO uint32_t TX_CLR
Definition: MIMXRT1052.h:40690
ENET_Type::RDSR
__IO uint32_t RDSR
Definition: MIMXRT1052.h:15637
kXBARA1_InputAcmp1Out
@ kXBARA1_InputAcmp1Out
Definition: MIMXRT1052.h:901
GPIO_Type::ICR1
__IO uint32_t ICR1
Definition: MIMXRT1052.h:19129
kXBARA1_InputIomuxXbarIn22
@ kXBARA1_InputIomuxXbarIn22
Definition: MIMXRT1052.h:897
kXBARB2_InputLogicHigh
@ kXBARB2_InputLogicHigh
Definition: MIMXRT1052.h:964
kXBARB2_InputFlexpwm4Pwm1OutTrig01
@ kXBARB2_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1052.h:995
kXBARA1_OutputFlexpwm234Exta1
@ kXBARA1_OutputFlexpwm234Exta1
Definition: MIMXRT1052.h:1124
ACMP4_IRQn
@ ACMP4_IRQn
Definition: MIMXRT1052.h:220
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08
Definition: MIMXRT1052.h:523
PXP_Type::AS_CTRL
__IO uint32_t AS_CTRL
Definition: MIMXRT1052.h:32560
kDmaRequestMuxQTIMER1CaptTimer0
@ kDmaRequestMuxQTIMER1CaptTimer0
Definition: MIMXRT1052.h:353
GPIO_Type::ISR
__IO uint32_t ISR
Definition: MIMXRT1052.h:19132
kIOMUXC_LPUART3_RX_SELECT_INPUT
@ kIOMUXC_LPUART3_RX_SELECT_INPUT
Definition: MIMXRT1052.h:798
ENET_Type::RMON_R_P256TO511
__I uint32_t RMON_R_P256TO511
Definition: MIMXRT1052.h:15697
DCP_Type::CH1CMDPTR
__IO uint32_t CH1CMDPTR
Definition: MIMXRT1052.h:10318
PXP_Type::AS_CLRKEYLOW
__IO uint32_t AS_CLRKEYLOW
Definition: MIMXRT1052.h:32566
SEMC_Type::NANDCR1
__IO uint32_t NANDCR1
Definition: MIMXRT1052.h:34143
kIOMUXC_LPI2C4_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C4_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:778
CAN_Type::ESR2
__I uint32_t ESR2
Definition: MIMXRT1052.h:3327
CCM_Type::CACRR
__IO uint32_t CACRR
Definition: MIMXRT1052.h:4159
kDmaRequestMuxFlexPWM4ValueSub2
@ kDmaRequestMuxFlexPWM4ValueSub2
Definition: MIMXRT1052.h:408
kIOMUXC_LPUART7_TX_SELECT_INPUT
@ kIOMUXC_LPUART7_TX_SELECT_INPUT
Definition: MIMXRT1052.h:807
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ
Definition: MIMXRT1052.h:22804
USB_PHY1_IRQn
@ USB_PHY1_IRQn
Definition: MIMXRT1052.h:159
kXBARA1_InputPitTrigger1
@ kXBARA1_InputPitTrigger1
Definition: MIMXRT1052.h:932
I2S_Type::RMR
__IO uint32_t RMR
Definition: MIMXRT1052.h:19892
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1052.h:498
XBARA_Type::SEL31
__IO uint16_t SEL31
Definition: MIMXRT1052.h:44166
USB_ANALOG_Type::@342::VBUS_DETECT
__IO uint32_t VBUS_DETECT
Definition: MIMXRT1052.h:41801
CCM_Type::CGPR
__IO uint32_t CGPR
Definition: MIMXRT1052.h:4178
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1052.h:702
kXBARA1_OutputFlexpwm234ExtClk
@ kXBARA1_OutputFlexpwm234ExtClk
Definition: MIMXRT1052.h:1131
kXBARA1_InputFlexpwm3Pwm4OutTrig01
@ kXBARA1_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1052.h:926
FLEXSPI_Type::STS1
__I uint32_t STS1
Definition: MIMXRT1052.h:18116
ENET_Type::IEEE_T_EXCOL
__I uint32_t IEEE_T_EXCOL
Definition: MIMXRT1052.h:15678
SEMC_Type::STS4
uint32_t STS4
Definition: MIMXRT1052.h:34169
kDmaRequestMuxLPUART3Tx
@ kDmaRequestMuxLPUART3Tx
Definition: MIMXRT1052.h:312
kXBARA1_OutputLpuart4TrgInput
@ kXBARA1_OutputLpuart4TrgInput
Definition: MIMXRT1052.h:1205
kXBARB2_InputFlexpwm4Pwm3OutTrig01
@ kXBARB2_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1052.h:997
LPI2C_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:25095
AIPSTZ_Type::OPACR2
__IO uint32_t OPACR2
Definition: MIMXRT1052.h:2082
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1052.h:606
USB_Type::ENDPTNAKEN
__IO uint32_t ENDPTNAKEN
Definition: MIMXRT1052.h:39035
kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
Definition: MIMXRT1052.h:746
kIOMUXC_USDHC1_CD_B_SELECT_INPUT
@ kIOMUXC_USDHC1_CD_B_SELECT_INPUT
Definition: MIMXRT1052.h:837
PWM1_1_IRQn
@ PWM1_1_IRQn
Definition: MIMXRT1052.h:197
CAN2_IRQn
@ CAN2_IRQn
Definition: MIMXRT1052.h:131
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1052.h:587
PWM1_2_IRQn
@ PWM1_2_IRQn
Definition: MIMXRT1052.h:198
BEE_Type::CTR_NONCE0_W3
__O uint32_t CTR_NONCE0_W3
Definition: MIMXRT1052.h:3022
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT
@ kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT
Definition: MIMXRT1052.h:717
xbar_input_signal_t
enum _xbar_input_signal xbar_input_signal_t
kXBARB2_InputQtimer3Tmr2Output
@ kXBARB2_InputQtimer3Tmr2Output
Definition: MIMXRT1052.h:977
XTALOSC24M_Type::OSC_CONFIG2_SET
__IO uint32_t OSC_CONFIG2_SET
Definition: MIMXRT1052.h:45189
PWM_Type::FCTRL2
__IO uint16_t FCTRL2
Definition: MIMXRT1052.h:30900
kXBARA1_OutputEnc1Index
@ kXBARA1_OutputEnc1Index
Definition: MIMXRT1052.h:1151
DCP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:10270
kIOMUXC_LPSPI4_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI4_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:793
LPUART_Type::PINCFG
__IO uint32_t PINCFG
Definition: MIMXRT1052.h:26775
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1052.h:469
ADC_ETC_ERROR_IRQ_IRQn
@ ADC_ETC_ERROR_IRQ_IRQn
Definition: MIMXRT1052.h:215
DCP_Type::CH1OPTS_TOG
__IO uint32_t CH1OPTS_TOG
Definition: MIMXRT1052.h:10329
FLEXIO_Type::SHIFTSTATE
__IO uint32_t SHIFTSTATE
Definition: MIMXRT1052.h:17381
LCDIF_Type::VDCTRL1
__IO uint32_t VDCTRL1
Definition: MIMXRT1052.h:23541
PMU_Type::MISC2_CLR
__IO uint32_t MISC2_CLR
Definition: MIMXRT1052.h:28695
TEMP_LOW_HIGH_IRQn
@ TEMP_LOW_HIGH_IRQn
Definition: MIMXRT1052.h:157
XBARA_Type::SEL63
__IO uint16_t SEL63
Definition: MIMXRT1052.h:44198
USDHC_Type::INT_SIGNAL_EN
__IO uint32_t INT_SIGNAL_EN
Definition: MIMXRT1052.h:42268
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07
Definition: MIMXRT1052.h:681
TSC_Type::MEASEURE_VALUE
__I uint32_t MEASEURE_VALUE
Definition: MIMXRT1052.h:38553
kXBARA1_OutputQtimer3Tmr3Input
@ kXBARA1_OutputQtimer3Tmr3Input
Definition: MIMXRT1052.h:1180
kXBARB2_InputFlexpwm1Pwm2OutTrig01
@ kXBARB2_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1052.h:984
XBARA_Type::SEL7
__IO uint16_t SEL7
Definition: MIMXRT1052.h:44142
kDmaRequestMuxLPUART6Rx
@ kDmaRequestMuxLPUART6Rx
Definition: MIMXRT1052.h:372
kDmaRequestMuxFlexPWM2CaptureSub3
@ kDmaRequestMuxFlexPWM2CaptureSub3
Definition: MIMXRT1052.h:397
kXBARA1_InputDmaDone5
@ kXBARA1_InputDmaDone5
Definition: MIMXRT1052.h:944
kXBARA1_OutputFlexpwm234Exta3
@ kXBARA1_OutputFlexpwm234Exta3
Definition: MIMXRT1052.h:1126
kXBARA1_OutputEnc2Trigger
@ kXBARA1_OutputEnc2Trigger
Definition: MIMXRT1052.h:1158
USDHC_Type::DLL_CTRL
__IO uint32_t DLL_CTRL
Definition: MIMXRT1052.h:42278
SRC_Type::SBMR2
__I uint32_t SBMR2
Definition: MIMXRT1052.h:36906
SNVS_Type::LPSMCLR
__I uint32_t LPSMCLR
Definition: MIMXRT1052.h:35344
TMR_Type::@317::HOLD
__IO uint16_t HOLD
Definition: MIMXRT1052.h:37384
TRNG_Type::INT_CTRL
__IO uint32_t INT_CTRL
Definition: MIMXRT1052.h:37931
kXBARB2_InputRESERVED2
@ kXBARB2_InputRESERVED2
Definition: MIMXRT1052.h:965
WDOG_Type::WICR
__IO uint16_t WICR
Definition: MIMXRT1052.h:43940
kXBARA1_InputAdcEtcXbar0Coco0
@ kXBARA1_InputAdcEtcXbar0Coco0
Definition: MIMXRT1052.h:955
LPUART_Type
Definition: MIMXRT1052.h:26771
LCDIF_Type::CTRL1_TOG
__IO uint32_t CTRL1_TOG
Definition: MIMXRT1052.h:23526
kXBARA1_OutputFlexpwm4Fault1
@ kXBARA1_OutputFlexpwm4Fault1
Definition: MIMXRT1052.h:1147
kXBARA1_InputFlexpwm3Pwm2OutTrig01
@ kXBARA1_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1052.h:924
TRNG_Type::@322::FRQCNT
__I uint32_t FRQCNT
Definition: MIMXRT1052.h:37889
EWM_Type
Definition: MIMXRT1052.h:17246
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1052.h:598
SAI3_RX_IRQn
@ SAI3_RX_IRQn
Definition: MIMXRT1052.h:152
I2S_Type::RCR2
__IO uint32_t RCR2
Definition: MIMXRT1052.h:19884
kDmaRequestMuxFlexPWM1ValueSub1
@ kDmaRequestMuxFlexPWM1ValueSub1
Definition: MIMXRT1052.h:342
USDHC_Type::DLL_STATUS
__I uint32_t DLL_STATUS
Definition: MIMXRT1052.h:42279
PXP_Type::AS_PITCH
__IO uint32_t AS_PITCH
Definition: MIMXRT1052.h:32564
OCOTP_Type::MEM2
__IO uint32_t MEM2
Definition: MIMXRT1052.h:27742
ENC1_IRQn
@ ENC1_IRQn
Definition: MIMXRT1052.h:223
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06
Definition: MIMXRT1052.h:680
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06
Definition: MIMXRT1052.h:521
kXBARB3_InputDmaDone3
@ kXBARB3_InputDmaDone3
Definition: MIMXRT1052.h:1074
TMR1_IRQn
@ TMR1_IRQn
Definition: MIMXRT1052.h:227
USB_ANALOG_Type::@342::VBUS_DETECT_SET
__IO uint32_t VBUS_DETECT_SET
Definition: MIMXRT1052.h:41802
IOMUXC_GPR_Type::GPR7
__IO uint32_t GPR7
Definition: MIMXRT1052.h:20865
PWM_Type::MCTRL
__IO uint16_t MCTRL
Definition: MIMXRT1052.h:30894
PXP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:32512
USDHC_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1052.h:42266
PWM_Type::@314::CAPTCTRLX
__IO uint16_t CAPTCTRLX
Definition: MIMXRT1052.h:30874
kDmaRequestMuxLPI2C4
@ kDmaRequestMuxLPI2C4
Definition: MIMXRT1052.h:382
kIOMUXC_LPSPI3_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI3_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:789
CCM_ANALOG_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1052.h:6127
kDmaRequestMuxFlexPWM4CaptureSub1
@ kDmaRequestMuxFlexPWM4CaptureSub1
Definition: MIMXRT1052.h:403
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1052.h:615
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1052.h:605
WDOG2_IRQn
@ WDOG2_IRQn
Definition: MIMXRT1052.h:139
OCOTP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:27700
SNVS_Type::HPHACIVR
__IO uint32_t HPHACIVR
Definition: MIMXRT1052.h:35327
OCOTP_Type::GP2
__IO uint32_t GP2
Definition: MIMXRT1052.h:27782
Reserved86_IRQn
@ Reserved86_IRQn
Definition: MIMXRT1052.h:164
LPI2C_Type::MRDR
__I uint32_t MRDR
Definition: MIMXRT1052.h:25117
RTWDOG_Type::CS
__IO uint32_t CS
Definition: MIMXRT1052.h:33928
TEMPMON_Type::TEMPSENSE2_CLR
__IO uint32_t TEMPSENSE2_CLR
Definition: MIMXRT1052.h:37142
TRNG_Type::@320::TOTSAM
__I uint32_t TOTSAM
Definition: MIMXRT1052.h:37885
DMA_Type::DCHPRI6
__IO uint8_t DCHPRI6
Definition: MIMXRT1052.h:11976
USB_Type::ENDPTCOMPLETE
__IO uint32_t ENDPTCOMPLETE
Definition: MIMXRT1052.h:39045
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1052.h:617
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1052.h:453
ENET_Type::TAFL
__IO uint32_t TAFL
Definition: MIMXRT1052.h:15647
DCP_Type::CH2SEMA
__IO uint32_t CH2SEMA
Definition: MIMXRT1052.h:10332
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:829
KPP_Type::KPSR
__IO uint16_t KPSR
Definition: MIMXRT1052.h:23379
PXP_Type::AS_CLRKEYHIGH
__IO uint32_t AS_CLRKEYHIGH
Definition: MIMXRT1052.h:32568
PMU_Type::REG_CORE_SET
__IO uint32_t REG_CORE_SET
Definition: MIMXRT1052.h:28682
kXBARA1_OutputIomuxXbarInout17
@ kXBARA1_OutputIomuxXbarInout17
Definition: MIMXRT1052.h:1100
PWM_Type::@314::CVAL2CYC
__I uint16_t CVAL2CYC
Definition: MIMXRT1052.h:30881
kXBARB2_OutputAoi1In05
@ kXBARB2_OutputAoi1In05
Definition: MIMXRT1052.h:1219
XBARA_Type::SEL41
__IO uint16_t SEL41
Definition: MIMXRT1052.h:44176
PXP_Type::PS_BUF
__IO uint32_t PS_BUF
Definition: MIMXRT1052.h:32542
FLEXIO2_IRQn
@ FLEXIO2_IRQn
Definition: MIMXRT1052.h:185
USDHC_Type::DS_ADDR
__IO uint32_t DS_ADDR
Definition: MIMXRT1052.h:42254
kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:827
DCP_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1052.h:10274
IOMUXC_GPR_Type::GPR2
__IO uint32_t GPR2
Definition: MIMXRT1052.h:20860
kIOMUXC_LPUART2_TX_SELECT_INPUT
@ kIOMUXC_LPUART2_TX_SELECT_INPUT
Definition: MIMXRT1052.h:796
ENET_Type::TAEM
__IO uint32_t TAEM
Definition: MIMXRT1052.h:15646
kXBARA1_OutputFlexpwm1Exta0
@ kXBARA1_OutputFlexpwm1Exta0
Definition: MIMXRT1052.h:1109
DCDC_Type::REG0
__IO uint32_t REG0
Definition: MIMXRT1052.h:10085
SRC_Type::SRSR
__IO uint32_t SRSR
Definition: MIMXRT1052.h:36904
OCOTP_Type::SRK4
__IO uint32_t SRK4
Definition: MIMXRT1052.h:27762
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1052.h:557
LCDIF_Type::THRES
__IO uint32_t THRES
Definition: MIMXRT1052.h:23555
PMU_Type::REG_2P5_CLR
__IO uint32_t REG_2P5_CLR
Definition: MIMXRT1052.h:28679
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1052.h:640
kXBARB3_InputFlexpwm1Pwm2OutTrig01
@ kXBARB3_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1052.h:1042
DMA_Type::CINT
__O uint8_t CINT
Definition: MIMXRT1052.h:11961
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1052.h:647
DCP_Type::CH0STAT_CLR
__IO uint32_t CH0STAT_CLR
Definition: MIMXRT1052.h:10312
LCDIF_Type::PIGEONCTRL2_CLR
__IO uint32_t PIGEONCTRL2_CLR
Definition: MIMXRT1052.h:23567
kXBARA1_OutputLpi2c1TrgInput
@ kXBARA1_OutputLpi2c1TrgInput
Definition: MIMXRT1052.h:1194
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05
Definition: MIMXRT1052.h:536
IOMUXC_GPR_Type::GPR21
__IO uint32_t GPR21
Definition: MIMXRT1052.h:20879
USB_Type::USBMODE
__IO uint32_t USBMODE
Definition: MIMXRT1052.h:39040
TMR_Type::@317::FILT
__IO uint16_t FILT
Definition: MIMXRT1052.h:37391
kXBARA1_OutputAdcEtcXbar1Trig0
@ kXBARA1_OutputAdcEtcXbar1Trig0
Definition: MIMXRT1052.h:1190
kXBARA1_InputIomuxXbarIn24
@ kXBARA1_InputIomuxXbarIn24
Definition: MIMXRT1052.h:899
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
Definition: MIMXRT1052.h:661
kIOMUXC_LPSPI3_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI3_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:787
SNVS_Type::LPSVCR
__IO uint32_t LPSVCR
Definition: MIMXRT1052.h:35336
BEE_Type::AES_KEY0_W0
__IO uint32_t AES_KEY0_W0
Definition: MIMXRT1052.h:3014
DMA_Type::DCHPRI20
__IO uint8_t DCHPRI20
Definition: MIMXRT1052.h:11994
XBARA_Type::SEL43
__IO uint16_t SEL43
Definition: MIMXRT1052.h:44178
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1052.h:696
LPUART_Type::MODIR
__IO uint32_t MODIR
Definition: MIMXRT1052.h:26781
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11
Definition: MIMXRT1052.h:685
FLEXRAM_IRQn
@ FLEXRAM_IRQn
Definition: MIMXRT1052.h:132
TMR_Type::@317::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1052.h:37386
kXBARA1_OutputLpi2c3TrgInput
@ kXBARA1_OutputLpi2c3TrgInput
Definition: MIMXRT1052.h:1196
kXBARA1_OutputQtimer1Tmr0Input
@ kXBARA1_OutputQtimer1Tmr0Input
Definition: MIMXRT1052.h:1169
PXP_Type::OUT_BUF
__IO uint32_t OUT_BUF
Definition: MIMXRT1052.h:32522
XTALOSC24M_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1052.h:45170
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08
Definition: MIMXRT1052.h:682
XBARA_Type::SEL44
__IO uint16_t SEL44
Definition: MIMXRT1052.h:44179
CAN_Type::CTRL1
__IO uint32_t CTRL1
Definition: MIMXRT1052.h:3314
CCM_ANALOG_Type::PLL_SYS_CLR
__IO uint32_t PLL_SYS_CLR
Definition: MIMXRT1052.h:6087
XTALOSC24M_Type::OSC_CONFIG0_CLR
__IO uint32_t OSC_CONFIG0_CLR
Definition: MIMXRT1052.h:45182
I2S_Type::TMR
__IO uint32_t TMR
Definition: MIMXRT1052.h:19880
kDmaRequestMuxSai1Rx
@ kDmaRequestMuxSai1Rx
Definition: MIMXRT1052.h:325
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1052.h:489
ENET_Type::RMON_T_OVERSIZE
__I uint32_t RMON_T_OVERSIZE
Definition: MIMXRT1052.h:15660
PWM3_3_IRQn
@ PWM3_3_IRQn
Definition: MIMXRT1052.h:239
CMP_Type::FPR
__IO uint8_t FPR
Definition: MIMXRT1052.h:8544
XBARA_Type
Definition: MIMXRT1052.h:44134
GPT_Type::CR
__IO uint32_t CR
Definition: MIMXRT1052.h:19578
SNVS_Type::HPVIDR2
__I uint32_t HPVIDR2
Definition: MIMXRT1052.h:35354
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1052.h:472
DCP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:10272
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1052.h:475
IOMUXC_GPR_Type::GPR3
__IO uint32_t GPR3
Definition: MIMXRT1052.h:20861
ENET_Type::TGSR
__IO uint32_t TGSR
Definition: MIMXRT1052.h:15718
kXBARB3_InputAcmp3Out
@ kXBARB3_InputAcmp3Out
Definition: MIMXRT1052.h:1029
kIOMUXC_USDHC2_DATA3_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:845
USB_ANALOG_Type::@342::CHRG_DETECT
__IO uint32_t CHRG_DETECT
Definition: MIMXRT1052.h:41805
PWM_Type::@314::CNT
__I uint16_t CNT
Definition: MIMXRT1052.h:30845
IOMUXC_Type
Definition: MIMXRT1052.h:20698
CMP_Type::SCR
__IO uint8_t SCR
Definition: MIMXRT1052.h:8545
kXBARA1_InputIomuxXbarInout04
@ kXBARA1_InputIomuxXbarInout04
Definition: MIMXRT1052.h:879
I2S_Type::TCR1
__IO uint32_t TCR1
Definition: MIMXRT1052.h:19871
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1052.h:596
BEE_Type::CTR_NONCE1_W3
__O uint32_t CTR_NONCE1_W3
Definition: MIMXRT1052.h:3026
kIOMUXC_LPSPI1_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI1_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:779
GPIO3_Combined_0_15_IRQn
@ GPIO3_Combined_0_15_IRQn
Definition: MIMXRT1052.h:178
TRNG_Type::@328::SCR2C
__I uint32_t SCR2C
Definition: MIMXRT1052.h:37901
ENC_Type::FILT
__IO uint16_t FILT
Definition: MIMXRT1052.h:15140
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1052.h:694
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:821
CMP_Type
Definition: MIMXRT1052.h:8541
ENET_Type::IEEE_T_SQE
__I uint32_t IEEE_T_SQE
Definition: MIMXRT1052.h:15681
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09
Definition: MIMXRT1052.h:683
kXBARA1_OutputIomuxXbarInout05
@ kXBARA1_OutputIomuxXbarInout05
Definition: MIMXRT1052.h:1088
USB_Type::HCIVERSION
__I uint16_t HCIVERSION
Definition: MIMXRT1052.h:39009
kXBARA1_InputIomuxXbarInout07
@ kXBARA1_InputIomuxXbarInout07
Definition: MIMXRT1052.h:882
GPIO4_Combined_16_31_IRQn
@ GPIO4_Combined_16_31_IRQn
Definition: MIMXRT1052.h:181
DMA_Type::DCHPRI12
__IO uint8_t DCHPRI12
Definition: MIMXRT1052.h:11986
kIOMUXC_ENET0_TIMER_SELECT_INPUT
@ kIOMUXC_ENET0_TIMER_SELECT_INPUT
Definition: MIMXRT1052.h:737
LPSPI_Type::RSR
__I uint32_t RSR
Definition: MIMXRT1052.h:26165
GPIO_Type::ICR2
__IO uint32_t ICR2
Definition: MIMXRT1052.h:19130
CCM_Type::CSCMR1
__IO uint32_t CSCMR1
Definition: MIMXRT1052.h:4162
USDHC_Type::TUNING_CTRL
__IO uint32_t TUNING_CTRL
Definition: MIMXRT1052.h:42285
kDmaRequestMuxFlexPWM1ValueSub0
@ kDmaRequestMuxFlexPWM1ValueSub0
Definition: MIMXRT1052.h:341
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1052.h:634
SPDIF_Type::SRR
__I uint32_t SRR
Definition: MIMXRT1052.h:36426
kXBARB3_InputDmaDone0
@ kXBARB3_InputDmaDone0
Definition: MIMXRT1052.h:1071
kIOMUXC_USB_OTG1_OC_SELECT_INPUT
@ kIOMUXC_USB_OTG1_OC_SELECT_INPUT
Definition: MIMXRT1052.h:836
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1052.h:697
OCOTP_Type::SRK6
__IO uint32_t SRK6
Definition: MIMXRT1052.h:27766
IOMUXC_GPR_Type::GPR19
__IO uint32_t GPR19
Definition: MIMXRT1052.h:20877
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B
__IO uint32_t SW_PAD_CTL_PAD_POR_B
Definition: MIMXRT1052.h:22800
USBPHY_Type::RX
__IO uint32_t RX
Definition: MIMXRT1052.h:40692
kDmaRequestMuxLPSPI2Tx
@ kDmaRequestMuxLPSPI2Tx
Definition: MIMXRT1052.h:378
LCDIF_Type::PIGEONCTRL1_TOG
__IO uint32_t PIGEONCTRL1_TOG
Definition: MIMXRT1052.h:23564
TEMPMON_Type::TEMPSENSE0_TOG
__IO uint32_t TEMPSENSE0_TOG
Definition: MIMXRT1052.h:37134
PGC_Type::CPU_PDNSCR
__IO uint32_t CPU_PDNSCR
Definition: MIMXRT1052.h:28381
kXBARB3_InputAdcEtcXbar1Coco3
@ kXBARB3_InputAdcEtcXbar1Coco3
Definition: MIMXRT1052.h:1066
kIOMUXC_LPUART4_TX_SELECT_INPUT
@ kIOMUXC_LPUART4_TX_SELECT_INPUT
Definition: MIMXRT1052.h:801
XBARA_Type::SEL34
__IO uint16_t SEL34
Definition: MIMXRT1052.h:44169
ENET_Type::IEEE_R_OCTETS_OK
__I uint32_t IEEE_R_OCTETS_OK
Definition: MIMXRT1052.h:15708
BEE_Type::CTR_NONCE1_W2
__O uint32_t CTR_NONCE1_W2
Definition: MIMXRT1052.h:3025
kDmaRequestMuxLPUART4Tx
@ kDmaRequestMuxLPUART4Tx
Definition: MIMXRT1052.h:369
kXBARA1_OutputDmaChMuxReq95
@ kXBARA1_OutputDmaChMuxReq95
Definition: MIMXRT1052.h:1086
kXBARB2_InputQtimer3Tmr0Output
@ kXBARB2_InputQtimer3Tmr0Output
Definition: MIMXRT1052.h:975
TMR_Type::@317::COMP1
__IO uint16_t COMP1
Definition: MIMXRT1052.h:37380
DMA_Type::CDNE
__O uint8_t CDNE
Definition: MIMXRT1052.h:11958
kIOMUXC_LPI2C1_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C1_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:772
kIOMUXC_LPUART8_TX_SELECT_INPUT
@ kIOMUXC_LPUART8_TX_SELECT_INPUT
Definition: MIMXRT1052.h:809
XBARA_Type::SEL30
__IO uint16_t SEL30
Definition: MIMXRT1052.h:44165
PMU_Type::REG_CORE_CLR
__IO uint32_t REG_CORE_CLR
Definition: MIMXRT1052.h:28683
kXBARA1_OutputAcmp4Sample
@ kXBARA1_OutputAcmp4Sample
Definition: MIMXRT1052.h:1106
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
FLEXSPI_Type::IPCMD
__IO uint32_t IPCMD
Definition: MIMXRT1052.h:18109
kXBARA1_OutputEnc4PhaseAInput
@ kXBARA1_OutputEnc4PhaseAInput
Definition: MIMXRT1052.h:1164
DMA_Type::DCHPRI7
__IO uint8_t DCHPRI7
Definition: MIMXRT1052.h:11975
PWM_Type::FCTRL
__IO uint16_t FCTRL
Definition: MIMXRT1052.h:30896
kXBARB2_InputQtimer4Tmr0Output
@ kXBARB2_InputQtimer4Tmr0Output
Definition: MIMXRT1052.h:979
DCP_Type::CH1OPTS_CLR
__IO uint32_t CH1OPTS_CLR
Definition: MIMXRT1052.h:10328
DMA11_DMA27_IRQn
@ DMA11_DMA27_IRQn
Definition: MIMXRT1052.h:105
kIOMUXC_ENET0_RXDATA_SELECT_INPUT
@ kIOMUXC_ENET0_RXDATA_SELECT_INPUT
Definition: MIMXRT1052.h:733
EWM_IRQn
@ EWM_IRQn
Definition: MIMXRT1052.h:188
OCOTP_Type::MAC0
__IO uint32_t MAC0
Definition: MIMXRT1052.h:27774
DCP_Type::CH3SEMA
__IO uint32_t CH3SEMA
Definition: MIMXRT1052.h:10344
kDmaRequestMuxLPSPI2Rx
@ kDmaRequestMuxLPSPI2Rx
Definition: MIMXRT1052.h:377
XBARA_Type::SEL38
__IO uint16_t SEL38
Definition: MIMXRT1052.h:44173
BEE_Type::AES_KEY0_W3
__IO uint32_t AES_KEY0_W3
Definition: MIMXRT1052.h:3017
LPSPI_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:26146
kIOMUXC_LPUART4_RX_SELECT_INPUT
@ kIOMUXC_LPUART4_RX_SELECT_INPUT
Definition: MIMXRT1052.h:800
TRNG_Type::PKRCNT54
__I uint32_t PKRCNT54
Definition: MIMXRT1052.h:37924
KPP_Type
Definition: MIMXRT1052.h:23377
PMU_Type::REG_3P0_TOG
__IO uint32_t REG_3P0_TOG
Definition: MIMXRT1052.h:28676
PMU_Type::REG_1P1_TOG
__IO uint32_t REG_1P1_TOG
Definition: MIMXRT1052.h:28672
DMA_Type::SEEI
__O uint8_t SEEI
Definition: MIMXRT1052.h:11955
CCM_ANALOG_Type::PFD_528
__IO uint32_t PFD_528
Definition: MIMXRT1052.h:6119
USBPHY_Type::STATUS
__IO uint32_t STATUS
Definition: MIMXRT1052.h:40700
TSC_Type
Definition: MIMXRT1052.h:38546
TRNG_Type::@336::SCR6PC
__I uint32_t SCR6PC
Definition: MIMXRT1052.h:37917
PWM_Type::@314::FRACVAL4
__IO uint16_t FRACVAL4
Definition: MIMXRT1052.h:30857
TRNG_Type::@324::SCMC
__I uint32_t SCMC
Definition: MIMXRT1052.h:37893
I2S_Type::TCR3
__IO uint32_t TCR3
Definition: MIMXRT1052.h:19873
ENC_Type::IMR
__I uint16_t IMR
Definition: MIMXRT1052.h:15152
LPUART2_IRQn
@ LPUART2_IRQn
Definition: MIMXRT1052.h:115
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1052.h:555
kXBARA1_InputPitTrigger2
@ kXBARA1_InputPitTrigger2
Definition: MIMXRT1052.h:933
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
Definition: MIMXRT1052.h:544
SNVS_Type
Definition: MIMXRT1052.h:35319
DMA_Type::CEEI
__O uint8_t CEEI
Definition: MIMXRT1052.h:11954
ADC_ETC_Type::@301::TRIGn_CTRL
__IO uint32_t TRIGn_CTRL
Definition: MIMXRT1052.h:1623
XTALOSC24M_Type::LOWPWR_CTRL
__IO uint32_t LOWPWR_CTRL
Definition: MIMXRT1052.h:45175
DCP_Type::CH3STAT_SET
__IO uint32_t CH3STAT_SET
Definition: MIMXRT1052.h:10347
DCP_Type::CH0OPTS
__IO uint32_t CH0OPTS
Definition: MIMXRT1052.h:10314
kXBARA1_OutputIomuxXbarInout16
@ kXBARA1_OutputIomuxXbarInout16
Definition: MIMXRT1052.h:1099
kXBARB3_OutputAoi2In06
@ kXBARB3_OutputAoi2In06
Definition: MIMXRT1052.h:1236
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05
Definition: MIMXRT1052.h:679
DCP_Type::CH0STAT_TOG
__IO uint32_t CH0STAT_TOG
Definition: MIMXRT1052.h:10313
CCM_Type::CSCMR2
__IO uint32_t CSCMR2
Definition: MIMXRT1052.h:4163
kXBARA1_OutputEnc1Trigger
@ kXBARA1_OutputEnc1Trigger
Definition: MIMXRT1052.h:1153
kXBARB2_InputFlexpwm2Pwm2OutTrig01
@ kXBARB2_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1052.h:988
USDHC_Type::PRES_STATE
__I uint32_t PRES_STATE
Definition: MIMXRT1052.h:42263
ADC_ETC_Type::@301::TRIGn_RESULT_5_4
__I uint32_t TRIGn_RESULT_5_4
Definition: MIMXRT1052.h:1631
SNVS_Type::LPMKCR
__IO uint32_t LPMKCR
Definition: MIMXRT1052.h:35335
kXBARA1_InputQtimer3Tmr1Output
@ kXBARA1_InputQtimer3Tmr1Output
Definition: MIMXRT1052.h:908
TRNG_Type::@324::SCML
__IO uint32_t SCML
Definition: MIMXRT1052.h:37894
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1052.h:480

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:13:56