GPIO Peripheral Access Layer

Collaboration diagram for GPIO Peripheral Access Layer:

Modules
	GPIO Register Masks

Classes
struct	GPIO_Type

Macros
#define	GPIO1   ((GPIO_Type *)GPIO1_BASE)
#define	GPIO1_BASE   (0x401B8000u)
#define	GPIO2   ((GPIO_Type *)GPIO2_BASE)
#define	GPIO2_BASE   (0x401BC000u)
#define	GPIO3   ((GPIO_Type *)GPIO3_BASE)
#define	GPIO3_BASE   (0x401C0000u)
#define	GPIO4   ((GPIO_Type *)GPIO4_BASE)
#define	GPIO4_BASE   (0x401C4000u)
#define	GPIO5   ((GPIO_Type *)GPIO5_BASE)
#define	GPIO5_BASE   (0x400C0000u)
#define	GPIO_BASE_ADDRS   { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
#define	GPIO_BASE_PTRS   { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
#define	GPIO_COMBINED_HIGH_IRQS   { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
#define	GPIO_COMBINED_LOW_IRQS   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
#define	GPIO_IRQS   { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

Detailed Description

Macro Definition Documentation

GPIO1

#define GPIO1   ((GPIO_Type *)GPIO1_BASE)

Peripheral GPIO1 base pointer

Definition at line 19536 of file MIMXRT1052.h.

GPIO1_BASE

#define GPIO1_BASE   (0x401B8000u)

Peripheral GPIO1 base address

Definition at line 19534 of file MIMXRT1052.h.

GPIO2

#define GPIO2   ((GPIO_Type *)GPIO2_BASE)

Peripheral GPIO2 base pointer

Definition at line 19540 of file MIMXRT1052.h.

GPIO2_BASE

#define GPIO2_BASE   (0x401BC000u)

Peripheral GPIO2 base address

Definition at line 19538 of file MIMXRT1052.h.

GPIO3

#define GPIO3   ((GPIO_Type *)GPIO3_BASE)

Peripheral GPIO3 base pointer

Definition at line 19544 of file MIMXRT1052.h.

GPIO3_BASE

#define GPIO3_BASE   (0x401C0000u)

Peripheral GPIO3 base address

Definition at line 19542 of file MIMXRT1052.h.

GPIO4

#define GPIO4   ((GPIO_Type *)GPIO4_BASE)

Peripheral GPIO4 base pointer

Definition at line 19548 of file MIMXRT1052.h.

GPIO4_BASE

#define GPIO4_BASE   (0x401C4000u)

Peripheral GPIO4 base address

Definition at line 19546 of file MIMXRT1052.h.

GPIO5

#define GPIO5   ((GPIO_Type *)GPIO5_BASE)

Peripheral GPIO5 base pointer

Definition at line 19552 of file MIMXRT1052.h.

GPIO5_BASE

#define GPIO5_BASE   (0x400C0000u)

Peripheral GPIO5 base address

Definition at line 19550 of file MIMXRT1052.h.

GPIO_BASE_ADDRS

#define GPIO_BASE_ADDRS   { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }

Array initializer of GPIO peripheral base addresses

Definition at line 19554 of file MIMXRT1052.h.

GPIO_BASE_PTRS

#define GPIO_BASE_PTRS   { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }

Array initializer of GPIO peripheral base pointers

Definition at line 19556 of file MIMXRT1052.h.

GPIO_COMBINED_HIGH_IRQS

#define GPIO_COMBINED_HIGH_IRQS   { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }

Definition at line 19560 of file MIMXRT1052.h.

GPIO_COMBINED_LOW_IRQS

#define GPIO_COMBINED_LOW_IRQS   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }

Definition at line 19559 of file MIMXRT1052.h.

GPIO_IRQS

#define GPIO_IRQS   { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

Interrupt vectors for the GPIO peripheral type

Definition at line 19558 of file MIMXRT1052.h.