TCM_CTRL - TCM CRTL Register | |
| #define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) |
| #define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) |
| #define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) |
| #define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) |
| #define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) |
| #define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) |
| #define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) |
| #define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) |
| #define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) |
INT_STAT_EN - Interrupt Status Enable Register | |
| #define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) |
| #define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) |
| #define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) |
| #define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) |
| #define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) |
| #define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) |
| #define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) |
| #define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) |
| #define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) |
INT_SIG_EN - Interrupt Enable Register | |
| #define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) |
| #define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) |
| #define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) |
| #define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) |
| #define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) |
| #define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) |
| #define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) |
| #define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) |
| #define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) |
Detailed Description
Macro Definition Documentation
◆ FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN
| #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) |
DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable 0b0..Masked 0b1..Enabled
Definition at line 18046 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK
| #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) |
Definition at line 18040 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT
| #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) |
Definition at line 18041 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN
| #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) |
ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable 0b0..Masked 0b1..Enabled
Definition at line 18039 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK
| #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) |
Definition at line 18033 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT
| #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) |
Definition at line 18034 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN
| #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) |
OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable 0b0..Masked 0b1..Enabled
Definition at line 18053 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK
| #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) |
Definition at line 18047 of file MIMXRT1052.h.
◆ FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT
| #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) |
Definition at line 18048 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN
| #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) |
DTCM_ERR_STAT_EN - DTCM Access Error Status Enable 0b0..Masked 0b1..Enabled
Definition at line 18021 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK
| #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) |
Definition at line 18015 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT
| #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) |
Definition at line 18016 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN
| #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) |
ITCM_ERR_STAT_EN - ITCM Access Error Status Enable 0b0..Masked 0b1..Enabled
Definition at line 18014 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK
| #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) |
Definition at line 18008 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT
| #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) |
Definition at line 18009 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN
| #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) |
OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable 0b0..Masked 0b1..Enabled
Definition at line 18028 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK
| #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) |
Definition at line 18022 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT
| #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) |
Definition at line 18023 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_DTCM_ERR_STATUS
| #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) |
DTCM_ERR_STATUS - DTCM Access Error Status 0b0..DTCM access error does not happen 0b1..DTCM access error happens.
Definition at line 17996 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK
| #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) |
Definition at line 17990 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT
| #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) |
Definition at line 17991 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_ITCM_ERR_STATUS
| #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) |
ITCM_ERR_STATUS - ITCM Access Error Status 0b0..ITCM access error does not happen 0b1..ITCM access error happens.
Definition at line 17989 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK
| #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) |
Definition at line 17983 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT
| #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) |
Definition at line 17984 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS
| #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) |
OCRAM_ERR_STATUS - OCRAM Access Error Status 0b0..OCRAM access error does not happen 0b1..OCRAM access error happens.
Definition at line 18003 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK
| #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) |
Definition at line 17997 of file MIMXRT1052.h.
◆ FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT
| #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) |
Definition at line 17998 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_FORCE_CLK_ON
| #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) |
FORCE_CLK_ON - Force RAM Clock Always On
Definition at line 17978 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK
| #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) |
Definition at line 17974 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT
| #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) |
Definition at line 17975 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_TCM_RWAIT_EN
| #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) |
TCM_RWAIT_EN - TCM Read Wait Mode Enable 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
Definition at line 17973 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK
| #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) |
Definition at line 17967 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT
| #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) |
Definition at line 17968 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_TCM_WWAIT_EN
| #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) |
TCM_WWAIT_EN - TCM Write Wait Mode Enable 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
Definition at line 17966 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK
| #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) |
Definition at line 17960 of file MIMXRT1052.h.
◆ FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT
| #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) |
Definition at line 17961 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_ENT_VAL
| #define TRNG_INT_STATUS_ENT_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) |
ENT_VAL 0b0..Busy generation entropy. Any value read is invalid. 0b1..TRNG can be stopped and entropy is valid if read.
Definition at line 38453 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_ENT_VAL_MASK
| #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) |
Definition at line 38447 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_ENT_VAL_SHIFT
| #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) |
Definition at line 38448 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_FRQ_CT_FAIL
| #define TRNG_INT_STATUS_FRQ_CT_FAIL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) |
FRQ_CT_FAIL 0b0..No hardware nor self test frequency errors. 0b1..The frequency counter has detected a failure.
Definition at line 38460 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_FRQ_CT_FAIL_MASK
| #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) |
Definition at line 38454 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT
| #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) |
Definition at line 38455 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_HW_ERR
| #define TRNG_INT_STATUS_HW_ERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) |
HW_ERR 0b0..no error 0b1..error detected.
Definition at line 38446 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_HW_ERR_MASK
| #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) |
Definition at line 38440 of file MIMXRT1052.h.
◆ TRNG_INT_STATUS_HW_ERR_SHIFT
| #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) |
Definition at line 38441 of file MIMXRT1052.h.