Modules | |
GPT Register Masks | |
Classes | |
struct | GPT_Type |
Macros | |
#define | GPT1 ((GPT_Type *)GPT1_BASE) |
#define | GPT1_BASE (0x401EC000u) |
#define | GPT2 ((GPT_Type *)GPT2_BASE) |
#define | GPT2_BASE (0x401F0000u) |
#define | GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } |
#define | GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } |
#define | GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } |
Peripheral GPT1 base pointer
Definition at line 19840 of file MIMXRT1052.h.
#define GPT1_BASE (0x401EC000u) |
Peripheral GPT1 base address
Definition at line 19838 of file MIMXRT1052.h.
Peripheral GPT2 base pointer
Definition at line 19844 of file MIMXRT1052.h.
#define GPT2_BASE (0x401F0000u) |
Peripheral GPT2 base address
Definition at line 19842 of file MIMXRT1052.h.
Array initializer of GPT peripheral base addresses
Definition at line 19846 of file MIMXRT1052.h.
Array initializer of GPT peripheral base pointers
Definition at line 19848 of file MIMXRT1052.h.
#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } |
Interrupt vectors for the GPT peripheral type
Definition at line 19850 of file MIMXRT1052.h.