Macros | |
| #define | SRC_GPR_COUNT (10U) |
SBMR1 - SRC Boot Mode Register 1 | |
| #define | SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) |
| #define | SRC_SBMR1_BOOT_CFG1_SHIFT (0U) |
| #define | SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) |
| #define | SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) |
| #define | SRC_SBMR1_BOOT_CFG2_SHIFT (8U) |
| #define | SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) |
| #define | SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) |
| #define | SRC_SBMR1_BOOT_CFG3_SHIFT (16U) |
| #define | SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) |
| #define | SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) |
| #define | SRC_SBMR1_BOOT_CFG4_SHIFT (24U) |
| #define | SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) |
SBMR2 - SRC Boot Mode Register 2 | |
| #define | SRC_SBMR2_SEC_CONFIG_MASK (0x3U) |
| #define | SRC_SBMR2_SEC_CONFIG_SHIFT (0U) |
| #define | SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) |
| #define | SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) |
| #define | SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) |
| #define | SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) |
| #define | SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) |
| #define | SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) |
| #define | SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) |
| #define | SRC_SBMR2_BMOD_MASK (0x3000000U) |
| #define | SRC_SBMR2_BMOD_SHIFT (24U) |
| #define | SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) |
GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 | |
| #define | SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) |
| #define | SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) |
| #define | SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) |
| #define | SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) |
| #define | SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) |
| #define | SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) |
Detailed Description
Macro Definition Documentation
◆ SRC_GPR_COUNT
| #define SRC_GPR_COUNT (10U) |
Definition at line 37068 of file MIMXRT1052.h.
◆ SRC_GPR_PERSISTENT_ARG0
| #define SRC_GPR_PERSISTENT_ARG0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) |
Definition at line 37061 of file MIMXRT1052.h.
◆ SRC_GPR_PERSISTENT_ARG0_MASK
| #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) |
Definition at line 37059 of file MIMXRT1052.h.
◆ SRC_GPR_PERSISTENT_ARG0_SHIFT
| #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) |
Definition at line 37060 of file MIMXRT1052.h.
◆ SRC_GPR_PERSISTENT_ENTRY0
| #define SRC_GPR_PERSISTENT_ENTRY0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) |
Definition at line 37064 of file MIMXRT1052.h.
◆ SRC_GPR_PERSISTENT_ENTRY0_MASK
| #define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) |
Definition at line 37062 of file MIMXRT1052.h.
◆ SRC_GPR_PERSISTENT_ENTRY0_SHIFT
| #define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) |
Definition at line 37063 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG1
| #define SRC_SBMR1_BOOT_CFG1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) |
Definition at line 36962 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG1_MASK
| #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) |
Definition at line 36960 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG1_SHIFT
| #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) |
Definition at line 36961 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG2
| #define SRC_SBMR1_BOOT_CFG2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) |
Definition at line 36965 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG2_MASK
| #define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) |
Definition at line 36963 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG2_SHIFT
| #define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) |
Definition at line 36964 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG3
| #define SRC_SBMR1_BOOT_CFG3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) |
Definition at line 36968 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG3_MASK
| #define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) |
Definition at line 36966 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG3_SHIFT
| #define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) |
Definition at line 36967 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG4
| #define SRC_SBMR1_BOOT_CFG4 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) |
Definition at line 36971 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG4_MASK
| #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) |
Definition at line 36969 of file MIMXRT1052.h.
◆ SRC_SBMR1_BOOT_CFG4_SHIFT
| #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) |
Definition at line 36970 of file MIMXRT1052.h.
◆ SRC_SBMR2_BMOD
| #define SRC_SBMR2_BMOD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) |
Definition at line 37054 of file MIMXRT1052.h.
◆ SRC_SBMR2_BMOD_MASK
| #define SRC_SBMR2_BMOD_MASK (0x3000000U) |
Definition at line 37052 of file MIMXRT1052.h.
◆ SRC_SBMR2_BMOD_SHIFT
| #define SRC_SBMR2_BMOD_SHIFT (24U) |
Definition at line 37053 of file MIMXRT1052.h.
◆ SRC_SBMR2_BT_FUSE_SEL
| #define SRC_SBMR2_BT_FUSE_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) |
Definition at line 37051 of file MIMXRT1052.h.
◆ SRC_SBMR2_BT_FUSE_SEL_MASK
| #define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) |
Definition at line 37049 of file MIMXRT1052.h.
◆ SRC_SBMR2_BT_FUSE_SEL_SHIFT
| #define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) |
Definition at line 37050 of file MIMXRT1052.h.
◆ SRC_SBMR2_DIR_BT_DIS
| #define SRC_SBMR2_DIR_BT_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) |
Definition at line 37048 of file MIMXRT1052.h.
◆ SRC_SBMR2_DIR_BT_DIS_MASK
| #define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) |
Definition at line 37046 of file MIMXRT1052.h.
◆ SRC_SBMR2_DIR_BT_DIS_SHIFT
| #define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) |
Definition at line 37047 of file MIMXRT1052.h.
◆ SRC_SBMR2_SEC_CONFIG
| #define SRC_SBMR2_SEC_CONFIG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) |
Definition at line 37045 of file MIMXRT1052.h.
◆ SRC_SBMR2_SEC_CONFIG_MASK
| #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) |
Definition at line 37043 of file MIMXRT1052.h.
◆ SRC_SBMR2_SEC_CONFIG_SHIFT
| #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) |
Definition at line 37044 of file MIMXRT1052.h.
◆ SRC_SCR_CORE0_DBG_RST
| #define SRC_SCR_CORE0_DBG_RST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) |
core0_dbg_rst 0b0..do not assert core0 debug reset 0b1..assert core0 debug reset
Definition at line 36941 of file MIMXRT1052.h.
◆ SRC_SCR_CORE0_DBG_RST_MASK
| #define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) |
Definition at line 36935 of file MIMXRT1052.h.
◆ SRC_SCR_CORE0_DBG_RST_SHIFT
| #define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) |
Definition at line 36936 of file MIMXRT1052.h.
◆ SRC_SCR_CORE0_RST
| #define SRC_SCR_CORE0_RST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) |
core0_rst 0b0..do not assert core0 reset 0b1..assert core0 reset
Definition at line 36934 of file MIMXRT1052.h.
◆ SRC_SCR_CORE0_RST_MASK
| #define SRC_SCR_CORE0_RST_MASK (0x2000U) |
Definition at line 36928 of file MIMXRT1052.h.
◆ SRC_SCR_CORE0_RST_SHIFT
| #define SRC_SCR_CORE0_RST_SHIFT (13U) |
Definition at line 36929 of file MIMXRT1052.h.
◆ SRC_SCR_DBG_RST_MSK_PG
| #define SRC_SCR_DBG_RST_MSK_PG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) |
dbg_rst_msk_pg 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) 0b1..mask core debug resets (debug resets won't be asserted after power gating event)
Definition at line 36948 of file MIMXRT1052.h.
◆ SRC_SCR_DBG_RST_MSK_PG_MASK
| #define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) |
Definition at line 36942 of file MIMXRT1052.h.
◆ SRC_SCR_DBG_RST_MSK_PG_SHIFT
| #define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) |
Definition at line 36943 of file MIMXRT1052.h.
◆ SRC_SCR_MASK_WDOG3_RST
| #define SRC_SCR_MASK_WDOG3_RST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) |
mask_wdog3_rst 0b0101..wdog3_rst_b is masked 0b1010..wdog3_rst_b is not masked
Definition at line 36955 of file MIMXRT1052.h.
◆ SRC_SCR_MASK_WDOG3_RST_MASK
| #define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) |
Definition at line 36949 of file MIMXRT1052.h.
◆ SRC_SCR_MASK_WDOG3_RST_SHIFT
| #define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) |
Definition at line 36950 of file MIMXRT1052.h.
◆ SRC_SCR_MASK_WDOG_RST
| #define SRC_SCR_MASK_WDOG_RST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) |
mask_wdog_rst 0b0101..wdog_rst_b is masked 0b1010..wdog_rst_b is not masked (default)
Definition at line 36927 of file MIMXRT1052.h.
◆ SRC_SCR_MASK_WDOG_RST_MASK
| #define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) |
Definition at line 36921 of file MIMXRT1052.h.
◆ SRC_SCR_MASK_WDOG_RST_SHIFT
| #define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) |
Definition at line 36922 of file MIMXRT1052.h.
◆ SRC_SRSR_CSU_RESET_B
| #define SRC_SRSR_CSU_RESET_B | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) |
csu_reset_b 0b0..Reset is not a result of the csu_reset_b event. 0b1..Reset is a result of the csu_reset_b event.
Definition at line 36996 of file MIMXRT1052.h.
◆ SRC_SRSR_CSU_RESET_B_MASK
| #define SRC_SRSR_CSU_RESET_B_MASK (0x4U) |
Definition at line 36990 of file MIMXRT1052.h.
◆ SRC_SRSR_CSU_RESET_B_SHIFT
| #define SRC_SRSR_CSU_RESET_B_SHIFT (2U) |
Definition at line 36991 of file MIMXRT1052.h.
◆ SRC_SRSR_IPP_RESET_B
| #define SRC_SRSR_IPP_RESET_B | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) |
ipp_reset_b 0b0..Reset is not a result of ipp_reset_b pin. 0b1..Reset is a result of ipp_reset_b pin.
Definition at line 36982 of file MIMXRT1052.h.
◆ SRC_SRSR_IPP_RESET_B_MASK
| #define SRC_SRSR_IPP_RESET_B_MASK (0x1U) |
Definition at line 36976 of file MIMXRT1052.h.
◆ SRC_SRSR_IPP_RESET_B_SHIFT
| #define SRC_SRSR_IPP_RESET_B_SHIFT (0U) |
Definition at line 36977 of file MIMXRT1052.h.
◆ SRC_SRSR_IPP_USER_RESET_B
| #define SRC_SRSR_IPP_USER_RESET_B | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) |
ipp_user_reset_b 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
Definition at line 37003 of file MIMXRT1052.h.
◆ SRC_SRSR_IPP_USER_RESET_B_MASK
| #define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) |
Definition at line 36997 of file MIMXRT1052.h.
◆ SRC_SRSR_IPP_USER_RESET_B_SHIFT
| #define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) |
Definition at line 36998 of file MIMXRT1052.h.
◆ SRC_SRSR_JTAG_RST_B
| #define SRC_SRSR_JTAG_RST_B | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) |
jtag_rst_b 0b0..Reset is not a result of HIGH-Z reset from JTAG. 0b1..Reset is a result of HIGH-Z reset from JTAG.
Definition at line 37017 of file MIMXRT1052.h.
◆ SRC_SRSR_JTAG_RST_B_MASK
| #define SRC_SRSR_JTAG_RST_B_MASK (0x20U) |
Definition at line 37011 of file MIMXRT1052.h.
◆ SRC_SRSR_JTAG_RST_B_SHIFT
| #define SRC_SRSR_JTAG_RST_B_SHIFT (5U) |
Definition at line 37012 of file MIMXRT1052.h.
◆ SRC_SRSR_JTAG_SW_RST
| #define SRC_SRSR_JTAG_SW_RST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) |
jtag_sw_rst 0b0..Reset is not a result of software reset from JTAG. 0b1..Reset is a result of software reset from JTAG.
Definition at line 37024 of file MIMXRT1052.h.
◆ SRC_SRSR_JTAG_SW_RST_MASK
| #define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) |
Definition at line 37018 of file MIMXRT1052.h.
◆ SRC_SRSR_JTAG_SW_RST_SHIFT
| #define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) |
Definition at line 37019 of file MIMXRT1052.h.
◆ SRC_SRSR_LOCKUP_SYSRESETREQ
| #define SRC_SRSR_LOCKUP_SYSRESETREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) |
lockup_sysresetreq 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.
Definition at line 36989 of file MIMXRT1052.h.
◆ SRC_SRSR_LOCKUP_SYSRESETREQ_MASK
| #define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) |
Definition at line 36983 of file MIMXRT1052.h.
◆ SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT
| #define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) |
Definition at line 36984 of file MIMXRT1052.h.
◆ SRC_SRSR_TEMPSENSE_RST_B
| #define SRC_SRSR_TEMPSENSE_RST_B | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) |
tempsense_rst_b 0b0..Reset is not a result of software reset from Temperature Sensor. 0b1..Reset is a result of software reset from Temperature Sensor.
Definition at line 37038 of file MIMXRT1052.h.
◆ SRC_SRSR_TEMPSENSE_RST_B_MASK
| #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) |
Definition at line 37032 of file MIMXRT1052.h.
◆ SRC_SRSR_TEMPSENSE_RST_B_SHIFT
| #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) |
Definition at line 37033 of file MIMXRT1052.h.
◆ SRC_SRSR_WDOG3_RST_B
| #define SRC_SRSR_WDOG3_RST_B | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) |
wdog3_rst_b 0b0..Reset is not a result of the watchdog3 time-out event. 0b1..Reset is a result of the watchdog3 time-out event.
Definition at line 37031 of file MIMXRT1052.h.
◆ SRC_SRSR_WDOG3_RST_B_MASK
| #define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) |
Definition at line 37025 of file MIMXRT1052.h.
◆ SRC_SRSR_WDOG3_RST_B_SHIFT
| #define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) |
Definition at line 37026 of file MIMXRT1052.h.
◆ SRC_SRSR_WDOG_RST_B
| #define SRC_SRSR_WDOG_RST_B | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) |
wdog_rst_b 0b0..Reset is not a result of the watchdog time-out event. 0b1..Reset is a result of the watchdog time-out event.
Definition at line 37010 of file MIMXRT1052.h.
◆ SRC_SRSR_WDOG_RST_B_MASK
| #define SRC_SRSR_WDOG_RST_B_MASK (0x10U) |
Definition at line 37004 of file MIMXRT1052.h.
◆ SRC_SRSR_WDOG_RST_B_SHIFT
| #define SRC_SRSR_WDOG_RST_B_SHIFT (4U) |
Definition at line 37005 of file MIMXRT1052.h.