Collaboration diagram for SNVS Register Masks:

Macros
#define	SNVS_LPGPR_ALIAS_COUNT (4U)

#define	SNVS_LPGPR_COUNT (8U)

#define	SNVS_LPZMKR_COUNT (8U)

HPLR - SNVS_HP Lock Register
#define	SNVS_HPLR_ZMK_WSL_MASK (0x1U)

#define	SNVS_HPLR_ZMK_WSL_SHIFT (0U)

#define	SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)

#define	SNVS_HPLR_ZMK_RSL_MASK (0x2U)

#define	SNVS_HPLR_ZMK_RSL_SHIFT (1U)

#define	SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)

#define	SNVS_HPLR_SRTC_SL_MASK (0x4U)

#define	SNVS_HPLR_SRTC_SL_SHIFT (2U)

#define	SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)

#define	SNVS_HPLR_LPCALB_SL_MASK (0x8U)

#define	SNVS_HPLR_LPCALB_SL_SHIFT (3U)

#define	SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)

#define	SNVS_HPLR_MC_SL_MASK (0x10U)

#define	SNVS_HPLR_MC_SL_SHIFT (4U)

#define	SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)

#define	SNVS_HPLR_GPR_SL_MASK (0x20U)

#define	SNVS_HPLR_GPR_SL_SHIFT (5U)

#define	SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)

#define	SNVS_HPLR_LPSVCR_SL_MASK (0x40U)

#define	SNVS_HPLR_LPSVCR_SL_SHIFT (6U)

#define	SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)

#define	SNVS_HPLR_LPTDCR_SL_MASK (0x100U)

#define	SNVS_HPLR_LPTDCR_SL_SHIFT (8U)

#define	SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)

#define	SNVS_HPLR_MKS_SL_MASK (0x200U)

#define	SNVS_HPLR_MKS_SL_SHIFT (9U)

#define	SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)

#define	SNVS_HPLR_HPSVCR_L_MASK (0x10000U)

#define	SNVS_HPLR_HPSVCR_L_SHIFT (16U)

#define	SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)

#define	SNVS_HPLR_HPSICR_L_MASK (0x20000U)

#define	SNVS_HPLR_HPSICR_L_SHIFT (17U)

#define	SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)

#define	SNVS_HPLR_HAC_L_MASK (0x40000U)

#define	SNVS_HPLR_HAC_L_SHIFT (18U)

#define	SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)

HPCOMR - SNVS_HP Command Register
#define	SNVS_HPCOMR_SSM_ST_MASK (0x1U)

#define	SNVS_HPCOMR_SSM_ST_SHIFT (0U)

#define	SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)

#define	SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)

#define	SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)

#define	SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)

#define	SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)

#define	SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)

#define	SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)

#define	SNVS_HPCOMR_LP_SWR_MASK (0x10U)

#define	SNVS_HPCOMR_LP_SWR_SHIFT (4U)

#define	SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)

#define	SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)

#define	SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)

#define	SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)

#define	SNVS_HPCOMR_SW_SV_MASK (0x100U)

#define	SNVS_HPCOMR_SW_SV_SHIFT (8U)

#define	SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)

#define	SNVS_HPCOMR_SW_FSV_MASK (0x200U)

#define	SNVS_HPCOMR_SW_FSV_SHIFT (9U)

#define	SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)

#define	SNVS_HPCOMR_SW_LPSV_MASK (0x400U)

#define	SNVS_HPCOMR_SW_LPSV_SHIFT (10U)

#define	SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)

#define	SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)

#define	SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)

#define	SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)

#define	SNVS_HPCOMR_MKS_EN_MASK (0x2000U)

#define	SNVS_HPCOMR_MKS_EN_SHIFT (13U)

#define	SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)

#define	SNVS_HPCOMR_HAC_EN_MASK (0x10000U)

#define	SNVS_HPCOMR_HAC_EN_SHIFT (16U)

#define	SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)

#define	SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)

#define	SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)

#define	SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)

#define	SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)

#define	SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)

#define	SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)

#define	SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)

#define	SNVS_HPCOMR_HAC_STOP_SHIFT (19U)

#define	SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)

#define	SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)

#define	SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)

#define	SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)

HPCR - SNVS_HP Control Register
#define	SNVS_HPCR_RTC_EN_MASK (0x1U)

#define	SNVS_HPCR_RTC_EN_SHIFT (0U)

#define	SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)

#define	SNVS_HPCR_HPTA_EN_MASK (0x2U)

#define	SNVS_HPCR_HPTA_EN_SHIFT (1U)

#define	SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)

#define	SNVS_HPCR_DIS_PI_MASK (0x4U)

#define	SNVS_HPCR_DIS_PI_SHIFT (2U)

#define	SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)

#define	SNVS_HPCR_PI_EN_MASK (0x8U)

#define	SNVS_HPCR_PI_EN_SHIFT (3U)

#define	SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)

#define	SNVS_HPCR_PI_FREQ_MASK (0xF0U)

#define	SNVS_HPCR_PI_FREQ_SHIFT (4U)

#define	SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)

#define	SNVS_HPCR_HPCALB_EN_MASK (0x100U)

#define	SNVS_HPCR_HPCALB_EN_SHIFT (8U)

#define	SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)

#define	SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)

#define	SNVS_HPCR_HPCALB_VAL_SHIFT (10U)

#define	SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)

#define	SNVS_HPCR_HP_TS_MASK (0x10000U)

#define	SNVS_HPCR_HP_TS_SHIFT (16U)

#define	SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)

#define	SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)

#define	SNVS_HPCR_BTN_CONFIG_SHIFT (24U)

#define	SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)

#define	SNVS_HPCR_BTN_MASK_MASK (0x8000000U)

#define	SNVS_HPCR_BTN_MASK_SHIFT (27U)

#define	SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)

HPSICR - SNVS_HP Security Interrupt Control Register
#define	SNVS_HPSICR_SV0_EN_MASK (0x1U)

#define	SNVS_HPSICR_SV0_EN_SHIFT (0U)

#define	SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)

#define	SNVS_HPSICR_SV1_EN_MASK (0x2U)

#define	SNVS_HPSICR_SV1_EN_SHIFT (1U)

#define	SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)

#define	SNVS_HPSICR_SV2_EN_MASK (0x4U)

#define	SNVS_HPSICR_SV2_EN_SHIFT (2U)

#define	SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)

#define	SNVS_HPSICR_SV3_EN_MASK (0x8U)

#define	SNVS_HPSICR_SV3_EN_SHIFT (3U)

#define	SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)

#define	SNVS_HPSICR_SV4_EN_MASK (0x10U)

#define	SNVS_HPSICR_SV4_EN_SHIFT (4U)

#define	SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)

#define	SNVS_HPSICR_SV5_EN_MASK (0x20U)

#define	SNVS_HPSICR_SV5_EN_SHIFT (5U)

#define	SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)

#define	SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)

#define	SNVS_HPSICR_LPSVI_EN_SHIFT (31U)

#define	SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)

HPSVCR - SNVS_HP Security Violation Control Register
#define	SNVS_HPSVCR_SV0_CFG_MASK (0x1U)

#define	SNVS_HPSVCR_SV0_CFG_SHIFT (0U)

#define	SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)

#define	SNVS_HPSVCR_SV1_CFG_MASK (0x2U)

#define	SNVS_HPSVCR_SV1_CFG_SHIFT (1U)

#define	SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)

#define	SNVS_HPSVCR_SV2_CFG_MASK (0x4U)

#define	SNVS_HPSVCR_SV2_CFG_SHIFT (2U)

#define	SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)

#define	SNVS_HPSVCR_SV3_CFG_MASK (0x8U)

#define	SNVS_HPSVCR_SV3_CFG_SHIFT (3U)

#define	SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)

#define	SNVS_HPSVCR_SV4_CFG_MASK (0x10U)

#define	SNVS_HPSVCR_SV4_CFG_SHIFT (4U)

#define	SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)

#define	SNVS_HPSVCR_SV5_CFG_MASK (0x60U)

#define	SNVS_HPSVCR_SV5_CFG_SHIFT (5U)

#define	SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)

#define	SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)

#define	SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)

#define	SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)

HPSR - SNVS_HP Status Register
#define	SNVS_HPSR_HPTA_MASK (0x1U)

#define	SNVS_HPSR_HPTA_SHIFT (0U)

#define	SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)

#define	SNVS_HPSR_PI_MASK (0x2U)

#define	SNVS_HPSR_PI_SHIFT (1U)

#define	SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)

#define	SNVS_HPSR_LPDIS_MASK (0x10U)

#define	SNVS_HPSR_LPDIS_SHIFT (4U)

#define	SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)

#define	SNVS_HPSR_BTN_MASK (0x40U)

#define	SNVS_HPSR_BTN_SHIFT (6U)

#define	SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)

#define	SNVS_HPSR_BI_MASK (0x80U)

#define	SNVS_HPSR_BI_SHIFT (7U)

#define	SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)

#define	SNVS_HPSR_SSM_STATE_MASK (0xF00U)

#define	SNVS_HPSR_SSM_STATE_SHIFT (8U)

#define	SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)

#define	SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)

#define	SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)

#define	SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)

#define	SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)

#define	SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)

#define	SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)

#define	SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)

#define	SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)

#define	SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)

#define	SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)

#define	SNVS_HPSR_ZMK_ZERO_SHIFT (31U)

#define	SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)

HPSVSR - SNVS_HP Security Violation Status Register
#define	SNVS_HPSVSR_SV0_MASK (0x1U)

#define	SNVS_HPSVSR_SV0_SHIFT (0U)

#define	SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)

#define	SNVS_HPSVSR_SV1_MASK (0x2U)

#define	SNVS_HPSVSR_SV1_SHIFT (1U)

#define	SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)

#define	SNVS_HPSVSR_SV2_MASK (0x4U)

#define	SNVS_HPSVSR_SV2_SHIFT (2U)

#define	SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)

#define	SNVS_HPSVSR_SV3_MASK (0x8U)

#define	SNVS_HPSVSR_SV3_SHIFT (3U)

#define	SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)

#define	SNVS_HPSVSR_SV4_MASK (0x10U)

#define	SNVS_HPSVSR_SV4_SHIFT (4U)

#define	SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)

#define	SNVS_HPSVSR_SV5_MASK (0x20U)

#define	SNVS_HPSVSR_SV5_SHIFT (5U)

#define	SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)

#define	SNVS_HPSVSR_SW_SV_MASK (0x2000U)

#define	SNVS_HPSVSR_SW_SV_SHIFT (13U)

#define	SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)

#define	SNVS_HPSVSR_SW_FSV_MASK (0x4000U)

#define	SNVS_HPSVSR_SW_FSV_SHIFT (14U)

#define	SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)

#define	SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)

#define	SNVS_HPSVSR_SW_LPSV_SHIFT (15U)

#define	SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)

#define	SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)

#define	SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)

#define	SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)

#define	SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)

#define	SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)

#define	SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)

#define	SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)

#define	SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)

#define	SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)

HPHACIVR - SNVS_HP High Assurance Counter IV Register
#define	SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)

#define	SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)

#define	SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)

HPHACR - SNVS_HP High Assurance Counter Register
#define	SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)

#define	SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)

#define	SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)

HPRTCMR - SNVS_HP Real Time Counter MSB Register
#define	SNVS_HPRTCMR_RTC_MASK (0x7FFFU)

#define	SNVS_HPRTCMR_RTC_SHIFT (0U)

#define	SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)

HPRTCLR - SNVS_HP Real Time Counter LSB Register
#define	SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)

#define	SNVS_HPRTCLR_RTC_SHIFT (0U)

#define	SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)

HPTAMR - SNVS_HP Time Alarm MSB Register
#define	SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)

#define	SNVS_HPTAMR_HPTA_MS_SHIFT (0U)

#define	SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)

HPTALR - SNVS_HP Time Alarm LSB Register
#define	SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)

#define	SNVS_HPTALR_HPTA_LS_SHIFT (0U)

#define	SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)

LPLR - SNVS_LP Lock Register
#define	SNVS_LPLR_ZMK_WHL_MASK (0x1U)

#define	SNVS_LPLR_ZMK_WHL_SHIFT (0U)

#define	SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)

#define	SNVS_LPLR_ZMK_RHL_MASK (0x2U)

#define	SNVS_LPLR_ZMK_RHL_SHIFT (1U)

#define	SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)

#define	SNVS_LPLR_SRTC_HL_MASK (0x4U)

#define	SNVS_LPLR_SRTC_HL_SHIFT (2U)

#define	SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)

#define	SNVS_LPLR_LPCALB_HL_MASK (0x8U)

#define	SNVS_LPLR_LPCALB_HL_SHIFT (3U)

#define	SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)

#define	SNVS_LPLR_MC_HL_MASK (0x10U)

#define	SNVS_LPLR_MC_HL_SHIFT (4U)

#define	SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)

#define	SNVS_LPLR_GPR_HL_MASK (0x20U)

#define	SNVS_LPLR_GPR_HL_SHIFT (5U)

#define	SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)

#define	SNVS_LPLR_LPSVCR_HL_MASK (0x40U)

#define	SNVS_LPLR_LPSVCR_HL_SHIFT (6U)

#define	SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)

#define	SNVS_LPLR_LPTDCR_HL_MASK (0x100U)

#define	SNVS_LPLR_LPTDCR_HL_SHIFT (8U)

#define	SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)

#define	SNVS_LPLR_MKS_HL_MASK (0x200U)

#define	SNVS_LPLR_MKS_HL_SHIFT (9U)

#define	SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)

LPCR - SNVS_LP Control Register
#define	SNVS_LPCR_SRTC_ENV_MASK (0x1U)

#define	SNVS_LPCR_SRTC_ENV_SHIFT (0U)

#define	SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)

#define	SNVS_LPCR_LPTA_EN_MASK (0x2U)

#define	SNVS_LPCR_LPTA_EN_SHIFT (1U)

#define	SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)

#define	SNVS_LPCR_MC_ENV_MASK (0x4U)

#define	SNVS_LPCR_MC_ENV_SHIFT (2U)

#define	SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)

#define	SNVS_LPCR_LPWUI_EN_MASK (0x8U)

#define	SNVS_LPCR_LPWUI_EN_SHIFT (3U)

#define	SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)

#define	SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)

#define	SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)

#define	SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)

#define	SNVS_LPCR_DP_EN_MASK (0x20U)

#define	SNVS_LPCR_DP_EN_SHIFT (5U)

#define	SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)

#define	SNVS_LPCR_TOP_MASK (0x40U)

#define	SNVS_LPCR_TOP_SHIFT (6U)

#define	SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)

#define	SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)

#define	SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)

#define	SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)

#define	SNVS_LPCR_LPCALB_EN_MASK (0x100U)

#define	SNVS_LPCR_LPCALB_EN_SHIFT (8U)

#define	SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)

#define	SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)

#define	SNVS_LPCR_LPCALB_VAL_SHIFT (10U)

#define	SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)

#define	SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)

#define	SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)

#define	SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)

#define	SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)

#define	SNVS_LPCR_DEBOUNCE_SHIFT (18U)

#define	SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)

#define	SNVS_LPCR_ON_TIME_MASK (0x300000U)

#define	SNVS_LPCR_ON_TIME_SHIFT (20U)

#define	SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)

#define	SNVS_LPCR_PK_EN_MASK (0x400000U)

#define	SNVS_LPCR_PK_EN_SHIFT (22U)

#define	SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)

#define	SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)

#define	SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)

#define	SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)

#define	SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)

#define	SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)

#define	SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)

LPMKCR - SNVS_LP Master Key Control Register
#define	SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)

#define	SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)

#define	SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)

#define	SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)

#define	SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)

#define	SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)

#define	SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)

#define	SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)

#define	SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)

#define	SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)

#define	SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)

#define	SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)

#define	SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)

#define	SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)

#define	SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)

LPSVCR - SNVS_LP Security Violation Control Register
#define	SNVS_LPSVCR_SV0_EN_MASK (0x1U)

#define	SNVS_LPSVCR_SV0_EN_SHIFT (0U)

#define	SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)

#define	SNVS_LPSVCR_SV1_EN_MASK (0x2U)

#define	SNVS_LPSVCR_SV1_EN_SHIFT (1U)

#define	SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)

#define	SNVS_LPSVCR_SV2_EN_MASK (0x4U)

#define	SNVS_LPSVCR_SV2_EN_SHIFT (2U)

#define	SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)

#define	SNVS_LPSVCR_SV3_EN_MASK (0x8U)

#define	SNVS_LPSVCR_SV3_EN_SHIFT (3U)

#define	SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)

#define	SNVS_LPSVCR_SV4_EN_MASK (0x10U)

#define	SNVS_LPSVCR_SV4_EN_SHIFT (4U)

#define	SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)

#define	SNVS_LPSVCR_SV5_EN_MASK (0x20U)

#define	SNVS_LPSVCR_SV5_EN_SHIFT (5U)

#define	SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)

LPTDCR - SNVS_LP Tamper Detectors Configuration Register
#define	SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)

#define	SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)

#define	SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)

#define	SNVS_LPTDCR_MCR_EN_MASK (0x4U)

#define	SNVS_LPTDCR_MCR_EN_SHIFT (2U)

#define	SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)

#define	SNVS_LPTDCR_ET1_EN_MASK (0x200U)

#define	SNVS_LPTDCR_ET1_EN_SHIFT (9U)

#define	SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)

#define	SNVS_LPTDCR_ET1P_MASK (0x800U)

#define	SNVS_LPTDCR_ET1P_SHIFT (11U)

#define	SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)

#define	SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)

#define	SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)

#define	SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)

#define	SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)

#define	SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)

#define	SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)

#define	SNVS_LPTDCR_OSCB_MASK (0x10000000U)

#define	SNVS_LPTDCR_OSCB_SHIFT (28U)

#define	SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)

LPSR - SNVS_LP Status Register
#define	SNVS_LPSR_LPTA_MASK (0x1U)

#define	SNVS_LPSR_LPTA_SHIFT (0U)

#define	SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)

#define	SNVS_LPSR_SRTCR_MASK (0x2U)

#define	SNVS_LPSR_SRTCR_SHIFT (1U)

#define	SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)

#define	SNVS_LPSR_MCR_MASK (0x4U)

#define	SNVS_LPSR_MCR_SHIFT (2U)

#define	SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)

#define	SNVS_LPSR_PGD_MASK (0x8U)

#define	SNVS_LPSR_PGD_SHIFT (3U)

#define	SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)

#define	SNVS_LPSR_ET1D_MASK (0x200U)

#define	SNVS_LPSR_ET1D_SHIFT (9U)

#define	SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)

#define	SNVS_LPSR_ESVD_MASK (0x10000U)

#define	SNVS_LPSR_ESVD_SHIFT (16U)

#define	SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)

#define	SNVS_LPSR_EO_MASK (0x20000U)

#define	SNVS_LPSR_EO_SHIFT (17U)

#define	SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)

#define	SNVS_LPSR_SPO_MASK (0x40000U)

#define	SNVS_LPSR_SPO_SHIFT (18U)

#define	SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)

#define	SNVS_LPSR_SED_MASK (0x100000U)

#define	SNVS_LPSR_SED_SHIFT (20U)

#define	SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)

#define	SNVS_LPSR_LPNS_MASK (0x40000000U)

#define	SNVS_LPSR_LPNS_SHIFT (30U)

#define	SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)

#define	SNVS_LPSR_LPS_MASK (0x80000000U)

#define	SNVS_LPSR_LPS_SHIFT (31U)

#define	SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)

LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register
#define	SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)

#define	SNVS_LPSRTCMR_SRTC_SHIFT (0U)

#define	SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)

LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register
#define	SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)

#define	SNVS_LPSRTCLR_SRTC_SHIFT (0U)

#define	SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)

LPTAR - SNVS_LP Time Alarm Register
#define	SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)

#define	SNVS_LPTAR_LPTA_SHIFT (0U)

#define	SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)

LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register
#define	SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)

#define	SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)

#define	SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)

#define	SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)

#define	SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)

#define	SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)

LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register
#define	SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)

#define	SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)

#define	SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)

LPPGDR - SNVS_LP Power Glitch Detector Register
#define	SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)

#define	SNVS_LPPGDR_PGD_SHIFT (0U)

#define	SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)

LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias)
#define	SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)

#define	SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)

#define	SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)

LPZMKR - SNVS_LP Zeroizable Master Key Register
#define	SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)

#define	SNVS_LPZMKR_ZMK_SHIFT (0U)

#define	SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)

LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3
#define	SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)

#define	SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)

#define	SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)

LPGPR - SNVS_LP General Purpose Registers 0 .. 7
#define	SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)

#define	SNVS_LPGPR_GPR_SHIFT (0U)

#define	SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)

HPVIDR1 - SNVS_HP Version ID Register 1
#define	SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)

#define	SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)

#define	SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)

#define	SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)

#define	SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)

#define	SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)

#define	SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)

#define	SNVS_HPVIDR1_IP_ID_SHIFT (16U)

#define	SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)

HPVIDR2 - SNVS_HP Version ID Register 2
#define	SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)

#define	SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)

#define	SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)

#define	SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)

#define	SNVS_HPVIDR2_ECO_REV_SHIFT (8U)

#define	SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)

#define	SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)

#define	SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)

#define	SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)

#define	SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)

#define	SNVS_HPVIDR2_IP_ERA_SHIFT (24U)

#define	SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)

Detailed Description

Macro Definition Documentation

◆ SNVS_HPCOMR_HAC_CLEAR

#define SNVS_HPCOMR_HAC_CLEAR ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)

HAC_CLEAR 0b0..No Action 0b1..Clear the HAC

Definition at line 35530 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_CLEAR_MASK

#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)

Definition at line 35524 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_CLEAR_SHIFT

#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)

Definition at line 35525 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_EN

#define SNVS_HPCOMR_HAC_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)

HAC_EN 0b0..High Assurance Counter is disabled 0b1..High Assurance Counter is enabled

Definition at line 35516 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_EN_MASK

#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)

Definition at line 35510 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_EN_SHIFT

#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)

Definition at line 35511 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_LOAD

#define SNVS_HPCOMR_HAC_LOAD ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)

HAC_LOAD 0b0..No Action 0b1..Load the HAC

Definition at line 35523 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_LOAD_MASK

#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)

Definition at line 35517 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_LOAD_SHIFT

#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)

Definition at line 35518 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_STOP

#define SNVS_HPCOMR_HAC_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)

Definition at line 35533 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_STOP_MASK

#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)

Definition at line 35531 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_HAC_STOP_SHIFT

#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)

Definition at line 35532 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_LP_SWR

#define SNVS_HPCOMR_LP_SWR ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)

LP_SWR 0b0..No Action 0b1..Reset LP section

Definition at line 35479 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_LP_SWR_DIS

#define SNVS_HPCOMR_LP_SWR_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)

LP_SWR_DIS 0b0..LP software reset is enabled 0b1..LP software reset is disabled

Definition at line 35486 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_LP_SWR_DIS_MASK

#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)

Definition at line 35480 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_LP_SWR_DIS_SHIFT

#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)

Definition at line 35481 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_LP_SWR_MASK

#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)

Definition at line 35473 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_LP_SWR_SHIFT

#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)

Definition at line 35474 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_MKS_EN

#define SNVS_HPCOMR_MKS_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)

MKS_EN 0b0..OTP master key is selected as an SNVS master key 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR

Definition at line 35509 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_MKS_EN_MASK

#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)

Definition at line 35503 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_MKS_EN_SHIFT

#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)

Definition at line 35504 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_NPSWA_EN

#define SNVS_HPCOMR_NPSWA_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)

Definition at line 35536 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_NPSWA_EN_MASK

#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)

Definition at line 35534 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_NPSWA_EN_SHIFT

#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)

Definition at line 35535 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_PROG_ZMK

#define SNVS_HPCOMR_PROG_ZMK ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)

PROG_ZMK 0b0..No Action 0b1..Activate hardware key programming mechanism

Definition at line 35502 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_PROG_ZMK_MASK

#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)

Definition at line 35496 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_PROG_ZMK_SHIFT

#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)

Definition at line 35497 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_SFNS_DIS

#define SNVS_HPCOMR_SSM_SFNS_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)

SSM_SFNS_DIS 0b0..Soft Fail to Non-Secure State transition is enabled 0b1..Soft Fail to Non-Secure State transition is disabled

Definition at line 35472 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_SFNS_DIS_MASK

#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)

Definition at line 35466 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT

#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)

Definition at line 35467 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_ST

#define SNVS_HPCOMR_SSM_ST ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)

Definition at line 35458 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_ST_DIS

#define SNVS_HPCOMR_SSM_ST_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)

SSM_ST_DIS 0b0..Secure to Trusted State transition is enabled 0b1..Secure to Trusted State transition is disabled

Definition at line 35465 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_ST_DIS_MASK

#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)

Definition at line 35459 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_ST_DIS_SHIFT

#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)

Definition at line 35460 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_ST_MASK

#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)

Definition at line 35456 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SSM_ST_SHIFT

#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)

Definition at line 35457 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_FSV

#define SNVS_HPCOMR_SW_FSV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)

Definition at line 35492 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_FSV_MASK

#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)

Definition at line 35490 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_FSV_SHIFT

#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)

Definition at line 35491 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_LPSV

#define SNVS_HPCOMR_SW_LPSV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)

Definition at line 35495 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_LPSV_MASK

#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)

Definition at line 35493 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_LPSV_SHIFT

#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)

Definition at line 35494 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_SV

#define SNVS_HPCOMR_SW_SV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)

Definition at line 35489 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_SV_MASK

#define SNVS_HPCOMR_SW_SV_MASK (0x100U)

Definition at line 35487 of file MIMXRT1052.h.

◆ SNVS_HPCOMR_SW_SV_SHIFT

#define SNVS_HPCOMR_SW_SV_SHIFT (8U)

Definition at line 35488 of file MIMXRT1052.h.

◆ SNVS_HPCR_BTN_CONFIG

#define SNVS_HPCR_BTN_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)

Definition at line 35619 of file MIMXRT1052.h.

◆ SNVS_HPCR_BTN_CONFIG_MASK

#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)

Definition at line 35617 of file MIMXRT1052.h.

◆ SNVS_HPCR_BTN_CONFIG_SHIFT

#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)

Definition at line 35618 of file MIMXRT1052.h.

◆ SNVS_HPCR_BTN_MASK

#define SNVS_HPCR_BTN_MASK ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)

Definition at line 35622 of file MIMXRT1052.h.

◆ SNVS_HPCR_BTN_MASK_MASK

#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)

Definition at line 35620 of file MIMXRT1052.h.

◆ SNVS_HPCR_BTN_MASK_SHIFT

#define SNVS_HPCR_BTN_MASK_SHIFT (27U)

Definition at line 35621 of file MIMXRT1052.h.

◆ SNVS_HPCR_DIS_PI

#define SNVS_HPCR_DIS_PI ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)

DIS_PI 0b0..Periodic interrupt will trigger a functional interrupt 0b1..Disable periodic interrupt in the function interrupt

Definition at line 35561 of file MIMXRT1052.h.

◆ SNVS_HPCR_DIS_PI_MASK

#define SNVS_HPCR_DIS_PI_MASK (0x4U)

Definition at line 35555 of file MIMXRT1052.h.

◆ SNVS_HPCR_DIS_PI_SHIFT

#define SNVS_HPCR_DIS_PI_SHIFT (2U)

Definition at line 35556 of file MIMXRT1052.h.

◆ SNVS_HPCR_HP_TS

#define SNVS_HPCR_HP_TS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)

HP_TS 0b0..No Action 0b1..Synchronize the HP Time Counter to the LP Time Counter

Definition at line 35616 of file MIMXRT1052.h.

◆ SNVS_HPCR_HP_TS_MASK

#define SNVS_HPCR_HP_TS_MASK (0x10000U)

Definition at line 35610 of file MIMXRT1052.h.

◆ SNVS_HPCR_HP_TS_SHIFT

#define SNVS_HPCR_HP_TS_SHIFT (16U)

Definition at line 35611 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPCALB_EN

#define SNVS_HPCR_HPCALB_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)

HPCALB_EN 0b0..HP Timer calibration disabled 0b1..HP Timer calibration enabled

Definition at line 35596 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPCALB_EN_MASK

#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)

Definition at line 35590 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPCALB_EN_SHIFT

#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)

Definition at line 35591 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPCALB_VAL

#define SNVS_HPCR_HPCALB_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)

HPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter 0b00001..+1 counts per each 32768 ticks of the counter 0b00010..+2 counts per each 32768 ticks of the counter 0b01111..+15 counts per each 32768 ticks of the counter 0b10000..-16 counts per each 32768 ticks of the counter 0b10001..-15 counts per each 32768 ticks of the counter 0b11110..-2 counts per each 32768 ticks of the counter 0b11111..-1 counts per each 32768 ticks of the counter

Definition at line 35609 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPCALB_VAL_MASK

#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)

Definition at line 35597 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPCALB_VAL_SHIFT

#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)

Definition at line 35598 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPTA_EN

#define SNVS_HPCR_HPTA_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)

HPTA_EN 0b0..HP Time Alarm Interrupt is disabled 0b1..HP Time Alarm Interrupt is enabled

Definition at line 35554 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPTA_EN_MASK

#define SNVS_HPCR_HPTA_EN_MASK (0x2U)

Definition at line 35548 of file MIMXRT1052.h.

◆ SNVS_HPCR_HPTA_EN_SHIFT

#define SNVS_HPCR_HPTA_EN_SHIFT (1U)

Definition at line 35549 of file MIMXRT1052.h.

◆ SNVS_HPCR_PI_EN

#define SNVS_HPCR_PI_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)

PI_EN 0b0..HP Periodic Interrupt is disabled 0b1..HP Periodic Interrupt is enabled

Definition at line 35568 of file MIMXRT1052.h.

◆ SNVS_HPCR_PI_EN_MASK

#define SNVS_HPCR_PI_EN_MASK (0x8U)

Definition at line 35562 of file MIMXRT1052.h.

◆ SNVS_HPCR_PI_EN_SHIFT

#define SNVS_HPCR_PI_EN_SHIFT (3U)

Definition at line 35563 of file MIMXRT1052.h.

◆ SNVS_HPCR_PI_FREQ

#define SNVS_HPCR_PI_FREQ ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)

PI_FREQ 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt

Definition at line 35589 of file MIMXRT1052.h.

◆ SNVS_HPCR_PI_FREQ_MASK

#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)

Definition at line 35569 of file MIMXRT1052.h.

◆ SNVS_HPCR_PI_FREQ_SHIFT

#define SNVS_HPCR_PI_FREQ_SHIFT (4U)

Definition at line 35570 of file MIMXRT1052.h.

◆ SNVS_HPCR_RTC_EN

#define SNVS_HPCR_RTC_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)

RTC_EN 0b0..RTC is disabled 0b1..RTC is enabled

Definition at line 35547 of file MIMXRT1052.h.

◆ SNVS_HPCR_RTC_EN_MASK

#define SNVS_HPCR_RTC_EN_MASK (0x1U)

Definition at line 35541 of file MIMXRT1052.h.

◆ SNVS_HPCR_RTC_EN_SHIFT

#define SNVS_HPCR_RTC_EN_SHIFT (0U)

Definition at line 35542 of file MIMXRT1052.h.

◆ SNVS_HPHACIVR_HAC_COUNTER_IV

#define SNVS_HPHACIVR_HAC_COUNTER_IV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)

Definition at line 35871 of file MIMXRT1052.h.

◆ SNVS_HPHACIVR_HAC_COUNTER_IV_MASK

#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)

Definition at line 35869 of file MIMXRT1052.h.

◆ SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT

#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)

Definition at line 35870 of file MIMXRT1052.h.

◆ SNVS_HPHACR_HAC_COUNTER

#define SNVS_HPHACR_HAC_COUNTER ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)

Definition at line 35878 of file MIMXRT1052.h.

◆ SNVS_HPHACR_HAC_COUNTER_MASK

#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)

Definition at line 35876 of file MIMXRT1052.h.

◆ SNVS_HPHACR_HAC_COUNTER_SHIFT

#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)

Definition at line 35877 of file MIMXRT1052.h.

◆ SNVS_HPLR_GPR_SL

#define SNVS_HPLR_GPR_SL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)

GPR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35409 of file MIMXRT1052.h.

◆ SNVS_HPLR_GPR_SL_MASK

#define SNVS_HPLR_GPR_SL_MASK (0x20U)

Definition at line 35403 of file MIMXRT1052.h.

◆ SNVS_HPLR_GPR_SL_SHIFT

#define SNVS_HPLR_GPR_SL_SHIFT (5U)

Definition at line 35404 of file MIMXRT1052.h.

◆ SNVS_HPLR_HAC_L

#define SNVS_HPLR_HAC_L ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)

HAC_L 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35451 of file MIMXRT1052.h.

◆ SNVS_HPLR_HAC_L_MASK

#define SNVS_HPLR_HAC_L_MASK (0x40000U)

Definition at line 35445 of file MIMXRT1052.h.

◆ SNVS_HPLR_HAC_L_SHIFT

#define SNVS_HPLR_HAC_L_SHIFT (18U)

Definition at line 35446 of file MIMXRT1052.h.

◆ SNVS_HPLR_HPSICR_L

#define SNVS_HPLR_HPSICR_L ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)

HPSICR_L 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35444 of file MIMXRT1052.h.

◆ SNVS_HPLR_HPSICR_L_MASK

#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)

Definition at line 35438 of file MIMXRT1052.h.

◆ SNVS_HPLR_HPSICR_L_SHIFT

#define SNVS_HPLR_HPSICR_L_SHIFT (17U)

Definition at line 35439 of file MIMXRT1052.h.

◆ SNVS_HPLR_HPSVCR_L

#define SNVS_HPLR_HPSVCR_L ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)

HPSVCR_L 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35437 of file MIMXRT1052.h.

◆ SNVS_HPLR_HPSVCR_L_MASK

#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)

Definition at line 35431 of file MIMXRT1052.h.

◆ SNVS_HPLR_HPSVCR_L_SHIFT

#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)

Definition at line 35432 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPCALB_SL

#define SNVS_HPLR_LPCALB_SL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)

LPCALB_SL 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35395 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPCALB_SL_MASK

#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)

Definition at line 35389 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPCALB_SL_SHIFT

#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)

Definition at line 35390 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPSVCR_SL

#define SNVS_HPLR_LPSVCR_SL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)

LPSVCR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35416 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPSVCR_SL_MASK

#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)

Definition at line 35410 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPSVCR_SL_SHIFT

#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)

Definition at line 35411 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPTDCR_SL

#define SNVS_HPLR_LPTDCR_SL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)

LPTDCR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35423 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPTDCR_SL_MASK

#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U)

Definition at line 35417 of file MIMXRT1052.h.

◆ SNVS_HPLR_LPTDCR_SL_SHIFT

#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U)

Definition at line 35418 of file MIMXRT1052.h.

◆ SNVS_HPLR_MC_SL

#define SNVS_HPLR_MC_SL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)

MC_SL 0b0..Write access (increment) is allowed 0b1..Write access (increment) is not allowed

Definition at line 35402 of file MIMXRT1052.h.

◆ SNVS_HPLR_MC_SL_MASK

#define SNVS_HPLR_MC_SL_MASK (0x10U)

Definition at line 35396 of file MIMXRT1052.h.

◆ SNVS_HPLR_MC_SL_SHIFT

#define SNVS_HPLR_MC_SL_SHIFT (4U)

Definition at line 35397 of file MIMXRT1052.h.

◆ SNVS_HPLR_MKS_SL

#define SNVS_HPLR_MKS_SL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)

MKS_SL 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35430 of file MIMXRT1052.h.

◆ SNVS_HPLR_MKS_SL_MASK

#define SNVS_HPLR_MKS_SL_MASK (0x200U)

Definition at line 35424 of file MIMXRT1052.h.

◆ SNVS_HPLR_MKS_SL_SHIFT

#define SNVS_HPLR_MKS_SL_SHIFT (9U)

Definition at line 35425 of file MIMXRT1052.h.

◆ SNVS_HPLR_SRTC_SL

#define SNVS_HPLR_SRTC_SL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)

SRTC_SL 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35388 of file MIMXRT1052.h.

◆ SNVS_HPLR_SRTC_SL_MASK

#define SNVS_HPLR_SRTC_SL_MASK (0x4U)

Definition at line 35382 of file MIMXRT1052.h.

◆ SNVS_HPLR_SRTC_SL_SHIFT

#define SNVS_HPLR_SRTC_SL_SHIFT (2U)

Definition at line 35383 of file MIMXRT1052.h.

◆ SNVS_HPLR_ZMK_RSL

#define SNVS_HPLR_ZMK_RSL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)

ZMK_RSL 0b0..Read access is allowed (only in software Programming mode) 0b1..Read access is not allowed

Definition at line 35381 of file MIMXRT1052.h.

◆ SNVS_HPLR_ZMK_RSL_MASK

#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)

Definition at line 35375 of file MIMXRT1052.h.

◆ SNVS_HPLR_ZMK_RSL_SHIFT

#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)

Definition at line 35376 of file MIMXRT1052.h.

◆ SNVS_HPLR_ZMK_WSL

#define SNVS_HPLR_ZMK_WSL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)

ZMK_WSL 0b0..Write access is allowed 0b1..Write access is not allowed

Definition at line 35374 of file MIMXRT1052.h.

◆ SNVS_HPLR_ZMK_WSL_MASK

#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)

Definition at line 35368 of file MIMXRT1052.h.

◆ SNVS_HPLR_ZMK_WSL_SHIFT

#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)

Definition at line 35369 of file MIMXRT1052.h.

◆ SNVS_HPRTCLR_RTC

#define SNVS_HPRTCLR_RTC ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)

Definition at line 35892 of file MIMXRT1052.h.

◆ SNVS_HPRTCLR_RTC_MASK

#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)

Definition at line 35890 of file MIMXRT1052.h.

◆ SNVS_HPRTCLR_RTC_SHIFT

#define SNVS_HPRTCLR_RTC_SHIFT (0U)

Definition at line 35891 of file MIMXRT1052.h.

◆ SNVS_HPRTCMR_RTC

#define SNVS_HPRTCMR_RTC ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)

Definition at line 35885 of file MIMXRT1052.h.

◆ SNVS_HPRTCMR_RTC_MASK

#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)

Definition at line 35883 of file MIMXRT1052.h.

◆ SNVS_HPRTCMR_RTC_SHIFT

#define SNVS_HPRTCMR_RTC_SHIFT (0U)

Definition at line 35884 of file MIMXRT1052.h.

◆ SNVS_HPSICR_LPSVI_EN

#define SNVS_HPSICR_LPSVI_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)

LPSVI_EN 0b0..LP Security Violation Interrupt is Disabled 0b1..LP Security Violation Interrupt is Enabled

Definition at line 35675 of file MIMXRT1052.h.

◆ SNVS_HPSICR_LPSVI_EN_MASK

#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)

Definition at line 35669 of file MIMXRT1052.h.

◆ SNVS_HPSICR_LPSVI_EN_SHIFT

#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)

Definition at line 35670 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV0_EN

#define SNVS_HPSICR_SV0_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)

SV0_EN 0b0..Security Violation 0 Interrupt is Disabled 0b1..Security Violation 0 Interrupt is Enabled

Definition at line 35633 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV0_EN_MASK

#define SNVS_HPSICR_SV0_EN_MASK (0x1U)

Definition at line 35627 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV0_EN_SHIFT

#define SNVS_HPSICR_SV0_EN_SHIFT (0U)

Definition at line 35628 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV1_EN

#define SNVS_HPSICR_SV1_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)

SV1_EN 0b0..Security Violation 1 Interrupt is Disabled 0b1..Security Violation 1 Interrupt is Enabled

Definition at line 35640 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV1_EN_MASK

#define SNVS_HPSICR_SV1_EN_MASK (0x2U)

Definition at line 35634 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV1_EN_SHIFT

#define SNVS_HPSICR_SV1_EN_SHIFT (1U)

Definition at line 35635 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV2_EN

#define SNVS_HPSICR_SV2_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)

SV2_EN 0b0..Security Violation 2 Interrupt is Disabled 0b1..Security Violation 2 Interrupt is Enabled

Definition at line 35647 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV2_EN_MASK

#define SNVS_HPSICR_SV2_EN_MASK (0x4U)

Definition at line 35641 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV2_EN_SHIFT

#define SNVS_HPSICR_SV2_EN_SHIFT (2U)

Definition at line 35642 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV3_EN

#define SNVS_HPSICR_SV3_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)

SV3_EN 0b0..Security Violation 3 Interrupt is Disabled 0b1..Security Violation 3 Interrupt is Enabled

Definition at line 35654 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV3_EN_MASK

#define SNVS_HPSICR_SV3_EN_MASK (0x8U)

Definition at line 35648 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV3_EN_SHIFT

#define SNVS_HPSICR_SV3_EN_SHIFT (3U)

Definition at line 35649 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV4_EN

#define SNVS_HPSICR_SV4_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)

SV4_EN 0b0..Security Violation 4 Interrupt is Disabled 0b1..Security Violation 4 Interrupt is Enabled

Definition at line 35661 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV4_EN_MASK

#define SNVS_HPSICR_SV4_EN_MASK (0x10U)

Definition at line 35655 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV4_EN_SHIFT

#define SNVS_HPSICR_SV4_EN_SHIFT (4U)

Definition at line 35656 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV5_EN

#define SNVS_HPSICR_SV5_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)

SV5_EN 0b0..Security Violation 5 Interrupt is Disabled 0b1..Security Violation 5 Interrupt is Enabled

Definition at line 35668 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV5_EN_MASK

#define SNVS_HPSICR_SV5_EN_MASK (0x20U)

Definition at line 35662 of file MIMXRT1052.h.

◆ SNVS_HPSICR_SV5_EN_SHIFT

#define SNVS_HPSICR_SV5_EN_SHIFT (5U)

Definition at line 35663 of file MIMXRT1052.h.

◆ SNVS_HPSR_BI

#define SNVS_HPSR_BI ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)

Definition at line 35757 of file MIMXRT1052.h.

◆ SNVS_HPSR_BI_MASK

#define SNVS_HPSR_BI_MASK (0x80U)

Definition at line 35755 of file MIMXRT1052.h.

◆ SNVS_HPSR_BI_SHIFT

#define SNVS_HPSR_BI_SHIFT (7U)

Definition at line 35756 of file MIMXRT1052.h.

◆ SNVS_HPSR_BTN

#define SNVS_HPSR_BTN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)

Definition at line 35754 of file MIMXRT1052.h.

◆ SNVS_HPSR_BTN_MASK

#define SNVS_HPSR_BTN_MASK (0x40U)

Definition at line 35752 of file MIMXRT1052.h.

◆ SNVS_HPSR_BTN_SHIFT

#define SNVS_HPSR_BTN_SHIFT (6U)

Definition at line 35753 of file MIMXRT1052.h.

◆ SNVS_HPSR_HPTA

#define SNVS_HPSR_HPTA ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)

HPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

Definition at line 35741 of file MIMXRT1052.h.

◆ SNVS_HPSR_HPTA_MASK

#define SNVS_HPSR_HPTA_MASK (0x1U)

Definition at line 35735 of file MIMXRT1052.h.

◆ SNVS_HPSR_HPTA_SHIFT

#define SNVS_HPSR_HPTA_SHIFT (0U)

Definition at line 35736 of file MIMXRT1052.h.

◆ SNVS_HPSR_LPDIS

#define SNVS_HPSR_LPDIS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)

Definition at line 35751 of file MIMXRT1052.h.

◆ SNVS_HPSR_LPDIS_MASK

#define SNVS_HPSR_LPDIS_MASK (0x10U)

Definition at line 35749 of file MIMXRT1052.h.

◆ SNVS_HPSR_LPDIS_SHIFT

#define SNVS_HPSR_LPDIS_SHIFT (4U)

Definition at line 35750 of file MIMXRT1052.h.

◆ SNVS_HPSR_OTPMK_SYNDROME

#define SNVS_HPSR_OTPMK_SYNDROME ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)

Definition at line 35782 of file MIMXRT1052.h.

◆ SNVS_HPSR_OTPMK_SYNDROME_MASK

#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)

Definition at line 35780 of file MIMXRT1052.h.

◆ SNVS_HPSR_OTPMK_SYNDROME_SHIFT

#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)

Definition at line 35781 of file MIMXRT1052.h.

◆ SNVS_HPSR_OTPMK_ZERO

#define SNVS_HPSR_OTPMK_ZERO ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)

OTPMK_ZERO 0b0..The OTPMK is not zero. 0b1..The OTPMK is zero.

Definition at line 35789 of file MIMXRT1052.h.

◆ SNVS_HPSR_OTPMK_ZERO_MASK

#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)

Definition at line 35783 of file MIMXRT1052.h.

◆ SNVS_HPSR_OTPMK_ZERO_SHIFT

#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)

Definition at line 35784 of file MIMXRT1052.h.

◆ SNVS_HPSR_PI

#define SNVS_HPSR_PI ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)

PI 0b0..No periodic interrupt occurred. 0b1..A periodic interrupt occurred.

Definition at line 35748 of file MIMXRT1052.h.

◆ SNVS_HPSR_PI_MASK

#define SNVS_HPSR_PI_MASK (0x2U)

Definition at line 35742 of file MIMXRT1052.h.

◆ SNVS_HPSR_PI_SHIFT

#define SNVS_HPSR_PI_SHIFT (1U)

Definition at line 35743 of file MIMXRT1052.h.

◆ SNVS_HPSR_SECURITY_CONFIG

#define SNVS_HPSR_SECURITY_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)

SECURITY_CONFIG 0b0000, 0b1000..FAB configuration 0b0001, 0b0010, 0b0011..OPEN configuration 0b1010, 0b1001, 0b1011..CLOSED configuration 0bx1xx..FIELD RETURN configuration

Definition at line 35779 of file MIMXRT1052.h.

◆ SNVS_HPSR_SECURITY_CONFIG_MASK

#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)

Definition at line 35771 of file MIMXRT1052.h.

◆ SNVS_HPSR_SECURITY_CONFIG_SHIFT

#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)

Definition at line 35772 of file MIMXRT1052.h.

◆ SNVS_HPSR_SSM_STATE

#define SNVS_HPSR_SSM_STATE ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)

SSM_STATE 0b0000..Init 0b0001..Hard Fail 0b0011..Soft Fail 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) 0b1001..Check 0b1011..Non-Secure 0b1101..Trusted 0b1111..Secure

Definition at line 35770 of file MIMXRT1052.h.

◆ SNVS_HPSR_SSM_STATE_MASK

#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)

Definition at line 35758 of file MIMXRT1052.h.

◆ SNVS_HPSR_SSM_STATE_SHIFT

#define SNVS_HPSR_SSM_STATE_SHIFT (8U)

Definition at line 35759 of file MIMXRT1052.h.

◆ SNVS_HPSR_ZMK_ZERO

#define SNVS_HPSR_ZMK_ZERO ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)

ZMK_ZERO 0b0..The ZMK is not zero. 0b1..The ZMK is zero.

Definition at line 35796 of file MIMXRT1052.h.

◆ SNVS_HPSR_ZMK_ZERO_MASK

#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)

Definition at line 35790 of file MIMXRT1052.h.

◆ SNVS_HPSR_ZMK_ZERO_SHIFT

#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)

Definition at line 35791 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_LPSV_CFG

#define SNVS_HPSVCR_LPSV_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)

LPSV_CFG 0b00..LP security violation is disabled 0b01..LP security violation is a non-fatal violation 0b1x..LP security violation is a fatal violation

Definition at line 35730 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_LPSV_CFG_MASK

#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)

Definition at line 35723 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_LPSV_CFG_SHIFT

#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)

Definition at line 35724 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV0_CFG

#define SNVS_HPSVCR_SV0_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)

SV0_CFG 0b0..Security Violation 0 is a non-fatal violation 0b1..Security Violation 0 is a fatal violation

Definition at line 35686 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV0_CFG_MASK

#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)

Definition at line 35680 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV0_CFG_SHIFT

#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)

Definition at line 35681 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV1_CFG

#define SNVS_HPSVCR_SV1_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)

SV1_CFG 0b0..Security Violation 1 is a non-fatal violation 0b1..Security Violation 1 is a fatal violation

Definition at line 35693 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV1_CFG_MASK

#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)

Definition at line 35687 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV1_CFG_SHIFT

#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)

Definition at line 35688 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV2_CFG

#define SNVS_HPSVCR_SV2_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)

SV2_CFG 0b0..Security Violation 2 is a non-fatal violation 0b1..Security Violation 2 is a fatal violation

Definition at line 35700 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV2_CFG_MASK

#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)

Definition at line 35694 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV2_CFG_SHIFT

#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)

Definition at line 35695 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV3_CFG

#define SNVS_HPSVCR_SV3_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)

SV3_CFG 0b0..Security Violation 3 is a non-fatal violation 0b1..Security Violation 3 is a fatal violation

Definition at line 35707 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV3_CFG_MASK

#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)

Definition at line 35701 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV3_CFG_SHIFT

#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)

Definition at line 35702 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV4_CFG

#define SNVS_HPSVCR_SV4_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)

SV4_CFG 0b0..Security Violation 4 is a non-fatal violation 0b1..Security Violation 4 is a fatal violation

Definition at line 35714 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV4_CFG_MASK

#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)

Definition at line 35708 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV4_CFG_SHIFT

#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)

Definition at line 35709 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV5_CFG

#define SNVS_HPSVCR_SV5_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)

SV5_CFG 0b00..Security Violation 5 is disabled 0b01..Security Violation 5 is a non-fatal violation 0b1x..Security Violation 5 is a fatal violation

Definition at line 35722 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV5_CFG_MASK

#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)

Definition at line 35715 of file MIMXRT1052.h.

◆ SNVS_HPSVCR_SV5_CFG_SHIFT

#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)

Definition at line 35716 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_LP_SEC_VIO

#define SNVS_HPSVSR_LP_SEC_VIO ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)

Definition at line 35864 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_LP_SEC_VIO_MASK

#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)

Definition at line 35862 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_LP_SEC_VIO_SHIFT

#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)

Definition at line 35863 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV0

#define SNVS_HPSVSR_SV0 ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)

SV0 0b0..No Security Violation 0 security violation was detected. 0b1..Security Violation 0 security violation was detected.

Definition at line 35807 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV0_MASK

#define SNVS_HPSVSR_SV0_MASK (0x1U)

Definition at line 35801 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV0_SHIFT

#define SNVS_HPSVSR_SV0_SHIFT (0U)

Definition at line 35802 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV1

#define SNVS_HPSVSR_SV1 ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)

SV1 0b0..No Security Violation 1 security violation was detected. 0b1..Security Violation 1 security violation was detected.

Definition at line 35814 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV1_MASK

#define SNVS_HPSVSR_SV1_MASK (0x2U)

Definition at line 35808 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV1_SHIFT

#define SNVS_HPSVSR_SV1_SHIFT (1U)

Definition at line 35809 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV2

#define SNVS_HPSVSR_SV2 ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)

SV2 0b0..No Security Violation 2 security violation was detected. 0b1..Security Violation 2 security violation was detected.

Definition at line 35821 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV2_MASK

#define SNVS_HPSVSR_SV2_MASK (0x4U)

Definition at line 35815 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV2_SHIFT

#define SNVS_HPSVSR_SV2_SHIFT (2U)

Definition at line 35816 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV3

#define SNVS_HPSVSR_SV3 ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)

SV3 0b0..No Security Violation 3 security violation was detected. 0b1..Security Violation 3 security violation was detected.

Definition at line 35828 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV3_MASK

#define SNVS_HPSVSR_SV3_MASK (0x8U)

Definition at line 35822 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV3_SHIFT

#define SNVS_HPSVSR_SV3_SHIFT (3U)

Definition at line 35823 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV4

#define SNVS_HPSVSR_SV4 ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)

SV4 0b0..No Security Violation 4 security violation was detected. 0b1..Security Violation 4 security violation was detected.

Definition at line 35835 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV4_MASK

#define SNVS_HPSVSR_SV4_MASK (0x10U)

Definition at line 35829 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV4_SHIFT

#define SNVS_HPSVSR_SV4_SHIFT (4U)

Definition at line 35830 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV5

#define SNVS_HPSVSR_SV5 ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)

SV5 0b0..No Security Violation 5 security violation was detected. 0b1..Security Violation 5 security violation was detected.

Definition at line 35842 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV5_MASK

#define SNVS_HPSVSR_SV5_MASK (0x20U)

Definition at line 35836 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SV5_SHIFT

#define SNVS_HPSVSR_SV5_SHIFT (5U)

Definition at line 35837 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_FSV

#define SNVS_HPSVSR_SW_FSV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)

Definition at line 35848 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_FSV_MASK

#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)

Definition at line 35846 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_FSV_SHIFT

#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)

Definition at line 35847 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_LPSV

#define SNVS_HPSVSR_SW_LPSV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)

Definition at line 35851 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_LPSV_MASK

#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)

Definition at line 35849 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_LPSV_SHIFT

#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)

Definition at line 35850 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_SV

#define SNVS_HPSVSR_SW_SV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)

Definition at line 35845 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_SV_MASK

#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)

Definition at line 35843 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_SW_SV_SHIFT

#define SNVS_HPSVSR_SW_SV_SHIFT (13U)

Definition at line 35844 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_ZMK_ECC_FAIL

#define SNVS_HPSVSR_ZMK_ECC_FAIL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)

ZMK_ECC_FAIL 0b0..ZMK ECC Failure was not detected. 0b1..ZMK ECC Failure was detected.

Definition at line 35861 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_ZMK_ECC_FAIL_MASK

#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)

Definition at line 35855 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT

#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)

Definition at line 35856 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_ZMK_SYNDROME

#define SNVS_HPSVSR_ZMK_SYNDROME ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)

Definition at line 35854 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_ZMK_SYNDROME_MASK

#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)

Definition at line 35852 of file MIMXRT1052.h.

◆ SNVS_HPSVSR_ZMK_SYNDROME_SHIFT

#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)

Definition at line 35853 of file MIMXRT1052.h.

◆ SNVS_HPTALR_HPTA_LS

#define SNVS_HPTALR_HPTA_LS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)

Definition at line 35906 of file MIMXRT1052.h.

◆ SNVS_HPTALR_HPTA_LS_MASK

#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)

Definition at line 35904 of file MIMXRT1052.h.

◆ SNVS_HPTALR_HPTA_LS_SHIFT

#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)

Definition at line 35905 of file MIMXRT1052.h.

◆ SNVS_HPTAMR_HPTA_MS

#define SNVS_HPTAMR_HPTA_MS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)

Definition at line 35899 of file MIMXRT1052.h.

◆ SNVS_HPTAMR_HPTA_MS_MASK

#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)

Definition at line 35897 of file MIMXRT1052.h.

◆ SNVS_HPTAMR_HPTA_MS_SHIFT

#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)

Definition at line 35898 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_IP_ID

#define SNVS_HPVIDR1_IP_ID ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)

Definition at line 36362 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_IP_ID_MASK

#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)

Definition at line 36360 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_IP_ID_SHIFT

#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)

Definition at line 36361 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_MAJOR_REV

#define SNVS_HPVIDR1_MAJOR_REV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)

Definition at line 36359 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_MAJOR_REV_MASK

#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)

Definition at line 36357 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_MAJOR_REV_SHIFT

#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)

Definition at line 36358 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_MINOR_REV

#define SNVS_HPVIDR1_MINOR_REV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)

Definition at line 36356 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_MINOR_REV_MASK

#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)

Definition at line 36354 of file MIMXRT1052.h.

◆ SNVS_HPVIDR1_MINOR_REV_SHIFT

#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)

Definition at line 36355 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_CONFIG_OPT

#define SNVS_HPVIDR2_CONFIG_OPT ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)

Definition at line 36369 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_CONFIG_OPT_MASK

#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)

Definition at line 36367 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_CONFIG_OPT_SHIFT

#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)

Definition at line 36368 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_ECO_REV

#define SNVS_HPVIDR2_ECO_REV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)

Definition at line 36372 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_ECO_REV_MASK

#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)

Definition at line 36370 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_ECO_REV_SHIFT

#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)

Definition at line 36371 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_INTG_OPT

#define SNVS_HPVIDR2_INTG_OPT ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)

Definition at line 36375 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_INTG_OPT_MASK

#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)

Definition at line 36373 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_INTG_OPT_SHIFT

#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)

Definition at line 36374 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_IP_ERA

#define SNVS_HPVIDR2_IP_ERA ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)

Definition at line 36378 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_IP_ERA_MASK

#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)

Definition at line 36376 of file MIMXRT1052.h.

◆ SNVS_HPVIDR2_IP_ERA_SHIFT

#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)

Definition at line 36377 of file MIMXRT1052.h.

◆ SNVS_LPCR_BTN_PRESS_TIME

#define SNVS_LPCR_BTN_PRESS_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)

Definition at line 36048 of file MIMXRT1052.h.

◆ SNVS_LPCR_BTN_PRESS_TIME_MASK

#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)

Definition at line 36046 of file MIMXRT1052.h.

◆ SNVS_LPCR_BTN_PRESS_TIME_SHIFT

#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)

Definition at line 36047 of file MIMXRT1052.h.

◆ SNVS_LPCR_DEBOUNCE

#define SNVS_LPCR_DEBOUNCE ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)

Definition at line 36051 of file MIMXRT1052.h.

◆ SNVS_LPCR_DEBOUNCE_MASK

#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)

Definition at line 36049 of file MIMXRT1052.h.

◆ SNVS_LPCR_DEBOUNCE_SHIFT

#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)

Definition at line 36050 of file MIMXRT1052.h.

◆ SNVS_LPCR_DP_EN

#define SNVS_LPCR_DP_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)

DP_EN 0b0..Smart PMIC enabled. 0b1..Dumb PMIC enabled.

Definition at line 36015 of file MIMXRT1052.h.

◆ SNVS_LPCR_DP_EN_MASK

#define SNVS_LPCR_DP_EN_MASK (0x20U)

Definition at line 36009 of file MIMXRT1052.h.

◆ SNVS_LPCR_DP_EN_SHIFT

#define SNVS_LPCR_DP_EN_SHIFT (5U)

Definition at line 36010 of file MIMXRT1052.h.

◆ SNVS_LPCR_GPR_Z_DIS

#define SNVS_LPCR_GPR_Z_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)

Definition at line 36063 of file MIMXRT1052.h.

◆ SNVS_LPCR_GPR_Z_DIS_MASK

#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)

Definition at line 36061 of file MIMXRT1052.h.

◆ SNVS_LPCR_GPR_Z_DIS_SHIFT

#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)

Definition at line 36062 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPCALB_EN

#define SNVS_LPCR_LPCALB_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)

LPCALB_EN 0b0..SRTC Time calibration is disabled. 0b1..SRTC Time calibration is enabled.

Definition at line 36032 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPCALB_EN_MASK

#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)

Definition at line 36026 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPCALB_EN_SHIFT

#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)

Definition at line 36027 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPCALB_VAL

#define SNVS_LPCR_LPCALB_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)

LPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter clock 0b00001..+1 counts per each 32768 ticks of the counter clock 0b00010..+2 counts per each 32768 ticks of the counter clock 0b01111..+15 counts per each 32768 ticks of the counter clock 0b10000..-16 counts per each 32768 ticks of the counter clock 0b10001..-15 counts per each 32768 ticks of the counter clock 0b11110..-2 counts per each 32768 ticks of the counter clock 0b11111..-1 counts per each 32768 ticks of the counter clock

Definition at line 36045 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPCALB_VAL_MASK

#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)

Definition at line 36033 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPCALB_VAL_SHIFT

#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)

Definition at line 36034 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPTA_EN

#define SNVS_LPCR_LPTA_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)

LPTA_EN 0b0..LP time alarm interrupt is disabled. 0b1..LP time alarm interrupt is enabled.

Definition at line 35991 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPTA_EN_MASK

#define SNVS_LPCR_LPTA_EN_MASK (0x2U)

Definition at line 35985 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPTA_EN_SHIFT

#define SNVS_LPCR_LPTA_EN_SHIFT (1U)

Definition at line 35986 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPWUI_EN

#define SNVS_LPCR_LPWUI_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)

Definition at line 36001 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPWUI_EN_MASK

#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)

Definition at line 35999 of file MIMXRT1052.h.

◆ SNVS_LPCR_LPWUI_EN_SHIFT

#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)

Definition at line 36000 of file MIMXRT1052.h.

◆ SNVS_LPCR_MC_ENV

#define SNVS_LPCR_MC_ENV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)

MC_ENV 0b0..MC is disabled or invalid. 0b1..MC is enabled and valid.

Definition at line 35998 of file MIMXRT1052.h.

◆ SNVS_LPCR_MC_ENV_MASK

#define SNVS_LPCR_MC_ENV_MASK (0x4U)

Definition at line 35992 of file MIMXRT1052.h.

◆ SNVS_LPCR_MC_ENV_SHIFT

#define SNVS_LPCR_MC_ENV_SHIFT (2U)

Definition at line 35993 of file MIMXRT1052.h.

◆ SNVS_LPCR_ON_TIME

#define SNVS_LPCR_ON_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)

Definition at line 36054 of file MIMXRT1052.h.

◆ SNVS_LPCR_ON_TIME_MASK

#define SNVS_LPCR_ON_TIME_MASK (0x300000U)

Definition at line 36052 of file MIMXRT1052.h.

◆ SNVS_LPCR_ON_TIME_SHIFT

#define SNVS_LPCR_ON_TIME_SHIFT (20U)

Definition at line 36053 of file MIMXRT1052.h.

◆ SNVS_LPCR_PK_EN

#define SNVS_LPCR_PK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)

Definition at line 36057 of file MIMXRT1052.h.

◆ SNVS_LPCR_PK_EN_MASK

#define SNVS_LPCR_PK_EN_MASK (0x400000U)

Definition at line 36055 of file MIMXRT1052.h.

◆ SNVS_LPCR_PK_EN_SHIFT

#define SNVS_LPCR_PK_EN_SHIFT (22U)

Definition at line 36056 of file MIMXRT1052.h.

◆ SNVS_LPCR_PK_OVERRIDE

#define SNVS_LPCR_PK_OVERRIDE ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)

Definition at line 36060 of file MIMXRT1052.h.

◆ SNVS_LPCR_PK_OVERRIDE_MASK

#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)

Definition at line 36058 of file MIMXRT1052.h.

◆ SNVS_LPCR_PK_OVERRIDE_SHIFT

#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)

Definition at line 36059 of file MIMXRT1052.h.

◆ SNVS_LPCR_PWR_GLITCH_EN

#define SNVS_LPCR_PWR_GLITCH_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)

Definition at line 36025 of file MIMXRT1052.h.

◆ SNVS_LPCR_PWR_GLITCH_EN_MASK

#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)

Definition at line 36023 of file MIMXRT1052.h.

◆ SNVS_LPCR_PWR_GLITCH_EN_SHIFT

#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)

Definition at line 36024 of file MIMXRT1052.h.

◆ SNVS_LPCR_SRTC_ENV

#define SNVS_LPCR_SRTC_ENV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)

SRTC_ENV 0b0..SRTC is disabled or invalid. 0b1..SRTC is enabled and valid.

Definition at line 35984 of file MIMXRT1052.h.

◆ SNVS_LPCR_SRTC_ENV_MASK

#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)

Definition at line 35978 of file MIMXRT1052.h.

◆ SNVS_LPCR_SRTC_ENV_SHIFT

#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)

Definition at line 35979 of file MIMXRT1052.h.

◆ SNVS_LPCR_SRTC_INV_EN

#define SNVS_LPCR_SRTC_INV_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)

SRTC_INV_EN 0b0..SRTC stays valid in the case of security violation. 0b1..SRTC is invalidated in the case of security violation.

Definition at line 36008 of file MIMXRT1052.h.

◆ SNVS_LPCR_SRTC_INV_EN_MASK

#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)

Definition at line 36002 of file MIMXRT1052.h.

◆ SNVS_LPCR_SRTC_INV_EN_SHIFT

#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)

Definition at line 36003 of file MIMXRT1052.h.

◆ SNVS_LPCR_TOP

#define SNVS_LPCR_TOP ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)

TOP 0b0..Leave system power on. 0b1..Turn off system power.

Definition at line 36022 of file MIMXRT1052.h.

◆ SNVS_LPCR_TOP_MASK

#define SNVS_LPCR_TOP_MASK (0x40U)

Definition at line 36016 of file MIMXRT1052.h.

◆ SNVS_LPCR_TOP_SHIFT

#define SNVS_LPCR_TOP_SHIFT (6U)

Definition at line 36017 of file MIMXRT1052.h.

◆ SNVS_LPGPR0_LEGACY_ALIAS_GPR

#define SNVS_LPGPR0_LEGACY_ALIAS_GPR ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)

Definition at line 36319 of file MIMXRT1052.h.

◆ SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK

#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)

Definition at line 36317 of file MIMXRT1052.h.

◆ SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT

#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)

Definition at line 36318 of file MIMXRT1052.h.

◆ SNVS_LPGPR_ALIAS_COUNT

#define SNVS_LPGPR_ALIAS_COUNT (4U)

Definition at line 36340 of file MIMXRT1052.h.

◆ SNVS_LPGPR_ALIAS_GPR

#define SNVS_LPGPR_ALIAS_GPR ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)

Definition at line 36336 of file MIMXRT1052.h.

◆ SNVS_LPGPR_ALIAS_GPR_MASK

#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)

Definition at line 36334 of file MIMXRT1052.h.

◆ SNVS_LPGPR_ALIAS_GPR_SHIFT

#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)

Definition at line 36335 of file MIMXRT1052.h.

◆ SNVS_LPGPR_COUNT

#define SNVS_LPGPR_COUNT (8U)

Definition at line 36350 of file MIMXRT1052.h.

◆ SNVS_LPGPR_GPR

#define SNVS_LPGPR_GPR ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)

Definition at line 36346 of file MIMXRT1052.h.

◆ SNVS_LPGPR_GPR_MASK

#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)

Definition at line 36344 of file MIMXRT1052.h.

◆ SNVS_LPGPR_GPR_SHIFT

#define SNVS_LPGPR_GPR_SHIFT (0U)

Definition at line 36345 of file MIMXRT1052.h.

◆ SNVS_LPLR_GPR_HL

#define SNVS_LPLR_GPR_HL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)

GPR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

Definition at line 35952 of file MIMXRT1052.h.

◆ SNVS_LPLR_GPR_HL_MASK

#define SNVS_LPLR_GPR_HL_MASK (0x20U)

Definition at line 35946 of file MIMXRT1052.h.

◆ SNVS_LPLR_GPR_HL_SHIFT

#define SNVS_LPLR_GPR_HL_SHIFT (5U)

Definition at line 35947 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPCALB_HL

#define SNVS_LPLR_LPCALB_HL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)

LPCALB_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

Definition at line 35938 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPCALB_HL_MASK

#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)

Definition at line 35932 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPCALB_HL_SHIFT

#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)

Definition at line 35933 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPSVCR_HL

#define SNVS_LPLR_LPSVCR_HL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)

LPSVCR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

Definition at line 35959 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPSVCR_HL_MASK

#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)

Definition at line 35953 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPSVCR_HL_SHIFT

#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)

Definition at line 35954 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPTDCR_HL

#define SNVS_LPLR_LPTDCR_HL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)

LPTDCR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

Definition at line 35966 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPTDCR_HL_MASK

#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U)

Definition at line 35960 of file MIMXRT1052.h.

◆ SNVS_LPLR_LPTDCR_HL_SHIFT

#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U)

Definition at line 35961 of file MIMXRT1052.h.

◆ SNVS_LPLR_MC_HL

#define SNVS_LPLR_MC_HL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)

MC_HL 0b0..Write access (increment) is allowed. 0b1..Write access (increment) is not allowed.

Definition at line 35945 of file MIMXRT1052.h.

◆ SNVS_LPLR_MC_HL_MASK

#define SNVS_LPLR_MC_HL_MASK (0x10U)

Definition at line 35939 of file MIMXRT1052.h.

◆ SNVS_LPLR_MC_HL_SHIFT

#define SNVS_LPLR_MC_HL_SHIFT (4U)

Definition at line 35940 of file MIMXRT1052.h.

◆ SNVS_LPLR_MKS_HL

#define SNVS_LPLR_MKS_HL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)

MKS_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

Definition at line 35973 of file MIMXRT1052.h.

◆ SNVS_LPLR_MKS_HL_MASK

#define SNVS_LPLR_MKS_HL_MASK (0x200U)

Definition at line 35967 of file MIMXRT1052.h.

◆ SNVS_LPLR_MKS_HL_SHIFT

#define SNVS_LPLR_MKS_HL_SHIFT (9U)

Definition at line 35968 of file MIMXRT1052.h.

◆ SNVS_LPLR_SRTC_HL

#define SNVS_LPLR_SRTC_HL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)

SRTC_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

Definition at line 35931 of file MIMXRT1052.h.

◆ SNVS_LPLR_SRTC_HL_MASK

#define SNVS_LPLR_SRTC_HL_MASK (0x4U)

Definition at line 35925 of file MIMXRT1052.h.

◆ SNVS_LPLR_SRTC_HL_SHIFT

#define SNVS_LPLR_SRTC_HL_SHIFT (2U)

Definition at line 35926 of file MIMXRT1052.h.

◆ SNVS_LPLR_ZMK_RHL

#define SNVS_LPLR_ZMK_RHL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)

ZMK_RHL 0b0..Read access is allowed (only in software programming mode). 0b1..Read access is not allowed.

Definition at line 35924 of file MIMXRT1052.h.

◆ SNVS_LPLR_ZMK_RHL_MASK

#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)

Definition at line 35918 of file MIMXRT1052.h.

◆ SNVS_LPLR_ZMK_RHL_SHIFT

#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)

Definition at line 35919 of file MIMXRT1052.h.

◆ SNVS_LPLR_ZMK_WHL

#define SNVS_LPLR_ZMK_WHL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)

ZMK_WHL 0b0..Write access is allowed. 0b1..Write access is not allowed.

Definition at line 35917 of file MIMXRT1052.h.

◆ SNVS_LPLR_ZMK_WHL_MASK

#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)

Definition at line 35911 of file MIMXRT1052.h.

◆ SNVS_LPLR_ZMK_WHL_SHIFT

#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)

Definition at line 35912 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_MASTER_KEY_SEL

#define SNVS_LPMKCR_MASTER_KEY_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)

MASTER_KEY_SEL 0b0x..Select one time programmable master key. 0b10..Select zeroizable master key when MKS_EN bit is set . 0b11..Select combined master key when MKS_EN bit is set .

Definition at line 36075 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_MASTER_KEY_SEL_MASK

#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)

Definition at line 36068 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT

#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)

Definition at line 36069 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_ECC_EN

#define SNVS_LPMKCR_ZMK_ECC_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)

ZMK_ECC_EN 0b0..ZMK ECC check is disabled. 0b1..ZMK ECC check is enabled.

Definition at line 36096 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_ECC_EN_MASK

#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)

Definition at line 36090 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_ECC_EN_SHIFT

#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)

Definition at line 36091 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_ECC_VALUE

#define SNVS_LPMKCR_ZMK_ECC_VALUE ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)

Definition at line 36099 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_ECC_VALUE_MASK

#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)

Definition at line 36097 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT

#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)

Definition at line 36098 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_HWP

#define SNVS_LPMKCR_ZMK_HWP ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)

ZMK_HWP 0b0..ZMK is in the software programming mode. 0b1..ZMK is in the hardware programming mode.

Definition at line 36082 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_HWP_MASK

#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)

Definition at line 36076 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_HWP_SHIFT

#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)

Definition at line 36077 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_VAL

#define SNVS_LPMKCR_ZMK_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)

ZMK_VAL 0b0..ZMK is not valid. 0b1..ZMK is valid.

Definition at line 36089 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_VAL_MASK

#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)

Definition at line 36083 of file MIMXRT1052.h.

◆ SNVS_LPMKCR_ZMK_VAL_SHIFT

#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)

Definition at line 36084 of file MIMXRT1052.h.

◆ SNVS_LPPGDR_PGD

#define SNVS_LPPGDR_PGD ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)

Definition at line 36312 of file MIMXRT1052.h.

◆ SNVS_LPPGDR_PGD_MASK

#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)

Definition at line 36310 of file MIMXRT1052.h.

◆ SNVS_LPPGDR_PGD_SHIFT

#define SNVS_LPPGDR_PGD_SHIFT (0U)

Definition at line 36311 of file MIMXRT1052.h.

◆ SNVS_LPSMCLR_MON_COUNTER

#define SNVS_LPSMCLR_MON_COUNTER ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)

Definition at line 36305 of file MIMXRT1052.h.

◆ SNVS_LPSMCLR_MON_COUNTER_MASK

#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)

Definition at line 36303 of file MIMXRT1052.h.

◆ SNVS_LPSMCLR_MON_COUNTER_SHIFT

#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)

Definition at line 36304 of file MIMXRT1052.h.

◆ SNVS_LPSMCMR_MC_ERA_BITS

#define SNVS_LPSMCMR_MC_ERA_BITS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)

Definition at line 36298 of file MIMXRT1052.h.

◆ SNVS_LPSMCMR_MC_ERA_BITS_MASK

#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)

Definition at line 36296 of file MIMXRT1052.h.

◆ SNVS_LPSMCMR_MC_ERA_BITS_SHIFT

#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)

Definition at line 36297 of file MIMXRT1052.h.

◆ SNVS_LPSMCMR_MON_COUNTER

#define SNVS_LPSMCMR_MON_COUNTER ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)

Definition at line 36295 of file MIMXRT1052.h.

◆ SNVS_LPSMCMR_MON_COUNTER_MASK

#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)

Definition at line 36293 of file MIMXRT1052.h.

◆ SNVS_LPSMCMR_MON_COUNTER_SHIFT

#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)

Definition at line 36294 of file MIMXRT1052.h.

◆ SNVS_LPSR_EO

#define SNVS_LPSR_EO ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)

EO 0b0..Emergency off was not detected. 0b1..Emergency off was detected.

Definition at line 36239 of file MIMXRT1052.h.

◆ SNVS_LPSR_EO_MASK

#define SNVS_LPSR_EO_MASK (0x20000U)

Definition at line 36233 of file MIMXRT1052.h.

◆ SNVS_LPSR_EO_SHIFT

#define SNVS_LPSR_EO_SHIFT (17U)

Definition at line 36234 of file MIMXRT1052.h.

◆ SNVS_LPSR_ESVD

#define SNVS_LPSR_ESVD ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)

ESVD 0b0..No external security violation. 0b1..External security violation is detected.

Definition at line 36232 of file MIMXRT1052.h.

◆ SNVS_LPSR_ESVD_MASK

#define SNVS_LPSR_ESVD_MASK (0x10000U)

Definition at line 36226 of file MIMXRT1052.h.

◆ SNVS_LPSR_ESVD_SHIFT

#define SNVS_LPSR_ESVD_SHIFT (16U)

Definition at line 36227 of file MIMXRT1052.h.

◆ SNVS_LPSR_ET1D

#define SNVS_LPSR_ET1D ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)

ET1D 0b0..External tampering 1 not detected. 0b1..External tampering 1 detected.

Definition at line 36225 of file MIMXRT1052.h.

◆ SNVS_LPSR_ET1D_MASK

#define SNVS_LPSR_ET1D_MASK (0x200U)

Definition at line 36219 of file MIMXRT1052.h.

◆ SNVS_LPSR_ET1D_SHIFT

#define SNVS_LPSR_ET1D_SHIFT (9U)

Definition at line 36220 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPNS

#define SNVS_LPSR_LPNS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)

LPNS 0b0..LP section was not programmed in the non-secure state. 0b1..LP section was programmed in the non-secure state.

Definition at line 36260 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPNS_MASK

#define SNVS_LPSR_LPNS_MASK (0x40000000U)

Definition at line 36254 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPNS_SHIFT

#define SNVS_LPSR_LPNS_SHIFT (30U)

Definition at line 36255 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPS

#define SNVS_LPSR_LPS ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)

LPS 0b0..LP section was not programmed in secure or trusted state. 0b1..LP section was programmed in secure or trusted state.

Definition at line 36267 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPS_MASK

#define SNVS_LPSR_LPS_MASK (0x80000000U)

Definition at line 36261 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPS_SHIFT

#define SNVS_LPSR_LPS_SHIFT (31U)

Definition at line 36262 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPTA

#define SNVS_LPSR_LPTA ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)

LPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

Definition at line 36201 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPTA_MASK

#define SNVS_LPSR_LPTA_MASK (0x1U)

Definition at line 36195 of file MIMXRT1052.h.

◆ SNVS_LPSR_LPTA_SHIFT

#define SNVS_LPSR_LPTA_SHIFT (0U)

Definition at line 36196 of file MIMXRT1052.h.

◆ SNVS_LPSR_MCR

#define SNVS_LPSR_MCR ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)

MCR 0b0..MC has not reached its maximum value. 0b1..MC has reached its maximum value.

Definition at line 36215 of file MIMXRT1052.h.

◆ SNVS_LPSR_MCR_MASK

#define SNVS_LPSR_MCR_MASK (0x4U)

Definition at line 36209 of file MIMXRT1052.h.

◆ SNVS_LPSR_MCR_SHIFT

#define SNVS_LPSR_MCR_SHIFT (2U)

Definition at line 36210 of file MIMXRT1052.h.

◆ SNVS_LPSR_PGD

#define SNVS_LPSR_PGD ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)

Definition at line 36218 of file MIMXRT1052.h.

◆ SNVS_LPSR_PGD_MASK

#define SNVS_LPSR_PGD_MASK (0x8U)

Definition at line 36216 of file MIMXRT1052.h.

◆ SNVS_LPSR_PGD_SHIFT

#define SNVS_LPSR_PGD_SHIFT (3U)

Definition at line 36217 of file MIMXRT1052.h.

◆ SNVS_LPSR_SED

#define SNVS_LPSR_SED ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)

SED 0b0..Scan exit was not detected. 0b1..Scan exit was detected.

Definition at line 36253 of file MIMXRT1052.h.

◆ SNVS_LPSR_SED_MASK

#define SNVS_LPSR_SED_MASK (0x100000U)

Definition at line 36247 of file MIMXRT1052.h.

◆ SNVS_LPSR_SED_SHIFT

#define SNVS_LPSR_SED_SHIFT (20U)

Definition at line 36248 of file MIMXRT1052.h.

◆ SNVS_LPSR_SPO

#define SNVS_LPSR_SPO ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)

SPO 0b0..Set Power Off was not detected. 0b1..Set Power Off was detected.

Definition at line 36246 of file MIMXRT1052.h.

◆ SNVS_LPSR_SPO_MASK

#define SNVS_LPSR_SPO_MASK (0x40000U)

Definition at line 36240 of file MIMXRT1052.h.

◆ SNVS_LPSR_SPO_SHIFT

#define SNVS_LPSR_SPO_SHIFT (18U)

Definition at line 36241 of file MIMXRT1052.h.

◆ SNVS_LPSR_SRTCR

#define SNVS_LPSR_SRTCR ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)

SRTCR 0b0..SRTC has not reached its maximum value. 0b1..SRTC has reached its maximum value.

Definition at line 36208 of file MIMXRT1052.h.

◆ SNVS_LPSR_SRTCR_MASK

#define SNVS_LPSR_SRTCR_MASK (0x2U)

Definition at line 36202 of file MIMXRT1052.h.

◆ SNVS_LPSR_SRTCR_SHIFT

#define SNVS_LPSR_SRTCR_SHIFT (1U)

Definition at line 36203 of file MIMXRT1052.h.

◆ SNVS_LPSRTCLR_SRTC

#define SNVS_LPSRTCLR_SRTC ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)

Definition at line 36281 of file MIMXRT1052.h.

◆ SNVS_LPSRTCLR_SRTC_MASK

#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)

Definition at line 36279 of file MIMXRT1052.h.

◆ SNVS_LPSRTCLR_SRTC_SHIFT

#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)

Definition at line 36280 of file MIMXRT1052.h.

◆ SNVS_LPSRTCMR_SRTC

#define SNVS_LPSRTCMR_SRTC ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)

Definition at line 36274 of file MIMXRT1052.h.

◆ SNVS_LPSRTCMR_SRTC_MASK

#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)

Definition at line 36272 of file MIMXRT1052.h.

◆ SNVS_LPSRTCMR_SRTC_SHIFT

#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)

Definition at line 36273 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV0_EN

#define SNVS_LPSVCR_SV0_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)

SV0_EN 0b0..Security Violation 0 is disabled in the LP domain. 0b1..Security Violation 0 is enabled in the LP domain.

Definition at line 36110 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV0_EN_MASK

#define SNVS_LPSVCR_SV0_EN_MASK (0x1U)

Definition at line 36104 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV0_EN_SHIFT

#define SNVS_LPSVCR_SV0_EN_SHIFT (0U)

Definition at line 36105 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV1_EN

#define SNVS_LPSVCR_SV1_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)

SV1_EN 0b0..Security Violation 1 is disabled in the LP domain. 0b1..Security Violation 1 is enabled in the LP domain.

Definition at line 36117 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV1_EN_MASK

#define SNVS_LPSVCR_SV1_EN_MASK (0x2U)

Definition at line 36111 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV1_EN_SHIFT

#define SNVS_LPSVCR_SV1_EN_SHIFT (1U)

Definition at line 36112 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV2_EN

#define SNVS_LPSVCR_SV2_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)

SV2_EN 0b0..Security Violation 2 is disabled in the LP domain. 0b1..Security Violation 2 is enabled in the LP domain.

Definition at line 36124 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV2_EN_MASK

#define SNVS_LPSVCR_SV2_EN_MASK (0x4U)

Definition at line 36118 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV2_EN_SHIFT

#define SNVS_LPSVCR_SV2_EN_SHIFT (2U)

Definition at line 36119 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV3_EN

#define SNVS_LPSVCR_SV3_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)

SV3_EN 0b0..Security Violation 3 is disabled in the LP domain. 0b1..Security Violation 3 is enabled in the LP domain.

Definition at line 36131 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV3_EN_MASK

#define SNVS_LPSVCR_SV3_EN_MASK (0x8U)

Definition at line 36125 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV3_EN_SHIFT

#define SNVS_LPSVCR_SV3_EN_SHIFT (3U)

Definition at line 36126 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV4_EN

#define SNVS_LPSVCR_SV4_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)

SV4_EN 0b0..Security Violation 4 is disabled in the LP domain. 0b1..Security Violation 4 is enabled in the LP domain.

Definition at line 36138 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV4_EN_MASK

#define SNVS_LPSVCR_SV4_EN_MASK (0x10U)

Definition at line 36132 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV4_EN_SHIFT

#define SNVS_LPSVCR_SV4_EN_SHIFT (4U)

Definition at line 36133 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV5_EN

#define SNVS_LPSVCR_SV5_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)

SV5_EN 0b0..Security Violation 5 is disabled in the LP domain. 0b1..Security Violation 5 is enabled in the LP domain.

Definition at line 36145 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV5_EN_MASK

#define SNVS_LPSVCR_SV5_EN_MASK (0x20U)

Definition at line 36139 of file MIMXRT1052.h.

◆ SNVS_LPSVCR_SV5_EN_SHIFT

#define SNVS_LPSVCR_SV5_EN_SHIFT (5U)

Definition at line 36140 of file MIMXRT1052.h.

◆ SNVS_LPTAR_LPTA

#define SNVS_LPTAR_LPTA ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)

Definition at line 36288 of file MIMXRT1052.h.

◆ SNVS_LPTAR_LPTA_MASK

#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)

Definition at line 36286 of file MIMXRT1052.h.

◆ SNVS_LPTAR_LPTA_SHIFT

#define SNVS_LPTAR_LPTA_SHIFT (0U)

Definition at line 36287 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_ET1_EN

#define SNVS_LPTDCR_ET1_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)

ET1_EN 0b0..External tamper 1 is disabled. 0b1..External tamper 1 is enabled.

Definition at line 36170 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_ET1_EN_MASK

#define SNVS_LPTDCR_ET1_EN_MASK (0x200U)

Definition at line 36164 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_ET1_EN_SHIFT

#define SNVS_LPTDCR_ET1_EN_SHIFT (9U)

Definition at line 36165 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_ET1P

#define SNVS_LPTDCR_ET1P ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)

ET1P 0b0..External tamper 1 is active low. 0b1..External tamper 1 is active high.

Definition at line 36177 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_ET1P_MASK

#define SNVS_LPTDCR_ET1P_MASK (0x800U)

Definition at line 36171 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_ET1P_SHIFT

#define SNVS_LPTDCR_ET1P_SHIFT (11U)

Definition at line 36172 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_MCR_EN

#define SNVS_LPTDCR_MCR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)

MCR_EN 0b0..MC rollover is disabled. 0b1..MC rollover is enabled.

Definition at line 36163 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_MCR_EN_MASK

#define SNVS_LPTDCR_MCR_EN_MASK (0x4U)

Definition at line 36157 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_MCR_EN_SHIFT

#define SNVS_LPTDCR_MCR_EN_SHIFT (2U)

Definition at line 36158 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_OSCB

#define SNVS_LPTDCR_OSCB ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)

OSCB 0b0..Normal SRTC clock oscillator not bypassed. 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.

Definition at line 36190 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_OSCB_MASK

#define SNVS_LPTDCR_OSCB_MASK (0x10000000U)

Definition at line 36184 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_OSCB_SHIFT

#define SNVS_LPTDCR_OSCB_SHIFT (28U)

Definition at line 36185 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_PFD_OBSERV

#define SNVS_LPTDCR_PFD_OBSERV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)

Definition at line 36180 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_PFD_OBSERV_MASK

#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)

Definition at line 36178 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_PFD_OBSERV_SHIFT

#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)

Definition at line 36179 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_POR_OBSERV

#define SNVS_LPTDCR_POR_OBSERV ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)

Definition at line 36183 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_POR_OBSERV_MASK

#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)

Definition at line 36181 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_POR_OBSERV_SHIFT

#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)

Definition at line 36182 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_SRTCR_EN

#define SNVS_LPTDCR_SRTCR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)

SRTCR_EN 0b0..SRTC rollover is disabled. 0b1..SRTC rollover is enabled.

Definition at line 36156 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_SRTCR_EN_MASK

#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)

Definition at line 36150 of file MIMXRT1052.h.

◆ SNVS_LPTDCR_SRTCR_EN_SHIFT

#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)

Definition at line 36151 of file MIMXRT1052.h.

◆ SNVS_LPZMKR_COUNT

#define SNVS_LPZMKR_COUNT (8U)

Definition at line 36330 of file MIMXRT1052.h.

◆ SNVS_LPZMKR_ZMK

#define SNVS_LPZMKR_ZMK ( x ) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)

Definition at line 36326 of file MIMXRT1052.h.

◆ SNVS_LPZMKR_ZMK_MASK

#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)

Definition at line 36324 of file MIMXRT1052.h.

◆ SNVS_LPZMKR_ZMK_SHIFT

#define SNVS_LPZMKR_ZMK_SHIFT (0U)

Definition at line 36325 of file MIMXRT1052.h.

Macros

HPLR - SNVS_HP Lock Register

HPCOMR - SNVS_HP Command Register

HPCR - SNVS_HP Control Register

HPSICR - SNVS_HP Security Interrupt Control Register

HPSVCR - SNVS_HP Security Violation Control Register

HPSR - SNVS_HP Status Register

HPSVSR - SNVS_HP Security Violation Status Register

HPHACIVR - SNVS_HP High Assurance Counter IV Register

HPHACR - SNVS_HP High Assurance Counter Register

HPRTCMR - SNVS_HP Real Time Counter MSB Register

HPRTCLR - SNVS_HP Real Time Counter LSB Register

HPTAMR - SNVS_HP Time Alarm MSB Register

HPTALR - SNVS_HP Time Alarm LSB Register

LPLR - SNVS_LP Lock Register

LPCR - SNVS_LP Control Register

LPMKCR - SNVS_LP Master Key Control Register

LPSVCR - SNVS_LP Security Violation Control Register

LPTDCR - SNVS_LP Tamper Detectors Configuration Register

LPSR - SNVS_LP Status Register

LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register

LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register

LPTAR - SNVS_LP Time Alarm Register

LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register

LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register

LPPGDR - SNVS_LP Power Glitch Detector Register

LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias)

LPZMKR - SNVS_LP Zeroizable Master Key Register

LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3

LPGPR - SNVS_LP General Purpose Registers 0 .. 7

HPVIDR1 - SNVS_HP Version ID Register 1

HPVIDR2 - SNVS_HP Version ID Register 2