Iomuxc_pads

Collaboration diagram for Iomuxc_pads:

Modules
	Device Peripheral Access Layer
	Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
	SDK Compatibility

Typedefs
typedef enum _iomuxc_select_input	iomuxc_select_input_t
	Enumeration for the IOMUXC select input. More...
typedef enum _iomuxc_sw_mux_ctl_pad	iomuxc_sw_mux_ctl_pad_t
	Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...
typedef enum _iomuxc_sw_pad_ctl_pad	iomuxc_sw_pad_ctl_pad_t
	Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...
typedef enum _xbar_input_signal	xbar_input_signal_t
typedef enum _xbar_output_signal	xbar_output_signal_t

Enumerations
enum	_iomuxc_select_input {   kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U,   kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U,   kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U,   kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U,   kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U,   kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U,   kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U,   kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U,   kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U,   kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U,   kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U,   kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U,   kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U,   kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U,   kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U,   kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U,   kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U,   kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U,   kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U,   kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U,   kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U,   kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U,   kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U,   kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, kIOMUXC_NMI_SELECT_INPUT = 93U, kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U,   kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U,   kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U,   kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U,   kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U,   kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U,   kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U,   kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U,   kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U,   kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U,   kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U,   kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U,   kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U,   kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U,   kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U,   kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U }
	Enumeration for the IOMUXC select input. More...
enum	_iomuxc_sw_mux_ctl_pad {   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U }
	Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...
enum	_iomuxc_sw_pad_ctl_pad {   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U }
	Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...
enum	_xbar_input_signal {   kXBARA1_InputLogicLow = 0|0x100U, kXBARA1_InputLogicHigh = 1|0x100U, kXBARA1_InputIomuxXbarIn02 = 2|0x100U, kXBARA1_InputIomuxXbarIn03 = 3|0x100U,   kXBARA1_InputIomuxXbarInout04 = 4|0x100U, kXBARA1_InputIomuxXbarInout05 = 5|0x100U, kXBARA1_InputIomuxXbarInout06 = 6|0x100U, kXBARA1_InputIomuxXbarInout07 = 7|0x100U,   kXBARA1_InputIomuxXbarInout08 = 8|0x100U, kXBARA1_InputIomuxXbarInout09 = 9|0x100U, kXBARA1_InputIomuxXbarInout10 = 10|0x100U, kXBARA1_InputIomuxXbarInout11 = 11|0x100U,   kXBARA1_InputIomuxXbarInout12 = 12|0x100U, kXBARA1_InputIomuxXbarInout13 = 13|0x100U, kXBARA1_InputIomuxXbarInout14 = 14|0x100U, kXBARA1_InputIomuxXbarInout15 = 15|0x100U,   kXBARA1_InputIomuxXbarInout16 = 16|0x100U, kXBARA1_InputIomuxXbarInout17 = 17|0x100U, kXBARA1_InputIomuxXbarInout18 = 18|0x100U, kXBARA1_InputIomuxXbarInout19 = 19|0x100U,   kXBARA1_InputIomuxXbarIn20 = 20|0x100U, kXBARA1_InputIomuxXbarIn21 = 21|0x100U, kXBARA1_InputIomuxXbarIn22 = 22|0x100U, kXBARA1_InputIomuxXbarIn23 = 23|0x100U,   kXBARA1_InputIomuxXbarIn24 = 24|0x100U, kXBARA1_InputIomuxXbarIn25 = 25|0x100U, kXBARA1_InputAcmp1Out = 26|0x100U, kXBARA1_InputAcmp2Out = 27|0x100U,   kXBARA1_InputAcmp3Out = 28|0x100U, kXBARA1_InputAcmp4Out = 29|0x100U, kXBARA1_InputRESERVED30 = 30|0x100U, kXBARA1_InputRESERVED31 = 31|0x100U,   kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, kXBARA1_InputQtimer3Tmr3Output = 35|0x100U,   kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, kXBARA1_InputQtimer4Tmr3Output = 39|0x100U,   kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U,   kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U,   kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U,   kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U,   kXBARA1_InputPitTrigger0 = 56|0x100U, kXBARA1_InputPitTrigger1 = 57|0x100U, kXBARA1_InputPitTrigger2 = 58|0x100U, kXBARA1_InputPitTrigger3 = 59|0x100U,   kXBARA1_InputEnc1PosMatch = 60|0x100U, kXBARA1_InputEnc2PosMatch = 61|0x100U, kXBARA1_InputEnc3PosMatch = 62|0x100U, kXBARA1_InputEnc4PosMatch = 63|0x100U,   kXBARA1_InputDmaDone0 = 64|0x100U, kXBARA1_InputDmaDone1 = 65|0x100U, kXBARA1_InputDmaDone2 = 66|0x100U, kXBARA1_InputDmaDone3 = 67|0x100U,   kXBARA1_InputDmaDone4 = 68|0x100U, kXBARA1_InputDmaDone5 = 69|0x100U, kXBARA1_InputDmaDone6 = 70|0x100U, kXBARA1_InputDmaDone7 = 71|0x100U,   kXBARA1_InputAoi1Out0 = 72|0x100U, kXBARA1_InputAoi1Out1 = 73|0x100U, kXBARA1_InputAoi1Out2 = 74|0x100U, kXBARA1_InputAoi1Out3 = 75|0x100U,   kXBARA1_InputAoi2Out0 = 76|0x100U, kXBARA1_InputAoi2Out1 = 77|0x100U, kXBARA1_InputAoi2Out2 = 78|0x100U, kXBARA1_InputAoi2Out3 = 79|0x100U,   kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U,   kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U,   kXBARB2_InputLogicLow = 0|0x200U, kXBARB2_InputLogicHigh = 1|0x200U, kXBARB2_InputRESERVED2 = 2|0x200U, kXBARB2_InputRESERVED3 = 3|0x200U,   kXBARB2_InputRESERVED4 = 4|0x200U, kXBARB2_InputRESERVED5 = 5|0x200U, kXBARB2_InputAcmp1Out = 6|0x200U, kXBARB2_InputAcmp2Out = 7|0x200U,   kXBARB2_InputAcmp3Out = 8|0x200U, kXBARB2_InputAcmp4Out = 9|0x200U, kXBARB2_InputRESERVED10 = 10|0x200U, kXBARB2_InputRESERVED11 = 11|0x200U,   kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, kXBARB2_InputQtimer3Tmr3Output = 15|0x200U,   kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, kXBARB2_InputQtimer4Tmr3Output = 19|0x200U,   kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U,   kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U,   kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U,   kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U,   kXBARB2_InputPitTrigger0 = 36|0x200U, kXBARB2_InputPitTrigger1 = 37|0x200U, kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U,   kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U,   kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, kXBARB2_InputEnc1PosMatch = 46|0x200U, kXBARB2_InputEnc2PosMatch = 47|0x200U,   kXBARB2_InputEnc3PosMatch = 48|0x200U, kXBARB2_InputEnc4PosMatch = 49|0x200U, kXBARB2_InputDmaDone0 = 50|0x200U, kXBARB2_InputDmaDone1 = 51|0x200U,   kXBARB2_InputDmaDone2 = 52|0x200U, kXBARB2_InputDmaDone3 = 53|0x200U, kXBARB2_InputDmaDone4 = 54|0x200U, kXBARB2_InputDmaDone5 = 55|0x200U,   kXBARB2_InputDmaDone6 = 56|0x200U, kXBARB2_InputDmaDone7 = 57|0x200U, kXBARB3_InputLogicLow = 0|0x300U, kXBARB3_InputLogicHigh = 1|0x300U,   kXBARB3_InputRESERVED2 = 2|0x300U, kXBARB3_InputRESERVED3 = 3|0x300U, kXBARB3_InputRESERVED4 = 4|0x300U, kXBARB3_InputRESERVED5 = 5|0x300U,   kXBARB3_InputAcmp1Out = 6|0x300U, kXBARB3_InputAcmp2Out = 7|0x300U, kXBARB3_InputAcmp3Out = 8|0x300U, kXBARB3_InputAcmp4Out = 9|0x300U,   kXBARB3_InputRESERVED10 = 10|0x300U, kXBARB3_InputRESERVED11 = 11|0x300U, kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, kXBARB3_InputQtimer3Tmr1Output = 13|0x300U,   kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, kXBARB3_InputQtimer4Tmr1Output = 17|0x300U,   kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U,   kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U,   kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U,   kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U,   kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, kXBARB3_InputPitTrigger0 = 36|0x300U, kXBARB3_InputPitTrigger1 = 37|0x300U,   kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U,   kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U,   kXBARB3_InputEnc1PosMatch = 46|0x300U, kXBARB3_InputEnc2PosMatch = 47|0x300U, kXBARB3_InputEnc3PosMatch = 48|0x300U, kXBARB3_InputEnc4PosMatch = 49|0x300U,   kXBARB3_InputDmaDone0 = 50|0x300U, kXBARB3_InputDmaDone1 = 51|0x300U, kXBARB3_InputDmaDone2 = 52|0x300U, kXBARB3_InputDmaDone3 = 53|0x300U,   kXBARB3_InputDmaDone4 = 54|0x300U, kXBARB3_InputDmaDone5 = 55|0x300U, kXBARB3_InputDmaDone6 = 56|0x300U, kXBARB3_InputDmaDone7 = 57|0x300U }
enum	_xbar_output_signal {   kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, kXBARA1_OutputDmaChMuxReq95 = 3|0x100U,   kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, kXBARA1_OutputIomuxXbarInout07 = 7|0x100U,   kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, kXBARA1_OutputIomuxXbarInout11 = 11|0x100U,   kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, kXBARA1_OutputIomuxXbarInout15 = 15|0x100U,   kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, kXBARA1_OutputIomuxXbarInout19 = 19|0x100U,   kXBARA1_OutputAcmp1Sample = 20|0x100U, kXBARA1_OutputAcmp2Sample = 21|0x100U, kXBARA1_OutputAcmp3Sample = 22|0x100U, kXBARA1_OutputAcmp4Sample = 23|0x100U,   kXBARA1_OutputRESERVED24 = 24|0x100U, kXBARA1_OutputRESERVED25 = 25|0x100U, kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U,   kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U,   kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U,   kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U,   kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U,   kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U,   kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U,   kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U,   kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U,   kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U,   kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, kXBARA1_OutputEnc1PhaseBInput = 67|0x100U,   kXBARA1_OutputEnc1Index = 68|0x100U, kXBARA1_OutputEnc1Home = 69|0x100U, kXBARA1_OutputEnc1Trigger = 70|0x100U, kXBARA1_OutputEnc2PhaseAInput = 71|0x100U,   kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, kXBARA1_OutputEnc2Index = 73|0x100U, kXBARA1_OutputEnc2Home = 74|0x100U, kXBARA1_OutputEnc2Trigger = 75|0x100U,   kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, kXBARA1_OutputEnc3Index = 78|0x100U, kXBARA1_OutputEnc3Home = 79|0x100U,   kXBARA1_OutputEnc3Trigger = 80|0x100U, kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, kXBARA1_OutputEnc4Index = 83|0x100U,   kXBARA1_OutputEnc4Home = 84|0x100U, kXBARA1_OutputEnc4Trigger = 85|0x100U, kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U,   kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U,   kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U,   kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U,   kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, kXBARA1_OutputEwmEwmIn = 102|0x100U, kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U,   kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U,   kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, kXBARA1_OutputLpi2c1TrgInput = 111|0x100U,   kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, kXBARA1_OutputLpspi1TrgInput = 115|0x100U,   kXBARA1_OutputLpspi2TrgInput = 116|0x100U, kXBARA1_OutputLpspi3TrgInput = 117|0x100U, kXBARA1_OutputLpspi4TrgInput = 118|0x100U, kXBARA1_OutputLpuart1TrgInput = 119|0x100U,   kXBARA1_OutputLpuart2TrgInput = 120|0x100U, kXBARA1_OutputLpuart3TrgInput = 121|0x100U, kXBARA1_OutputLpuart4TrgInput = 122|0x100U, kXBARA1_OutputLpuart5TrgInput = 123|0x100U,   kXBARA1_OutputLpuart6TrgInput = 124|0x100U, kXBARA1_OutputLpuart7TrgInput = 125|0x100U, kXBARA1_OutputLpuart8TrgInput = 126|0x100U, kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,   kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, kXBARB2_OutputAoi1In00 = 0|0x200U,   kXBARB2_OutputAoi1In01 = 1|0x200U, kXBARB2_OutputAoi1In02 = 2|0x200U, kXBARB2_OutputAoi1In03 = 3|0x200U, kXBARB2_OutputAoi1In04 = 4|0x200U,   kXBARB2_OutputAoi1In05 = 5|0x200U, kXBARB2_OutputAoi1In06 = 6|0x200U, kXBARB2_OutputAoi1In07 = 7|0x200U, kXBARB2_OutputAoi1In08 = 8|0x200U,   kXBARB2_OutputAoi1In09 = 9|0x200U, kXBARB2_OutputAoi1In10 = 10|0x200U, kXBARB2_OutputAoi1In11 = 11|0x200U, kXBARB2_OutputAoi1In12 = 12|0x200U,   kXBARB2_OutputAoi1In13 = 13|0x200U, kXBARB2_OutputAoi1In14 = 14|0x200U, kXBARB2_OutputAoi1In15 = 15|0x200U, kXBARB3_OutputAoi2In00 = 0|0x300U,   kXBARB3_OutputAoi2In01 = 1|0x300U, kXBARB3_OutputAoi2In02 = 2|0x300U, kXBARB3_OutputAoi2In03 = 3|0x300U, kXBARB3_OutputAoi2In04 = 4|0x300U,   kXBARB3_OutputAoi2In05 = 5|0x300U, kXBARB3_OutputAoi2In06 = 6|0x300U, kXBARB3_OutputAoi2In07 = 7|0x300U, kXBARB3_OutputAoi2In08 = 8|0x300U,   kXBARB3_OutputAoi2In09 = 9|0x300U, kXBARB3_OutputAoi2In10 = 10|0x300U, kXBARB3_OutputAoi2In11 = 11|0x300U, kXBARB3_OutputAoi2In12 = 12|0x300U,   kXBARB3_OutputAoi2In13 = 13|0x300U, kXBARB3_OutputAoi2In14 = 14|0x300U, kXBARB3_OutputAoi2In15 = 15|0x300U }

Variables
union {
__IO uint32_t   DMA_Type::NBYTES_MLNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFYES
}
union {
__IO uint16_t   DMA_Type::CITER_ELINKNO
__IO uint16_t   DMA_Type::CITER_ELINKYES
}
union {
__IO uint16_t   DMA_Type::BITER_ELINKNO
__IO uint16_t   DMA_Type::BITER_ELINKYES
}
union {
__O uint32_t   SPDIF_Type::SIC
__I uint32_t   SPDIF_Type::SIS
};
union {
__IO uint32_t   TRNG_Type::PKRMAX
__I uint32_t   TRNG_Type::PKRSQ
};
union {
__IO uint32_t   TRNG_Type::SBLIM
__I uint32_t   TRNG_Type::TOTSAM
};
union {
__I uint32_t   TRNG_Type::FRQCNT
__IO uint32_t   TRNG_Type::FRQMAX
};
union {
__I uint32_t   TRNG_Type::SCMC
__IO uint32_t   TRNG_Type::SCML
};
union {
__I uint32_t   TRNG_Type::SCR1C
__IO uint32_t   TRNG_Type::SCR1L
};
union {
__I uint32_t   TRNG_Type::SCR2C
__IO uint32_t   TRNG_Type::SCR2L
};
union {
__I uint32_t   TRNG_Type::SCR3C
__IO uint32_t   TRNG_Type::SCR3L
};
union {
__I uint32_t   TRNG_Type::SCR4C
__IO uint32_t   TRNG_Type::SCR4L
};
union {
__I uint32_t   TRNG_Type::SCR5C
__IO uint32_t   TRNG_Type::SCR5L
};
union {
__I uint32_t   TRNG_Type::SCR6PC
__IO uint32_t   TRNG_Type::SCR6PL
};
union {
__IO uint32_t   USB_Type::DEVICEADDR
__IO uint32_t   USB_Type::PERIODICLISTBASE
};
union {
__IO uint32_t   USB_Type::ASYNCLISTADDR
__IO uint32_t   USB_Type::ENDPTLISTADDR
};
__IO uint32_t	BEE_Type::ADDR_OFFSET0
__IO uint32_t	BEE_Type::ADDR_OFFSET1
__I uint32_t	USDHC_Type::ADMA_ERR_STATUS
__IO uint32_t	USDHC_Type::ADMA_SYS_ADDR
__IO uint32_t	BEE_Type::AES_KEY0_W0
__IO uint32_t	BEE_Type::AES_KEY0_W1
__IO uint32_t	BEE_Type::AES_KEY0_W2
__IO uint32_t	BEE_Type::AES_KEY0_W3
__IO uint32_t	FLEXSPI_Type::AHBCR
__IO uint32_t	FLEXSPI_Type::AHBRXBUFCR0 [4]
__I uint32_t	FLEXSPI_Type::AHBSPNDSTS
__IO uint32_t	OCOTP_Type::ANA0
__IO uint32_t	OCOTP_Type::ANA1
__IO uint32_t	OCOTP_Type::ANA2
__IO uint32_t	PXP_Type::AS_BUF
__IO uint32_t	PXP_Type::AS_CLRKEYHIGH
__IO uint32_t	PXP_Type::AS_CLRKEYLOW
__IO uint32_t	PXP_Type::AS_CTRL
__IO uint32_t	PXP_Type::AS_PITCH
__IO uint32_t   USB_Type::ASYNCLISTADDR
__IO uint32_t	ENET_Type::ATCOR
__IO uint32_t	ENET_Type::ATCR
__IO uint32_t	ENET_Type::ATINC
__IO uint32_t	ENET_Type::ATOFF
__IO uint32_t	ENET_Type::ATPER
__I uint32_t	ENET_Type::ATSTMP
__IO uint16_t   DMA_Type::ATTR
__IO uint32_t	ENET_Type::ATVR
__IO uint32_t	USDHC_Type::AUTOCMD12_ERR_STATUS
__IO uint32_t	TSC_Type::BASIC_SETTING
__IO uint32_t	LPUART_Type::BAUD
struct {
__IO uint16_t   AOI_Type::BFCRT01
__IO uint16_t   AOI_Type::BFCRT23
}	AOI_Type::BFCRT [4]
__IO uint16_t   AOI_Type::BFCRT01
__IO uint16_t   AOI_Type::BFCRT23
__IO uint16_t   DMA_Type::BITER_ELINKNO
__IO uint16_t   DMA_Type::BITER_ELINKYES
__IO uint32_t	USDHC_Type::BLK_ATT
__IO uint32_t	LCDIF_Type::BM_ERROR_STAT
__IO uint32_t	SEMC_Type::BMCR0
__IO uint32_t	SEMC_Type::BMCR1
__IO uint32_t	SEMC_Type::BR [9]
__IO uint32_t	USB_Type::BURSTSIZE
__IO uint32_t	CCM_Type::CACRR
__IO uint32_t	ADC_Type::CAL
__IO uint32_t	DCP_Type::CAPABILITY0
__I uint32_t	DCP_Type::CAPABILITY1
__I uint8_t	USB_Type::CAPLENGTH
__IO uint16_t   TMR_Type::CAPT
__IO uint16_t   PWM_Type::CAPTCOMPA
__IO uint16_t   PWM_Type::CAPTCOMPB
__IO uint16_t   PWM_Type::CAPTCOMPX
__IO uint16_t   PWM_Type::CAPTCTRLA
__IO uint16_t   PWM_Type::CAPTCTRLB
__IO uint16_t   PWM_Type::CAPTCTRLX
__IO uint32_t	CCM_Type::CBCDR
__IO uint32_t	CCM_Type::CBCMR
__IO uint32_t	CCM_Type::CCGR0
__IO uint32_t	CCM_Type::CCGR1
__IO uint32_t	CCM_Type::CCGR2
__IO uint32_t	CCM_Type::CCGR3
__IO uint32_t	CCM_Type::CCGR4
__IO uint32_t	CCM_Type::CCGR5
__IO uint32_t	CCM_Type::CCGR6
__IO uint32_t	CCM_Type::CCOSR
__IO uint32_t	CCM_Type::CCR
__IO uint32_t	LPSPI_Type::CCR
__IO uint32_t	CCM_Type::CCSR
__IO uint32_t	CCM_Type::CDCDR
__I uint32_t	CCM_Type::CDHIPR
__O uint8_t	DMA_Type::CDNE
__O uint8_t	DMA_Type::CEEI
__O uint8_t	DMA_Type::CERQ
__O uint8_t	DMA_Type::CERR
__IO uint32_t	ADC_Type::CFG
__IO uint32_t	OCOTP_Type::CFG0
__IO uint32_t	OCOTP_Type::CFG1
__IO uint32_t	OCOTP_Type::CFG2
__IO uint32_t	OCOTP_Type::CFG3
__IO uint32_t	OCOTP_Type::CFG4
__IO uint32_t	OCOTP_Type::CFG5
__IO uint32_t	OCOTP_Type::CFG6
__IO uint32_t	LPSPI_Type::CFGR0
__IO uint32_t	LPSPI_Type::CFGR1
__IO uint32_t	CCM_Type::CGPR
__IO uint32_t	DCP_Type::CH0CMDPTR
__IO uint32_t	DCP_Type::CH0OPTS
__IO uint32_t	DCP_Type::CH0OPTS_CLR
__IO uint32_t	DCP_Type::CH0OPTS_SET
__IO uint32_t	DCP_Type::CH0OPTS_TOG
__IO uint32_t	DCP_Type::CH0SEMA
__IO uint32_t	DCP_Type::CH0STAT
__IO uint32_t	DCP_Type::CH0STAT_CLR
__IO uint32_t	DCP_Type::CH0STAT_SET
__IO uint32_t	DCP_Type::CH0STAT_TOG
__IO uint32_t	DCP_Type::CH1CMDPTR
__IO uint32_t	DCP_Type::CH1OPTS
__IO uint32_t	DCP_Type::CH1OPTS_CLR
__IO uint32_t	DCP_Type::CH1OPTS_SET
__IO uint32_t	DCP_Type::CH1OPTS_TOG
__IO uint32_t	DCP_Type::CH1SEMA
__IO uint32_t	DCP_Type::CH1STAT
__IO uint32_t	DCP_Type::CH1STAT_CLR
__IO uint32_t	DCP_Type::CH1STAT_SET
__IO uint32_t	DCP_Type::CH1STAT_TOG
__IO uint32_t	DCP_Type::CH2CMDPTR
__IO uint32_t	DCP_Type::CH2OPTS
__IO uint32_t	DCP_Type::CH2OPTS_CLR
__IO uint32_t	DCP_Type::CH2OPTS_SET
__IO uint32_t	DCP_Type::CH2OPTS_TOG
__IO uint32_t	DCP_Type::CH2SEMA
__IO uint32_t	DCP_Type::CH2STAT
__IO uint32_t	DCP_Type::CH2STAT_CLR
__IO uint32_t	DCP_Type::CH2STAT_SET
__IO uint32_t	DCP_Type::CH2STAT_TOG
__IO uint32_t	DCP_Type::CH3CMDPTR
__IO uint32_t	DCP_Type::CH3OPTS
__IO uint32_t	DCP_Type::CH3OPTS_CLR
__IO uint32_t	DCP_Type::CH3OPTS_SET
__IO uint32_t	DCP_Type::CH3OPTS_TOG
__IO uint32_t	DCP_Type::CH3SEMA
__IO uint32_t	DCP_Type::CH3STAT
__IO uint32_t	DCP_Type::CH3STAT_CLR
__IO uint32_t	DCP_Type::CH3STAT_SET
__IO uint32_t	DCP_Type::CH3STAT_TOG
struct {
__IO uint32_t   ENET_Type::TCCR
__IO uint32_t   ENET_Type::TCSR
}	ENET_Type::CHANNEL [4]
struct {
__I uint32_t   PIT_Type::CVAL
__IO uint32_t   PIT_Type::LDVAL
__IO uint32_t   PIT_Type::TCTRL
__IO uint32_t   PIT_Type::TFLG
}	PIT_Type::CHANNEL [4]
struct {
__IO uint16_t   TMR_Type::CAPT
__IO uint16_t   TMR_Type::CMPLD1
__IO uint16_t   TMR_Type::CMPLD2
__IO uint16_t   TMR_Type::CNTR
__IO uint16_t   TMR_Type::COMP1
__IO uint16_t   TMR_Type::COMP2
__IO uint16_t   TMR_Type::CSCTRL
__IO uint16_t   TMR_Type::CTRL
__IO uint16_t   TMR_Type::DMA
__IO uint16_t   TMR_Type::ENBL
__IO uint16_t   TMR_Type::FILT
__IO uint16_t   TMR_Type::HOLD
__IO uint16_t   TMR_Type::LOAD
uint8_t   TMR_Type::RESERVED_0 [4]
__IO uint16_t   TMR_Type::SCTRL
}	TMR_Type::CHANNEL [4]
__IO uint32_t	DCP_Type::CHANNELCTRL
__IO uint32_t	DCP_Type::CHANNELCTRL_CLR
__IO uint32_t	DCP_Type::CHANNELCTRL_SET
__IO uint32_t	DCP_Type::CHANNELCTRL_TOG
__IO uint32_t	DMAMUX_Type::CHCFG [32]
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_CLR
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_SET
__I uint32_t   USB_ANALOG_Type::CHRG_DETECT_STAT
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_TOG
__IO uint32_t	CCM_Type::CIMR
__O uint8_t	DMA_Type::CINT
__IO uint32_t	CCM_Type::CISR
__IO uint16_t   DMA_Type::CITER_ELINKNO
__IO uint16_t   DMA_Type::CITER_ELINKYES
__IO uint32_t	USDHC_Type::CLK_TUNE_CTRL_STATUS
__IO uint8_t	EWM_Type::CLKCTRL
__IO uint8_t	EWM_Type::CLKPRESCALER
__IO uint32_t	CCM_Type::CLPCR
__IO uint32_t	USDHC_Type::CMD_ARG
__I uint32_t	USDHC_Type::CMD_RSP0
__I uint32_t	USDHC_Type::CMD_RSP1
__I uint32_t	USDHC_Type::CMD_RSP2
__I uint32_t	USDHC_Type::CMD_RSP3
__IO uint32_t	USDHC_Type::CMD_XFR_TYP
__IO uint32_t	CCM_Type::CMEOR
__IO uint8_t	EWM_Type::CMPH
__IO uint8_t	EWM_Type::CMPL
__IO uint16_t   TMR_Type::CMPLD1
__IO uint16_t   TMR_Type::CMPLD2
__I uint32_t	GPT_Type::CNT
__I uint16_t   PWM_Type::CNT
__IO uint32_t	RTWDOG_Type::CNT
__IO uint32_t	GPC_Type::CNTR
__IO uint16_t   TMR_Type::CNTR
__IO uint16_t   TMR_Type::COMP1
__IO uint16_t   TMR_Type::COMP2
__I uint32_t	USB_Type::CONFIGFLAG
__IO uint32_t	DCP_Type::CONTEXT
__IO uint32_t	PGC_Type::CPU_CTRL
__IO uint32_t	PGC_Type::CPU_PDNSCR
__IO uint32_t	PGC_Type::CPU_PUPSCR
__IO uint32_t	PGC_Type::CPU_SR
__IO uint32_t	DMA_Type::CR
__IO uint32_t	GPT_Type::CR
__IO uint32_t	LPSPI_Type::CR
__IO uint8_t	CMP_Type::CR0
__IO uint8_t	CMP_Type::CR1
__IO uint32_t	LCDIF_Type::CRC_STAT
__I uint32_t	CAN_Type::CRCR
__IO uint32_t   CAN_Type::CS
__IO uint32_t	RTWDOG_Type::CS
__IO uint32_t	CCM_Type::CS1CDR
__IO uint32_t	CCM_Type::CS2CDR
__IO uint32_t	PXP_Type::CSC1_COEF0
__IO uint32_t	PXP_Type::CSC1_COEF1
__IO uint32_t	PXP_Type::CSC1_COEF2
__IO uint32_t	CCM_Type::CSCDR1
__IO uint32_t	CCM_Type::CSCDR2
__IO uint32_t	CCM_Type::CSCDR3
__IO uint32_t	CCM_Type::CSCMR1
__IO uint32_t	CCM_Type::CSCMR2
__IO uint16_t   TMR_Type::CSCTRL
__IO uint32_t	CSI_Type::CSICR1
__IO uint32_t	CSI_Type::CSICR18
__IO uint32_t	CSI_Type::CSICR19
__IO uint32_t	CSI_Type::CSICR2
__IO uint32_t	CSI_Type::CSICR3
__IO uint32_t	CSI_Type::CSIDMASA_FB1
__IO uint32_t	CSI_Type::CSIDMASA_FB2
__IO uint32_t	CSI_Type::CSIDMASA_STATFIFO
__IO uint32_t	CSI_Type::CSIDMATS_STATFIFO
__IO uint32_t	CSI_Type::CSIFBUF_PARA
__IO uint32_t	CSI_Type::CSIIMAG_PARA
__I uint32_t	CSI_Type::CSIRFIFO
__IO uint32_t	CSI_Type::CSIRXCNT
__IO uint32_t	CSI_Type::CSISR
__I uint32_t	CSI_Type::CSISTATFIFO
__IO uint32_t	CSU_Type::CSL [32]
__I uint32_t	CCM_Type::CSR
__IO uint16_t   DMA_Type::CSR
__O uint32_t	BEE_Type::CTR_NONCE0_W0
__O uint32_t	BEE_Type::CTR_NONCE0_W1
__O uint32_t	BEE_Type::CTR_NONCE0_W2
__O uint32_t	BEE_Type::CTR_NONCE0_W3
__O uint32_t	BEE_Type::CTR_NONCE1_W0
__O uint32_t	BEE_Type::CTR_NONCE1_W1
__O uint32_t	BEE_Type::CTR_NONCE1_W2
__O uint32_t	BEE_Type::CTR_NONCE1_W3
__IO uint32_t	ADC_ETC_Type::CTRL
__IO uint32_t	BEE_Type::CTRL
__IO uint32_t	DCP_Type::CTRL
__IO uint16_t	ENC_Type::CTRL
__IO uint8_t	EWM_Type::CTRL
__IO uint32_t	FLEXIO_Type::CTRL
__IO uint32_t	LCDIF_Type::CTRL
__IO uint32_t	LPUART_Type::CTRL
__IO uint32_t	OCOTP_Type::CTRL
__IO uint16_t   PWM_Type::CTRL
__IO uint32_t	PXP_Type::CTRL
__IO uint16_t   TMR_Type::CTRL
__IO uint32_t	USBPHY_Type::CTRL
__IO uint16_t	XBARA_Type::CTRL0
__IO uint32_t	CAN_Type::CTRL1
__IO uint32_t	LCDIF_Type::CTRL1
__IO uint16_t	XBARA_Type::CTRL1
__IO uint32_t	LCDIF_Type::CTRL1_CLR
__IO uint32_t	LCDIF_Type::CTRL1_SET
__IO uint32_t	LCDIF_Type::CTRL1_TOG
__IO uint32_t	CAN_Type::CTRL2
__IO uint16_t	ENC_Type::CTRL2
__IO uint32_t	LCDIF_Type::CTRL2
__IO uint16_t   PWM_Type::CTRL2
__IO uint32_t	LCDIF_Type::CTRL2_CLR
__IO uint32_t	LCDIF_Type::CTRL2_SET
__IO uint32_t	LCDIF_Type::CTRL2_TOG
__IO uint32_t	DCP_Type::CTRL_CLR
__IO uint32_t	LCDIF_Type::CTRL_CLR
__IO uint32_t	OCOTP_Type::CTRL_CLR
__IO uint32_t	PXP_Type::CTRL_CLR
__IO uint32_t	USBPHY_Type::CTRL_CLR
__IO uint32_t	DCP_Type::CTRL_SET
__IO uint32_t	LCDIF_Type::CTRL_SET
__IO uint32_t	OCOTP_Type::CTRL_SET
__IO uint32_t	PXP_Type::CTRL_SET
__IO uint32_t	USBPHY_Type::CTRL_SET
__IO uint32_t	DCP_Type::CTRL_TOG
__IO uint32_t	LCDIF_Type::CTRL_TOG
__IO uint32_t	OCOTP_Type::CTRL_TOG
__IO uint32_t	PXP_Type::CTRL_TOG
__IO uint32_t	USBPHY_Type::CTRL_TOG
__IO uint32_t	LCDIF_Type::CUR_BUF
__IO uint32_t	ADC_Type::CV
__I uint32_t   PIT_Type::CVAL
__I uint16_t   PWM_Type::CVAL0
__I uint16_t   PWM_Type::CVAL0CYC
__I uint16_t   PWM_Type::CVAL1
__I uint16_t   PWM_Type::CVAL1CYC
__I uint16_t   PWM_Type::CVAL2
__I uint16_t   PWM_Type::CVAL2CYC
__I uint16_t   PWM_Type::CVAL3
__I uint16_t   PWM_Type::CVAL3CYC
__I uint16_t   PWM_Type::CVAL4
__I uint16_t   PWM_Type::CVAL4CYC
__I uint16_t   PWM_Type::CVAL5
__I uint16_t   PWM_Type::CVAL5CYC
__IO uint8_t	CMP_Type::DACCR
__IO uint32_t   DMA_Type::DADDR
__IO uint32_t	LPUART_Type::DATA
__IO uint32_t	OCOTP_Type::DATA
__IO uint32_t	USDHC_Type::DATA_BUFF_ACC_PORT
__I uint32_t	CAN_Type::DBG1
__I uint32_t	CAN_Type::DBG2
__I uint32_t	DCP_Type::DBGDATA
__IO uint32_t	DCP_Type::DBGSELECT
__IO uint32_t	SEMC_Type::DBICR0
__IO uint32_t	SEMC_Type::DBICR1
__I uint32_t	USB_Type::DCCPARAMS
__IO uint8_t	DMA_Type::DCHPRI0
__IO uint8_t	DMA_Type::DCHPRI1
__IO uint8_t	DMA_Type::DCHPRI10
__IO uint8_t	DMA_Type::DCHPRI11
__IO uint8_t	DMA_Type::DCHPRI12
__IO uint8_t	DMA_Type::DCHPRI13
__IO uint8_t	DMA_Type::DCHPRI14
__IO uint8_t	DMA_Type::DCHPRI15
__IO uint8_t	DMA_Type::DCHPRI16
__IO uint8_t	DMA_Type::DCHPRI17
__IO uint8_t	DMA_Type::DCHPRI18
__IO uint8_t	DMA_Type::DCHPRI19
__IO uint8_t	DMA_Type::DCHPRI2
__IO uint8_t	DMA_Type::DCHPRI20
__IO uint8_t	DMA_Type::DCHPRI21
__IO uint8_t	DMA_Type::DCHPRI22
__IO uint8_t	DMA_Type::DCHPRI23
__IO uint8_t	DMA_Type::DCHPRI24
__IO uint8_t	DMA_Type::DCHPRI25
__IO uint8_t	DMA_Type::DCHPRI26
__IO uint8_t	DMA_Type::DCHPRI27
__IO uint8_t	DMA_Type::DCHPRI28
__IO uint8_t	DMA_Type::DCHPRI29
__IO uint8_t	DMA_Type::DCHPRI3
__IO uint8_t	DMA_Type::DCHPRI30
__IO uint8_t	DMA_Type::DCHPRI31
__IO uint8_t	DMA_Type::DCHPRI4
__IO uint8_t	DMA_Type::DCHPRI5
__IO uint8_t	DMA_Type::DCHPRI6
__IO uint8_t	DMA_Type::DCHPRI7
__IO uint8_t	DMA_Type::DCHPRI8
__IO uint8_t	DMA_Type::DCHPRI9
__I uint16_t	USB_Type::DCIVERSION
__I uint32_t	USBPHY_Type::DEBUG0_STATUS
__IO uint32_t	USBPHY_Type::DEBUG1
__IO uint32_t	USBPHY_Type::DEBUG1_CLR
__IO uint32_t	USBPHY_Type::DEBUG1_SET
__IO uint32_t	USBPHY_Type::DEBUG1_TOG
__IO uint32_t	USBPHY_Type::DEBUG_CLR
__IO uint32_t	TSC_Type::DEBUG_MODE
__IO uint32_t	TSC_Type::DEBUG_MODE2
__IO uint32_t	USBPHY_Type::DEBUG_SET
__IO uint32_t	USBPHY_Type::DEBUG_TOG
__IO uint32_t	USBPHY_Type::DEBUGr
__IO uint32_t	LPSPI_Type::DER
__IO uint32_t   USB_Type::DEVICEADDR
__I uint32_t	USB_ANALOG_Type::DIGPROG
__IO uint16_t   PWM_Type::DISMAP [2]
__IO uint32_t   DMA_Type::DLAST_SGA
__IO uint32_t	USDHC_Type::DLL_CTRL
__I uint32_t	USDHC_Type::DLL_STATUS
__IO uint32_t	FLEXSPI_Type::DLLCR [2]
__IO uint16_t   TMR_Type::DMA
__IO uint32_t	ADC_ETC_Type::DMA_CTRL
__IO uint16_t   PWM_Type::DMAEN
__IO uint32_t	LPSPI_Type::DMR0
__IO uint32_t	LPSPI_Type::DMR1
__IO uint16_t   DMA_Type::DOFF
__IO uint32_t	ADC_ETC_Type::DONE0_1_IRQ
__IO uint32_t	ADC_ETC_Type::DONE2_ERR_IRQ
__IO uint32_t	GPIO_Type::DR
__O uint32_t	GPIO_Type::DR_CLEAR
__O uint32_t	GPIO_Type::DR_SET
__O uint32_t	GPIO_Type::DR_TOGGLE
__IO uint32_t	USDHC_Type::DS_ADDR
__IO uint16_t   PWM_Type::DTCNT0
__IO uint16_t   PWM_Type::DTCNT1
__IO uint16_t	PWM_Type::DTSRCSEL
__IO uint32_t	DMA_Type::EARS
__IO uint32_t	CAN_Type::ECR
__IO uint32_t	ENET_Type::ECR
__IO uint32_t	GPIO_Type::EDGE_SEL
__IO uint32_t	DMA_Type::EEI
__IO uint32_t	ENET_Type::EIMR
__IO uint32_t	ENET_Type::EIR
__IO uint16_t   TMR_Type::ENBL
__IO uint32_t	USB_Type::ENDPTCOMPLETE
__IO uint32_t	USB_Type::ENDPTCTRL [7]
__IO uint32_t	USB_Type::ENDPTCTRL0
__IO uint32_t	USB_Type::ENDPTFLUSH
__IO uint32_t   USB_Type::ENDPTLISTADDR
__IO uint32_t	USB_Type::ENDPTNAK
__IO uint32_t	USB_Type::ENDPTNAKEN
__IO uint32_t	USB_Type::ENDPTPRIME
__IO uint32_t	USB_Type::ENDPTSETUPSTAT
__I uint32_t	USB_Type::ENDPTSTAT
__I uint32_t	TRNG_Type::ENT [16]
__IO uint32_t	DMA_Type::ERQ
__IO uint32_t	DMA_Type::ERR
__I uint32_t	DMA_Type::ES
__IO uint32_t	CAN_Type::ESR1
__I uint32_t	CAN_Type::ESR2
__IO uint32_t	LPSPI_Type::FCR
__IO uint16_t	PWM_Type::FCTRL
__IO uint16_t	PWM_Type::FCTRL2
__IO uint16_t	PWM_Type::FFILT
__IO uint32_t	LPUART_Type::FIFO
__IO uint16_t	ENC_Type::FILT
__IO uint16_t   TMR_Type::FILT
__IO uint32_t	TSC_Type::FLOW_CONTROL
__IO uint32_t	FLEXSPI_Type::FLSHCR0 [4]
__IO uint32_t	FLEXSPI_Type::FLSHCR1 [4]
__IO uint32_t	FLEXSPI_Type::FLSHCR2 [4]
__IO uint32_t	FLEXSPI_Type::FLSHCR4
__O uint32_t	USDHC_Type::FORCE_EVENT
__IO uint8_t	CMP_Type::FPR
__IO uint16_t   PWM_Type::FRACVAL1
__IO uint16_t   PWM_Type::FRACVAL2
__IO uint16_t   PWM_Type::FRACVAL3
__IO uint16_t   PWM_Type::FRACVAL4
__IO uint16_t   PWM_Type::FRACVAL5
__IO uint16_t   PWM_Type::FRCTRL
__IO uint32_t	USB_Type::FRINDEX
__I uint32_t   TRNG_Type::FRQCNT
__IO uint32_t   TRNG_Type::FRQMAX
__IO uint32_t	TRNG_Type::FRQMIN
__I uint32_t	LPSPI_Type::FSR
__IO uint16_t	PWM_Type::FSTS
__IO uint32_t	ENET_Type::FTRL
__IO uint16_t	PWM_Type::FTST
__IO uint32_t	ENET_Type::GALR
__IO uint32_t	ENET_Type::GAUR
__IO uint32_t	ADC_Type::GC
__IO uint32_t	GPIO_Type::GDIR
__IO uint32_t	CAN_Type::GFWR
__IO uint32_t	LPUART_Type::GLOBAL
__IO uint32_t	OCOTP_Type::GP1
__IO uint32_t	OCOTP_Type::GP2
__IO uint32_t	OCOTP_Type::GP3
__IO uint32_t	SRC_Type::GPR [10]
uint32_t	IOMUXC_GPR_Type::GPR0
uint32_t	IOMUXC_SNVS_GPR_Type::GPR0
__IO uint32_t	IOMUXC_GPR_Type::GPR1
uint32_t	IOMUXC_SNVS_GPR_Type::GPR1
__IO uint32_t	IOMUXC_GPR_Type::GPR10
__IO uint32_t	IOMUXC_GPR_Type::GPR11
__IO uint32_t	IOMUXC_GPR_Type::GPR12
__IO uint32_t	IOMUXC_GPR_Type::GPR13
__IO uint32_t	IOMUXC_GPR_Type::GPR14
uint32_t	IOMUXC_GPR_Type::GPR15
__IO uint32_t	IOMUXC_GPR_Type::GPR16
__IO uint32_t	IOMUXC_GPR_Type::GPR17
__IO uint32_t	IOMUXC_GPR_Type::GPR18
__IO uint32_t	IOMUXC_GPR_Type::GPR19
__IO uint32_t	IOMUXC_GPR_Type::GPR2
uint32_t	IOMUXC_SNVS_GPR_Type::GPR2
__IO uint32_t	IOMUXC_GPR_Type::GPR20
__IO uint32_t	IOMUXC_GPR_Type::GPR21
__IO uint32_t	IOMUXC_GPR_Type::GPR22
__IO uint32_t	IOMUXC_GPR_Type::GPR23
__IO uint32_t	IOMUXC_GPR_Type::GPR24
__IO uint32_t	IOMUXC_GPR_Type::GPR25
__IO uint32_t	IOMUXC_GPR_Type::GPR3
__IO uint32_t	IOMUXC_SNVS_GPR_Type::GPR3
__IO uint32_t	IOMUXC_GPR_Type::GPR4
__IO uint32_t	IOMUXC_GPR_Type::GPR5
__IO uint32_t	IOMUXC_GPR_Type::GPR6
__IO uint32_t	IOMUXC_GPR_Type::GPR7
__IO uint32_t	IOMUXC_GPR_Type::GPR8
uint32_t	IOMUXC_GPR_Type::GPR9
__IO uint32_t	USB_Type::GPTIMER0CTRL
__IO uint32_t	USB_Type::GPTIMER0LD
__IO uint32_t	USB_Type::GPTIMER1CTRL
__IO uint32_t	USB_Type::GPTIMER1LD
__IO uint32_t	ADC_Type::GS
__IO uint32_t	ADC_Type::HC [8]
__I uint32_t	USB_Type::HCCPARAMS
__I uint16_t	USB_Type::HCIVERSION
__I uint32_t	USB_Type::HCSPARAMS
__IO uint16_t   TMR_Type::HOLD
__IO uint32_t	USDHC_Type::HOST_CTRL_CAP
__IO uint32_t	CSU_Type::HP0
__IO uint32_t	SNVS_Type::HPCOMR
__IO uint32_t	CSU_Type::HPCONTROL0
__IO uint32_t	SNVS_Type::HPCR
__IO uint32_t	SNVS_Type::HPHACIVR
__I uint32_t	SNVS_Type::HPHACR
__IO uint32_t	SNVS_Type::HPLR
__IO uint32_t	SNVS_Type::HPRTCLR
__IO uint32_t	SNVS_Type::HPRTCMR
__IO uint32_t	SNVS_Type::HPSICR
__IO uint32_t	SNVS_Type::HPSR
__IO uint32_t	SNVS_Type::HPSVCR
__IO uint32_t	SNVS_Type::HPSVSR
__IO uint32_t	SNVS_Type::HPTALR
__IO uint32_t	SNVS_Type::HPTAMR
__I uint32_t	SNVS_Type::HPVIDR1
__I uint32_t	SNVS_Type::HPVIDR2
__I uint32_t	DMA_Type::HRS
__I uint32_t	ADC_Type::HS
__I uint32_t	USB_Type::HWDEVICE
__I uint32_t	USB_Type::HWGENERAL
__I uint32_t	USB_Type::HWHOST
__I uint32_t	USB_Type::HWRXBUF
__I uint32_t	USB_Type::HWTXBUF
__IO uint32_t	ENET_Type::IALR
__IO uint32_t	ENET_Type::IAUR
__I uint32_t	GPT_Type::ICR [2]
__IO uint32_t	GPIO_Type::ICR1
__IO uint32_t	GPIO_Type::ICR2
__IO uint32_t   CAN_Type::ID
__I uint32_t	USB_Type::ID
__I uint32_t	ENET_Type::IEEE_R_ALIGN
__I uint32_t	ENET_Type::IEEE_R_CRC
__I uint32_t	ENET_Type::IEEE_R_DROP
__I uint32_t	ENET_Type::IEEE_R_FDXFC
__I uint32_t	ENET_Type::IEEE_R_FRAME_OK
__I uint32_t	ENET_Type::IEEE_R_MACERR
__I uint32_t	ENET_Type::IEEE_R_OCTETS_OK
__I uint32_t	ENET_Type::IEEE_T_1COL
__I uint32_t	ENET_Type::IEEE_T_CSERR
__I uint32_t	ENET_Type::IEEE_T_DEF
uint32_t	ENET_Type::IEEE_T_DROP
__I uint32_t	ENET_Type::IEEE_T_EXCOL
__I uint32_t	ENET_Type::IEEE_T_FDXFC
__I uint32_t	ENET_Type::IEEE_T_FRAME_OK
__I uint32_t	ENET_Type::IEEE_T_LCOL
__I uint32_t	ENET_Type::IEEE_T_MACERR
__I uint32_t	ENET_Type::IEEE_T_MCOL
__I uint32_t	ENET_Type::IEEE_T_OCTETS_OK
__I uint32_t	ENET_Type::IEEE_T_SQE
__IO uint32_t	LPSPI_Type::IER
__IO uint32_t	CAN_Type::IFLAG1
__IO uint32_t	CAN_Type::IFLAG2
__IO uint32_t	CAN_Type::IMASK1
__IO uint32_t	CAN_Type::IMASK2
__IO uint32_t	GPC_Type::IMR [4]
__I uint16_t	ENC_Type::IMR
__IO uint32_t	GPIO_Type::IMR
__IO uint32_t	GPC_Type::IMR5
__IO uint16_t   PWM_Type::INIT
struct {
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_CLR
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_SET
__I uint32_t   USB_ANALOG_Type::CHRG_DETECT_STAT
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_TOG
__IO uint32_t   USB_ANALOG_Type::LOOPBACK
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_CLR
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_SET
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_TOG
__IO uint32_t   USB_ANALOG_Type::MISC
__IO uint32_t   USB_ANALOG_Type::MISC_CLR
__IO uint32_t   USB_ANALOG_Type::MISC_SET
__IO uint32_t   USB_ANALOG_Type::MISC_TOG
uint8_t   USB_ANALOG_Type::RESERVED_0 [12]
uint8_t   USB_ANALOG_Type::RESERVED_1 [12]
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_CLR
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_SET
__I uint32_t   USB_ANALOG_Type::VBUS_DETECT_STAT
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_TOG
}	USB_ANALOG_Type::INSTANCE [2]
__IO uint32_t	DMA_Type::INT
__IO uint32_t	TRNG_Type::INT_CTRL
__IO uint32_t	TSC_Type::INT_EN
__IO uint32_t	TRNG_Type::INT_MASK
__IO uint32_t	FLEXRAM_Type::INT_SIG_EN
__IO uint32_t	TSC_Type::INT_SIG_EN
__IO uint32_t	USDHC_Type::INT_SIGNAL_EN
__IO uint32_t	FLEXRAM_Type::INT_STAT_EN
__IO uint32_t	FLEXRAM_Type::INT_STATUS
__I uint32_t	TRNG_Type::INT_STATUS
__IO uint32_t	TSC_Type::INT_STATUS
__IO uint32_t	USDHC_Type::INT_STATUS
__IO uint32_t	USDHC_Type::INT_STATUS_EN
__IO uint32_t	FLEXSPI_Type::INTEN
__IO uint16_t   PWM_Type::INTEN
__IO uint32_t	SEMC_Type::INTEN
__IO uint32_t	FLEXSPI_Type::INTR
__IO uint32_t	SEMC_Type::INTR
__IO uint32_t	SEMC_Type::IOCR
__IO uint32_t	FLEXSPI_Type::IPCMD
__IO uint32_t	SEMC_Type::IPCMD
__IO uint32_t	FLEXSPI_Type::IPCR0
__IO uint32_t	SEMC_Type::IPCR0
__IO uint32_t	FLEXSPI_Type::IPCR1
__IO uint32_t	SEMC_Type::IPCR1
__IO uint32_t	SEMC_Type::IPCR2
__I uint32_t	SEMC_Type::IPRXDAT
__IO uint32_t	FLEXSPI_Type::IPRXFCR
__I uint32_t	FLEXSPI_Type::IPRXFSTS
__IO uint32_t	SEMC_Type::IPTXDAT
__IO uint32_t	FLEXSPI_Type::IPTXFCR
__I uint32_t	FLEXSPI_Type::IPTXFSTS
__IO uint32_t	GPT_Type::IR
__I uint32_t	GPC_Type::ISR [4]
__IO uint32_t	GPIO_Type::ISR
__I uint32_t	GPC_Type::ISR5
__IO uint16_t	KPP_Type::KDDR
__IO uint32_t	DCP_Type::KEY
__IO uint32_t	DCP_Type::KEYDATA
__IO uint16_t	KPP_Type::KPCR
__IO uint16_t	KPP_Type::KPDR
__IO uint16_t	KPP_Type::KPSR
__IO uint16_t	ENC_Type::LCOMP
__IO uint32_t   PIT_Type::LDVAL
__IO uint16_t	ENC_Type::LINIT
__IO uint16_t	ENC_Type::LMOD
__IO uint16_t   TMR_Type::LOAD
__IO uint32_t	OCOTP_Type::LOCK
__IO uint32_t   USB_ANALOG_Type::LOOPBACK
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_CLR
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_SET
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_TOG
__IO uint32_t	XTALOSC24M_Type::LOWPWR_CTRL
__IO uint32_t	XTALOSC24M_Type::LOWPWR_CTRL_CLR
__IO uint32_t	XTALOSC24M_Type::LOWPWR_CTRL_SET
__IO uint32_t	XTALOSC24M_Type::LOWPWR_CTRL_TOG
__IO uint32_t	SNVS_Type::LPCR
__IO uint32_t	SNVS_Type::LPGPR [8]
__IO uint32_t	SNVS_Type::LPGPR0_LEGACY_ALIAS
__IO uint32_t	SNVS_Type::LPGPR_ALIAS [4]
__IO uint32_t	SNVS_Type::LPLR
__IO uint32_t	SNVS_Type::LPMKCR
__IO uint16_t	ENC_Type::LPOS
__I uint16_t	ENC_Type::LPOSH
__IO uint32_t	SNVS_Type::LPPGDR
__I uint32_t	SNVS_Type::LPSMCLR
__I uint32_t	SNVS_Type::LPSMCMR
__IO uint32_t	SNVS_Type::LPSR
__IO uint32_t	SNVS_Type::LPSRTCLR
__IO uint32_t	SNVS_Type::LPSRTCMR
__IO uint32_t	SNVS_Type::LPSVCR
__IO uint32_t	SNVS_Type::LPTAR
__IO uint32_t	SNVS_Type::LPTDCR
__IO uint32_t	SNVS_Type::LPZMKR [8]
__I uint32_t	PIT_Type::LTMR64H
__I uint32_t	PIT_Type::LTMR64L
__IO uint32_t	FLEXSPI_Type::LUT [64]
__IO uint32_t	LCDIF_Type::LUT0_ADDR
__IO uint32_t	LCDIF_Type::LUT0_DATA
__IO uint32_t	LCDIF_Type::LUT1_ADDR
__IO uint32_t	LCDIF_Type::LUT1_DATA
__IO uint32_t	LCDIF_Type::LUT_CTRL
__IO uint32_t	FLEXSPI_Type::LUTCR
__IO uint32_t	FLEXSPI_Type::LUTKEY
__IO uint32_t	OCOTP_Type::MAC0
__IO uint32_t	OCOTP_Type::MAC1
__IO uint16_t	PWM_Type::MASK
__IO uint32_t	LPUART_Type::MATCH
struct {
__IO uint32_t   CAN_Type::CS
__IO uint32_t   CAN_Type::ID
__IO uint32_t   CAN_Type::WORD0
__IO uint32_t   CAN_Type::WORD1
}	CAN_Type::MB [64]
__IO uint32_t	LPI2C_Type::MCCR0
__IO uint32_t	LPI2C_Type::MCCR1
__IO uint32_t	LPI2C_Type::MCFGR0
__IO uint32_t	LPI2C_Type::MCFGR1
__IO uint32_t	LPI2C_Type::MCFGR2
__IO uint32_t	LPI2C_Type::MCFGR3
__IO uint32_t	CAN_Type::MCR
__IO uint32_t	LPI2C_Type::MCR
__IO uint32_t	PIT_Type::MCR
__IO uint32_t	SEMC_Type::MCR
__IO uint32_t	FLEXSPI_Type::MCR0
__IO uint32_t	FLEXSPI_Type::MCR1
__IO uint32_t	FLEXSPI_Type::MCR2
__IO uint32_t	TRNG_Type::MCTL
__IO uint16_t	PWM_Type::MCTRL
__IO uint16_t	PWM_Type::MCTRL2
__IO uint32_t	LPI2C_Type::MDER
__IO uint32_t	LPI2C_Type::MDMR
__I uint32_t	TSC_Type::MEASEURE_VALUE
__IO uint32_t	PGC_Type::MEGA_CTRL
__IO uint32_t	PGC_Type::MEGA_PDNSCR
__IO uint32_t	PGC_Type::MEGA_PUPSCR
__IO uint32_t	PGC_Type::MEGA_SR
__IO uint32_t	OCOTP_Type::MEM0
__IO uint32_t	OCOTP_Type::MEM1
__IO uint32_t	OCOTP_Type::MEM2
__IO uint32_t	OCOTP_Type::MEM3
__IO uint32_t	OCOTP_Type::MEM4
__IO uint32_t	LPI2C_Type::MFCR
__I uint32_t	LPI2C_Type::MFSR
__IO uint32_t	ENET_Type::MIBC
__IO uint32_t	LPI2C_Type::MIER
__IO uint32_t   USB_ANALOG_Type::MISC
__IO uint32_t	CCM_ANALOG_Type::MISC0
__IO uint32_t	PMU_Type::MISC0
__IO uint32_t	XTALOSC24M_Type::MISC0
__IO uint32_t	CCM_ANALOG_Type::MISC0_CLR
__IO uint32_t	PMU_Type::MISC0_CLR
__IO uint32_t	XTALOSC24M_Type::MISC0_CLR
__IO uint32_t	CCM_ANALOG_Type::MISC0_SET
__IO uint32_t	PMU_Type::MISC0_SET
__IO uint32_t	XTALOSC24M_Type::MISC0_SET
__IO uint32_t	CCM_ANALOG_Type::MISC0_TOG
__IO uint32_t	PMU_Type::MISC0_TOG
__IO uint32_t	XTALOSC24M_Type::MISC0_TOG
__IO uint32_t	CCM_ANALOG_Type::MISC1
__IO uint32_t	PMU_Type::MISC1
__IO uint32_t	CCM_ANALOG_Type::MISC1_CLR
__IO uint32_t	PMU_Type::MISC1_CLR
__IO uint32_t	CCM_ANALOG_Type::MISC1_SET
__IO uint32_t	PMU_Type::MISC1_SET
__IO uint32_t	CCM_ANALOG_Type::MISC1_TOG
__IO uint32_t	PMU_Type::MISC1_TOG
__IO uint32_t	CCM_ANALOG_Type::MISC2
__IO uint32_t	PMU_Type::MISC2
__IO uint32_t	CCM_ANALOG_Type::MISC2_CLR
__IO uint32_t	PMU_Type::MISC2_CLR
__IO uint32_t	CCM_ANALOG_Type::MISC2_SET
__IO uint32_t	PMU_Type::MISC2_SET
__IO uint32_t	CCM_ANALOG_Type::MISC2_TOG
__IO uint32_t	PMU_Type::MISC2_TOG
__IO uint32_t   USB_ANALOG_Type::MISC_CLR
__IO uint32_t	OCOTP_Type::MISC_CONF0
__IO uint32_t	OCOTP_Type::MISC_CONF1
__IO uint32_t   USB_ANALOG_Type::MISC_SET
__IO uint32_t   USB_ANALOG_Type::MISC_TOG
__IO uint32_t	USDHC_Type::MIX_CTRL
__IO uint32_t	USDHC_Type::MMC_BOOT
__IO uint32_t	ENET_Type::MMFR
__IO uint32_t	LPUART_Type::MODIR
__IO uint32_t	AIPSTZ_Type::MPR
__IO uint32_t	ENET_Type::MRBR
__I uint32_t	LPI2C_Type::MRDR
__IO uint32_t	ENET_Type::MSCR
__IO uint32_t	LPI2C_Type::MSR
__O uint32_t	LPI2C_Type::MTDR
__IO uint8_t	CMP_Type::MUXCR
__IO uint32_t	SEMC_Type::NANDCR0
__IO uint32_t	SEMC_Type::NANDCR1
__IO uint32_t	SEMC_Type::NANDCR2
__IO uint32_t	SEMC_Type::NANDCR3
__IO uint32_t   DMA_Type::NBYTES_MLNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFYES
__IO uint32_t	PXP_Type::NEXT
__IO uint32_t	LCDIF_Type::NEXT_BUF
__IO uint32_t	SEMC_Type::NORCR0
__IO uint32_t	SEMC_Type::NORCR1
__IO uint32_t	SEMC_Type::NORCR2
uint32_t	SEMC_Type::NORCR3
__IO uint32_t	GPT_Type::OCR [3]
__IO uint16_t   PWM_Type::OCTRL
__IO uint32_t	ADC_Type::OFS
__IO uint32_t	AIPSTZ_Type::OPACR
__IO uint32_t	AIPSTZ_Type::OPACR1
__IO uint32_t	AIPSTZ_Type::OPACR2
__IO uint32_t	AIPSTZ_Type::OPACR3
__IO uint32_t	AIPSTZ_Type::OPACR4
__IO uint32_t	ENET_Type::OPD
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG0
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG0_CLR
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG0_SET
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG0_TOG
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG1
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG1_CLR
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG1_SET
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG1_TOG
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG2
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG2_CLR
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG2_SET
__IO uint32_t	XTALOSC24M_Type::OSC_CONFIG2_TOG
__IO uint32_t	USB_Type::OTGSC
__IO uint32_t	PXP_Type::OUT_AS_LRC
__IO uint32_t	PXP_Type::OUT_AS_ULC
__IO uint32_t	PXP_Type::OUT_BUF
__IO uint32_t	PXP_Type::OUT_BUF2
__IO uint32_t	PXP_Type::OUT_CTRL
__IO uint32_t	PXP_Type::OUT_CTRL_CLR
__IO uint32_t	PXP_Type::OUT_CTRL_SET
__IO uint32_t	PXP_Type::OUT_CTRL_TOG
__IO uint32_t	PXP_Type::OUT_LRC
__IO uint32_t	PXP_Type::OUT_PITCH
__IO uint32_t	PXP_Type::OUT_PS_LRC
__IO uint32_t	PXP_Type::OUT_PS_ULC
__IO uint16_t	PWM_Type::OUTEN
__I uint32_t	DCP_Type::PACKET0
__I uint32_t	DCP_Type::PACKET1
__I uint32_t	DCP_Type::PACKET2
__I uint32_t	DCP_Type::PACKET3
__I uint32_t	DCP_Type::PACKET4
__I uint32_t	DCP_Type::PACKET5
__I uint32_t	DCP_Type::PACKET6
__IO uint32_t	DCP_Type::PAGETABLE
__IO uint32_t	ENET_Type::PALR
__I uint32_t	FLEXIO_Type::PARAM
__I uint32_t	I2S_Type::PARAM
__I uint32_t	LPI2C_Type::PARAM
__I uint32_t	LPSPI_Type::PARAM
__I uint32_t	LPUART_Type::PARAM
__IO uint32_t	ENET_Type::PAUR
__IO uint32_t   USB_Type::PERIODICLISTBASE
__IO uint32_t	CCM_ANALOG_Type::PFD_480
__IO uint32_t	CCM_ANALOG_Type::PFD_480_CLR
__IO uint32_t	CCM_ANALOG_Type::PFD_480_SET
__IO uint32_t	CCM_ANALOG_Type::PFD_480_TOG
__IO uint32_t	CCM_ANALOG_Type::PFD_528
__IO uint32_t	CCM_ANALOG_Type::PFD_528_CLR
__IO uint32_t	CCM_ANALOG_Type::PFD_528_SET
__IO uint32_t	CCM_ANALOG_Type::PFD_528_TOG
struct {
__IO uint32_t   LCDIF_Type::PIGEON_0
__IO uint32_t   LCDIF_Type::PIGEON_1
__IO uint32_t   LCDIF_Type::PIGEON_2
uint8_t   LCDIF_Type::RESERVED_0 [12]
uint8_t   LCDIF_Type::RESERVED_1 [12]
uint8_t   LCDIF_Type::RESERVED_2 [28]
}	LCDIF_Type::PIGEON [12]
__IO uint32_t   LCDIF_Type::PIGEON_0
__IO uint32_t   LCDIF_Type::PIGEON_1
__IO uint32_t   LCDIF_Type::PIGEON_2
__IO uint32_t	LCDIF_Type::PIGEONCTRL0
__IO uint32_t	LCDIF_Type::PIGEONCTRL0_CLR
__IO uint32_t	LCDIF_Type::PIGEONCTRL0_SET
__IO uint32_t	LCDIF_Type::PIGEONCTRL0_TOG
__IO uint32_t	LCDIF_Type::PIGEONCTRL1
__IO uint32_t	LCDIF_Type::PIGEONCTRL1_CLR
__IO uint32_t	LCDIF_Type::PIGEONCTRL1_SET
__IO uint32_t	LCDIF_Type::PIGEONCTRL1_TOG
__IO uint32_t	LCDIF_Type::PIGEONCTRL2
__IO uint32_t	LCDIF_Type::PIGEONCTRL2_CLR
__IO uint32_t	LCDIF_Type::PIGEONCTRL2_SET
__IO uint32_t	LCDIF_Type::PIGEONCTRL2_TOG
__I uint32_t	FLEXIO_Type::PIN
__IO uint32_t	LPUART_Type::PINCFG
__I uint32_t	TRNG_Type::PKRCNT10
__I uint32_t	TRNG_Type::PKRCNT32
__I uint32_t	TRNG_Type::PKRCNT54
__I uint32_t	TRNG_Type::PKRCNT76
__I uint32_t	TRNG_Type::PKRCNT98
__I uint32_t	TRNG_Type::PKRCNTBA
__I uint32_t	TRNG_Type::PKRCNTDC
__I uint32_t	TRNG_Type::PKRCNTFE
__IO uint32_t   TRNG_Type::PKRMAX
__IO uint32_t	TRNG_Type::PKRRNG
__I uint32_t   TRNG_Type::PKRSQ
__IO uint32_t	CCM_ANALOG_Type::PLL_ARM
__IO uint32_t	CCM_ANALOG_Type::PLL_ARM_CLR
__IO uint32_t	CCM_ANALOG_Type::PLL_ARM_SET
__IO uint32_t	CCM_ANALOG_Type::PLL_ARM_TOG
__IO uint32_t	CCM_ANALOG_Type::PLL_AUDIO
__IO uint32_t	CCM_ANALOG_Type::PLL_AUDIO_CLR
__IO uint32_t	CCM_ANALOG_Type::PLL_AUDIO_DENOM
__IO uint32_t	CCM_ANALOG_Type::PLL_AUDIO_NUM
__IO uint32_t	CCM_ANALOG_Type::PLL_AUDIO_SET
__IO uint32_t	CCM_ANALOG_Type::PLL_AUDIO_TOG
__IO uint32_t	CCM_ANALOG_Type::PLL_ENET
__IO uint32_t	CCM_ANALOG_Type::PLL_ENET_CLR
__IO uint32_t	CCM_ANALOG_Type::PLL_ENET_SET
__IO uint32_t	CCM_ANALOG_Type::PLL_ENET_TOG
__IO uint32_t	CCM_ANALOG_Type::PLL_SYS
__IO uint32_t	CCM_ANALOG_Type::PLL_SYS_CLR
__IO uint32_t	CCM_ANALOG_Type::PLL_SYS_DENOM
__IO uint32_t	CCM_ANALOG_Type::PLL_SYS_NUM
__IO uint32_t	CCM_ANALOG_Type::PLL_SYS_SET
__IO uint32_t	CCM_ANALOG_Type::PLL_SYS_SS
__IO uint32_t	CCM_ANALOG_Type::PLL_SYS_TOG
__IO uint32_t	CCM_ANALOG_Type::PLL_USB1
__IO uint32_t	CCM_ANALOG_Type::PLL_USB1_CLR
__IO uint32_t	CCM_ANALOG_Type::PLL_USB1_SET
__IO uint32_t	CCM_ANALOG_Type::PLL_USB1_TOG
__IO uint32_t	CCM_ANALOG_Type::PLL_USB2
__IO uint32_t	CCM_ANALOG_Type::PLL_USB2_CLR
__IO uint32_t	CCM_ANALOG_Type::PLL_USB2_SET
__IO uint32_t	CCM_ANALOG_Type::PLL_USB2_TOG
__IO uint32_t	CCM_ANALOG_Type::PLL_VIDEO
__IO uint32_t	CCM_ANALOG_Type::PLL_VIDEO_CLR
__IO uint32_t	CCM_ANALOG_Type::PLL_VIDEO_DENOM
__IO uint32_t	CCM_ANALOG_Type::PLL_VIDEO_NUM
__IO uint32_t	CCM_ANALOG_Type::PLL_VIDEO_SET
__IO uint32_t	CCM_ANALOG_Type::PLL_VIDEO_TOG
__IO uint32_t	PXP_Type::PORTER_DUFF_CTRL
__IO uint32_t	USB_Type::PORTSC1
__IO uint16_t	ENC_Type::POSD
__I uint16_t	ENC_Type::POSDH
__IO uint32_t	PXP_Type::POWER
__IO uint32_t	GPT_Type::PR
__IO uint32_t	TSC_Type::PRE_CHARGE_TIME
__I uint32_t	USDHC_Type::PRES_STATE
__IO uint32_t	USDHC_Type::PROT_CTRL
__IO uint32_t	PXP_Type::PS_BACKGROUND
__IO uint32_t	PXP_Type::PS_BUF
__IO uint32_t	PXP_Type::PS_CLRKEYHIGH
__IO uint32_t	PXP_Type::PS_CLRKEYLOW
__IO uint32_t	PXP_Type::PS_CTRL
__IO uint32_t	PXP_Type::PS_CTRL_CLR
__IO uint32_t	PXP_Type::PS_CTRL_SET
__IO uint32_t	PXP_Type::PS_CTRL_TOG
__IO uint32_t	PXP_Type::PS_OFFSET
__IO uint32_t	PXP_Type::PS_PITCH
__IO uint32_t	PXP_Type::PS_SCALE
__IO uint32_t	PXP_Type::PS_UBUF
__IO uint32_t	PXP_Type::PS_VBUF
__I uint32_t	GPIO_Type::PSR
__IO uint32_t	USBPHY_Type::PWD
__IO uint32_t	USBPHY_Type::PWD_CLR
__IO uint32_t	USBPHY_Type::PWD_SET
__IO uint32_t	USBPHY_Type::PWD_TOG
__I uint32_t	ADC_Type::R [8]
__IO uint32_t	ENET_Type::RACC
__IO uint32_t	ENET_Type::RAEM
__IO uint32_t	ENET_Type::RAFL
__IO uint32_t	ENET_Type::RCR
__IO uint32_t	I2S_Type::RCR1
__IO uint32_t	I2S_Type::RCR2
__IO uint32_t	I2S_Type::RCR3
__IO uint32_t	I2S_Type::RCR4
__IO uint32_t	I2S_Type::RCR5
__IO uint32_t	I2S_Type::RCSR
__IO uint32_t	ENET_Type::RDAR
__I uint32_t	I2S_Type::RDR [4]
__I uint32_t	LPSPI_Type::RDR
__IO uint32_t	ENET_Type::RDSR
__IO uint32_t	OCOTP_Type::READ_CTRL
__IO uint32_t	OCOTP_Type::READ_FUSE_DATA
__IO uint32_t	DCDC_Type::REG0
__IO uint32_t	DCDC_Type::REG1
__IO uint32_t	DCDC_Type::REG2
__IO uint32_t	DCDC_Type::REG3
__IO uint32_t	PMU_Type::REG_1P1
__IO uint32_t	PMU_Type::REG_1P1_CLR
__IO uint32_t	PMU_Type::REG_1P1_SET
__IO uint32_t	PMU_Type::REG_1P1_TOG
__IO uint32_t	PMU_Type::REG_2P5
__IO uint32_t	PMU_Type::REG_2P5_CLR
__IO uint32_t	PMU_Type::REG_2P5_SET
__IO uint32_t	PMU_Type::REG_2P5_TOG
__IO uint32_t	PMU_Type::REG_3P0
__IO uint32_t	PMU_Type::REG_3P0_CLR
__IO uint32_t	PMU_Type::REG_3P0_SET
__IO uint32_t	PMU_Type::REG_3P0_TOG
__IO uint32_t	PMU_Type::REG_CORE
__IO uint32_t	PMU_Type::REG_CORE_CLR
__IO uint32_t	PMU_Type::REG_CORE_SET
__IO uint32_t	PMU_Type::REG_CORE_TOG
__IO uint32_t	BEE_Type::REGION1_BOT
__IO uint32_t	BEE_Type::REGION1_TOP
uint8_t	GPIO_Type::RESERVED_0 [100]
uint8_t	USB_Type::RESERVED_0 [104]
uint8_t	CCM_ANALOG_Type::RESERVED_0 [12]
uint8_t	DCP_Type::RESERVED_0 [12]
uint8_t	FLEXRAM_Type::RESERVED_0 [12]
uint8_t	LCDIF_Type::RESERVED_0 [12]
uint8_t   LCDIF_Type::RESERVED_0 [12]
uint8_t	OCOTP_Type::RESERVED_0 [12]
uint8_t	PXP_Type::RESERVED_0 [12]
uint8_t	TSC_Type::RESERVED_0 [12]
uint8_t	USBPHY_Type::RESERVED_0 [12]
uint8_t   USB_ANALOG_Type::RESERVED_0 [12]
uint8_t	I2S_Type::RESERVED_0 [16]
uint8_t	SRC_Type::RESERVED_0 [16]
uint8_t	USBNC_Type::RESERVED_0 [2048]
uint8_t	IOMUXC_Type::RESERVED_0 [20]
uint8_t	ROMC_Type::RESERVED_0 [212]
uint8_t	PIT_Type::RESERVED_0 [220]
uint8_t	PMU_Type::RESERVED_0 [272]
uint8_t   PWM_Type::RESERVED_0 [2]
uint8_t	XTALOSC24M_Type::RESERVED_0 [336]
uint8_t	CSU_Type::RESERVED_0 [384]
uint8_t	TEMPMON_Type::RESERVED_0 [384]
uint8_t	USB_ANALOG_Type::RESERVED_0 [416]
uint8_t	FLEXSPI_Type::RESERVED_0 [48]
uint8_t	CAN_Type::RESERVED_0 [4]
uint8_t	CCM_Type::RESERVED_0 [4]
uint8_t	CSI_Type::RESERVED_0 [4]
uint8_t	DMA_Type::RESERVED_0 [4]
uint8_t	ENET_Type::RESERVED_0 [4]
uint8_t	FLEXIO_Type::RESERVED_0 [4]
uint8_t	GPC_Type::RESERVED_0 [4]
uint8_t	SEMC_Type::RESERVED_0 [4]
uint8_t	SNVS_Type::RESERVED_0 [4]
uint8_t   TMR_Type::RESERVED_0 [4]
uint8_t	USDHC_Type::RESERVED_0 [4]
uint8_t	PGC_Type::RESERVED_0 [544]
uint8_t	AIPSTZ_Type::RESERVED_0 [60]
uint8_t	TRNG_Type::RESERVED_0 [64]
uint8_t	LPI2C_Type::RESERVED_0 [8]
uint8_t	LPSPI_Type::RESERVED_0 [8]
uint8_t	SPDIF_Type::RESERVED_0 [8]
uint8_t	USB_Type::RESERVED_1 [108]
uint8_t	PGC_Type::RESERVED_1 [112]
uint8_t	CCM_ANALOG_Type::RESERVED_1 [12]
uint8_t	DCP_Type::RESERVED_1 [12]
uint8_t	GPC_Type::RESERVED_1 [12]
uint8_t	LCDIF_Type::RESERVED_1 [12]
uint8_t   LCDIF_Type::RESERVED_1 [12]
uint8_t	OCOTP_Type::RESERVED_1 [12]
uint8_t	PXP_Type::RESERVED_1 [12]
uint8_t	TSC_Type::RESERVED_1 [12]
uint8_t	USBPHY_Type::RESERVED_1 [12]
uint8_t   USB_ANALOG_Type::RESERVED_1 [12]
uint8_t	CSI_Type::RESERVED_1 [16]
uint8_t	I2S_Type::RESERVED_1 [16]
uint8_t	LPI2C_Type::RESERVED_1 [16]
uint8_t	ROMC_Type::RESERVED_1 [200]
uint8_t	CSU_Type::RESERVED_1 [20]
uint8_t	USBNC_Type::RESERVED_1 [20]
uint8_t	TEMPMON_Type::RESERVED_1 [240]
uint8_t	PIT_Type::RESERVED_1 [24]
uint8_t	XTALOSC24M_Type::RESERVED_1 [272]
uint8_t	CCM_Type::RESERVED_1 [4]
uint8_t	DMA_Type::RESERVED_1 [4]
uint8_t	ENET_Type::RESERVED_1 [4]
uint8_t	FLEXIO_Type::RESERVED_1 [4]
uint8_t	FLEXSPI_Type::RESERVED_1 [4]
uint8_t	SNVS_Type::RESERVED_1 [4]
uint8_t	USDHC_Type::RESERVED_1 [4]
uint8_t	CAN_Type::RESERVED_1 [8]
uint8_t	LPSPI_Type::RESERVED_1 [8]
uint8_t   PWM_Type::RESERVED_1 [8]
uint8_t	SEMC_Type::RESERVED_1 [8]
uint8_t	SPDIF_Type::RESERVED_1 [8]
uint8_t	FLEXIO_Type::RESERVED_10 [112]
uint8_t	DCP_Type::RESERVED_10 [12]
uint8_t	OCOTP_Type::RESERVED_10 [12]
uint8_t	PXP_Type::RESERVED_10 [12]
uint8_t	ENET_Type::RESERVED_10 [28]
uint8_t	LCDIF_Type::RESERVED_10 [380]
uint8_t	LPI2C_Type::RESERVED_10 [8]
uint8_t	LCDIF_Type::RESERVED_11 [1104]
uint8_t	FLEXIO_Type::RESERVED_11 [112]
uint8_t	LPI2C_Type::RESERVED_11 [12]
uint8_t	OCOTP_Type::RESERVED_11 [12]
uint8_t	PXP_Type::RESERVED_11 [12]
uint8_t	DCP_Type::RESERVED_11 [28]
uint8_t	ENET_Type::RESERVED_11 [56]
uint8_t	DCP_Type::RESERVED_12 [12]
uint8_t	LCDIF_Type::RESERVED_12 [12]
uint8_t	OCOTP_Type::RESERVED_12 [12]
uint8_t	PXP_Type::RESERVED_12 [12]
uint8_t	FLEXIO_Type::RESERVED_12 [368]
uint8_t	ENET_Type::RESERVED_12 [4]
uint8_t	FLEXIO_Type::RESERVED_13 [112]
uint8_t	DCP_Type::RESERVED_13 [12]
uint8_t	ENET_Type::RESERVED_13 [12]
uint8_t	LCDIF_Type::RESERVED_13 [12]
uint8_t	OCOTP_Type::RESERVED_13 [12]
uint8_t	PXP_Type::RESERVED_13 [12]
uint8_t	FLEXIO_Type::RESERVED_14 [112]
uint8_t	DCP_Type::RESERVED_14 [12]
uint8_t	LCDIF_Type::RESERVED_14 [12]
uint8_t	OCOTP_Type::RESERVED_14 [12]
uint8_t	PXP_Type::RESERVED_14 [12]
uint8_t	ENET_Type::RESERVED_14 [56]
uint8_t	DCP_Type::RESERVED_15 [12]
uint8_t	ENET_Type::RESERVED_15 [12]
uint8_t	LCDIF_Type::RESERVED_15 [12]
uint8_t	OCOTP_Type::RESERVED_15 [12]
uint8_t	PXP_Type::RESERVED_15 [12]
uint8_t	DCP_Type::RESERVED_16 [12]
uint8_t	OCOTP_Type::RESERVED_16 [12]
uint8_t	PXP_Type::RESERVED_16 [12]
uint8_t	ENET_Type::RESERVED_16 [284]
uint8_t	DCP_Type::RESERVED_17 [12]
uint8_t	OCOTP_Type::RESERVED_17 [12]
uint8_t	PXP_Type::RESERVED_17 [12]
uint8_t	ENET_Type::RESERVED_17 [488]
uint8_t	DCP_Type::RESERVED_18 [12]
uint8_t	OCOTP_Type::RESERVED_18 [12]
uint8_t	PXP_Type::RESERVED_18 [12]
uint8_t	DCP_Type::RESERVED_19 [12]
uint8_t	OCOTP_Type::RESERVED_19 [12]
uint8_t	PXP_Type::RESERVED_19 [12]
uint8_t	CCM_ANALOG_Type::RESERVED_2 [12]
uint8_t	DCP_Type::RESERVED_2 [12]
uint8_t	ENET_Type::RESERVED_2 [12]
uint8_t	FLEXIO_Type::RESERVED_2 [12]
uint8_t	OCOTP_Type::RESERVED_2 [12]
uint8_t	PXP_Type::RESERVED_2 [12]
uint8_t	SEMC_Type::RESERVED_2 [12]
uint8_t	TSC_Type::RESERVED_2 [12]
uint8_t	USB_Type::RESERVED_2 [1]
uint8_t	LCDIF_Type::RESERVED_2 [28]
uint8_t   LCDIF_Type::RESERVED_2 [28]
uint8_t	CSU_Type::RESERVED_2 [316]
uint8_t	XTALOSC24M_Type::RESERVED_2 [32]
uint8_t	I2S_Type::RESERVED_2 [36]
uint8_t	DMA_Type::RESERVED_2 [4]
uint8_t	LPI2C_Type::RESERVED_2 [4]
uint8_t	USDHC_Type::RESERVED_2 [84]
uint8_t	CAN_Type::RESERVED_2 [8]
uint8_t	CCM_Type::RESERVED_2 [8]
uint8_t	FLEXSPI_Type::RESERVED_2 [8]
uint8_t	LPSPI_Type::RESERVED_2 [8]
uint8_t	SNVS_Type::RESERVED_2 [96]
uint8_t	OCOTP_Type::RESERVED_20 [12]
uint8_t	PXP_Type::RESERVED_20 [12]
uint8_t	DCP_Type::RESERVED_20 [512]
uint8_t	DCP_Type::RESERVED_21 [12]
uint8_t	OCOTP_Type::RESERVED_21 [12]
uint8_t	PXP_Type::RESERVED_21 [12]
uint8_t	DCP_Type::RESERVED_22 [12]
uint8_t	OCOTP_Type::RESERVED_22 [12]
uint8_t	PXP_Type::RESERVED_22 [12]
uint8_t	DCP_Type::RESERVED_23 [12]
uint8_t	PXP_Type::RESERVED_23 [12]
uint8_t	OCOTP_Type::RESERVED_23 [140]
uint8_t	OCOTP_Type::RESERVED_24 [12]
uint8_t	PXP_Type::RESERVED_24 [348]
uint8_t	OCOTP_Type::RESERVED_25 [12]
uint8_t	PXP_Type::RESERVED_25 [220]
uint8_t	OCOTP_Type::RESERVED_26 [12]
uint8_t	PXP_Type::RESERVED_26 [60]
uint8_t	OCOTP_Type::RESERVED_27 [12]
uint8_t	OCOTP_Type::RESERVED_28 [12]
uint8_t	OCOTP_Type::RESERVED_29 [12]
uint8_t	CCM_ANALOG_Type::RESERVED_3 [12]
uint8_t	DCP_Type::RESERVED_3 [12]
uint8_t	LCDIF_Type::RESERVED_3 [12]
uint8_t	OCOTP_Type::RESERVED_3 [12]
uint8_t	PXP_Type::RESERVED_3 [12]
uint8_t	SEMC_Type::RESERVED_3 [12]
uint8_t	TSC_Type::RESERVED_3 [12]
uint8_t	I2S_Type::RESERVED_3 [16]
uint8_t	LPSPI_Type::RESERVED_3 [20]
uint8_t	USB_Type::RESERVED_3 [20]
uint8_t	ENET_Type::RESERVED_3 [24]
uint8_t	SNVS_Type::RESERVED_3 [2776]
uint8_t	CAN_Type::RESERVED_3 [32]
uint8_t	DMA_Type::RESERVED_3 [4]
uint8_t	LPI2C_Type::RESERVED_3 [4]
uint8_t	FLEXIO_Type::RESERVED_3 [60]
uint8_t	CCM_Type::RESERVED_3 [8]
uint8_t	FLEXSPI_Type::RESERVED_3 [8]
uint8_t	OCOTP_Type::RESERVED_30 [12]
uint8_t	OCOTP_Type::RESERVED_31 [12]
uint8_t	OCOTP_Type::RESERVED_32 [12]
uint8_t	OCOTP_Type::RESERVED_33 [12]
uint8_t	OCOTP_Type::RESERVED_34 [12]
uint8_t	OCOTP_Type::RESERVED_35 [12]
uint8_t	OCOTP_Type::RESERVED_36 [28]
uint8_t	OCOTP_Type::RESERVED_37 [12]
uint8_t	OCOTP_Type::RESERVED_38 [12]
uint8_t	OCOTP_Type::RESERVED_39 [12]
uint8_t	CAN_Type::RESERVED_4 [1024]
uint8_t	FLEXIO_Type::RESERVED_4 [112]
uint8_t	CCM_ANALOG_Type::RESERVED_4 [12]
uint8_t	DCP_Type::RESERVED_4 [12]
uint8_t	LCDIF_Type::RESERVED_4 [12]
uint8_t	OCOTP_Type::RESERVED_4 [12]
uint8_t	PXP_Type::RESERVED_4 [12]
uint8_t	TSC_Type::RESERVED_4 [12]
uint8_t	I2S_Type::RESERVED_4 [16]
uint8_t	ENET_Type::RESERVED_4 [28]
uint8_t	USB_Type::RESERVED_4 [2]
uint8_t	CCM_Type::RESERVED_4 [4]
uint8_t	DMA_Type::RESERVED_4 [4]
uint8_t	FLEXSPI_Type::RESERVED_4 [4]
uint8_t	LPI2C_Type::RESERVED_4 [4]
uint8_t	LPSPI_Type::RESERVED_4 [8]
uint8_t	OCOTP_Type::RESERVED_40 [12]
uint8_t	OCOTP_Type::RESERVED_41 [12]
uint8_t	OCOTP_Type::RESERVED_42 [12]
uint8_t	OCOTP_Type::RESERVED_43 [12]
uint8_t	OCOTP_Type::RESERVED_44 [12]
uint8_t	OCOTP_Type::RESERVED_45 [12]
uint8_t	CCM_ANALOG_Type::RESERVED_5 [12]
uint8_t	DCP_Type::RESERVED_5 [12]
uint8_t	DMA_Type::RESERVED_5 [12]
uint8_t	LCDIF_Type::RESERVED_5 [12]
uint8_t	LPI2C_Type::RESERVED_5 [12]
uint8_t	PXP_Type::RESERVED_5 [12]
uint8_t	TSC_Type::RESERVED_5 [12]
uint8_t	FLEXIO_Type::RESERVED_5 [240]
uint8_t	FLEXSPI_Type::RESERVED_5 [24]
uint8_t	USB_Type::RESERVED_5 [24]
uint8_t	ENET_Type::RESERVED_5 [28]
uint8_t	OCOTP_Type::RESERVED_5 [32]
uint8_t	CAN_Type::RESERVED_5 [96]
uint8_t	OCOTP_Type::RESERVED_6 [108]
uint8_t	FLEXIO_Type::RESERVED_6 [112]
uint8_t	DCP_Type::RESERVED_6 [12]
uint8_t	PXP_Type::RESERVED_6 [12]
uint8_t	TSC_Type::RESERVED_6 [12]
uint8_t	LPI2C_Type::RESERVED_6 [156]
uint8_t	DMA_Type::RESERVED_6 [184]
uint8_t	LCDIF_Type::RESERVED_6 [220]
uint8_t	CCM_ANALOG_Type::RESERVED_6 [28]
uint8_t	USB_Type::RESERVED_6 [4]
uint8_t	ENET_Type::RESERVED_6 [60]
uint8_t	FLEXSPI_Type::RESERVED_6 [8]
uint8_t	FLEXIO_Type::RESERVED_7 [112]
uint8_t	DCP_Type::RESERVED_7 [12]
uint8_t	LCDIF_Type::RESERVED_7 [12]
uint8_t	PXP_Type::RESERVED_7 [12]
uint8_t	TSC_Type::RESERVED_7 [12]
uint8_t	ENET_Type::RESERVED_7 [28]
uint8_t	DMA_Type::RESERVED_7 [3808]
uint8_t	LPI2C_Type::RESERVED_7 [4]
uint8_t	USB_Type::RESERVED_7 [4]
uint8_t	CCM_ANALOG_Type::RESERVED_7 [64]
uint8_t	OCOTP_Type::RESERVED_7 [764]
uint8_t	FLEXIO_Type::RESERVED_8 [112]
uint8_t	DCP_Type::RESERVED_8 [12]
uint8_t	ENET_Type::RESERVED_8 [12]
uint8_t	LCDIF_Type::RESERVED_8 [12]
uint8_t	OCOTP_Type::RESERVED_8 [12]
uint8_t	PXP_Type::RESERVED_8 [12]
uint8_t	USB_Type::RESERVED_8 [16]
uint8_t	LPI2C_Type::RESERVED_8 [20]
uint8_t	FLEXIO_Type::RESERVED_9 [112]
uint8_t	DCP_Type::RESERVED_9 [12]
uint8_t	LPI2C_Type::RESERVED_9 [12]
uint8_t	OCOTP_Type::RESERVED_9 [12]
uint8_t	PXP_Type::RESERVED_9 [12]
uint8_t	ENET_Type::RESERVED_9 [20]
uint8_t	USB_Type::RESERVED_9 [28]
uint8_t	LCDIF_Type::RESERVED_9 [76]
__IO uint16_t	ENC_Type::REV
__I uint16_t	ENC_Type::REVH
__I uint32_t	FLEXSPI_Type::RFDR [32]
__I uint32_t	I2S_Type::RFR [4]
__I uint32_t	ENET_Type::RMON_R_BC_PKT
__I uint32_t	ENET_Type::RMON_R_CRC_ALIGN
__I uint32_t	ENET_Type::RMON_R_FRAG
__I uint32_t	ENET_Type::RMON_R_JAB
__I uint32_t	ENET_Type::RMON_R_MC_PKT
__I uint32_t	ENET_Type::RMON_R_OCTETS
__I uint32_t	ENET_Type::RMON_R_OVERSIZE
__I uint32_t	ENET_Type::RMON_R_P1024TO2047
__I uint32_t	ENET_Type::RMON_R_P128TO255
__I uint32_t	ENET_Type::RMON_R_P256TO511
__I uint32_t	ENET_Type::RMON_R_P512TO1023
__I uint32_t	ENET_Type::RMON_R_P64
__I uint32_t	ENET_Type::RMON_R_P65TO127
__I uint32_t	ENET_Type::RMON_R_P_GTE2048
__I uint32_t	ENET_Type::RMON_R_PACKETS
uint32_t	ENET_Type::RMON_R_RESVD_0
__I uint32_t	ENET_Type::RMON_R_UNDERSIZE
__I uint32_t	ENET_Type::RMON_T_BC_PKT
__I uint32_t	ENET_Type::RMON_T_COL
__I uint32_t	ENET_Type::RMON_T_CRC_ALIGN
uint32_t	ENET_Type::RMON_T_DROP
__I uint32_t	ENET_Type::RMON_T_FRAG
__I uint32_t	ENET_Type::RMON_T_JAB
__I uint32_t	ENET_Type::RMON_T_MC_PKT
__I uint32_t	ENET_Type::RMON_T_OCTETS
__I uint32_t	ENET_Type::RMON_T_OVERSIZE
__I uint32_t	ENET_Type::RMON_T_P1024TO2047
__I uint32_t	ENET_Type::RMON_T_P128TO255
__I uint32_t	ENET_Type::RMON_T_P256TO511
__I uint32_t	ENET_Type::RMON_T_P512TO1023
__I uint32_t	ENET_Type::RMON_T_P64
__I uint32_t	ENET_Type::RMON_T_P65TO127
__I uint32_t	ENET_Type::RMON_T_P_GTE2048
__I uint32_t	ENET_Type::RMON_T_PACKETS
__I uint32_t	ENET_Type::RMON_T_UNDERSIZE
__IO uint32_t	I2S_Type::RMR
__IO uint32_t	ROMC_Type::ROMPATCHA [16]
__IO uint32_t	ROMC_Type::ROMPATCHCNTL
__IO uint32_t	ROMC_Type::ROMPATCHD [8]
uint32_t	ROMC_Type::ROMPATCHENH
__IO uint32_t	ROMC_Type::ROMPATCHENL
__IO uint32_t	ROMC_Type::ROMPATCHSR
__IO uint32_t	ENET_Type::RSEM
__IO uint32_t	ENET_Type::RSFL
__I uint32_t	LPSPI_Type::RSR
__IO uint32_t	USBPHY_Type::RX
__IO uint32_t	CAN_Type::RX14MASK
__IO uint32_t	CAN_Type::RX15MASK
__IO uint32_t	USBPHY_Type::RX_CLR
__IO uint32_t	USBPHY_Type::RX_SET
__IO uint32_t	USBPHY_Type::RX_TOG
__IO uint32_t	CAN_Type::RXFGMASK
__I uint32_t	CAN_Type::RXFIR
__IO uint32_t	ENET_Type::RXIC
__IO uint32_t	CAN_Type::RXIMR [64]
__IO uint32_t	CAN_Type::RXMGMASK
__IO uint32_t	CSU_Type::SA
__IO uint32_t   DMA_Type::SADDR
__IO uint32_t	LPI2C_Type::SAMR
__I uint32_t	LPI2C_Type::SASR
__IO uint32_t   TRNG_Type::SBLIM
__I uint32_t	SRC_Type::SBMR1
__I uint32_t	SRC_Type::SBMR2
__IO uint32_t	USB_Type::SBUSCFG
__IO uint32_t	LPI2C_Type::SCFGR1
__IO uint32_t	LPI2C_Type::SCFGR2
__I uint32_t   TRNG_Type::SCMC
__IO uint32_t	TRNG_Type::SCMISC
__IO uint32_t   TRNG_Type::SCML
__IO uint8_t	CMP_Type::SCR
__IO uint32_t	LPI2C_Type::SCR
__IO uint32_t	SPDIF_Type::SCR
__IO uint32_t	SRC_Type::SCR
__I uint32_t   TRNG_Type::SCR1C
__IO uint32_t   TRNG_Type::SCR1L
__I uint32_t   TRNG_Type::SCR2C
__IO uint32_t   TRNG_Type::SCR2L
__I uint32_t   TRNG_Type::SCR3C
__IO uint32_t   TRNG_Type::SCR3L
__I uint32_t   TRNG_Type::SCR4C
__IO uint32_t   TRNG_Type::SCR4L
__I uint32_t   TRNG_Type::SCR5C
__IO uint32_t   TRNG_Type::SCR5L
__I uint32_t   TRNG_Type::SCR6PC
__IO uint32_t   TRNG_Type::SCR6PL
__IO uint32_t	OCOTP_Type::SCS
__IO uint32_t	OCOTP_Type::SCS_CLR
__IO uint32_t	OCOTP_Type::SCS_SET
__IO uint32_t	OCOTP_Type::SCS_TOG
__IO uint16_t   TMR_Type::SCTRL
__IO uint32_t	TRNG_Type::SDCTL
__IO uint32_t	LPI2C_Type::SDER
__IO uint32_t	SEMC_Type::SDRAMCR0
__IO uint32_t	SEMC_Type::SDRAMCR1
__IO uint32_t	SEMC_Type::SDRAMCR2
__IO uint32_t	SEMC_Type::SDRAMCR3
__IO uint32_t	TRNG_Type::SEC_CFG
__O uint8_t	DMA_Type::SEEI
__IO uint16_t	XBARA_Type::SEL0
__IO uint16_t	XBARB_Type::SEL0
__IO uint16_t	XBARA_Type::SEL1
__IO uint16_t	XBARB_Type::SEL1
__IO uint16_t	XBARA_Type::SEL10
__IO uint16_t	XBARA_Type::SEL11
__IO uint16_t	XBARA_Type::SEL12
__IO uint16_t	XBARA_Type::SEL13
__IO uint16_t	XBARA_Type::SEL14
__IO uint16_t	XBARA_Type::SEL15
__IO uint16_t	XBARA_Type::SEL16
__IO uint16_t	XBARA_Type::SEL17
__IO uint16_t	XBARA_Type::SEL18
__IO uint16_t	XBARA_Type::SEL19
__IO uint16_t	XBARA_Type::SEL2
__IO uint16_t	XBARB_Type::SEL2
__IO uint16_t	XBARA_Type::SEL20
__IO uint16_t	XBARA_Type::SEL21
__IO uint16_t	XBARA_Type::SEL22
__IO uint16_t	XBARA_Type::SEL23
__IO uint16_t	XBARA_Type::SEL24
__IO uint16_t	XBARA_Type::SEL25
__IO uint16_t	XBARA_Type::SEL26
__IO uint16_t	XBARA_Type::SEL27
__IO uint16_t	XBARA_Type::SEL28
__IO uint16_t	XBARA_Type::SEL29
__IO uint16_t	XBARA_Type::SEL3
__IO uint16_t	XBARB_Type::SEL3
__IO uint16_t	XBARA_Type::SEL30
__IO uint16_t	XBARA_Type::SEL31
__IO uint16_t	XBARA_Type::SEL32
__IO uint16_t	XBARA_Type::SEL33
__IO uint16_t	XBARA_Type::SEL34
__IO uint16_t	XBARA_Type::SEL35
__IO uint16_t	XBARA_Type::SEL36
__IO uint16_t	XBARA_Type::SEL37
__IO uint16_t	XBARA_Type::SEL38
__IO uint16_t	XBARA_Type::SEL39
__IO uint16_t	XBARA_Type::SEL4
__IO uint16_t	XBARB_Type::SEL4
__IO uint16_t	XBARA_Type::SEL40
__IO uint16_t	XBARA_Type::SEL41
__IO uint16_t	XBARA_Type::SEL42
__IO uint16_t	XBARA_Type::SEL43
__IO uint16_t	XBARA_Type::SEL44
__IO uint16_t	XBARA_Type::SEL45
__IO uint16_t	XBARA_Type::SEL46
__IO uint16_t	XBARA_Type::SEL47
__IO uint16_t	XBARA_Type::SEL48
__IO uint16_t	XBARA_Type::SEL49
__IO uint16_t	XBARA_Type::SEL5
__IO uint16_t	XBARB_Type::SEL5
__IO uint16_t	XBARA_Type::SEL50
__IO uint16_t	XBARA_Type::SEL51
__IO uint16_t	XBARA_Type::SEL52
__IO uint16_t	XBARA_Type::SEL53
__IO uint16_t	XBARA_Type::SEL54
__IO uint16_t	XBARA_Type::SEL55
__IO uint16_t	XBARA_Type::SEL56
__IO uint16_t	XBARA_Type::SEL57
__IO uint16_t	XBARA_Type::SEL58
__IO uint16_t	XBARA_Type::SEL59
__IO uint16_t	XBARA_Type::SEL6
__IO uint16_t	XBARB_Type::SEL6
__IO uint16_t	XBARA_Type::SEL60
__IO uint16_t	XBARA_Type::SEL61
__IO uint16_t	XBARA_Type::SEL62
__IO uint16_t	XBARA_Type::SEL63
__IO uint16_t	XBARA_Type::SEL64
__IO uint16_t	XBARA_Type::SEL65
__IO uint16_t	XBARA_Type::SEL7
__IO uint16_t	XBARB_Type::SEL7
__IO uint16_t	XBARA_Type::SEL8
__IO uint16_t	XBARA_Type::SEL9
__IO uint32_t	IOMUXC_Type::SELECT_INPUT [154]
__O uint8_t	DMA_Type::SERQ
__O uint8_t	EWM_Type::SERV
__IO uint32_t	FLEXIO_Type::SHIFTBUF [4]
__IO uint32_t	FLEXIO_Type::SHIFTBUFBBS [4]
__IO uint32_t	FLEXIO_Type::SHIFTBUFBIS [4]
__IO uint32_t	FLEXIO_Type::SHIFTBUFBYS [4]
__IO uint32_t	FLEXIO_Type::SHIFTBUFHWS [4]
__IO uint32_t	FLEXIO_Type::SHIFTBUFNBS [4]
__IO uint32_t	FLEXIO_Type::SHIFTBUFNIS [4]
__IO uint32_t	FLEXIO_Type::SHIFTCFG [4]
__IO uint32_t	FLEXIO_Type::SHIFTCTL [4]
__IO uint32_t	FLEXIO_Type::SHIFTEIEN
__IO uint32_t	FLEXIO_Type::SHIFTERR
__IO uint32_t	FLEXIO_Type::SHIFTSDEN
__IO uint32_t	FLEXIO_Type::SHIFTSIEN
__IO uint32_t	FLEXIO_Type::SHIFTSTAT
__IO uint32_t	FLEXIO_Type::SHIFTSTATE
__O uint32_t   SPDIF_Type::SIC
__IO uint32_t	SPDIF_Type::SIE
__IO uint32_t	LPI2C_Type::SIER
__I uint32_t   SPDIF_Type::SIS
__IO uint32_t	OCOTP_Type::SJC_RESP0
__IO uint32_t	OCOTP_Type::SJC_RESP1
__IO uint32_t   DMA_Type::SLAST
struct {
__IO uint16_t   PWM_Type::CAPTCOMPA
__IO uint16_t   PWM_Type::CAPTCOMPB
__IO uint16_t   PWM_Type::CAPTCOMPX
__IO uint16_t   PWM_Type::CAPTCTRLA
__IO uint16_t   PWM_Type::CAPTCTRLB
__IO uint16_t   PWM_Type::CAPTCTRLX
__I uint16_t   PWM_Type::CNT
__IO uint16_t   PWM_Type::CTRL
__IO uint16_t   PWM_Type::CTRL2
__I uint16_t   PWM_Type::CVAL0
__I uint16_t   PWM_Type::CVAL0CYC
__I uint16_t   PWM_Type::CVAL1
__I uint16_t   PWM_Type::CVAL1CYC
__I uint16_t   PWM_Type::CVAL2
__I uint16_t   PWM_Type::CVAL2CYC
__I uint16_t   PWM_Type::CVAL3
__I uint16_t   PWM_Type::CVAL3CYC
__I uint16_t   PWM_Type::CVAL4
__I uint16_t   PWM_Type::CVAL4CYC
__I uint16_t   PWM_Type::CVAL5
__I uint16_t   PWM_Type::CVAL5CYC
__IO uint16_t   PWM_Type::DISMAP [2]
__IO uint16_t   PWM_Type::DMAEN
__IO uint16_t   PWM_Type::DTCNT0
__IO uint16_t   PWM_Type::DTCNT1
__IO uint16_t   PWM_Type::FRACVAL1
__IO uint16_t   PWM_Type::FRACVAL2
__IO uint16_t   PWM_Type::FRACVAL3
__IO uint16_t   PWM_Type::FRACVAL4
__IO uint16_t   PWM_Type::FRACVAL5
__IO uint16_t   PWM_Type::FRCTRL
__IO uint16_t   PWM_Type::INIT
__IO uint16_t   PWM_Type::INTEN
__IO uint16_t   PWM_Type::OCTRL
uint8_t   PWM_Type::RESERVED_0 [2]
uint8_t   PWM_Type::RESERVED_1 [8]
__IO uint16_t   PWM_Type::STS
__IO uint16_t   PWM_Type::TCTRL
__IO uint16_t   PWM_Type::VAL0
__IO uint16_t   PWM_Type::VAL1
__IO uint16_t   PWM_Type::VAL2
__IO uint16_t   PWM_Type::VAL3
__IO uint16_t   PWM_Type::VAL4
__IO uint16_t   PWM_Type::VAL5
}	PWM_Type::SM [4]
__IO uint16_t   DMA_Type::SOFF
__IO uint32_t	GPT_Type::SR
__IO uint32_t	LPSPI_Type::SR
__IO uint32_t	SEMC_Type::SRAMCR0
__IO uint32_t	SEMC_Type::SRAMCR1
__IO uint32_t	SEMC_Type::SRAMCR2
uint32_t	SEMC_Type::SRAMCR3
__IO uint32_t	SPDIF_Type::SRCD
__I uint32_t	SPDIF_Type::SRCSH
__I uint32_t	SPDIF_Type::SRCSL
__I uint32_t	LPI2C_Type::SRDR
__I uint32_t	SPDIF_Type::SRFM
__IO uint32_t	OCOTP_Type::SRK0
__IO uint32_t	OCOTP_Type::SRK1
__IO uint32_t	OCOTP_Type::SRK2
__IO uint32_t	OCOTP_Type::SRK3
__IO uint32_t	OCOTP_Type::SRK4
__IO uint32_t	OCOTP_Type::SRK5
__IO uint32_t	OCOTP_Type::SRK6
__IO uint32_t	OCOTP_Type::SRK7
__IO uint32_t	OCOTP_Type::SRK_REVOKE
__I uint32_t	SPDIF_Type::SRL
__IO uint32_t	SPDIF_Type::SRPC
__I uint32_t	SPDIF_Type::SRQ
__I uint32_t	SPDIF_Type::SRR
__IO uint32_t	SRC_Type::SRSR
__I uint32_t	SPDIF_Type::SRU
__IO uint32_t	LPI2C_Type::SSR
__O uint8_t	DMA_Type::SSRT
__IO uint32_t	LPI2C_Type::STAR
__IO uint32_t	DCP_Type::STAT
__I uint32_t	LCDIF_Type::STAT
__IO uint32_t	LPUART_Type::STAT
__IO uint32_t	PXP_Type::STAT
__IO uint32_t	DCP_Type::STAT_CLR
__IO uint32_t	PXP_Type::STAT_CLR
__IO uint32_t	DCP_Type::STAT_SET
__IO uint32_t	PXP_Type::STAT_SET
__IO uint32_t	DCP_Type::STAT_TOG
__IO uint32_t	PXP_Type::STAT_TOG
__IO uint32_t	BEE_Type::STATUS
__I uint32_t	TRNG_Type::STATUS
__IO uint32_t	USBPHY_Type::STATUS
__IO uint32_t	SPDIF_Type::STC
__IO uint32_t	SPDIF_Type::STCSCH
__IO uint32_t	SPDIF_Type::STCSCL
__O uint32_t	LPI2C_Type::STDR
__O uint32_t	SPDIF_Type::STL
__O uint32_t	SPDIF_Type::STR
__IO uint16_t   PWM_Type::STS
__I uint32_t	FLEXSPI_Type::STS0
__I uint32_t	SEMC_Type::STS0
__I uint32_t	FLEXSPI_Type::STS1
uint32_t	SEMC_Type::STS1
uint32_t	SEMC_Type::STS10
uint32_t	SEMC_Type::STS11
__I uint32_t	SEMC_Type::STS12
uint32_t	SEMC_Type::STS13
uint32_t	SEMC_Type::STS14
uint32_t	SEMC_Type::STS15
__I uint32_t	FLEXSPI_Type::STS2
__I uint32_t	SEMC_Type::STS2
uint32_t	SEMC_Type::STS3
uint32_t	SEMC_Type::STS4
uint32_t	SEMC_Type::STS5
uint32_t	SEMC_Type::STS6
uint32_t	SEMC_Type::STS7
uint32_t	SEMC_Type::STS8
uint32_t	SEMC_Type::STS9
__IO uint32_t	OCOTP_Type::SW_GP1
__IO uint32_t	OCOTP_Type::SW_GP20
__IO uint32_t	OCOTP_Type::SW_GP21
__IO uint32_t	OCOTP_Type::SW_GP22
__IO uint32_t	OCOTP_Type::SW_GP23
__IO uint32_t	IOMUXC_Type::SW_MUX_CTL_PAD [124]
__IO uint32_t	IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ
__IO uint32_t	IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t	IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP
__IO uint32_t	IOMUXC_Type::SW_PAD_CTL_PAD [124]
__IO uint32_t	IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF
__IO uint32_t	IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ
__IO uint32_t	IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t	IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B
__IO uint32_t	IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE
__IO uint32_t	IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP
__IO uint32_t	OCOTP_Type::SW_STICKY
__IO uint16_t	PWM_Type::SWCOUT
__IO uint32_t	USDHC_Type::SYS_CTRL
__IO uint32_t	ENET_Type::TACC
__IO uint32_t	ENET_Type::TAEM
__IO uint32_t	ENET_Type::TAFL
__IO uint32_t   ENET_Type::TCCR
struct {
union {
__IO uint32_t   DMA_Type::NBYTES_MLNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFYES
}
union {
__IO uint16_t   DMA_Type::CITER_ELINKNO
__IO uint16_t   DMA_Type::CITER_ELINKYES
}
union {
__IO uint16_t   DMA_Type::BITER_ELINKNO
__IO uint16_t   DMA_Type::BITER_ELINKYES
}
__IO uint16_t   DMA_Type::ATTR
__IO uint16_t   DMA_Type::CSR
__IO uint32_t   DMA_Type::DADDR
__IO uint32_t   DMA_Type::DLAST_SGA
__IO uint16_t   DMA_Type::DOFF
__IO uint32_t   DMA_Type::SADDR
__IO uint32_t   DMA_Type::SLAST
__IO uint16_t   DMA_Type::SOFF
}	DMA_Type::TCD [32]
__IO uint32_t	FLEXRAM_Type::TCM_CTRL
__IO uint32_t	ENET_Type::TCR
__IO uint32_t	LPSPI_Type::TCR
__IO uint32_t	I2S_Type::TCR1
__IO uint32_t	I2S_Type::TCR2
__IO uint32_t	I2S_Type::TCR3
__IO uint32_t	I2S_Type::TCR4
__IO uint32_t	I2S_Type::TCR5
__IO uint32_t   ENET_Type::TCSR
__IO uint32_t	I2S_Type::TCSR
__IO uint32_t   PIT_Type::TCTRL
__IO uint16_t   PWM_Type::TCTRL
__IO uint32_t	ENET_Type::TDAR
__O uint32_t	I2S_Type::TDR [4]
__O uint32_t	LPSPI_Type::TDR
__IO uint32_t	ENET_Type::TDSR
__IO uint32_t	TEMPMON_Type::TEMPSENSE0
__IO uint32_t	TEMPMON_Type::TEMPSENSE0_CLR
__IO uint32_t	TEMPMON_Type::TEMPSENSE0_SET
__IO uint32_t	TEMPMON_Type::TEMPSENSE0_TOG
__IO uint32_t	TEMPMON_Type::TEMPSENSE1
__IO uint32_t	TEMPMON_Type::TEMPSENSE1_CLR
__IO uint32_t	TEMPMON_Type::TEMPSENSE1_SET
__IO uint32_t	TEMPMON_Type::TEMPSENSE1_TOG
__IO uint32_t	TEMPMON_Type::TEMPSENSE2
__IO uint32_t	TEMPMON_Type::TEMPSENSE2_CLR
__IO uint32_t	TEMPMON_Type::TEMPSENSE2_SET
__IO uint32_t	TEMPMON_Type::TEMPSENSE2_TOG
__O uint32_t	FLEXSPI_Type::TFDR [32]
__IO uint32_t   PIT_Type::TFLG
__I uint32_t	I2S_Type::TFR [4]
__IO uint32_t	ENET_Type::TFWR
__IO uint32_t	ENET_Type::TGSR
__IO uint32_t	LCDIF_Type::THRES
__IO uint32_t	FLEXIO_Type::TIMCFG [4]
__IO uint32_t	FLEXIO_Type::TIMCMP [4]
__IO uint32_t	FLEXIO_Type::TIMCTL [4]
__IO uint32_t	CAN_Type::TIMER
__IO uint32_t	FLEXIO_Type::TIMIEN
__IO uint32_t	OCOTP_Type::TIMING
__IO uint32_t	OCOTP_Type::TIMING2
__IO uint32_t	FLEXIO_Type::TIMSTAT
__IO uint32_t	ENET_Type::TIPG
__IO uint32_t	I2S_Type::TMR
__I uint32_t   TRNG_Type::TOTSAM
__IO uint32_t	RTWDOG_Type::TOVAL
__IO uint32_t	LCDIF_Type::TRANSFER_COUNT
struct {
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
__IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
__IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
}	ADC_ETC_Type::TRIG [8]
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
__IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
__IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
__IO uint32_t	ENET_Type::TSEM
__IO uint16_t	ENC_Type::TST
__IO uint32_t	USDHC_Type::TUNING_CTRL
__IO uint32_t	USBPHY_Type::TX
__IO uint32_t	USBPHY_Type::TX_CLR
__IO uint32_t	USBPHY_Type::TX_SET
__IO uint32_t	USBPHY_Type::TX_TOG
__IO uint32_t	USB_Type::TXFILLTUNING
__IO uint32_t	ENET_Type::TXIC
__IO uint16_t	ENC_Type::UCOMP
__IO uint16_t	ENC_Type::UINIT
__IO uint16_t	ENC_Type::UMOD
__IO uint16_t	ENC_Type::UPOS
__I uint16_t	ENC_Type::UPOSH
__IO uint32_t	USBNC_Type::USB_OTGn_CTRL
__IO uint32_t	USBNC_Type::USB_OTGn_PHY_CTRL_0
__IO uint32_t	USB_Type::USBCMD
__IO uint32_t	USB_Type::USBINTR
__IO uint32_t	USB_Type::USBMODE
__IO uint32_t	USB_Type::USBSTS
__IO uint16_t   PWM_Type::VAL0
__IO uint16_t   PWM_Type::VAL1
__IO uint16_t   PWM_Type::VAL2
__IO uint16_t   PWM_Type::VAL3
__IO uint16_t   PWM_Type::VAL4
__IO uint16_t   PWM_Type::VAL5
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_CLR
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_SET
__I uint32_t   USB_ANALOG_Type::VBUS_DETECT_STAT
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_TOG
__IO uint32_t	LCDIF_Type::VDCTRL0
__IO uint32_t	LCDIF_Type::VDCTRL0_CLR
__IO uint32_t	LCDIF_Type::VDCTRL0_SET
__IO uint32_t	LCDIF_Type::VDCTRL0_TOG
__IO uint32_t	LCDIF_Type::VDCTRL1
__IO uint32_t	LCDIF_Type::VDCTRL2
__IO uint32_t	LCDIF_Type::VDCTRL3
__IO uint32_t	LCDIF_Type::VDCTRL4
__IO uint32_t	USDHC_Type::VEND_SPEC
__IO uint32_t	USDHC_Type::VEND_SPEC2
__I uint32_t	FLEXIO_Type::VERID
__I uint32_t	I2S_Type::VERID
__I uint32_t	LPI2C_Type::VERID
__I uint32_t	LPSPI_Type::VERID
__I uint32_t	LPUART_Type::VERID
__I uint32_t	DCP_Type::VERSION
__I uint32_t	OCOTP_Type::VERSION
__I uint32_t	USBPHY_Type::VERSION
__I uint32_t	TRNG_Type::VID1
__I uint32_t	TRNG_Type::VID2
__IO uint32_t	LPUART_Type::WATER
__IO uint16_t	WDOG_Type::WCR
__IO uint16_t	WDOG_Type::WICR
__IO uint32_t	RTWDOG_Type::WIN
__IO uint16_t	WDOG_Type::WMCR
__IO uint32_t   CAN_Type::WORD0
__IO uint32_t   CAN_Type::WORD1
__I uint16_t	WDOG_Type::WRSR
__IO uint16_t	WDOG_Type::WSR
__IO uint32_t	USDHC_Type::WTMK_LVL
__IO uint16_t	ENC_Type::WTR

Detailed Description

Typedef Documentation

iomuxc_select_input_t

typedef enum _iomuxc_select_input iomuxc_select_input_t

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

iomuxc_sw_mux_ctl_pad_t

typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

iomuxc_sw_pad_ctl_pad_t

typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

xbar_input_signal_t

typedef enum _xbar_input_signal xbar_input_signal_t

xbar_output_signal_t

typedef enum _xbar_output_signal xbar_output_signal_t

Enumeration Type Documentation

_iomuxc_select_input

enum _iomuxc_select_input

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

Enumerator
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CCM_PMIC_READY_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA02_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA03_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA04_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA05_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA06_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA07_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA08_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_DATA09_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_HSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_PIXCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_CSI_VSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET_MDIO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET0_RXDATA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET1_RXDATA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET_RXEN_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET_RXERR_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET0_TIMER_SELECT_INPUT	IOMUXC select input index
kIOMUXC_ENET_TXCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C1_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C1_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C2_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C2_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C3_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C3_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C4_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPI2C4_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI1_PCS0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI1_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI1_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI1_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI2_PCS0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI2_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI2_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI2_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI3_PCS0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI3_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI3_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI3_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI4_PCS0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI4_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI4_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSPI4_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART2_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART2_TX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART3_CTS_B_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART3_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART3_TX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART4_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART4_TX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART5_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART5_TX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART6_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART6_TX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART7_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART7_TX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART8_RX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPUART8_TX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_NMI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_MCLK2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI2_MCLK2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_SPDIF_IN_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USB_OTG2_OC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USB_OTG1_OC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC1_CD_B_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC1_WP_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_CLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_CD_B_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_CMD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA0_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA1_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA2_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA3_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA4_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA5_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA6_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_DATA7_SELECT_INPUT	IOMUXC select input index
kIOMUXC_USDHC2_WP_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN02_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN03_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN04_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN05_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN06_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN07_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN08_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN09_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN17_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN18_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN20_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN22_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN23_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN24_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN14_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN15_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN16_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN25_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN19_SELECT_INPUT	IOMUXC select input index
kIOMUXC_XBAR1_IN21_SELECT_INPUT	IOMUXC select input index

Definition at line 715 of file MIMXRT1052.h.

_iomuxc_sw_mux_ctl_pad

enum _iomuxc_sw_mux_ctl_pad

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

Enumerator
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11	IOMUXC SW_MUX_CTL_PAD index

Definition at line 437 of file MIMXRT1052.h.

_iomuxc_sw_pad_ctl_pad

enum _iomuxc_sw_pad_ctl_pad

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

Enumerator
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11	IOMUXC SW_PAD_CTL_PAD index

Definition at line 580 of file MIMXRT1052.h.

_xbar_input_signal

enum _xbar_input_signal

Enumerator
kXBARA1_InputLogicLow	LOGIC_LOW output assigned to XBARA1_IN0 input.
kXBARA1_InputLogicHigh	LOGIC_HIGH output assigned to XBARA1_IN1 input.
kXBARA1_InputIomuxXbarIn02	IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input.
kXBARA1_InputIomuxXbarIn03	IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input.
kXBARA1_InputIomuxXbarInout04	IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input.
kXBARA1_InputIomuxXbarInout05	IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input.
kXBARA1_InputIomuxXbarInout06	IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input.
kXBARA1_InputIomuxXbarInout07	IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input.
kXBARA1_InputIomuxXbarInout08	IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input.
kXBARA1_InputIomuxXbarInout09	IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input.
kXBARA1_InputIomuxXbarInout10	IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input.
kXBARA1_InputIomuxXbarInout11	IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input.
kXBARA1_InputIomuxXbarInout12	IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input.
kXBARA1_InputIomuxXbarInout13	IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input.
kXBARA1_InputIomuxXbarInout14	IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input.
kXBARA1_InputIomuxXbarInout15	IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input.
kXBARA1_InputIomuxXbarInout16	IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input.
kXBARA1_InputIomuxXbarInout17	IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input.
kXBARA1_InputIomuxXbarInout18	IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input.
kXBARA1_InputIomuxXbarInout19	IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input.
kXBARA1_InputIomuxXbarIn20	IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input.
kXBARA1_InputIomuxXbarIn21	IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input.
kXBARA1_InputIomuxXbarIn22	IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input.
kXBARA1_InputIomuxXbarIn23	IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input.
kXBARA1_InputIomuxXbarIn24	IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input.
kXBARA1_InputIomuxXbarIn25	IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input.
kXBARA1_InputAcmp1Out	ACMP1_OUT output assigned to XBARA1_IN26 input.
kXBARA1_InputAcmp2Out	ACMP2_OUT output assigned to XBARA1_IN27 input.
kXBARA1_InputAcmp3Out	ACMP3_OUT output assigned to XBARA1_IN28 input.
kXBARA1_InputAcmp4Out	ACMP4_OUT output assigned to XBARA1_IN29 input.
kXBARA1_InputRESERVED30	XBARA1_IN30 input is reserved.
kXBARA1_InputRESERVED31	XBARA1_IN31 input is reserved.
kXBARA1_InputQtimer3Tmr0Output	QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input.
kXBARA1_InputQtimer3Tmr1Output	QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input.
kXBARA1_InputQtimer3Tmr2Output	QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input.
kXBARA1_InputQtimer3Tmr3Output	QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input.
kXBARA1_InputQtimer4Tmr0Output	QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input.
kXBARA1_InputQtimer4Tmr1Output	QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input.
kXBARA1_InputQtimer4Tmr2Output	QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input.
kXBARA1_InputQtimer4Tmr3Output	QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input.
kXBARA1_InputFlexpwm1Pwm1OutTrig01	FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input.
kXBARA1_InputFlexpwm1Pwm2OutTrig01	FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input.
kXBARA1_InputFlexpwm1Pwm3OutTrig01	FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input.
kXBARA1_InputFlexpwm1Pwm4OutTrig01	FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input.
kXBARA1_InputFlexpwm2Pwm1OutTrig01	FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input.
kXBARA1_InputFlexpwm2Pwm2OutTrig01	FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input.
kXBARA1_InputFlexpwm2Pwm3OutTrig01	FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input.
kXBARA1_InputFlexpwm2Pwm4OutTrig01	FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input.
kXBARA1_InputFlexpwm3Pwm1OutTrig01	FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input.
kXBARA1_InputFlexpwm3Pwm2OutTrig01	FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input.
kXBARA1_InputFlexpwm3Pwm3OutTrig01	FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input.
kXBARA1_InputFlexpwm3Pwm4OutTrig01	FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input.
kXBARA1_InputFlexpwm4Pwm1OutTrig01	FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input.
kXBARA1_InputFlexpwm4Pwm2OutTrig01	FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input.
kXBARA1_InputFlexpwm4Pwm3OutTrig01	FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input.
kXBARA1_InputFlexpwm4Pwm4OutTrig01	FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input.
kXBARA1_InputPitTrigger0	PIT_TRIGGER0 output assigned to XBARA1_IN56 input.
kXBARA1_InputPitTrigger1	PIT_TRIGGER1 output assigned to XBARA1_IN57 input.
kXBARA1_InputPitTrigger2	PIT_TRIGGER2 output assigned to XBARA1_IN58 input.
kXBARA1_InputPitTrigger3	PIT_TRIGGER3 output assigned to XBARA1_IN59 input.
kXBARA1_InputEnc1PosMatch	ENC1_POS_MATCH output assigned to XBARA1_IN60 input.
kXBARA1_InputEnc2PosMatch	ENC2_POS_MATCH output assigned to XBARA1_IN61 input.
kXBARA1_InputEnc3PosMatch	ENC3_POS_MATCH output assigned to XBARA1_IN62 input.
kXBARA1_InputEnc4PosMatch	ENC4_POS_MATCH output assigned to XBARA1_IN63 input.
kXBARA1_InputDmaDone0	DMA_DONE0 output assigned to XBARA1_IN64 input.
kXBARA1_InputDmaDone1	DMA_DONE1 output assigned to XBARA1_IN65 input.
kXBARA1_InputDmaDone2	DMA_DONE2 output assigned to XBARA1_IN66 input.
kXBARA1_InputDmaDone3	DMA_DONE3 output assigned to XBARA1_IN67 input.
kXBARA1_InputDmaDone4	DMA_DONE4 output assigned to XBARA1_IN68 input.
kXBARA1_InputDmaDone5	DMA_DONE5 output assigned to XBARA1_IN69 input.
kXBARA1_InputDmaDone6	DMA_DONE6 output assigned to XBARA1_IN70 input.
kXBARA1_InputDmaDone7	DMA_DONE7 output assigned to XBARA1_IN71 input.
kXBARA1_InputAoi1Out0	AOI1_OUT0 output assigned to XBARA1_IN72 input.
kXBARA1_InputAoi1Out1	AOI1_OUT1 output assigned to XBARA1_IN73 input.
kXBARA1_InputAoi1Out2	AOI1_OUT2 output assigned to XBARA1_IN74 input.
kXBARA1_InputAoi1Out3	AOI1_OUT3 output assigned to XBARA1_IN75 input.
kXBARA1_InputAoi2Out0	AOI2_OUT0 output assigned to XBARA1_IN76 input.
kXBARA1_InputAoi2Out1	AOI2_OUT1 output assigned to XBARA1_IN77 input.
kXBARA1_InputAoi2Out2	AOI2_OUT2 output assigned to XBARA1_IN78 input.
kXBARA1_InputAoi2Out3	AOI2_OUT3 output assigned to XBARA1_IN79 input.
kXBARA1_InputAdcEtcXbar0Coco0	ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input.
kXBARA1_InputAdcEtcXbar0Coco1	ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input.
kXBARA1_InputAdcEtcXbar0Coco2	ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input.
kXBARA1_InputAdcEtcXbar0Coco3	ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input.
kXBARA1_InputAdcEtcXbar1Coco0	ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input.
kXBARA1_InputAdcEtcXbar1Coco1	ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input.
kXBARA1_InputAdcEtcXbar1Coco2	ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input.
kXBARA1_InputAdcEtcXbar1Coco3	ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input.
kXBARB2_InputLogicLow	LOGIC_LOW output assigned to XBARB2_IN0 input.
kXBARB2_InputLogicHigh	LOGIC_HIGH output assigned to XBARB2_IN1 input.
kXBARB2_InputRESERVED2	XBARB2_IN2 input is reserved.
kXBARB2_InputRESERVED3	XBARB2_IN3 input is reserved.
kXBARB2_InputRESERVED4	XBARB2_IN4 input is reserved.
kXBARB2_InputRESERVED5	XBARB2_IN5 input is reserved.
kXBARB2_InputAcmp1Out	ACMP1_OUT output assigned to XBARB2_IN6 input.
kXBARB2_InputAcmp2Out	ACMP2_OUT output assigned to XBARB2_IN7 input.
kXBARB2_InputAcmp3Out	ACMP3_OUT output assigned to XBARB2_IN8 input.
kXBARB2_InputAcmp4Out	ACMP4_OUT output assigned to XBARB2_IN9 input.
kXBARB2_InputRESERVED10	XBARB2_IN10 input is reserved.
kXBARB2_InputRESERVED11	XBARB2_IN11 input is reserved.
kXBARB2_InputQtimer3Tmr0Output	QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input.
kXBARB2_InputQtimer3Tmr1Output	QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input.
kXBARB2_InputQtimer3Tmr2Output	QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input.
kXBARB2_InputQtimer3Tmr3Output	QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input.
kXBARB2_InputQtimer4Tmr0Output	QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input.
kXBARB2_InputQtimer4Tmr1Output	QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input.
kXBARB2_InputQtimer4Tmr2Output	QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input.
kXBARB2_InputQtimer4Tmr3Output	QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input.
kXBARB2_InputFlexpwm1Pwm1OutTrig01	FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input.
kXBARB2_InputFlexpwm1Pwm2OutTrig01	FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input.
kXBARB2_InputFlexpwm1Pwm3OutTrig01	FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input.
kXBARB2_InputFlexpwm1Pwm4OutTrig01	FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input.
kXBARB2_InputFlexpwm2Pwm1OutTrig01	FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input.
kXBARB2_InputFlexpwm2Pwm2OutTrig01	FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input.
kXBARB2_InputFlexpwm2Pwm3OutTrig01	FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input.
kXBARB2_InputFlexpwm2Pwm4OutTrig01	FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input.
kXBARB2_InputFlexpwm3Pwm1OutTrig01	FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input.
kXBARB2_InputFlexpwm3Pwm2OutTrig01	FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input.
kXBARB2_InputFlexpwm3Pwm3OutTrig01	FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input.
kXBARB2_InputFlexpwm3Pwm4OutTrig01	FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input.
kXBARB2_InputFlexpwm4Pwm1OutTrig01	FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input.
kXBARB2_InputFlexpwm4Pwm2OutTrig01	FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input.
kXBARB2_InputFlexpwm4Pwm3OutTrig01	FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input.
kXBARB2_InputFlexpwm4Pwm4OutTrig01	FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input.
kXBARB2_InputPitTrigger0	PIT_TRIGGER0 output assigned to XBARB2_IN36 input.
kXBARB2_InputPitTrigger1	PIT_TRIGGER1 output assigned to XBARB2_IN37 input.
kXBARB2_InputAdcEtcXbar0Coco0	ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input.
kXBARB2_InputAdcEtcXbar0Coco1	ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input.
kXBARB2_InputAdcEtcXbar0Coco2	ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input.
kXBARB2_InputAdcEtcXbar0Coco3	ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input.
kXBARB2_InputAdcEtcXbar1Coco0	ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input.
kXBARB2_InputAdcEtcXbar1Coco1	ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input.
kXBARB2_InputAdcEtcXbar1Coco2	ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input.
kXBARB2_InputAdcEtcXbar1Coco3	ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input.
kXBARB2_InputEnc1PosMatch	ENC1_POS_MATCH output assigned to XBARB2_IN46 input.
kXBARB2_InputEnc2PosMatch	ENC2_POS_MATCH output assigned to XBARB2_IN47 input.
kXBARB2_InputEnc3PosMatch	ENC3_POS_MATCH output assigned to XBARB2_IN48 input.
kXBARB2_InputEnc4PosMatch	ENC4_POS_MATCH output assigned to XBARB2_IN49 input.
kXBARB2_InputDmaDone0	DMA_DONE0 output assigned to XBARB2_IN50 input.
kXBARB2_InputDmaDone1	DMA_DONE1 output assigned to XBARB2_IN51 input.
kXBARB2_InputDmaDone2	DMA_DONE2 output assigned to XBARB2_IN52 input.
kXBARB2_InputDmaDone3	DMA_DONE3 output assigned to XBARB2_IN53 input.
kXBARB2_InputDmaDone4	DMA_DONE4 output assigned to XBARB2_IN54 input.
kXBARB2_InputDmaDone5	DMA_DONE5 output assigned to XBARB2_IN55 input.
kXBARB2_InputDmaDone6	DMA_DONE6 output assigned to XBARB2_IN56 input.
kXBARB2_InputDmaDone7	DMA_DONE7 output assigned to XBARB2_IN57 input.
kXBARB3_InputLogicLow	LOGIC_LOW output assigned to XBARB3_IN0 input.
kXBARB3_InputLogicHigh	LOGIC_HIGH output assigned to XBARB3_IN1 input.
kXBARB3_InputRESERVED2	XBARB3_IN2 input is reserved.
kXBARB3_InputRESERVED3	XBARB3_IN3 input is reserved.
kXBARB3_InputRESERVED4	XBARB3_IN4 input is reserved.
kXBARB3_InputRESERVED5	XBARB3_IN5 input is reserved.
kXBARB3_InputAcmp1Out	ACMP1_OUT output assigned to XBARB3_IN6 input.
kXBARB3_InputAcmp2Out	ACMP2_OUT output assigned to XBARB3_IN7 input.
kXBARB3_InputAcmp3Out	ACMP3_OUT output assigned to XBARB3_IN8 input.
kXBARB3_InputAcmp4Out	ACMP4_OUT output assigned to XBARB3_IN9 input.
kXBARB3_InputRESERVED10	XBARB3_IN10 input is reserved.
kXBARB3_InputRESERVED11	XBARB3_IN11 input is reserved.
kXBARB3_InputQtimer3Tmr0Output	QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input.
kXBARB3_InputQtimer3Tmr1Output	QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input.
kXBARB3_InputQtimer3Tmr2Output	QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input.
kXBARB3_InputQtimer3Tmr3Output	QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input.
kXBARB3_InputQtimer4Tmr0Output	QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input.
kXBARB3_InputQtimer4Tmr1Output	QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input.
kXBARB3_InputQtimer4Tmr2Output	QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input.
kXBARB3_InputQtimer4Tmr3Output	QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input.
kXBARB3_InputFlexpwm1Pwm1OutTrig01	FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input.
kXBARB3_InputFlexpwm1Pwm2OutTrig01	FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input.
kXBARB3_InputFlexpwm1Pwm3OutTrig01	FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input.
kXBARB3_InputFlexpwm1Pwm4OutTrig01	FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input.
kXBARB3_InputFlexpwm2Pwm1OutTrig01	FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input.
kXBARB3_InputFlexpwm2Pwm2OutTrig01	FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input.
kXBARB3_InputFlexpwm2Pwm3OutTrig01	FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input.
kXBARB3_InputFlexpwm2Pwm4OutTrig01	FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input.
kXBARB3_InputFlexpwm3Pwm1OutTrig01	FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input.
kXBARB3_InputFlexpwm3Pwm2OutTrig01	FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input.
kXBARB3_InputFlexpwm3Pwm3OutTrig01	FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input.
kXBARB3_InputFlexpwm3Pwm4OutTrig01	FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input.
kXBARB3_InputFlexpwm4Pwm1OutTrig01	FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input.
kXBARB3_InputFlexpwm4Pwm2OutTrig01	FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input.
kXBARB3_InputFlexpwm4Pwm3OutTrig01	FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input.
kXBARB3_InputFlexpwm4Pwm4OutTrig01	FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input.
kXBARB3_InputPitTrigger0	PIT_TRIGGER0 output assigned to XBARB3_IN36 input.
kXBARB3_InputPitTrigger1	PIT_TRIGGER1 output assigned to XBARB3_IN37 input.
kXBARB3_InputAdcEtcXbar0Coco0	ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input.
kXBARB3_InputAdcEtcXbar0Coco1	ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input.
kXBARB3_InputAdcEtcXbar0Coco2	ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input.
kXBARB3_InputAdcEtcXbar0Coco3	ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input.
kXBARB3_InputAdcEtcXbar1Coco0	ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input.
kXBARB3_InputAdcEtcXbar1Coco1	ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input.
kXBARB3_InputAdcEtcXbar1Coco2	ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input.
kXBARB3_InputAdcEtcXbar1Coco3	ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input.
kXBARB3_InputEnc1PosMatch	ENC1_POS_MATCH output assigned to XBARB3_IN46 input.
kXBARB3_InputEnc2PosMatch	ENC2_POS_MATCH output assigned to XBARB3_IN47 input.
kXBARB3_InputEnc3PosMatch	ENC3_POS_MATCH output assigned to XBARB3_IN48 input.
kXBARB3_InputEnc4PosMatch	ENC4_POS_MATCH output assigned to XBARB3_IN49 input.
kXBARB3_InputDmaDone0	DMA_DONE0 output assigned to XBARB3_IN50 input.
kXBARB3_InputDmaDone1	DMA_DONE1 output assigned to XBARB3_IN51 input.
kXBARB3_InputDmaDone2	DMA_DONE2 output assigned to XBARB3_IN52 input.
kXBARB3_InputDmaDone3	DMA_DONE3 output assigned to XBARB3_IN53 input.
kXBARB3_InputDmaDone4	DMA_DONE4 output assigned to XBARB3_IN54 input.
kXBARB3_InputDmaDone5	DMA_DONE5 output assigned to XBARB3_IN55 input.
kXBARB3_InputDmaDone6	DMA_DONE6 output assigned to XBARB3_IN56 input.
kXBARB3_InputDmaDone7	DMA_DONE7 output assigned to XBARB3_IN57 input.

Definition at line 873 of file MIMXRT1052.h.

_xbar_output_signal

enum _xbar_output_signal

Enumerator
kXBARA1_OutputDmaChMuxReq30	XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30
kXBARA1_OutputDmaChMuxReq31	XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31
kXBARA1_OutputDmaChMuxReq94	XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94
kXBARA1_OutputDmaChMuxReq95	XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95
kXBARA1_OutputIomuxXbarInout04	XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04
kXBARA1_OutputIomuxXbarInout05	XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05
kXBARA1_OutputIomuxXbarInout06	XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06
kXBARA1_OutputIomuxXbarInout07	XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07
kXBARA1_OutputIomuxXbarInout08	XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08
kXBARA1_OutputIomuxXbarInout09	XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09
kXBARA1_OutputIomuxXbarInout10	XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10
kXBARA1_OutputIomuxXbarInout11	XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11
kXBARA1_OutputIomuxXbarInout12	XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12
kXBARA1_OutputIomuxXbarInout13	XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13
kXBARA1_OutputIomuxXbarInout14	XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14
kXBARA1_OutputIomuxXbarInout15	XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15
kXBARA1_OutputIomuxXbarInout16	XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16
kXBARA1_OutputIomuxXbarInout17	XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17
kXBARA1_OutputIomuxXbarInout18	XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18
kXBARA1_OutputIomuxXbarInout19	XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19
kXBARA1_OutputAcmp1Sample	XBARA1_OUT20 output assigned to ACMP1_SAMPLE
kXBARA1_OutputAcmp2Sample	XBARA1_OUT21 output assigned to ACMP2_SAMPLE
kXBARA1_OutputAcmp3Sample	XBARA1_OUT22 output assigned to ACMP3_SAMPLE
kXBARA1_OutputAcmp4Sample	XBARA1_OUT23 output assigned to ACMP4_SAMPLE
kXBARA1_OutputRESERVED24	XBARA1_OUT24 output is reserved.
kXBARA1_OutputRESERVED25	XBARA1_OUT25 output is reserved.
kXBARA1_OutputFlexpwm1Exta0	XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0
kXBARA1_OutputFlexpwm1Exta1	XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1
kXBARA1_OutputFlexpwm1Exta2	XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2
kXBARA1_OutputFlexpwm1Exta3	XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3
kXBARA1_OutputFlexpwm1ExtSync0	XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0
kXBARA1_OutputFlexpwm1ExtSync1	XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1
kXBARA1_OutputFlexpwm1ExtSync2	XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2
kXBARA1_OutputFlexpwm1ExtSync3	XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3
kXBARA1_OutputFlexpwm1ExtClk	XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK
kXBARA1_OutputFlexpwm1Fault0	XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0
kXBARA1_OutputFlexpwm1Fault1	XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1
kXBARA1_OutputFlexpwm1234Fault2	XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2
kXBARA1_OutputFlexpwm1234Fault3	XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3
kXBARA1_OutputFlexpwm1ExtForce	XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE
kXBARA1_OutputFlexpwm234Exta0	XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0
kXBARA1_OutputFlexpwm234Exta1	XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1
kXBARA1_OutputFlexpwm234Exta2	XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2
kXBARA1_OutputFlexpwm234Exta3	XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3
kXBARA1_OutputFlexpwm2ExtSync0	XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0
kXBARA1_OutputFlexpwm2ExtSync1	XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1
kXBARA1_OutputFlexpwm2ExtSync2	XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2
kXBARA1_OutputFlexpwm2ExtSync3	XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3
kXBARA1_OutputFlexpwm234ExtClk	XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK
kXBARA1_OutputFlexpwm2Fault0	XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0
kXBARA1_OutputFlexpwm2Fault1	XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1
kXBARA1_OutputFlexpwm2ExtForce	XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE
kXBARA1_OutputFlexpwm3ExtSync0	XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0
kXBARA1_OutputFlexpwm3ExtSync1	XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1
kXBARA1_OutputFlexpwm3ExtSync2	XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2
kXBARA1_OutputFlexpwm3ExtSync3	XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3
kXBARA1_OutputFlexpwm3Fault0	XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0
kXBARA1_OutputFlexpwm3Fault1	XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1
kXBARA1_OutputFlexpwm3ExtForce	XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE
kXBARA1_OutputFlexpwm4ExtSync0	XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0
kXBARA1_OutputFlexpwm4ExtSync1	XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1
kXBARA1_OutputFlexpwm4ExtSync2	XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2
kXBARA1_OutputFlexpwm4ExtSync3	XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3
kXBARA1_OutputFlexpwm4Fault0	XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0
kXBARA1_OutputFlexpwm4Fault1	XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1
kXBARA1_OutputFlexpwm4ExtForce	XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE
kXBARA1_OutputEnc1PhaseAInput	XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT
kXBARA1_OutputEnc1PhaseBInput	XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT
kXBARA1_OutputEnc1Index	XBARA1_OUT68 output assigned to ENC1_INDEX
kXBARA1_OutputEnc1Home	XBARA1_OUT69 output assigned to ENC1_HOME
kXBARA1_OutputEnc1Trigger	XBARA1_OUT70 output assigned to ENC1_TRIGGER
kXBARA1_OutputEnc2PhaseAInput	XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT
kXBARA1_OutputEnc2PhaseBInput	XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT
kXBARA1_OutputEnc2Index	XBARA1_OUT73 output assigned to ENC2_INDEX
kXBARA1_OutputEnc2Home	XBARA1_OUT74 output assigned to ENC2_HOME
kXBARA1_OutputEnc2Trigger	XBARA1_OUT75 output assigned to ENC2_TRIGGER
kXBARA1_OutputEnc3PhaseAInput	XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT
kXBARA1_OutputEnc3PhaseBInput	XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT
kXBARA1_OutputEnc3Index	XBARA1_OUT78 output assigned to ENC3_INDEX
kXBARA1_OutputEnc3Home	XBARA1_OUT79 output assigned to ENC3_HOME
kXBARA1_OutputEnc3Trigger	XBARA1_OUT80 output assigned to ENC3_TRIGGER
kXBARA1_OutputEnc4PhaseAInput	XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT
kXBARA1_OutputEnc4PhaseBInput	XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT
kXBARA1_OutputEnc4Index	XBARA1_OUT83 output assigned to ENC4_INDEX
kXBARA1_OutputEnc4Home	XBARA1_OUT84 output assigned to ENC4_HOME
kXBARA1_OutputEnc4Trigger	XBARA1_OUT85 output assigned to ENC4_TRIGGER
kXBARA1_OutputQtimer1Tmr0Input	XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT
kXBARA1_OutputQtimer1Tmr1Input	XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT
kXBARA1_OutputQtimer1Tmr2Input	XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT
kXBARA1_OutputQtimer1Tmr3Input	XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT
kXBARA1_OutputQtimer2Tmr0Input	XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT
kXBARA1_OutputQtimer2Tmr1Input	XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT
kXBARA1_OutputQtimer2Tmr2Input	XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT
kXBARA1_OutputQtimer2Tmr3Input	XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT
kXBARA1_OutputQtimer3Tmr0Input	XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT
kXBARA1_OutputQtimer3Tmr1Input	XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT
kXBARA1_OutputQtimer3Tmr2Input	XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT
kXBARA1_OutputQtimer3Tmr3Input	XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT
kXBARA1_OutputQtimer4Tmr0Input	XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT
kXBARA1_OutputQtimer4Tmr1Input	XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT
kXBARA1_OutputQtimer4Tmr2Input	XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT
kXBARA1_OutputQtimer4Tmr3Input	XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT
kXBARA1_OutputEwmEwmIn	XBARA1_OUT102 output assigned to EWM_EWM_IN
kXBARA1_OutputAdcEtcXbar0Trig0	XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0
kXBARA1_OutputAdcEtcXbar0Trig1	XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1
kXBARA1_OutputAdcEtcXbar0Trig2	XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2
kXBARA1_OutputAdcEtcXbar0Trig3	XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3
kXBARA1_OutputAdcEtcXbar1Trig0	XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0
kXBARA1_OutputAdcEtcXbar1Trig1	XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1
kXBARA1_OutputAdcEtcXbar1Trig2	XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2
kXBARA1_OutputAdcEtcXbar1Trig3	XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3
kXBARA1_OutputLpi2c1TrgInput	XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT
kXBARA1_OutputLpi2c2TrgInput	XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT
kXBARA1_OutputLpi2c3TrgInput	XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT
kXBARA1_OutputLpi2c4TrgInput	XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT
kXBARA1_OutputLpspi1TrgInput	XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT
kXBARA1_OutputLpspi2TrgInput	XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT
kXBARA1_OutputLpspi3TrgInput	XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT
kXBARA1_OutputLpspi4TrgInput	XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT
kXBARA1_OutputLpuart1TrgInput	XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT
kXBARA1_OutputLpuart2TrgInput	XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT
kXBARA1_OutputLpuart3TrgInput	XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT
kXBARA1_OutputLpuart4TrgInput	XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT
kXBARA1_OutputLpuart5TrgInput	XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT
kXBARA1_OutputLpuart6TrgInput	XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT
kXBARA1_OutputLpuart7TrgInput	XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT
kXBARA1_OutputLpuart8TrgInput	XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT
kXBARA1_OutputFlexio1TriggerIn0	XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0
kXBARA1_OutputFlexio1TriggerIn1	XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1
kXBARA1_OutputFlexio2TriggerIn0	XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0
kXBARA1_OutputFlexio2TriggerIn1	XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1
kXBARB2_OutputAoi1In00	XBARB2_OUT0 output assigned to AOI1_IN00
kXBARB2_OutputAoi1In01	XBARB2_OUT1 output assigned to AOI1_IN01
kXBARB2_OutputAoi1In02	XBARB2_OUT2 output assigned to AOI1_IN02
kXBARB2_OutputAoi1In03	XBARB2_OUT3 output assigned to AOI1_IN03
kXBARB2_OutputAoi1In04	XBARB2_OUT4 output assigned to AOI1_IN04
kXBARB2_OutputAoi1In05	XBARB2_OUT5 output assigned to AOI1_IN05
kXBARB2_OutputAoi1In06	XBARB2_OUT6 output assigned to AOI1_IN06
kXBARB2_OutputAoi1In07	XBARB2_OUT7 output assigned to AOI1_IN07
kXBARB2_OutputAoi1In08	XBARB2_OUT8 output assigned to AOI1_IN08
kXBARB2_OutputAoi1In09	XBARB2_OUT9 output assigned to AOI1_IN09
kXBARB2_OutputAoi1In10	XBARB2_OUT10 output assigned to AOI1_IN10
kXBARB2_OutputAoi1In11	XBARB2_OUT11 output assigned to AOI1_IN11
kXBARB2_OutputAoi1In12	XBARB2_OUT12 output assigned to AOI1_IN12
kXBARB2_OutputAoi1In13	XBARB2_OUT13 output assigned to AOI1_IN13
kXBARB2_OutputAoi1In14	XBARB2_OUT14 output assigned to AOI1_IN14
kXBARB2_OutputAoi1In15	XBARB2_OUT15 output assigned to AOI1_IN15
kXBARB3_OutputAoi2In00	XBARB3_OUT0 output assigned to AOI2_IN00
kXBARB3_OutputAoi2In01	XBARB3_OUT1 output assigned to AOI2_IN01
kXBARB3_OutputAoi2In02	XBARB3_OUT2 output assigned to AOI2_IN02
kXBARB3_OutputAoi2In03	XBARB3_OUT3 output assigned to AOI2_IN03
kXBARB3_OutputAoi2In04	XBARB3_OUT4 output assigned to AOI2_IN04
kXBARB3_OutputAoi2In05	XBARB3_OUT5 output assigned to AOI2_IN05
kXBARB3_OutputAoi2In06	XBARB3_OUT6 output assigned to AOI2_IN06
kXBARB3_OutputAoi2In07	XBARB3_OUT7 output assigned to AOI2_IN07
kXBARB3_OutputAoi2In08	XBARB3_OUT8 output assigned to AOI2_IN08
kXBARB3_OutputAoi2In09	XBARB3_OUT9 output assigned to AOI2_IN09
kXBARB3_OutputAoi2In10	XBARB3_OUT10 output assigned to AOI2_IN10
kXBARB3_OutputAoi2In11	XBARB3_OUT11 output assigned to AOI2_IN11
kXBARB3_OutputAoi2In12	XBARB3_OUT12 output assigned to AOI2_IN12
kXBARB3_OutputAoi2In13	XBARB3_OUT13 output assigned to AOI2_IN13
kXBARB3_OutputAoi2In14	XBARB3_OUT14 output assigned to AOI2_IN14
kXBARB3_OutputAoi2In15	XBARB3_OUT15 output assigned to AOI2_IN15

Definition at line 1081 of file MIMXRT1052.h.

Variable Documentation

@306

union { ... }

@308

union { ... }

@310

union { ... }

@316

union { ... }

@319

union { ... }

@321

union { ... }

@323

union { ... }

@325

union { ... }

@327

union { ... }

@329

union { ... }

@331

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@333

union { ... }

@335

union { ... }

@337

union { ... }

@339

union { ... }

@341

union { ... }

ADDR_OFFSET0

__IO uint32_t BEE_Type::ADDR_OFFSET0

Offset region 0 Register, offset: 0x4

Definition at line 3012 of file MIMXRT1052.h.

ADDR_OFFSET1

__IO uint32_t BEE_Type::ADDR_OFFSET1

Offset region 1 Register, offset: 0x8

Definition at line 3013 of file MIMXRT1052.h.

ADMA_ERR_STATUS

__I uint32_t USDHC_Type::ADMA_ERR_STATUS

ADMA Error Status Register, offset: 0x54

Definition at line 42275 of file MIMXRT1052.h.

ADMA_SYS_ADDR

__IO uint32_t USDHC_Type::ADMA_SYS_ADDR

ADMA System Address, offset: 0x58

Definition at line 42276 of file MIMXRT1052.h.

AES_KEY0_W0

__IO uint32_t BEE_Type::AES_KEY0_W0

AES Key 0 Register, offset: 0xC

Definition at line 3014 of file MIMXRT1052.h.

AES_KEY0_W1

__IO uint32_t BEE_Type::AES_KEY0_W1

AES Key 1 Register, offset: 0x10

Definition at line 3015 of file MIMXRT1052.h.

AES_KEY0_W2

__IO uint32_t BEE_Type::AES_KEY0_W2

AES Key 2 Register, offset: 0x14

Definition at line 3016 of file MIMXRT1052.h.

AES_KEY0_W3

__IO uint32_t BEE_Type::AES_KEY0_W3

AES Key 3 Register, offset: 0x18

Definition at line 3017 of file MIMXRT1052.h.

AHBCR

__IO uint32_t FLEXSPI_Type::AHBCR

AHB Bus Control Register, offset: 0xC

Definition at line 18093 of file MIMXRT1052.h.

AHBRXBUFCR0

__IO uint32_t FLEXSPI_Type::AHBRXBUFCR0[4]

AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4

Definition at line 18098 of file MIMXRT1052.h.

AHBSPNDSTS

__I uint32_t FLEXSPI_Type::AHBSPNDSTS

AHB Suspend Status Register, offset: 0xEC

Definition at line 18118 of file MIMXRT1052.h.

ANA0

__IO uint32_t OCOTP_Type::ANA0

Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0

Definition at line 27748 of file MIMXRT1052.h.

ANA1

__IO uint32_t OCOTP_Type::ANA1

Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0

Definition at line 27750 of file MIMXRT1052.h.

ANA2

__IO uint32_t OCOTP_Type::ANA2

Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0

Definition at line 27752 of file MIMXRT1052.h.

AS_BUF

__IO uint32_t PXP_Type::AS_BUF

Alpha Surface Buffer Pointer, offset: 0x160

Definition at line 32562 of file MIMXRT1052.h.

AS_CLRKEYHIGH

__IO uint32_t PXP_Type::AS_CLRKEYHIGH

Overlay Color Key High, offset: 0x190

Definition at line 32568 of file MIMXRT1052.h.

AS_CLRKEYLOW

__IO uint32_t PXP_Type::AS_CLRKEYLOW

Overlay Color Key Low, offset: 0x180

Definition at line 32566 of file MIMXRT1052.h.

AS_CTRL

__IO uint32_t PXP_Type::AS_CTRL

Alpha Surface Control, offset: 0x150

Definition at line 32560 of file MIMXRT1052.h.

AS_PITCH

__IO uint32_t PXP_Type::AS_PITCH

Alpha Surface Pitch, offset: 0x170

Definition at line 32564 of file MIMXRT1052.h.

ASYNCLISTADDR [1/2]

__IO uint32_t USB_Type::ASYNCLISTADDR

Next Asynch. Address, offset: 0x158

Definition at line 39027 of file MIMXRT1052.h.

ASYNCLISTADDR [2/2]

__IO { ... } ::ASYNCLISTADDR

Next Asynch. Address, offset: 0x158

Definition at line 39027 of file MIMXRT1052.h.

ATCOR

__IO uint32_t ENET_Type::ATCOR

Timer Correction Register, offset: 0x410

Definition at line 15714 of file MIMXRT1052.h.

ATCR

__IO uint32_t ENET_Type::ATCR

Adjustable Timer Control Register, offset: 0x400

Definition at line 15710 of file MIMXRT1052.h.

ATINC

__IO uint32_t ENET_Type::ATINC

Time-Stamping Clock Period Register, offset: 0x414

Definition at line 15715 of file MIMXRT1052.h.

ATOFF

__IO uint32_t ENET_Type::ATOFF

Timer Offset Register, offset: 0x408

Definition at line 15712 of file MIMXRT1052.h.

ATPER

__IO uint32_t ENET_Type::ATPER

Timer Period Register, offset: 0x40C

Definition at line 15713 of file MIMXRT1052.h.

ATSTMP

__I uint32_t ENET_Type::ATSTMP

Timestamp of Last Transmitted Frame, offset: 0x418

Definition at line 15716 of file MIMXRT1052.h.

ATTR [1/2]

__IO uint16_t DMA_Type::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

Definition at line 12007 of file MIMXRT1052.h.

ATTR [2/2]

__IO { ... } ::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

Definition at line 12007 of file MIMXRT1052.h.

ATVR

__IO uint32_t ENET_Type::ATVR

Timer Value Register, offset: 0x404

Definition at line 15711 of file MIMXRT1052.h.

AUTOCMD12_ERR_STATUS

__IO uint32_t USDHC_Type::AUTOCMD12_ERR_STATUS

Auto CMD12 Error Status, offset: 0x3C

Definition at line 42269 of file MIMXRT1052.h.

BASIC_SETTING

__IO uint32_t TSC_Type::BASIC_SETTING

Basic Setting, offset: 0x0

Definition at line 38547 of file MIMXRT1052.h.

BAUD

__IO uint32_t LPUART_Type::BAUD

LPUART Baud Rate Register, offset: 0x10

Definition at line 26776 of file MIMXRT1052.h.

BFCRT

struct { ... } AOI_Type::BFCRT[4]

BFCRT01 [1/2]

__IO uint16_t AOI_Type::BFCRT01

Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4

Definition at line 2803 of file MIMXRT1052.h.

BFCRT01 [2/2]

__IO { ... } ::BFCRT01

Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4

Definition at line 2803 of file MIMXRT1052.h.

BFCRT23 [1/2]

__IO uint16_t AOI_Type::BFCRT23

Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4

Definition at line 2804 of file MIMXRT1052.h.

BFCRT23 [2/2]

__IO { ... } ::BFCRT23

Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4

Definition at line 2804 of file MIMXRT1052.h.

BITER_ELINKNO [1/2]

__IO uint16_t DMA_Type::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

Definition at line 12023 of file MIMXRT1052.h.

BITER_ELINKNO [2/2]

__IO { ... } ::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

Definition at line 12023 of file MIMXRT1052.h.

BITER_ELINKYES [1/2]

__IO uint16_t DMA_Type::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

Definition at line 12024 of file MIMXRT1052.h.

BITER_ELINKYES [2/2]

__IO { ... } ::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

Definition at line 12024 of file MIMXRT1052.h.

BLK_ATT

__IO uint32_t USDHC_Type::BLK_ATT

Block Attributes, offset: 0x4

Definition at line 42255 of file MIMXRT1052.h.

BM_ERROR_STAT

__IO uint32_t LCDIF_Type::BM_ERROR_STAT

Bus Master Error Status Register, offset: 0x190

Definition at line 23549 of file MIMXRT1052.h.

BMCR0

__IO uint32_t SEMC_Type::BMCR0

Master Bus (AXI) Control Register 0, offset: 0x8

Definition at line 34132 of file MIMXRT1052.h.

BMCR1

__IO uint32_t SEMC_Type::BMCR1

Master Bus (AXI) Control Register 1, offset: 0xC

Definition at line 34133 of file MIMXRT1052.h.

BR

__IO uint32_t SEMC_Type::BR[9]

Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4

Definition at line 34134 of file MIMXRT1052.h.

BURSTSIZE

__IO uint32_t USB_Type::BURSTSIZE

Programmable Burst Size, offset: 0x160

Definition at line 39031 of file MIMXRT1052.h.

CACRR

__IO uint32_t CCM_Type::CACRR

CCM Arm Clock Root Register, offset: 0x10

Definition at line 4159 of file MIMXRT1052.h.

CAL

__IO uint32_t ADC_Type::CAL

Calibration value register, offset: 0x58

Definition at line 1305 of file MIMXRT1052.h.

CAPABILITY0

__IO uint32_t DCP_Type::CAPABILITY0

DCP capability 0 register, offset: 0x30

Definition at line 10282 of file MIMXRT1052.h.

CAPABILITY1

__I uint32_t DCP_Type::CAPABILITY1

DCP capability 1 register, offset: 0x40

Definition at line 10284 of file MIMXRT1052.h.

CAPLENGTH

__I uint8_t USB_Type::CAPLENGTH

Capability Registers Length, offset: 0x100

Definition at line 39007 of file MIMXRT1052.h.

CAPT [1/2]

__IO { ... } ::CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

Definition at line 37382 of file MIMXRT1052.h.

CAPT [2/2]

__IO uint16_t TMR_Type::CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

Definition at line 37382 of file MIMXRT1052.h.

CAPTCOMPA [1/2]

__IO uint16_t PWM_Type::CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

Definition at line 30871 of file MIMXRT1052.h.

CAPTCOMPA [2/2]

__IO { ... } ::CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

Definition at line 30871 of file MIMXRT1052.h.

CAPTCOMPB [1/2]

__IO uint16_t PWM_Type::CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

Definition at line 30873 of file MIMXRT1052.h.

CAPTCOMPB [2/2]

__IO { ... } ::CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

Definition at line 30873 of file MIMXRT1052.h.

CAPTCOMPX [1/2]

__IO uint16_t PWM_Type::CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

Definition at line 30875 of file MIMXRT1052.h.

CAPTCOMPX [2/2]

__IO { ... } ::CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

Definition at line 30875 of file MIMXRT1052.h.

CAPTCTRLA [1/2]

__IO { ... } ::CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

Definition at line 30870 of file MIMXRT1052.h.

CAPTCTRLA [2/2]

__IO uint16_t PWM_Type::CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

Definition at line 30870 of file MIMXRT1052.h.

CAPTCTRLB [1/2]

__IO uint16_t PWM_Type::CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

Definition at line 30872 of file MIMXRT1052.h.

CAPTCTRLB [2/2]

__IO { ... } ::CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

Definition at line 30872 of file MIMXRT1052.h.

CAPTCTRLX [1/2]

__IO uint16_t PWM_Type::CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

Definition at line 30874 of file MIMXRT1052.h.

CAPTCTRLX [2/2]

__IO { ... } ::CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

Definition at line 30874 of file MIMXRT1052.h.

CBCDR

__IO uint32_t CCM_Type::CBCDR

CCM Bus Clock Divider Register, offset: 0x14

Definition at line 4160 of file MIMXRT1052.h.

CBCMR

__IO uint32_t CCM_Type::CBCMR

CCM Bus Clock Multiplexer Register, offset: 0x18

Definition at line 4161 of file MIMXRT1052.h.

CCGR0

__IO uint32_t CCM_Type::CCGR0

CCM Clock Gating Register 0, offset: 0x68

Definition at line 4179 of file MIMXRT1052.h.

CCGR1

__IO uint32_t CCM_Type::CCGR1

CCM Clock Gating Register 1, offset: 0x6C

Definition at line 4180 of file MIMXRT1052.h.

CCGR2

__IO uint32_t CCM_Type::CCGR2

CCM Clock Gating Register 2, offset: 0x70

Definition at line 4181 of file MIMXRT1052.h.

CCGR3

__IO uint32_t CCM_Type::CCGR3

CCM Clock Gating Register 3, offset: 0x74

Definition at line 4182 of file MIMXRT1052.h.

CCGR4

__IO uint32_t CCM_Type::CCGR4

CCM Clock Gating Register 4, offset: 0x78

Definition at line 4183 of file MIMXRT1052.h.

CCGR5

__IO uint32_t CCM_Type::CCGR5

CCM Clock Gating Register 5, offset: 0x7C

Definition at line 4184 of file MIMXRT1052.h.

CCGR6

__IO uint32_t CCM_Type::CCGR6

CCM Clock Gating Register 6, offset: 0x80

Definition at line 4185 of file MIMXRT1052.h.

CCOSR

__IO uint32_t CCM_Type::CCOSR

CCM Clock Output Source Register, offset: 0x60

Definition at line 4177 of file MIMXRT1052.h.

CCR [1/2]

__IO uint32_t CCM_Type::CCR

CCM Control Register, offset: 0x0

Definition at line 4155 of file MIMXRT1052.h.

CCR [2/2]

__IO uint32_t LPSPI_Type::CCR

Clock Configuration Register, offset: 0x40

Definition at line 26158 of file MIMXRT1052.h.

CCSR

__IO uint32_t CCM_Type::CCSR

CCM Clock Switcher Register, offset: 0xC

Definition at line 4158 of file MIMXRT1052.h.

CDCDR

__IO uint32_t CCM_Type::CDCDR

CCM D1 Clock Divider Register, offset: 0x30

Definition at line 4167 of file MIMXRT1052.h.

CDHIPR

__I uint32_t CCM_Type::CDHIPR

CCM Divider Handshake In-Process Register, offset: 0x48

Definition at line 4172 of file MIMXRT1052.h.

CDNE

__O uint8_t DMA_Type::CDNE

Clear DONE Status Bit Register, offset: 0x1C

Definition at line 11958 of file MIMXRT1052.h.

CEEI

__O uint8_t DMA_Type::CEEI

Clear Enable Error Interrupt Register, offset: 0x18

Definition at line 11954 of file MIMXRT1052.h.

CERQ

__O uint8_t DMA_Type::CERQ

Clear Enable Request Register, offset: 0x1A

Definition at line 11956 of file MIMXRT1052.h.

CERR

__O uint8_t DMA_Type::CERR

Clear Error Register, offset: 0x1E

Definition at line 11960 of file MIMXRT1052.h.

CFG

__IO uint32_t ADC_Type::CFG

Configuration register, offset: 0x44

Definition at line 1300 of file MIMXRT1052.h.

CFG0

__IO uint32_t OCOTP_Type::CFG0

Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410

Definition at line 27724 of file MIMXRT1052.h.

CFG1

__IO uint32_t OCOTP_Type::CFG1

Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420

Definition at line 27726 of file MIMXRT1052.h.

CFG2

__IO uint32_t OCOTP_Type::CFG2

Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430

Definition at line 27728 of file MIMXRT1052.h.

CFG3

__IO uint32_t OCOTP_Type::CFG3

Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440

Definition at line 27730 of file MIMXRT1052.h.

CFG4

__IO uint32_t OCOTP_Type::CFG4

Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450

Definition at line 27732 of file MIMXRT1052.h.

CFG5

__IO uint32_t OCOTP_Type::CFG5

Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460

Definition at line 27734 of file MIMXRT1052.h.

CFG6

__IO uint32_t OCOTP_Type::CFG6

Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470

Definition at line 27736 of file MIMXRT1052.h.

CFGR0

__IO uint32_t LPSPI_Type::CFGR0

Configuration Register 0, offset: 0x20

Definition at line 26152 of file MIMXRT1052.h.

CFGR1

__IO uint32_t LPSPI_Type::CFGR1

Configuration Register 1, offset: 0x24

Definition at line 26153 of file MIMXRT1052.h.

CGPR

__IO uint32_t CCM_Type::CGPR

CCM General Purpose Register, offset: 0x64

Definition at line 4178 of file MIMXRT1052.h.

CH0CMDPTR

__IO uint32_t DCP_Type::CH0CMDPTR

DCP channel 0 command pointer address register, offset: 0x100

Definition at line 10306 of file MIMXRT1052.h.

CH0OPTS

__IO uint32_t DCP_Type::CH0OPTS

DCP channel 0 options register, offset: 0x130

Definition at line 10314 of file MIMXRT1052.h.

CH0OPTS_CLR

__IO uint32_t DCP_Type::CH0OPTS_CLR

DCP channel 0 options register, offset: 0x138

Definition at line 10316 of file MIMXRT1052.h.

CH0OPTS_SET

__IO uint32_t DCP_Type::CH0OPTS_SET

DCP channel 0 options register, offset: 0x134

Definition at line 10315 of file MIMXRT1052.h.

CH0OPTS_TOG

__IO uint32_t DCP_Type::CH0OPTS_TOG

DCP channel 0 options register, offset: 0x13C

Definition at line 10317 of file MIMXRT1052.h.

CH0SEMA

__IO uint32_t DCP_Type::CH0SEMA

DCP channel 0 semaphore register, offset: 0x110

Definition at line 10308 of file MIMXRT1052.h.

CH0STAT

__IO uint32_t DCP_Type::CH0STAT

DCP channel 0 status register, offset: 0x120

Definition at line 10310 of file MIMXRT1052.h.

CH0STAT_CLR

__IO uint32_t DCP_Type::CH0STAT_CLR

DCP channel 0 status register, offset: 0x128

Definition at line 10312 of file MIMXRT1052.h.

CH0STAT_SET

__IO uint32_t DCP_Type::CH0STAT_SET

DCP channel 0 status register, offset: 0x124

Definition at line 10311 of file MIMXRT1052.h.

CH0STAT_TOG

__IO uint32_t DCP_Type::CH0STAT_TOG

DCP channel 0 status register, offset: 0x12C

Definition at line 10313 of file MIMXRT1052.h.

CH1CMDPTR

__IO uint32_t DCP_Type::CH1CMDPTR

DCP channel 1 command pointer address register, offset: 0x140

Definition at line 10318 of file MIMXRT1052.h.

CH1OPTS

__IO uint32_t DCP_Type::CH1OPTS

DCP channel 1 options register, offset: 0x170

Definition at line 10326 of file MIMXRT1052.h.

CH1OPTS_CLR

__IO uint32_t DCP_Type::CH1OPTS_CLR

DCP channel 1 options register, offset: 0x178

Definition at line 10328 of file MIMXRT1052.h.

CH1OPTS_SET

__IO uint32_t DCP_Type::CH1OPTS_SET

DCP channel 1 options register, offset: 0x174

Definition at line 10327 of file MIMXRT1052.h.

CH1OPTS_TOG

__IO uint32_t DCP_Type::CH1OPTS_TOG

DCP channel 1 options register, offset: 0x17C

Definition at line 10329 of file MIMXRT1052.h.

CH1SEMA

__IO uint32_t DCP_Type::CH1SEMA

DCP channel 1 semaphore register, offset: 0x150

Definition at line 10320 of file MIMXRT1052.h.

CH1STAT

__IO uint32_t DCP_Type::CH1STAT

DCP channel 1 status register, offset: 0x160

Definition at line 10322 of file MIMXRT1052.h.

CH1STAT_CLR

__IO uint32_t DCP_Type::CH1STAT_CLR

DCP channel 1 status register, offset: 0x168

Definition at line 10324 of file MIMXRT1052.h.

CH1STAT_SET

__IO uint32_t DCP_Type::CH1STAT_SET

DCP channel 1 status register, offset: 0x164

Definition at line 10323 of file MIMXRT1052.h.

CH1STAT_TOG

__IO uint32_t DCP_Type::CH1STAT_TOG

DCP channel 1 status register, offset: 0x16C

Definition at line 10325 of file MIMXRT1052.h.

CH2CMDPTR

__IO uint32_t DCP_Type::CH2CMDPTR

DCP channel 2 command pointer address register, offset: 0x180

Definition at line 10330 of file MIMXRT1052.h.

CH2OPTS

__IO uint32_t DCP_Type::CH2OPTS

DCP channel 2 options register, offset: 0x1B0

Definition at line 10338 of file MIMXRT1052.h.

CH2OPTS_CLR

__IO uint32_t DCP_Type::CH2OPTS_CLR

DCP channel 2 options register, offset: 0x1B8

Definition at line 10340 of file MIMXRT1052.h.

CH2OPTS_SET

__IO uint32_t DCP_Type::CH2OPTS_SET

DCP channel 2 options register, offset: 0x1B4

Definition at line 10339 of file MIMXRT1052.h.

CH2OPTS_TOG

__IO uint32_t DCP_Type::CH2OPTS_TOG

DCP channel 2 options register, offset: 0x1BC

Definition at line 10341 of file MIMXRT1052.h.

CH2SEMA

__IO uint32_t DCP_Type::CH2SEMA

DCP channel 2 semaphore register, offset: 0x190

Definition at line 10332 of file MIMXRT1052.h.

CH2STAT

__IO uint32_t DCP_Type::CH2STAT

DCP channel 2 status register, offset: 0x1A0

Definition at line 10334 of file MIMXRT1052.h.

CH2STAT_CLR

__IO uint32_t DCP_Type::CH2STAT_CLR

DCP channel 2 status register, offset: 0x1A8

Definition at line 10336 of file MIMXRT1052.h.

CH2STAT_SET

__IO uint32_t DCP_Type::CH2STAT_SET

DCP channel 2 status register, offset: 0x1A4

Definition at line 10335 of file MIMXRT1052.h.

CH2STAT_TOG

__IO uint32_t DCP_Type::CH2STAT_TOG

DCP channel 2 status register, offset: 0x1AC

Definition at line 10337 of file MIMXRT1052.h.

CH3CMDPTR

__IO uint32_t DCP_Type::CH3CMDPTR

DCP channel 3 command pointer address register, offset: 0x1C0

Definition at line 10342 of file MIMXRT1052.h.

CH3OPTS

__IO uint32_t DCP_Type::CH3OPTS

DCP channel 3 options register, offset: 0x1F0

Definition at line 10350 of file MIMXRT1052.h.

CH3OPTS_CLR

__IO uint32_t DCP_Type::CH3OPTS_CLR

DCP channel 3 options register, offset: 0x1F8

Definition at line 10352 of file MIMXRT1052.h.

CH3OPTS_SET

__IO uint32_t DCP_Type::CH3OPTS_SET

DCP channel 3 options register, offset: 0x1F4

Definition at line 10351 of file MIMXRT1052.h.

CH3OPTS_TOG

__IO uint32_t DCP_Type::CH3OPTS_TOG

DCP channel 3 options register, offset: 0x1FC

Definition at line 10353 of file MIMXRT1052.h.

CH3SEMA

__IO uint32_t DCP_Type::CH3SEMA

DCP channel 3 semaphore register, offset: 0x1D0

Definition at line 10344 of file MIMXRT1052.h.

CH3STAT

__IO uint32_t DCP_Type::CH3STAT

DCP channel 3 status register, offset: 0x1E0

Definition at line 10346 of file MIMXRT1052.h.

CH3STAT_CLR

__IO uint32_t DCP_Type::CH3STAT_CLR

DCP channel 3 status register, offset: 0x1E8

Definition at line 10348 of file MIMXRT1052.h.

CH3STAT_SET

__IO uint32_t DCP_Type::CH3STAT_SET

DCP channel 3 status register, offset: 0x1E4

Definition at line 10347 of file MIMXRT1052.h.

CH3STAT_TOG

__IO uint32_t DCP_Type::CH3STAT_TOG

DCP channel 3 status register, offset: 0x1EC

Definition at line 10349 of file MIMXRT1052.h.

CHANNEL [1/3]

struct { ... } ENET_Type::CHANNEL[4]

CHANNEL [2/3]

struct { ... } PIT_Type::CHANNEL[4]

CHANNEL [3/3]

struct { ... } TMR_Type::CHANNEL[4]

CHANNELCTRL

__IO uint32_t DCP_Type::CHANNELCTRL

DCP channel control register, offset: 0x20

Definition at line 10278 of file MIMXRT1052.h.

CHANNELCTRL_CLR

__IO uint32_t DCP_Type::CHANNELCTRL_CLR

DCP channel control register, offset: 0x28

Definition at line 10280 of file MIMXRT1052.h.

CHANNELCTRL_SET

__IO uint32_t DCP_Type::CHANNELCTRL_SET

DCP channel control register, offset: 0x24

Definition at line 10279 of file MIMXRT1052.h.

CHANNELCTRL_TOG

__IO uint32_t DCP_Type::CHANNELCTRL_TOG

DCP channel control register, offset: 0x2C

Definition at line 10281 of file MIMXRT1052.h.

CHCFG

__IO uint32_t DMAMUX_Type::CHCFG[32]

Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4

Definition at line 15061 of file MIMXRT1052.h.

CHRG_DETECT [1/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT

USB Charger Detect Register, array offset: 0x1B0, array step: 0x60

Definition at line 41805 of file MIMXRT1052.h.

CHRG_DETECT [2/2]

__IO { ... } ::CHRG_DETECT

USB Charger Detect Register, array offset: 0x1B0, array step: 0x60

Definition at line 41805 of file MIMXRT1052.h.

CHRG_DETECT_CLR [1/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT_CLR

USB Charger Detect Register, array offset: 0x1B8, array step: 0x60

Definition at line 41807 of file MIMXRT1052.h.

CHRG_DETECT_CLR [2/2]

__IO { ... } ::CHRG_DETECT_CLR

USB Charger Detect Register, array offset: 0x1B8, array step: 0x60

Definition at line 41807 of file MIMXRT1052.h.

CHRG_DETECT_SET [1/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT_SET

USB Charger Detect Register, array offset: 0x1B4, array step: 0x60

Definition at line 41806 of file MIMXRT1052.h.

CHRG_DETECT_SET [2/2]

__IO { ... } ::CHRG_DETECT_SET

USB Charger Detect Register, array offset: 0x1B4, array step: 0x60

Definition at line 41806 of file MIMXRT1052.h.

CHRG_DETECT_STAT [1/2]

__I uint32_t USB_ANALOG_Type::CHRG_DETECT_STAT

USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60

Definition at line 41811 of file MIMXRT1052.h.

CHRG_DETECT_STAT [2/2]

__I { ... } ::CHRG_DETECT_STAT

USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60

Definition at line 41811 of file MIMXRT1052.h.

CHRG_DETECT_TOG [1/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT_TOG

USB Charger Detect Register, array offset: 0x1BC, array step: 0x60

Definition at line 41808 of file MIMXRT1052.h.

CHRG_DETECT_TOG [2/2]

__IO { ... } ::CHRG_DETECT_TOG

USB Charger Detect Register, array offset: 0x1BC, array step: 0x60

Definition at line 41808 of file MIMXRT1052.h.

CIMR

__IO uint32_t CCM_Type::CIMR

CCM Interrupt Mask Register, offset: 0x5C

Definition at line 4176 of file MIMXRT1052.h.

CINT

__O uint8_t DMA_Type::CINT

Clear Interrupt Request Register, offset: 0x1F

Definition at line 11961 of file MIMXRT1052.h.

CISR

__IO uint32_t CCM_Type::CISR

CCM Interrupt Status Register, offset: 0x58

Definition at line 4175 of file MIMXRT1052.h.

CITER_ELINKNO [1/2]

__IO uint16_t DMA_Type::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

Definition at line 12017 of file MIMXRT1052.h.

CITER_ELINKNO [2/2]

__IO { ... } ::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

Definition at line 12017 of file MIMXRT1052.h.

CITER_ELINKYES [1/2]

__IO { ... } ::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

Definition at line 12018 of file MIMXRT1052.h.

CITER_ELINKYES [2/2]

__IO uint16_t DMA_Type::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

Definition at line 12018 of file MIMXRT1052.h.

CLK_TUNE_CTRL_STATUS

__IO uint32_t USDHC_Type::CLK_TUNE_CTRL_STATUS

CLK Tuning Control and Status, offset: 0x68

Definition at line 42280 of file MIMXRT1052.h.

CLKCTRL

__IO uint8_t EWM_Type::CLKCTRL

Clock Control Register, offset: 0x4

Definition at line 17251 of file MIMXRT1052.h.

CLKPRESCALER

__IO uint8_t EWM_Type::CLKPRESCALER

Clock Prescaler Register, offset: 0x5

Definition at line 17252 of file MIMXRT1052.h.

CLPCR

__IO uint32_t CCM_Type::CLPCR

CCM Low Power Control Register, offset: 0x54

Definition at line 4174 of file MIMXRT1052.h.

CMD_ARG

__IO uint32_t USDHC_Type::CMD_ARG

Command Argument, offset: 0x8

Definition at line 42256 of file MIMXRT1052.h.

CMD_RSP0

__I uint32_t USDHC_Type::CMD_RSP0

Command Response0, offset: 0x10

Definition at line 42258 of file MIMXRT1052.h.

CMD_RSP1

__I uint32_t USDHC_Type::CMD_RSP1

Command Response1, offset: 0x14

Definition at line 42259 of file MIMXRT1052.h.

CMD_RSP2

__I uint32_t USDHC_Type::CMD_RSP2

Command Response2, offset: 0x18

Definition at line 42260 of file MIMXRT1052.h.

CMD_RSP3

__I uint32_t USDHC_Type::CMD_RSP3

Command Response3, offset: 0x1C

Definition at line 42261 of file MIMXRT1052.h.

CMD_XFR_TYP

__IO uint32_t USDHC_Type::CMD_XFR_TYP

Command Transfer Type, offset: 0xC

Definition at line 42257 of file MIMXRT1052.h.

CMEOR

__IO uint32_t CCM_Type::CMEOR

CCM Module Enable Overide Register, offset: 0x88

Definition at line 4187 of file MIMXRT1052.h.

CMPH

__IO uint8_t EWM_Type::CMPH

Compare High Register, offset: 0x3

Definition at line 17250 of file MIMXRT1052.h.

CMPL

__IO uint8_t EWM_Type::CMPL

Compare Low Register, offset: 0x2

Definition at line 17249 of file MIMXRT1052.h.

CMPLD1 [1/2]

__IO { ... } ::CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

Definition at line 37388 of file MIMXRT1052.h.

CMPLD1 [2/2]

__IO uint16_t TMR_Type::CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

Definition at line 37388 of file MIMXRT1052.h.

CMPLD2 [1/2]

__IO uint16_t TMR_Type::CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

Definition at line 37389 of file MIMXRT1052.h.

CMPLD2 [2/2]

__IO { ... } ::CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

Definition at line 37389 of file MIMXRT1052.h.

CNT [1/4]

__I uint32_t GPT_Type::CNT

GPT Counter Register, offset: 0x24

Definition at line 19584 of file MIMXRT1052.h.

CNT [2/4]

__I uint16_t PWM_Type::CNT

Counter Register, array offset: 0x0, array step: 0x60

Definition at line 30845 of file MIMXRT1052.h.

CNT [3/4]

__I { ... } ::CNT

Counter Register, array offset: 0x0, array step: 0x60

Definition at line 30845 of file MIMXRT1052.h.

CNT [4/4]

__IO uint32_t RTWDOG_Type::CNT

Watchdog Counter Register, offset: 0x4

Definition at line 33929 of file MIMXRT1052.h.

CNTR [1/3]

__IO uint32_t GPC_Type::CNTR

GPC Interface control register, offset: 0x0

Definition at line 18997 of file MIMXRT1052.h.

CNTR [2/3]

__IO uint16_t TMR_Type::CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

Definition at line 37385 of file MIMXRT1052.h.

CNTR [3/3]

__IO { ... } ::CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

Definition at line 37385 of file MIMXRT1052.h.

COMP1 [1/2]

__IO uint16_t TMR_Type::COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

Definition at line 37380 of file MIMXRT1052.h.

COMP1 [2/2]

__IO { ... } ::COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

Definition at line 37380 of file MIMXRT1052.h.

COMP2 [1/2]

__IO { ... } ::COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

Definition at line 37381 of file MIMXRT1052.h.

COMP2 [2/2]

__IO uint16_t TMR_Type::COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

Definition at line 37381 of file MIMXRT1052.h.

CONFIGFLAG

__I uint32_t USB_Type::CONFIGFLAG

Configure Flag Register, offset: 0x180

Definition at line 39036 of file MIMXRT1052.h.

CONTEXT

__IO uint32_t DCP_Type::CONTEXT

DCP context buffer pointer, offset: 0x50

Definition at line 10286 of file MIMXRT1052.h.

CPU_CTRL

__IO uint32_t PGC_Type::CPU_CTRL

PGC CPU Control Register, offset: 0x2A0

Definition at line 28379 of file MIMXRT1052.h.

CPU_PDNSCR

__IO uint32_t PGC_Type::CPU_PDNSCR

PGC CPU Pull Down Sequence Control Register, offset: 0x2A8

Definition at line 28381 of file MIMXRT1052.h.

CPU_PUPSCR

__IO uint32_t PGC_Type::CPU_PUPSCR

PGC CPU Power Up Sequence Control Register, offset: 0x2A4

Definition at line 28380 of file MIMXRT1052.h.

CPU_SR

__IO uint32_t PGC_Type::CPU_SR

PGC CPU Power Gating Controller Status Register, offset: 0x2AC

Definition at line 28382 of file MIMXRT1052.h.

CR [1/3]

__IO uint32_t DMA_Type::CR

Control Register, offset: 0x0

Definition at line 11948 of file MIMXRT1052.h.

CR [2/3]

__IO uint32_t GPT_Type::CR

GPT Control Register, offset: 0x0

Definition at line 19578 of file MIMXRT1052.h.

CR [3/3]

__IO uint32_t LPSPI_Type::CR

Control Register, offset: 0x10

Definition at line 26148 of file MIMXRT1052.h.

CR0

__IO uint8_t CMP_Type::CR0

CMP Control Register 0, offset: 0x0

Definition at line 8542 of file MIMXRT1052.h.

CR1

__IO uint8_t CMP_Type::CR1

CMP Control Register 1, offset: 0x1

Definition at line 8543 of file MIMXRT1052.h.

CRC_STAT

__IO uint32_t LCDIF_Type::CRC_STAT

CRC Status Register, offset: 0x1A0

Definition at line 23551 of file MIMXRT1052.h.

CRCR

__I uint32_t CAN_Type::CRCR

CRC Register, offset: 0x44

Definition at line 3329 of file MIMXRT1052.h.

CS [1/3]

__IO uint32_t CAN_Type::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

Definition at line 3337 of file MIMXRT1052.h.

CS [2/3]

__IO { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

Definition at line 3337 of file MIMXRT1052.h.

CS [3/3]

__IO uint32_t RTWDOG_Type::CS

Watchdog Control and Status Register, offset: 0x0

Definition at line 33928 of file MIMXRT1052.h.

CS1CDR

__IO uint32_t CCM_Type::CS1CDR

CCM Clock Divider Register, offset: 0x28

Definition at line 4165 of file MIMXRT1052.h.

CS2CDR

__IO uint32_t CCM_Type::CS2CDR

CCM Clock Divider Register, offset: 0x2C

Definition at line 4166 of file MIMXRT1052.h.

CSC1_COEF0

__IO uint32_t PXP_Type::CSC1_COEF0

Color Space Conversion Coefficient Register 0, offset: 0x1A0

Definition at line 32570 of file MIMXRT1052.h.

CSC1_COEF1

__IO uint32_t PXP_Type::CSC1_COEF1

Color Space Conversion Coefficient Register 1, offset: 0x1B0

Definition at line 32572 of file MIMXRT1052.h.

CSC1_COEF2

__IO uint32_t PXP_Type::CSC1_COEF2

Color Space Conversion Coefficient Register 2, offset: 0x1C0

Definition at line 32574 of file MIMXRT1052.h.

CSCDR1

__IO uint32_t CCM_Type::CSCDR1

CCM Serial Clock Divider Register 1, offset: 0x24

Definition at line 4164 of file MIMXRT1052.h.

CSCDR2

__IO uint32_t CCM_Type::CSCDR2

CCM Serial Clock Divider Register 2, offset: 0x38

Definition at line 4169 of file MIMXRT1052.h.

CSCDR3

__IO uint32_t CCM_Type::CSCDR3

CCM Serial Clock Divider Register 3, offset: 0x3C

Definition at line 4170 of file MIMXRT1052.h.

CSCMR1

__IO uint32_t CCM_Type::CSCMR1

CCM Serial Clock Multiplexer Register 1, offset: 0x1C

Definition at line 4162 of file MIMXRT1052.h.

CSCMR2

__IO uint32_t CCM_Type::CSCMR2

CCM Serial Clock Multiplexer Register 2, offset: 0x20

Definition at line 4163 of file MIMXRT1052.h.

CSCTRL [1/2]

__IO uint16_t TMR_Type::CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

Definition at line 37390 of file MIMXRT1052.h.

CSCTRL [2/2]

__IO { ... } ::CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

Definition at line 37390 of file MIMXRT1052.h.

CSICR1

__IO uint32_t CSI_Type::CSICR1

CSI Control Register 1, offset: 0x0

Definition at line 8792 of file MIMXRT1052.h.

CSICR18

__IO uint32_t CSI_Type::CSICR18

CSI Control Register 18, offset: 0x48

Definition at line 8807 of file MIMXRT1052.h.

CSICR19

__IO uint32_t CSI_Type::CSICR19

CSI Control Register 19, offset: 0x4C

Definition at line 8808 of file MIMXRT1052.h.

CSICR2

__IO uint32_t CSI_Type::CSICR2

CSI Control Register 2, offset: 0x4

Definition at line 8793 of file MIMXRT1052.h.

CSICR3

__IO uint32_t CSI_Type::CSICR3

CSI Control Register 3, offset: 0x8

Definition at line 8794 of file MIMXRT1052.h.

CSIDMASA_FB1

__IO uint32_t CSI_Type::CSIDMASA_FB1

CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28

Definition at line 8802 of file MIMXRT1052.h.

CSIDMASA_FB2

__IO uint32_t CSI_Type::CSIDMASA_FB2

CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C

Definition at line 8803 of file MIMXRT1052.h.

CSIDMASA_STATFIFO

__IO uint32_t CSI_Type::CSIDMASA_STATFIFO

CSI DMA Start Address Register - for STATFIFO, offset: 0x20

Definition at line 8800 of file MIMXRT1052.h.

CSIDMATS_STATFIFO

__IO uint32_t CSI_Type::CSIDMATS_STATFIFO

CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24

Definition at line 8801 of file MIMXRT1052.h.

CSIFBUF_PARA

__IO uint32_t CSI_Type::CSIFBUF_PARA

CSI Frame Buffer Parameter Register, offset: 0x30

Definition at line 8804 of file MIMXRT1052.h.

CSIIMAG_PARA

__IO uint32_t CSI_Type::CSIIMAG_PARA

CSI Image Parameter Register, offset: 0x34

Definition at line 8805 of file MIMXRT1052.h.

CSIRFIFO

__I uint32_t CSI_Type::CSIRFIFO

CSI RX FIFO Register, offset: 0x10

Definition at line 8796 of file MIMXRT1052.h.

CSIRXCNT

__IO uint32_t CSI_Type::CSIRXCNT

CSI RX Count Register, offset: 0x14

Definition at line 8797 of file MIMXRT1052.h.

CSISR

__IO uint32_t CSI_Type::CSISR

CSI Status Register, offset: 0x18

Definition at line 8798 of file MIMXRT1052.h.

CSISTATFIFO

__I uint32_t CSI_Type::CSISTATFIFO

CSI Statistic FIFO Register, offset: 0xC

Definition at line 8795 of file MIMXRT1052.h.

CSL

__IO uint32_t CSU_Type::CSL[32]

Config security level register, array offset: 0x0, array step: 0x4

Definition at line 9470 of file MIMXRT1052.h.

CSR [1/3]

__I uint32_t CCM_Type::CSR

CCM Status Register, offset: 0x8

Definition at line 4157 of file MIMXRT1052.h.

CSR [2/3]

__IO uint16_t DMA_Type::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

Definition at line 12021 of file MIMXRT1052.h.

CSR [3/3]

__IO { ... } ::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

Definition at line 12021 of file MIMXRT1052.h.

CTR_NONCE0_W0

__O uint32_t BEE_Type::CTR_NONCE0_W0

NONCE00 Register, offset: 0x20

Definition at line 3019 of file MIMXRT1052.h.

CTR_NONCE0_W1

__O uint32_t BEE_Type::CTR_NONCE0_W1

NONCE01 Register, offset: 0x24

Definition at line 3020 of file MIMXRT1052.h.

CTR_NONCE0_W2

__O uint32_t BEE_Type::CTR_NONCE0_W2

NONCE02 Register, offset: 0x28

Definition at line 3021 of file MIMXRT1052.h.

CTR_NONCE0_W3

__O uint32_t BEE_Type::CTR_NONCE0_W3

NONCE03 Register, offset: 0x2C

Definition at line 3022 of file MIMXRT1052.h.

CTR_NONCE1_W0

__O uint32_t BEE_Type::CTR_NONCE1_W0

NONCE10 Register, offset: 0x30

Definition at line 3023 of file MIMXRT1052.h.

CTR_NONCE1_W1

__O uint32_t BEE_Type::CTR_NONCE1_W1

NONCE11 Register, offset: 0x34

Definition at line 3024 of file MIMXRT1052.h.

CTR_NONCE1_W2

__O uint32_t BEE_Type::CTR_NONCE1_W2

NONCE12 Register, offset: 0x38

Definition at line 3025 of file MIMXRT1052.h.

CTR_NONCE1_W3

__O uint32_t BEE_Type::CTR_NONCE1_W3

NONCE13 Register, offset: 0x3C

Definition at line 3026 of file MIMXRT1052.h.

CTRL [1/15]

__IO uint32_t ADC_ETC_Type::CTRL

ADC_ETC Global Control Register, offset: 0x0

Definition at line 1618 of file MIMXRT1052.h.

CTRL [2/15]

__IO uint32_t BEE_Type::CTRL

Control Register, offset: 0x0

Definition at line 3011 of file MIMXRT1052.h.

CTRL [3/15]

__IO uint32_t DCP_Type::CTRL

DCP control register 0, offset: 0x0

Definition at line 10270 of file MIMXRT1052.h.

CTRL [4/15]

__IO uint16_t ENC_Type::CTRL

Control Register, offset: 0x0

Definition at line 15139 of file MIMXRT1052.h.

CTRL [5/15]

__IO uint8_t EWM_Type::CTRL

Control Register, offset: 0x0

Definition at line 17247 of file MIMXRT1052.h.

CTRL [6/15]

__IO uint32_t FLEXIO_Type::CTRL

FlexIO Control Register, offset: 0x8

Definition at line 17369 of file MIMXRT1052.h.

CTRL [7/15]

__IO uint32_t LCDIF_Type::CTRL

LCDIF General Control Register, offset: 0x0

Definition at line 23519 of file MIMXRT1052.h.

CTRL [8/15]

__IO uint32_t LPUART_Type::CTRL

LPUART Control Register, offset: 0x18

Definition at line 26778 of file MIMXRT1052.h.

CTRL [9/15]

__IO uint32_t OCOTP_Type::CTRL

OTP Controller Control Register, offset: 0x0

Definition at line 27699 of file MIMXRT1052.h.

CTRL [10/15]

__IO uint16_t PWM_Type::CTRL

Control Register, array offset: 0x6, array step: 0x60

Definition at line 30848 of file MIMXRT1052.h.

CTRL [11/15]

__IO { ... } ::CTRL

Control Register, array offset: 0x6, array step: 0x60

Definition at line 30848 of file MIMXRT1052.h.

CTRL [12/15]

__IO uint32_t PXP_Type::CTRL

Control Register 0, offset: 0x0

Definition at line 32510 of file MIMXRT1052.h.

CTRL [13/15]

__IO uint16_t TMR_Type::CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

Definition at line 37386 of file MIMXRT1052.h.

CTRL [14/15]

__IO { ... } ::CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

Definition at line 37386 of file MIMXRT1052.h.

CTRL [15/15]

__IO uint32_t USBPHY_Type::CTRL

USB PHY General Control Register, offset: 0x30

Definition at line 40696 of file MIMXRT1052.h.

CTRL0

__IO uint16_t XBARA_Type::CTRL0

Crossbar A Control Register 0, offset: 0x84

Definition at line 44201 of file MIMXRT1052.h.

CTRL1 [1/3]

__IO uint32_t CAN_Type::CTRL1

Control 1 Register, offset: 0x4

Definition at line 3314 of file MIMXRT1052.h.

CTRL1 [2/3]

__IO uint32_t LCDIF_Type::CTRL1

LCDIF General Control1 Register, offset: 0x10

Definition at line 23523 of file MIMXRT1052.h.

CTRL1 [3/3]

__IO uint16_t XBARA_Type::CTRL1

Crossbar A Control Register 1, offset: 0x86

Definition at line 44202 of file MIMXRT1052.h.

CTRL1_CLR

__IO uint32_t LCDIF_Type::CTRL1_CLR

LCDIF General Control1 Register, offset: 0x18

Definition at line 23525 of file MIMXRT1052.h.

CTRL1_SET

__IO uint32_t LCDIF_Type::CTRL1_SET

LCDIF General Control1 Register, offset: 0x14

Definition at line 23524 of file MIMXRT1052.h.

CTRL1_TOG

__IO uint32_t LCDIF_Type::CTRL1_TOG

LCDIF General Control1 Register, offset: 0x1C

Definition at line 23526 of file MIMXRT1052.h.

CTRL2 [1/5]

__IO uint32_t CAN_Type::CTRL2

Control 2 Register, offset: 0x34

Definition at line 3326 of file MIMXRT1052.h.

CTRL2 [2/5]

__IO uint16_t ENC_Type::CTRL2

Control 2 Register, offset: 0x1E

Definition at line 15154 of file MIMXRT1052.h.

CTRL2 [3/5]

__IO uint32_t LCDIF_Type::CTRL2

LCDIF General Control2 Register, offset: 0x20

Definition at line 23527 of file MIMXRT1052.h.

CTRL2 [4/5]

__IO uint16_t PWM_Type::CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

Definition at line 30847 of file MIMXRT1052.h.

CTRL2 [5/5]

__IO { ... } ::CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

Definition at line 30847 of file MIMXRT1052.h.

CTRL2_CLR

__IO uint32_t LCDIF_Type::CTRL2_CLR

LCDIF General Control2 Register, offset: 0x28

Definition at line 23529 of file MIMXRT1052.h.

CTRL2_SET

__IO uint32_t LCDIF_Type::CTRL2_SET

LCDIF General Control2 Register, offset: 0x24

Definition at line 23528 of file MIMXRT1052.h.

CTRL2_TOG

__IO uint32_t LCDIF_Type::CTRL2_TOG

LCDIF General Control2 Register, offset: 0x2C

Definition at line 23530 of file MIMXRT1052.h.

CTRL_CLR [1/5]

__IO uint32_t DCP_Type::CTRL_CLR

DCP control register 0, offset: 0x8

Definition at line 10272 of file MIMXRT1052.h.

CTRL_CLR [2/5]

__IO uint32_t LCDIF_Type::CTRL_CLR

LCDIF General Control Register, offset: 0x8

Definition at line 23521 of file MIMXRT1052.h.

CTRL_CLR [3/5]

__IO uint32_t OCOTP_Type::CTRL_CLR

OTP Controller Control Register, offset: 0x8

Definition at line 27701 of file MIMXRT1052.h.

CTRL_CLR [4/5]

__IO uint32_t PXP_Type::CTRL_CLR

Control Register 0, offset: 0x8

Definition at line 32512 of file MIMXRT1052.h.

CTRL_CLR [5/5]

__IO uint32_t USBPHY_Type::CTRL_CLR

USB PHY General Control Register, offset: 0x38

Definition at line 40698 of file MIMXRT1052.h.

CTRL_SET [1/5]

__IO uint32_t DCP_Type::CTRL_SET

DCP control register 0, offset: 0x4

Definition at line 10271 of file MIMXRT1052.h.

CTRL_SET [2/5]

__IO uint32_t LCDIF_Type::CTRL_SET

LCDIF General Control Register, offset: 0x4

Definition at line 23520 of file MIMXRT1052.h.

CTRL_SET [3/5]

__IO uint32_t OCOTP_Type::CTRL_SET

OTP Controller Control Register, offset: 0x4

Definition at line 27700 of file MIMXRT1052.h.

CTRL_SET [4/5]

__IO uint32_t PXP_Type::CTRL_SET

Control Register 0, offset: 0x4

Definition at line 32511 of file MIMXRT1052.h.

CTRL_SET [5/5]

__IO uint32_t USBPHY_Type::CTRL_SET

USB PHY General Control Register, offset: 0x34

Definition at line 40697 of file MIMXRT1052.h.

CTRL_TOG [1/5]

__IO uint32_t DCP_Type::CTRL_TOG

DCP control register 0, offset: 0xC

Definition at line 10273 of file MIMXRT1052.h.

CTRL_TOG [2/5]

__IO uint32_t LCDIF_Type::CTRL_TOG

LCDIF General Control Register, offset: 0xC

Definition at line 23522 of file MIMXRT1052.h.

CTRL_TOG [3/5]

__IO uint32_t OCOTP_Type::CTRL_TOG

OTP Controller Control Register, offset: 0xC

Definition at line 27702 of file MIMXRT1052.h.

CTRL_TOG [4/5]

__IO uint32_t PXP_Type::CTRL_TOG

Control Register 0, offset: 0xC

Definition at line 32513 of file MIMXRT1052.h.

CTRL_TOG [5/5]

__IO uint32_t USBPHY_Type::CTRL_TOG

USB PHY General Control Register, offset: 0x3C

Definition at line 40699 of file MIMXRT1052.h.

CUR_BUF

__IO uint32_t LCDIF_Type::CUR_BUF

LCD Interface Current Buffer Address Register, offset: 0x40

Definition at line 23533 of file MIMXRT1052.h.

CV

__IO uint32_t ADC_Type::CV

Compare value register, offset: 0x50

Definition at line 1303 of file MIMXRT1052.h.

CVAL [1/2]

__I uint32_t PIT_Type::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

Definition at line 28517 of file MIMXRT1052.h.

CVAL [2/2]

__I { ... } ::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

Definition at line 28517 of file MIMXRT1052.h.

CVAL0 [1/2]

__I uint16_t PWM_Type::CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

Definition at line 30876 of file MIMXRT1052.h.

CVAL0 [2/2]

__I { ... } ::CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

Definition at line 30876 of file MIMXRT1052.h.

CVAL0CYC [1/2]

__I uint16_t PWM_Type::CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

Definition at line 30877 of file MIMXRT1052.h.

CVAL0CYC [2/2]

__I { ... } ::CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

Definition at line 30877 of file MIMXRT1052.h.

CVAL1 [1/2]

__I uint16_t PWM_Type::CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

Definition at line 30878 of file MIMXRT1052.h.

CVAL1 [2/2]

__I { ... } ::CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

Definition at line 30878 of file MIMXRT1052.h.

CVAL1CYC [1/2]

__I uint16_t PWM_Type::CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

Definition at line 30879 of file MIMXRT1052.h.

CVAL1CYC [2/2]

__I { ... } ::CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

Definition at line 30879 of file MIMXRT1052.h.

CVAL2 [1/2]

__I uint16_t PWM_Type::CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

Definition at line 30880 of file MIMXRT1052.h.

CVAL2 [2/2]

__I { ... } ::CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

Definition at line 30880 of file MIMXRT1052.h.

CVAL2CYC [1/2]

__I uint16_t PWM_Type::CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

Definition at line 30881 of file MIMXRT1052.h.

CVAL2CYC [2/2]

__I { ... } ::CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

Definition at line 30881 of file MIMXRT1052.h.

CVAL3 [1/2]

__I uint16_t PWM_Type::CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

Definition at line 30882 of file MIMXRT1052.h.

CVAL3 [2/2]

__I { ... } ::CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

Definition at line 30882 of file MIMXRT1052.h.

CVAL3CYC [1/2]

__I uint16_t PWM_Type::CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

Definition at line 30883 of file MIMXRT1052.h.

CVAL3CYC [2/2]

__I { ... } ::CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

Definition at line 30883 of file MIMXRT1052.h.

CVAL4 [1/2]

__I uint16_t PWM_Type::CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

Definition at line 30884 of file MIMXRT1052.h.

CVAL4 [2/2]

__I { ... } ::CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

Definition at line 30884 of file MIMXRT1052.h.

CVAL4CYC [1/2]

__I uint16_t PWM_Type::CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

Definition at line 30885 of file MIMXRT1052.h.

CVAL4CYC [2/2]

__I { ... } ::CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

Definition at line 30885 of file MIMXRT1052.h.

CVAL5 [1/2]

__I uint16_t PWM_Type::CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

Definition at line 30886 of file MIMXRT1052.h.

CVAL5 [2/2]

__I { ... } ::CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

Definition at line 30886 of file MIMXRT1052.h.

CVAL5CYC [1/2]

__I uint16_t PWM_Type::CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

Definition at line 30887 of file MIMXRT1052.h.

CVAL5CYC [2/2]

__I { ... } ::CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

Definition at line 30887 of file MIMXRT1052.h.

DACCR

__IO uint8_t CMP_Type::DACCR

DAC Control Register, offset: 0x4

Definition at line 8546 of file MIMXRT1052.h.

DADDR [1/2]

__IO uint32_t DMA_Type::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

Definition at line 12014 of file MIMXRT1052.h.

DADDR [2/2]

__IO { ... } ::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

Definition at line 12014 of file MIMXRT1052.h.

DATA [1/2]

__IO uint32_t LPUART_Type::DATA

LPUART Data Register, offset: 0x1C

Definition at line 26779 of file MIMXRT1052.h.

DATA [2/2]

__IO uint32_t OCOTP_Type::DATA

OTP Controller Write Data Register, offset: 0x20

Definition at line 27705 of file MIMXRT1052.h.

DATA_BUFF_ACC_PORT

__IO uint32_t USDHC_Type::DATA_BUFF_ACC_PORT

Data Buffer Access Port, offset: 0x20

Definition at line 42262 of file MIMXRT1052.h.

DBG1

__I uint32_t CAN_Type::DBG1

Debug 1 register, offset: 0x58

Definition at line 3333 of file MIMXRT1052.h.

DBG2

__I uint32_t CAN_Type::DBG2

Debug 2 register, offset: 0x5C

Definition at line 3334 of file MIMXRT1052.h.

DBGDATA

__I uint32_t DCP_Type::DBGDATA

DCP debug data register, offset: 0x410

Definition at line 10357 of file MIMXRT1052.h.

DBGSELECT

__IO uint32_t DCP_Type::DBGSELECT

DCP debug select register, offset: 0x400

Definition at line 10355 of file MIMXRT1052.h.

DBICR0

__IO uint32_t SEMC_Type::DBICR0

DBI-B control register 0, offset: 0x80

Definition at line 34154 of file MIMXRT1052.h.

DBICR1

__IO uint32_t SEMC_Type::DBICR1

DBI-B control register 1, offset: 0x84

Definition at line 34155 of file MIMXRT1052.h.

DCCPARAMS

__I uint32_t USB_Type::DCCPARAMS

Device Controller Capability Parameters, offset: 0x124

Definition at line 39015 of file MIMXRT1052.h.

DCHPRI0

__IO uint8_t DMA_Type::DCHPRI0

Channel n Priority Register, offset: 0x103

Definition at line 11974 of file MIMXRT1052.h.

DCHPRI1

__IO uint8_t DMA_Type::DCHPRI1

Channel n Priority Register, offset: 0x102

Definition at line 11973 of file MIMXRT1052.h.

DCHPRI10

__IO uint8_t DMA_Type::DCHPRI10

Channel n Priority Register, offset: 0x109

Definition at line 11980 of file MIMXRT1052.h.

DCHPRI11

__IO uint8_t DMA_Type::DCHPRI11

Channel n Priority Register, offset: 0x108

Definition at line 11979 of file MIMXRT1052.h.

DCHPRI12

__IO uint8_t DMA_Type::DCHPRI12

Channel n Priority Register, offset: 0x10F

Definition at line 11986 of file MIMXRT1052.h.

DCHPRI13

__IO uint8_t DMA_Type::DCHPRI13

Channel n Priority Register, offset: 0x10E

Definition at line 11985 of file MIMXRT1052.h.

DCHPRI14

__IO uint8_t DMA_Type::DCHPRI14

Channel n Priority Register, offset: 0x10D

Definition at line 11984 of file MIMXRT1052.h.

DCHPRI15

__IO uint8_t DMA_Type::DCHPRI15

Channel n Priority Register, offset: 0x10C

Definition at line 11983 of file MIMXRT1052.h.

DCHPRI16

__IO uint8_t DMA_Type::DCHPRI16

Channel n Priority Register, offset: 0x113

Definition at line 11990 of file MIMXRT1052.h.

DCHPRI17

__IO uint8_t DMA_Type::DCHPRI17

Channel n Priority Register, offset: 0x112

Definition at line 11989 of file MIMXRT1052.h.

DCHPRI18

__IO uint8_t DMA_Type::DCHPRI18

Channel n Priority Register, offset: 0x111

Definition at line 11988 of file MIMXRT1052.h.

DCHPRI19

__IO uint8_t DMA_Type::DCHPRI19

Channel n Priority Register, offset: 0x110

Definition at line 11987 of file MIMXRT1052.h.

DCHPRI2

__IO uint8_t DMA_Type::DCHPRI2

Channel n Priority Register, offset: 0x101

Definition at line 11972 of file MIMXRT1052.h.

DCHPRI20

__IO uint8_t DMA_Type::DCHPRI20

Channel n Priority Register, offset: 0x117

Definition at line 11994 of file MIMXRT1052.h.

DCHPRI21

__IO uint8_t DMA_Type::DCHPRI21

Channel n Priority Register, offset: 0x116

Definition at line 11993 of file MIMXRT1052.h.

DCHPRI22

__IO uint8_t DMA_Type::DCHPRI22

Channel n Priority Register, offset: 0x115

Definition at line 11992 of file MIMXRT1052.h.

DCHPRI23

__IO uint8_t DMA_Type::DCHPRI23

Channel n Priority Register, offset: 0x114

Definition at line 11991 of file MIMXRT1052.h.

DCHPRI24

__IO uint8_t DMA_Type::DCHPRI24

Channel n Priority Register, offset: 0x11B

Definition at line 11998 of file MIMXRT1052.h.

DCHPRI25

__IO uint8_t DMA_Type::DCHPRI25

Channel n Priority Register, offset: 0x11A

Definition at line 11997 of file MIMXRT1052.h.

DCHPRI26

__IO uint8_t DMA_Type::DCHPRI26

Channel n Priority Register, offset: 0x119

Definition at line 11996 of file MIMXRT1052.h.

DCHPRI27

__IO uint8_t DMA_Type::DCHPRI27

Channel n Priority Register, offset: 0x118

Definition at line 11995 of file MIMXRT1052.h.

DCHPRI28

__IO uint8_t DMA_Type::DCHPRI28

Channel n Priority Register, offset: 0x11F

Definition at line 12002 of file MIMXRT1052.h.

DCHPRI29

__IO uint8_t DMA_Type::DCHPRI29

Channel n Priority Register, offset: 0x11E

Definition at line 12001 of file MIMXRT1052.h.

DCHPRI3

__IO uint8_t DMA_Type::DCHPRI3

Channel n Priority Register, offset: 0x100

Definition at line 11971 of file MIMXRT1052.h.

DCHPRI30

__IO uint8_t DMA_Type::DCHPRI30

Channel n Priority Register, offset: 0x11D

Definition at line 12000 of file MIMXRT1052.h.

DCHPRI31

__IO uint8_t DMA_Type::DCHPRI31

Channel n Priority Register, offset: 0x11C

Definition at line 11999 of file MIMXRT1052.h.

DCHPRI4

__IO uint8_t DMA_Type::DCHPRI4

Channel n Priority Register, offset: 0x107

Definition at line 11978 of file MIMXRT1052.h.

DCHPRI5

__IO uint8_t DMA_Type::DCHPRI5

Channel n Priority Register, offset: 0x106

Definition at line 11977 of file MIMXRT1052.h.

DCHPRI6

__IO uint8_t DMA_Type::DCHPRI6

Channel n Priority Register, offset: 0x105

Definition at line 11976 of file MIMXRT1052.h.

DCHPRI7

__IO uint8_t DMA_Type::DCHPRI7

Channel n Priority Register, offset: 0x104

Definition at line 11975 of file MIMXRT1052.h.

DCHPRI8

__IO uint8_t DMA_Type::DCHPRI8

Channel n Priority Register, offset: 0x10B

Definition at line 11982 of file MIMXRT1052.h.

DCHPRI9

__IO uint8_t DMA_Type::DCHPRI9

Channel n Priority Register, offset: 0x10A

Definition at line 11981 of file MIMXRT1052.h.

DCIVERSION

__I uint16_t USB_Type::DCIVERSION

Device Controller Interface Version, offset: 0x120

Definition at line 39013 of file MIMXRT1052.h.

DEBUG0_STATUS

__I uint32_t USBPHY_Type::DEBUG0_STATUS

UTMI Debug Status Register 0, offset: 0x60

Definition at line 40706 of file MIMXRT1052.h.

DEBUG1

__IO uint32_t USBPHY_Type::DEBUG1

UTMI Debug Status Register 1, offset: 0x70

Definition at line 40708 of file MIMXRT1052.h.

DEBUG1_CLR

__IO uint32_t USBPHY_Type::DEBUG1_CLR

UTMI Debug Status Register 1, offset: 0x78

Definition at line 40710 of file MIMXRT1052.h.

DEBUG1_SET

__IO uint32_t USBPHY_Type::DEBUG1_SET

UTMI Debug Status Register 1, offset: 0x74

Definition at line 40709 of file MIMXRT1052.h.

DEBUG1_TOG

__IO uint32_t USBPHY_Type::DEBUG1_TOG

UTMI Debug Status Register 1, offset: 0x7C

Definition at line 40711 of file MIMXRT1052.h.

DEBUG_CLR

__IO uint32_t USBPHY_Type::DEBUG_CLR

USB PHY Debug Register, offset: 0x58

Definition at line 40704 of file MIMXRT1052.h.

DEBUG_MODE

__IO uint32_t TSC_Type::DEBUG_MODE

Debug Mode Register, offset: 0x70

Definition at line 38561 of file MIMXRT1052.h.

DEBUG_MODE2

__IO uint32_t TSC_Type::DEBUG_MODE2

Debug Mode Register 2, offset: 0x80

Definition at line 38563 of file MIMXRT1052.h.

DEBUG_SET

__IO uint32_t USBPHY_Type::DEBUG_SET

USB PHY Debug Register, offset: 0x54

Definition at line 40703 of file MIMXRT1052.h.

DEBUG_TOG

__IO uint32_t USBPHY_Type::DEBUG_TOG

USB PHY Debug Register, offset: 0x5C

Definition at line 40705 of file MIMXRT1052.h.

DEBUGr

__IO uint32_t USBPHY_Type::DEBUGr

USB PHY Debug Register, offset: 0x50

Definition at line 40702 of file MIMXRT1052.h.

DER

__IO uint32_t LPSPI_Type::DER

DMA Enable Register, offset: 0x1C

Definition at line 26151 of file MIMXRT1052.h.

DEVICEADDR [1/2]

__IO uint32_t USB_Type::DEVICEADDR

Device Address, offset: 0x154

Definition at line 39023 of file MIMXRT1052.h.

DEVICEADDR [2/2]

__IO { ... } ::DEVICEADDR

Device Address, offset: 0x154

Definition at line 39023 of file MIMXRT1052.h.

DIGPROG

__I uint32_t USB_ANALOG_Type::DIGPROG

Chip Silicon Version, offset: 0x260

Definition at line 41822 of file MIMXRT1052.h.

DISMAP [1/2]

__IO uint16_t PWM_Type::DISMAP[2]

Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2

Definition at line 30867 of file MIMXRT1052.h.

DISMAP [2/2]

__IO { ... } ::DISMAP[2]

Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2

Definition at line 30867 of file MIMXRT1052.h.

DLAST_SGA [1/2]

__IO uint32_t DMA_Type::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

Definition at line 12020 of file MIMXRT1052.h.

DLAST_SGA [2/2]

__IO { ... } ::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

Definition at line 12020 of file MIMXRT1052.h.

DLL_CTRL

__IO uint32_t USDHC_Type::DLL_CTRL

DLL (Delay Line) Control, offset: 0x60

Definition at line 42278 of file MIMXRT1052.h.

DLL_STATUS

__I uint32_t USDHC_Type::DLL_STATUS

DLL Status, offset: 0x64

Definition at line 42279 of file MIMXRT1052.h.

DLLCR

__IO uint32_t FLEXSPI_Type::DLLCR[2]

DLL Control Register 0, array offset: 0xC0, array step: 0x4

Definition at line 18113 of file MIMXRT1052.h.

DMA [1/2]

__IO { ... } ::DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

Definition at line 37392 of file MIMXRT1052.h.

DMA [2/2]

__IO uint16_t TMR_Type::DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

Definition at line 37392 of file MIMXRT1052.h.

DMA_CTRL

__IO uint32_t ADC_ETC_Type::DMA_CTRL

ETC DMA control Register, offset: 0xC

Definition at line 1621 of file MIMXRT1052.h.

DMAEN [1/2]

__IO uint16_t PWM_Type::DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

Definition at line 30865 of file MIMXRT1052.h.

DMAEN [2/2]

__IO { ... } ::DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

Definition at line 30865 of file MIMXRT1052.h.

DMR0

__IO uint32_t LPSPI_Type::DMR0

Data Match Register 0, offset: 0x30

Definition at line 26155 of file MIMXRT1052.h.

DMR1

__IO uint32_t LPSPI_Type::DMR1

Data Match Register 1, offset: 0x34

Definition at line 26156 of file MIMXRT1052.h.

DOFF [1/2]

__IO uint16_t DMA_Type::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

Definition at line 12015 of file MIMXRT1052.h.

DOFF [2/2]

__IO { ... } ::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

Definition at line 12015 of file MIMXRT1052.h.

DONE0_1_IRQ

__IO uint32_t ADC_ETC_Type::DONE0_1_IRQ

ETC DONE0 and DONE1 IRQ State Register, offset: 0x4

Definition at line 1619 of file MIMXRT1052.h.

DONE2_ERR_IRQ

__IO uint32_t ADC_ETC_Type::DONE2_ERR_IRQ

ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8

Definition at line 1620 of file MIMXRT1052.h.

DR

__IO uint32_t GPIO_Type::DR

GPIO data register, offset: 0x0

Definition at line 19126 of file MIMXRT1052.h.

DR_CLEAR

__O uint32_t GPIO_Type::DR_CLEAR

GPIO data register CLEAR, offset: 0x88

Definition at line 19136 of file MIMXRT1052.h.

DR_SET

__O uint32_t GPIO_Type::DR_SET

GPIO data register SET, offset: 0x84

Definition at line 19135 of file MIMXRT1052.h.

DR_TOGGLE

__O uint32_t GPIO_Type::DR_TOGGLE

GPIO data register TOGGLE, offset: 0x8C

Definition at line 19137 of file MIMXRT1052.h.

DS_ADDR

__IO uint32_t USDHC_Type::DS_ADDR

DMA System Address, offset: 0x0

Definition at line 42254 of file MIMXRT1052.h.

DTCNT0 [1/2]

__IO uint16_t PWM_Type::DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

Definition at line 30868 of file MIMXRT1052.h.

DTCNT0 [2/2]

__IO { ... } ::DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

Definition at line 30868 of file MIMXRT1052.h.

DTCNT1 [1/2]

__IO uint16_t PWM_Type::DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

Definition at line 30869 of file MIMXRT1052.h.

DTCNT1 [2/2]

__IO { ... } ::DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

Definition at line 30869 of file MIMXRT1052.h.

DTSRCSEL

__IO uint16_t PWM_Type::DTSRCSEL

PWM Source Select Register, offset: 0x186

Definition at line 30893 of file MIMXRT1052.h.

EARS

__IO uint32_t DMA_Type::EARS

Enable Asynchronous Request in Stop Register, offset: 0x44

Definition at line 11969 of file MIMXRT1052.h.

ECR [1/2]

__IO uint32_t CAN_Type::ECR

Error Counter Register, offset: 0x1C

Definition at line 3320 of file MIMXRT1052.h.

ECR [2/2]

__IO uint32_t ENET_Type::ECR

Ethernet Control Register, offset: 0x24

Definition at line 15612 of file MIMXRT1052.h.

EDGE_SEL

__IO uint32_t GPIO_Type::EDGE_SEL

GPIO edge select register, offset: 0x1C

Definition at line 19133 of file MIMXRT1052.h.

EEI

__IO uint32_t DMA_Type::EEI

Enable Error Interrupt Register, offset: 0x14

Definition at line 11953 of file MIMXRT1052.h.

EIMR

__IO uint32_t ENET_Type::EIMR

Interrupt Mask Register, offset: 0x8

Definition at line 15607 of file MIMXRT1052.h.

EIR

__IO uint32_t ENET_Type::EIR

Interrupt Event Register, offset: 0x4

Definition at line 15606 of file MIMXRT1052.h.

ENBL [1/2]

__IO uint16_t TMR_Type::ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

Definition at line 37394 of file MIMXRT1052.h.

ENBL [2/2]

__IO { ... } ::ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

Definition at line 37394 of file MIMXRT1052.h.

ENDPTCOMPLETE

__IO uint32_t USB_Type::ENDPTCOMPLETE

Endpoint Complete, offset: 0x1BC

Definition at line 39045 of file MIMXRT1052.h.

ENDPTCTRL

__IO uint32_t USB_Type::ENDPTCTRL[7]

Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4

Definition at line 39047 of file MIMXRT1052.h.

ENDPTCTRL0

__IO uint32_t USB_Type::ENDPTCTRL0

Endpoint Control0, offset: 0x1C0

Definition at line 39046 of file MIMXRT1052.h.

ENDPTFLUSH

__IO uint32_t USB_Type::ENDPTFLUSH

Endpoint Flush, offset: 0x1B4

Definition at line 39043 of file MIMXRT1052.h.

ENDPTLISTADDR [1/2]

__IO uint32_t USB_Type::ENDPTLISTADDR

Endpoint List Address, offset: 0x158

Definition at line 39028 of file MIMXRT1052.h.

ENDPTLISTADDR [2/2]

__IO { ... } ::ENDPTLISTADDR

Endpoint List Address, offset: 0x158

Definition at line 39028 of file MIMXRT1052.h.

ENDPTNAK

__IO uint32_t USB_Type::ENDPTNAK

Endpoint NAK, offset: 0x178

Definition at line 39034 of file MIMXRT1052.h.

ENDPTNAKEN

__IO uint32_t USB_Type::ENDPTNAKEN

Endpoint NAK Enable, offset: 0x17C

Definition at line 39035 of file MIMXRT1052.h.

ENDPTPRIME

__IO uint32_t USB_Type::ENDPTPRIME

Endpoint Prime, offset: 0x1B0

Definition at line 39042 of file MIMXRT1052.h.

ENDPTSETUPSTAT

__IO uint32_t USB_Type::ENDPTSETUPSTAT

Endpoint Setup Status, offset: 0x1AC

Definition at line 39041 of file MIMXRT1052.h.

ENDPTSTAT

__I uint32_t USB_Type::ENDPTSTAT

Endpoint Status, offset: 0x1B8

Definition at line 39044 of file MIMXRT1052.h.

ENT

__I uint32_t TRNG_Type::ENT[16]

Entropy Read Register, array offset: 0x40, array step: 0x4

Definition at line 37921 of file MIMXRT1052.h.

ERQ

__IO uint32_t DMA_Type::ERQ

Enable Request Register, offset: 0xC

Definition at line 11951 of file MIMXRT1052.h.

ERR

__IO uint32_t DMA_Type::ERR

Error Register, offset: 0x2C

Definition at line 11965 of file MIMXRT1052.h.

ES

__I uint32_t DMA_Type::ES

Error Status Register, offset: 0x4

Definition at line 11949 of file MIMXRT1052.h.

ESR1

__IO uint32_t CAN_Type::ESR1

Error and Status 1 Register, offset: 0x20

Definition at line 3321 of file MIMXRT1052.h.

ESR2

__I uint32_t CAN_Type::ESR2

Error and Status 2 Register, offset: 0x38

Definition at line 3327 of file MIMXRT1052.h.

FCR

__IO uint32_t LPSPI_Type::FCR

FIFO Control Register, offset: 0x58

Definition at line 26160 of file MIMXRT1052.h.

FCTRL

__IO uint16_t PWM_Type::FCTRL

Fault Control Register, offset: 0x18C

Definition at line 30896 of file MIMXRT1052.h.

FCTRL2

__IO uint16_t PWM_Type::FCTRL2

Fault Control 2 Register, offset: 0x194

Definition at line 30900 of file MIMXRT1052.h.

FFILT

__IO uint16_t PWM_Type::FFILT

Fault Filter Register, offset: 0x190

Definition at line 30898 of file MIMXRT1052.h.

FIFO

__IO uint32_t LPUART_Type::FIFO

LPUART FIFO Register, offset: 0x28

Definition at line 26782 of file MIMXRT1052.h.

FILT [1/3]

__IO uint16_t ENC_Type::FILT

Input Filter Register, offset: 0x2

Definition at line 15140 of file MIMXRT1052.h.

FILT [2/3]

__IO uint16_t TMR_Type::FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

Definition at line 37391 of file MIMXRT1052.h.

FILT [3/3]

__IO { ... } ::FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

Definition at line 37391 of file MIMXRT1052.h.

FLOW_CONTROL

__IO uint32_t TSC_Type::FLOW_CONTROL

Flow Control, offset: 0x20

Definition at line 38551 of file MIMXRT1052.h.

FLSHCR0

__IO uint32_t FLEXSPI_Type::FLSHCR0[4]

Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4

Definition at line 18100 of file MIMXRT1052.h.

FLSHCR1

__IO uint32_t FLEXSPI_Type::FLSHCR1[4]

Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4

Definition at line 18101 of file MIMXRT1052.h.

FLSHCR2

__IO uint32_t FLEXSPI_Type::FLSHCR2[4]

Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4

Definition at line 18102 of file MIMXRT1052.h.

FLSHCR4

__IO uint32_t FLEXSPI_Type::FLSHCR4

Flash Control Register 4, offset: 0x94

Definition at line 18104 of file MIMXRT1052.h.

FORCE_EVENT

__O uint32_t USDHC_Type::FORCE_EVENT

Force Event, offset: 0x50

Definition at line 42274 of file MIMXRT1052.h.

FPR

__IO uint8_t CMP_Type::FPR

CMP Filter Period Register, offset: 0x2

Definition at line 8544 of file MIMXRT1052.h.

FRACVAL1 [1/2]

__IO uint16_t PWM_Type::FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

Definition at line 30851 of file MIMXRT1052.h.

FRACVAL1 [2/2]

__IO { ... } ::FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

Definition at line 30851 of file MIMXRT1052.h.

FRACVAL2 [1/2]

__IO uint16_t PWM_Type::FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

Definition at line 30853 of file MIMXRT1052.h.

FRACVAL2 [2/2]

__IO { ... } ::FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

Definition at line 30853 of file MIMXRT1052.h.

FRACVAL3 [1/2]

__IO uint16_t PWM_Type::FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

Definition at line 30855 of file MIMXRT1052.h.

FRACVAL3 [2/2]

__IO { ... } ::FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

Definition at line 30855 of file MIMXRT1052.h.

FRACVAL4 [1/2]

__IO uint16_t PWM_Type::FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

Definition at line 30857 of file MIMXRT1052.h.

FRACVAL4 [2/2]

__IO { ... } ::FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

Definition at line 30857 of file MIMXRT1052.h.

FRACVAL5 [1/2]

__IO uint16_t PWM_Type::FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

Definition at line 30859 of file MIMXRT1052.h.

FRACVAL5 [2/2]

__IO { ... } ::FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

Definition at line 30859 of file MIMXRT1052.h.

FRCTRL [1/2]

__IO uint16_t PWM_Type::FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

Definition at line 30861 of file MIMXRT1052.h.

FRCTRL [2/2]

__IO { ... } ::FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

Definition at line 30861 of file MIMXRT1052.h.

FRINDEX

__IO uint32_t USB_Type::FRINDEX

USB Frame Index, offset: 0x14C

Definition at line 39020 of file MIMXRT1052.h.

FRQCNT [1/2]

__I uint32_t TRNG_Type::FRQCNT

Frequency Count Register, offset: 0x1C

Definition at line 37889 of file MIMXRT1052.h.

FRQCNT [2/2]

__I { ... } ::FRQCNT

Frequency Count Register, offset: 0x1C

Definition at line 37889 of file MIMXRT1052.h.

FRQMAX [1/2]

__IO uint32_t TRNG_Type::FRQMAX

Frequency Count Maximum Limit Register, offset: 0x1C

Definition at line 37890 of file MIMXRT1052.h.

FRQMAX [2/2]

__IO { ... } ::FRQMAX

Frequency Count Maximum Limit Register, offset: 0x1C

Definition at line 37890 of file MIMXRT1052.h.

FRQMIN

__IO uint32_t TRNG_Type::FRQMIN

Frequency Count Minimum Limit Register, offset: 0x18

Definition at line 37887 of file MIMXRT1052.h.

FSR

__I uint32_t LPSPI_Type::FSR

FIFO Status Register, offset: 0x5C

Definition at line 26161 of file MIMXRT1052.h.

FSTS

__IO uint16_t PWM_Type::FSTS

Fault Status Register, offset: 0x18E

Definition at line 30897 of file MIMXRT1052.h.

FTRL

__IO uint32_t ENET_Type::FTRL

Frame Truncation Length, offset: 0x1B0

Definition at line 15649 of file MIMXRT1052.h.

FTST

__IO uint16_t PWM_Type::FTST

Fault Test Register, offset: 0x192

Definition at line 30899 of file MIMXRT1052.h.

GALR

__IO uint32_t ENET_Type::GALR

Descriptor Group Lower Address Register, offset: 0x124

Definition at line 15633 of file MIMXRT1052.h.

GAUR

__IO uint32_t ENET_Type::GAUR

Descriptor Group Upper Address Register, offset: 0x120

Definition at line 15632 of file MIMXRT1052.h.

GC

__IO uint32_t ADC_Type::GC

General control register, offset: 0x48

Definition at line 1301 of file MIMXRT1052.h.

GDIR

__IO uint32_t GPIO_Type::GDIR

GPIO direction register, offset: 0x4

Definition at line 19127 of file MIMXRT1052.h.

GFWR

__IO uint32_t CAN_Type::GFWR

Glitch Filter Width Registers, offset: 0x9E0

Definition at line 3345 of file MIMXRT1052.h.

GLOBAL

__IO uint32_t LPUART_Type::GLOBAL

LPUART Global Register, offset: 0x8

Definition at line 26774 of file MIMXRT1052.h.

GP1

__IO uint32_t OCOTP_Type::GP1

Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660

Definition at line 27780 of file MIMXRT1052.h.

GP2

__IO uint32_t OCOTP_Type::GP2

Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670

Definition at line 27782 of file MIMXRT1052.h.

GP3

__IO uint32_t OCOTP_Type::GP3

Value of OTP Bank4 Word4 (MAC Address), offset: 0x640

Definition at line 27778 of file MIMXRT1052.h.

GPR

__IO uint32_t SRC_Type::GPR[10]

SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4

Definition at line 36907 of file MIMXRT1052.h.

GPR0 [1/2]

uint32_t IOMUXC_GPR_Type::GPR0

GPR0 General Purpose Register, offset: 0x0

Definition at line 20858 of file MIMXRT1052.h.

GPR0 [2/2]

uint32_t IOMUXC_SNVS_GPR_Type::GPR0

GPR0 General Purpose Register, offset: 0x0

Definition at line 23304 of file MIMXRT1052.h.

GPR1 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR1

GPR1 General Purpose Register, offset: 0x4

Definition at line 20859 of file MIMXRT1052.h.

GPR1 [2/2]

uint32_t IOMUXC_SNVS_GPR_Type::GPR1

GPR1 General Purpose Register, offset: 0x4

Definition at line 23305 of file MIMXRT1052.h.

GPR10

__IO uint32_t IOMUXC_GPR_Type::GPR10

GPR10 General Purpose Register, offset: 0x28

Definition at line 20868 of file MIMXRT1052.h.

GPR11

__IO uint32_t IOMUXC_GPR_Type::GPR11

GPR11 General Purpose Register, offset: 0x2C

Definition at line 20869 of file MIMXRT1052.h.

GPR12

__IO uint32_t IOMUXC_GPR_Type::GPR12

GPR12 General Purpose Register, offset: 0x30

Definition at line 20870 of file MIMXRT1052.h.

GPR13

__IO uint32_t IOMUXC_GPR_Type::GPR13

GPR13 General Purpose Register, offset: 0x34

Definition at line 20871 of file MIMXRT1052.h.

GPR14

__IO uint32_t IOMUXC_GPR_Type::GPR14

GPR14 General Purpose Register, offset: 0x38

Definition at line 20872 of file MIMXRT1052.h.

GPR15

uint32_t IOMUXC_GPR_Type::GPR15

GPR15 General Purpose Register, offset: 0x3C

Definition at line 20873 of file MIMXRT1052.h.

GPR16

__IO uint32_t IOMUXC_GPR_Type::GPR16

GPR16 General Purpose Register, offset: 0x40

Definition at line 20874 of file MIMXRT1052.h.

GPR17

__IO uint32_t IOMUXC_GPR_Type::GPR17

GPR17 General Purpose Register, offset: 0x44

Definition at line 20875 of file MIMXRT1052.h.

GPR18

__IO uint32_t IOMUXC_GPR_Type::GPR18

GPR18 General Purpose Register, offset: 0x48

Definition at line 20876 of file MIMXRT1052.h.

GPR19

__IO uint32_t IOMUXC_GPR_Type::GPR19

GPR19 General Purpose Register, offset: 0x4C

Definition at line 20877 of file MIMXRT1052.h.

GPR2 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR2

GPR2 General Purpose Register, offset: 0x8

Definition at line 20860 of file MIMXRT1052.h.

GPR2 [2/2]

uint32_t IOMUXC_SNVS_GPR_Type::GPR2

GPR2 General Purpose Register, offset: 0x8

Definition at line 23306 of file MIMXRT1052.h.

GPR20

__IO uint32_t IOMUXC_GPR_Type::GPR20

GPR20 General Purpose Register, offset: 0x50

Definition at line 20878 of file MIMXRT1052.h.

GPR21

__IO uint32_t IOMUXC_GPR_Type::GPR21

GPR21 General Purpose Register, offset: 0x54

Definition at line 20879 of file MIMXRT1052.h.

GPR22

__IO uint32_t IOMUXC_GPR_Type::GPR22

GPR22 General Purpose Register, offset: 0x58

Definition at line 20880 of file MIMXRT1052.h.

GPR23

__IO uint32_t IOMUXC_GPR_Type::GPR23

GPR23 General Purpose Register, offset: 0x5C

Definition at line 20881 of file MIMXRT1052.h.

GPR24

__IO uint32_t IOMUXC_GPR_Type::GPR24

GPR24 General Purpose Register, offset: 0x60

Definition at line 20882 of file MIMXRT1052.h.

GPR25

__IO uint32_t IOMUXC_GPR_Type::GPR25

GPR25 General Purpose Register, offset: 0x64

Definition at line 20883 of file MIMXRT1052.h.

GPR3 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR3

GPR3 General Purpose Register, offset: 0xC

Definition at line 20861 of file MIMXRT1052.h.

GPR3 [2/2]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR3

GPR3 General Purpose Register, offset: 0xC

Definition at line 23307 of file MIMXRT1052.h.

GPR4

__IO uint32_t IOMUXC_GPR_Type::GPR4

GPR4 General Purpose Register, offset: 0x10

Definition at line 20862 of file MIMXRT1052.h.

GPR5

__IO uint32_t IOMUXC_GPR_Type::GPR5

GPR5 General Purpose Register, offset: 0x14

Definition at line 20863 of file MIMXRT1052.h.

GPR6

__IO uint32_t IOMUXC_GPR_Type::GPR6

GPR6 General Purpose Register, offset: 0x18

Definition at line 20864 of file MIMXRT1052.h.

GPR7

__IO uint32_t IOMUXC_GPR_Type::GPR7

GPR7 General Purpose Register, offset: 0x1C

Definition at line 20865 of file MIMXRT1052.h.

GPR8

__IO uint32_t IOMUXC_GPR_Type::GPR8

GPR8 General Purpose Register, offset: 0x20

Definition at line 20866 of file MIMXRT1052.h.

GPR9

uint32_t IOMUXC_GPR_Type::GPR9

GPR9 General Purpose Register, offset: 0x24

Definition at line 20867 of file MIMXRT1052.h.

GPTIMER0CTRL

__IO uint32_t USB_Type::GPTIMER0CTRL

General Purpose Timer #0 Controller, offset: 0x84

Definition at line 39002 of file MIMXRT1052.h.

GPTIMER0LD

__IO uint32_t USB_Type::GPTIMER0LD

General Purpose Timer #0 Load, offset: 0x80

Definition at line 39001 of file MIMXRT1052.h.

GPTIMER1CTRL

__IO uint32_t USB_Type::GPTIMER1CTRL

General Purpose Timer #1 Controller, offset: 0x8C

Definition at line 39004 of file MIMXRT1052.h.

GPTIMER1LD

__IO uint32_t USB_Type::GPTIMER1LD

General Purpose Timer #1 Load, offset: 0x88

Definition at line 39003 of file MIMXRT1052.h.

GS

__IO uint32_t ADC_Type::GS

General status register, offset: 0x4C

Definition at line 1302 of file MIMXRT1052.h.

HC

__IO uint32_t ADC_Type::HC[8]

Control register for hardware triggers, array offset: 0x0, array step: 0x4

Definition at line 1297 of file MIMXRT1052.h.

HCCPARAMS

__I uint32_t USB_Type::HCCPARAMS

Host Controller Capability Parameters, offset: 0x108

Definition at line 39011 of file MIMXRT1052.h.

HCIVERSION

__I uint16_t USB_Type::HCIVERSION

Host Controller Interface Version, offset: 0x102

Definition at line 39009 of file MIMXRT1052.h.

HCSPARAMS

__I uint32_t USB_Type::HCSPARAMS

Host Controller Structural Parameters, offset: 0x104

Definition at line 39010 of file MIMXRT1052.h.

HOLD [1/2]

__IO uint16_t TMR_Type::HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

Definition at line 37384 of file MIMXRT1052.h.

HOLD [2/2]

__IO { ... } ::HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

Definition at line 37384 of file MIMXRT1052.h.

HOST_CTRL_CAP

__IO uint32_t USDHC_Type::HOST_CTRL_CAP

Host Controller Capabilities, offset: 0x40

Definition at line 42270 of file MIMXRT1052.h.

HP0

__IO uint32_t CSU_Type::HP0

HP0 register, offset: 0x200

Definition at line 9472 of file MIMXRT1052.h.

HPCOMR

__IO uint32_t SNVS_Type::HPCOMR

SNVS_HP Command Register, offset: 0x4

Definition at line 35321 of file MIMXRT1052.h.

HPCONTROL0

__IO uint32_t CSU_Type::HPCONTROL0

HPCONTROL0 register, offset: 0x358

Definition at line 9476 of file MIMXRT1052.h.

HPCR

__IO uint32_t SNVS_Type::HPCR

SNVS_HP Control Register, offset: 0x8

Definition at line 35322 of file MIMXRT1052.h.

HPHACIVR

__IO uint32_t SNVS_Type::HPHACIVR

SNVS_HP High Assurance Counter IV Register, offset: 0x1C

Definition at line 35327 of file MIMXRT1052.h.

HPHACR

__I uint32_t SNVS_Type::HPHACR

SNVS_HP High Assurance Counter Register, offset: 0x20

Definition at line 35328 of file MIMXRT1052.h.

HPLR

__IO uint32_t SNVS_Type::HPLR

SNVS_HP Lock Register, offset: 0x0

Definition at line 35320 of file MIMXRT1052.h.

HPRTCLR

__IO uint32_t SNVS_Type::HPRTCLR

SNVS_HP Real Time Counter LSB Register, offset: 0x28

Definition at line 35330 of file MIMXRT1052.h.

HPRTCMR

__IO uint32_t SNVS_Type::HPRTCMR

SNVS_HP Real Time Counter MSB Register, offset: 0x24

Definition at line 35329 of file MIMXRT1052.h.

HPSICR

__IO uint32_t SNVS_Type::HPSICR

SNVS_HP Security Interrupt Control Register, offset: 0xC

Definition at line 35323 of file MIMXRT1052.h.

HPSR

__IO uint32_t SNVS_Type::HPSR

SNVS_HP Status Register, offset: 0x14

Definition at line 35325 of file MIMXRT1052.h.

HPSVCR

__IO uint32_t SNVS_Type::HPSVCR

SNVS_HP Security Violation Control Register, offset: 0x10

Definition at line 35324 of file MIMXRT1052.h.

HPSVSR

__IO uint32_t SNVS_Type::HPSVSR

SNVS_HP Security Violation Status Register, offset: 0x18

Definition at line 35326 of file MIMXRT1052.h.

HPTALR

__IO uint32_t SNVS_Type::HPTALR

SNVS_HP Time Alarm LSB Register, offset: 0x30

Definition at line 35332 of file MIMXRT1052.h.

HPTAMR

__IO uint32_t SNVS_Type::HPTAMR

SNVS_HP Time Alarm MSB Register, offset: 0x2C

Definition at line 35331 of file MIMXRT1052.h.

HPVIDR1

__I uint32_t SNVS_Type::HPVIDR1

SNVS_HP Version ID Register 1, offset: 0xBF8

Definition at line 35353 of file MIMXRT1052.h.

HPVIDR2

__I uint32_t SNVS_Type::HPVIDR2

SNVS_HP Version ID Register 2, offset: 0xBFC

Definition at line 35354 of file MIMXRT1052.h.

HRS

__I uint32_t DMA_Type::HRS

Hardware Request Status Register, offset: 0x34

Definition at line 11967 of file MIMXRT1052.h.

HS

__I uint32_t ADC_Type::HS

Status register for HW triggers, offset: 0x20

Definition at line 1298 of file MIMXRT1052.h.

HWDEVICE

__I uint32_t USB_Type::HWDEVICE

Device Hardware Parameters, offset: 0xC

Definition at line 38997 of file MIMXRT1052.h.

HWGENERAL

__I uint32_t USB_Type::HWGENERAL

Hardware General, offset: 0x4

Definition at line 38995 of file MIMXRT1052.h.

HWHOST

__I uint32_t USB_Type::HWHOST

Host Hardware Parameters, offset: 0x8

Definition at line 38996 of file MIMXRT1052.h.

HWRXBUF

__I uint32_t USB_Type::HWRXBUF

RX Buffer Hardware Parameters, offset: 0x14

Definition at line 38999 of file MIMXRT1052.h.

HWTXBUF

__I uint32_t USB_Type::HWTXBUF

TX Buffer Hardware Parameters, offset: 0x10

Definition at line 38998 of file MIMXRT1052.h.

IALR

__IO uint32_t ENET_Type::IALR

Descriptor Individual Lower Address Register, offset: 0x11C

Definition at line 15631 of file MIMXRT1052.h.

IAUR

__IO uint32_t ENET_Type::IAUR

Descriptor Individual Upper Address Register, offset: 0x118

Definition at line 15630 of file MIMXRT1052.h.

ICR

__I uint32_t GPT_Type::ICR[2]

GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4

Definition at line 19583 of file MIMXRT1052.h.

ICR1

__IO uint32_t GPIO_Type::ICR1

GPIO interrupt configuration register1, offset: 0xC

Definition at line 19129 of file MIMXRT1052.h.

ICR2

__IO uint32_t GPIO_Type::ICR2

GPIO interrupt configuration register2, offset: 0x10

Definition at line 19130 of file MIMXRT1052.h.

ID [1/3]

__IO uint32_t CAN_Type::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

Definition at line 3338 of file MIMXRT1052.h.

ID [2/3]

__IO { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

Definition at line 3338 of file MIMXRT1052.h.

ID [3/3]

__I uint32_t USB_Type::ID

Identification register, offset: 0x0

Definition at line 38994 of file MIMXRT1052.h.

IEEE_R_ALIGN

__I uint32_t ENET_Type::IEEE_R_ALIGN

Frames Received with Alignment Error Statistic Register, offset: 0x2D4

Definition at line 15705 of file MIMXRT1052.h.

IEEE_R_CRC

__I uint32_t ENET_Type::IEEE_R_CRC

Frames Received with CRC Error Statistic Register, offset: 0x2D0

Definition at line 15704 of file MIMXRT1052.h.

IEEE_R_DROP

__I uint32_t ENET_Type::IEEE_R_DROP

Frames not Counted Correctly Statistic Register, offset: 0x2C8

Definition at line 15702 of file MIMXRT1052.h.

IEEE_R_FDXFC

__I uint32_t ENET_Type::IEEE_R_FDXFC

Flow Control Pause Frames Received Statistic Register, offset: 0x2DC

Definition at line 15707 of file MIMXRT1052.h.

IEEE_R_FRAME_OK

__I uint32_t ENET_Type::IEEE_R_FRAME_OK

Frames Received OK Statistic Register, offset: 0x2CC

Definition at line 15703 of file MIMXRT1052.h.

IEEE_R_MACERR

__I uint32_t ENET_Type::IEEE_R_MACERR

Receive FIFO Overflow Count Statistic Register, offset: 0x2D8

Definition at line 15706 of file MIMXRT1052.h.

IEEE_R_OCTETS_OK

__I uint32_t ENET_Type::IEEE_R_OCTETS_OK

Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0

Definition at line 15708 of file MIMXRT1052.h.

IEEE_T_1COL

__I uint32_t ENET_Type::IEEE_T_1COL

Frames Transmitted with Single Collision Statistic Register, offset: 0x250

Definition at line 15674 of file MIMXRT1052.h.

IEEE_T_CSERR

__I uint32_t ENET_Type::IEEE_T_CSERR

Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268

Definition at line 15680 of file MIMXRT1052.h.

IEEE_T_DEF

__I uint32_t ENET_Type::IEEE_T_DEF

Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258

Definition at line 15676 of file MIMXRT1052.h.

IEEE_T_DROP

uint32_t ENET_Type::IEEE_T_DROP

Reserved Statistic Register, offset: 0x248

Definition at line 15672 of file MIMXRT1052.h.

IEEE_T_EXCOL

__I uint32_t ENET_Type::IEEE_T_EXCOL

Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260

Definition at line 15678 of file MIMXRT1052.h.

IEEE_T_FDXFC

__I uint32_t ENET_Type::IEEE_T_FDXFC

Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270

Definition at line 15682 of file MIMXRT1052.h.

IEEE_T_FRAME_OK

__I uint32_t ENET_Type::IEEE_T_FRAME_OK

Frames Transmitted OK Statistic Register, offset: 0x24C

Definition at line 15673 of file MIMXRT1052.h.

IEEE_T_LCOL

__I uint32_t ENET_Type::IEEE_T_LCOL

Frames Transmitted with Late Collision Statistic Register, offset: 0x25C

Definition at line 15677 of file MIMXRT1052.h.

IEEE_T_MACERR

__I uint32_t ENET_Type::IEEE_T_MACERR

Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264

Definition at line 15679 of file MIMXRT1052.h.

IEEE_T_MCOL

__I uint32_t ENET_Type::IEEE_T_MCOL

Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254

Definition at line 15675 of file MIMXRT1052.h.

IEEE_T_OCTETS_OK

__I uint32_t ENET_Type::IEEE_T_OCTETS_OK

Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274

Definition at line 15683 of file MIMXRT1052.h.

IEEE_T_SQE

__I uint32_t ENET_Type::IEEE_T_SQE

Reserved Statistic Register, offset: 0x26C

Definition at line 15681 of file MIMXRT1052.h.

IER

__IO uint32_t LPSPI_Type::IER

Interrupt Enable Register, offset: 0x18

Definition at line 26150 of file MIMXRT1052.h.

IFLAG1

__IO uint32_t CAN_Type::IFLAG1

Interrupt Flags 1 Register, offset: 0x30

Definition at line 3325 of file MIMXRT1052.h.

IFLAG2

__IO uint32_t CAN_Type::IFLAG2

Interrupt Flags 2 Register, offset: 0x2C

Definition at line 3324 of file MIMXRT1052.h.

IMASK1

__IO uint32_t CAN_Type::IMASK1

Interrupt Masks 1 Register, offset: 0x28

Definition at line 3323 of file MIMXRT1052.h.

IMASK2

__IO uint32_t CAN_Type::IMASK2

Interrupt Masks 2 Register, offset: 0x24

Definition at line 3322 of file MIMXRT1052.h.

IMR [1/3]

__IO uint32_t GPC_Type::IMR[4]

IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4

Definition at line 18999 of file MIMXRT1052.h.

IMR [2/3]

__I uint16_t ENC_Type::IMR

Input Monitor Register, offset: 0x1A

Definition at line 15152 of file MIMXRT1052.h.

IMR [3/3]

__IO uint32_t GPIO_Type::IMR

GPIO interrupt mask register, offset: 0x14

Definition at line 19131 of file MIMXRT1052.h.

IMR5

__IO uint32_t GPC_Type::IMR5

IRQ masking register 5, offset: 0x34

Definition at line 19002 of file MIMXRT1052.h.

INIT [1/2]

__IO uint16_t PWM_Type::INIT

Initial Count Register, array offset: 0x2, array step: 0x60

Definition at line 30846 of file MIMXRT1052.h.

INIT [2/2]

__IO { ... } ::INIT

Initial Count Register, array offset: 0x2, array step: 0x60

Definition at line 30846 of file MIMXRT1052.h.

INSTANCE

struct { ... } USB_ANALOG_Type::INSTANCE[2]

INT

__IO uint32_t DMA_Type::INT

Interrupt Request Register, offset: 0x24

Definition at line 11963 of file MIMXRT1052.h.

INT_CTRL

__IO uint32_t TRNG_Type::INT_CTRL

Interrupt Control Register, offset: 0xA4

Definition at line 37931 of file MIMXRT1052.h.

INT_EN

__IO uint32_t TSC_Type::INT_EN

Interrupt Enable, offset: 0x40

Definition at line 38555 of file MIMXRT1052.h.

INT_MASK

__IO uint32_t TRNG_Type::INT_MASK

Mask Register, offset: 0xA8

Definition at line 37932 of file MIMXRT1052.h.

INT_SIG_EN [1/2]

__IO uint32_t FLEXRAM_Type::INT_SIG_EN

Interrupt Enable Register, offset: 0x18

Definition at line 17946 of file MIMXRT1052.h.

INT_SIG_EN [2/2]

__IO uint32_t TSC_Type::INT_SIG_EN

Interrupt Signal Enable, offset: 0x50

Definition at line 38557 of file MIMXRT1052.h.

INT_SIGNAL_EN

__IO uint32_t USDHC_Type::INT_SIGNAL_EN

Interrupt Signal Enable, offset: 0x38

Definition at line 42268 of file MIMXRT1052.h.

INT_STAT_EN

__IO uint32_t FLEXRAM_Type::INT_STAT_EN

Interrupt Status Enable Register, offset: 0x14

Definition at line 17945 of file MIMXRT1052.h.

INT_STATUS [1/4]

__IO uint32_t FLEXRAM_Type::INT_STATUS

Interrupt Status Register, offset: 0x10

Definition at line 17944 of file MIMXRT1052.h.

INT_STATUS [2/4]

__I uint32_t TRNG_Type::INT_STATUS

Interrupt Status Register, offset: 0xAC

Definition at line 37933 of file MIMXRT1052.h.

INT_STATUS [3/4]

__IO uint32_t TSC_Type::INT_STATUS

Intterrupt Status, offset: 0x60

Definition at line 38559 of file MIMXRT1052.h.

INT_STATUS [4/4]

__IO uint32_t USDHC_Type::INT_STATUS

Interrupt Status, offset: 0x30

Definition at line 42266 of file MIMXRT1052.h.

INT_STATUS_EN

__IO uint32_t USDHC_Type::INT_STATUS_EN

Interrupt Status Enable, offset: 0x34

Definition at line 42267 of file MIMXRT1052.h.

INTEN [1/4]

__IO uint32_t FLEXSPI_Type::INTEN

Interrupt Enable Register, offset: 0x10

Definition at line 18094 of file MIMXRT1052.h.

INTEN [2/4]

__IO uint16_t PWM_Type::INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

Definition at line 30864 of file MIMXRT1052.h.

INTEN [3/4]

__IO { ... } ::INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

Definition at line 30864 of file MIMXRT1052.h.

INTEN [4/4]

__IO uint32_t SEMC_Type::INTEN

Interrupt Enable Register, offset: 0x38

Definition at line 34136 of file MIMXRT1052.h.

INTR [1/2]

__IO uint32_t FLEXSPI_Type::INTR

Interrupt Register, offset: 0x14

Definition at line 18095 of file MIMXRT1052.h.

INTR [2/2]

__IO uint32_t SEMC_Type::INTR

Interrupt Enable Register, offset: 0x3C

Definition at line 34137 of file MIMXRT1052.h.

IOCR

__IO uint32_t SEMC_Type::IOCR

IO Mux Control Register, offset: 0x4

Definition at line 34131 of file MIMXRT1052.h.

IPCMD [1/2]

__IO uint32_t FLEXSPI_Type::IPCMD

IP Command Register, offset: 0xB0

Definition at line 18109 of file MIMXRT1052.h.

IPCMD [2/2]

__IO uint32_t SEMC_Type::IPCMD

IP Command register, offset: 0x9C

Definition at line 34160 of file MIMXRT1052.h.

IPCR0 [1/2]

__IO uint32_t FLEXSPI_Type::IPCR0

IP Control Register 0, offset: 0xA0

Definition at line 18106 of file MIMXRT1052.h.

IPCR0 [2/2]

__IO uint32_t SEMC_Type::IPCR0

IP Command control register 0, offset: 0x90

Definition at line 34157 of file MIMXRT1052.h.

IPCR1 [1/2]

__IO uint32_t FLEXSPI_Type::IPCR1

IP Control Register 1, offset: 0xA4

Definition at line 18107 of file MIMXRT1052.h.

IPCR1 [2/2]

__IO uint32_t SEMC_Type::IPCR1

IP Command control register 1, offset: 0x94

Definition at line 34158 of file MIMXRT1052.h.

IPCR2

__IO uint32_t SEMC_Type::IPCR2

IP Command control register 2, offset: 0x98

Definition at line 34159 of file MIMXRT1052.h.

IPRXDAT

__I uint32_t SEMC_Type::IPRXDAT

RX DATA register (for IP Command), offset: 0xB0

Definition at line 34163 of file MIMXRT1052.h.

IPRXFCR

__IO uint32_t FLEXSPI_Type::IPRXFCR

IP RX FIFO Control Register, offset: 0xB8

Definition at line 18111 of file MIMXRT1052.h.

IPRXFSTS

__I uint32_t FLEXSPI_Type::IPRXFSTS

IP RX FIFO Status Register, offset: 0xF0

Definition at line 18119 of file MIMXRT1052.h.

IPTXDAT

__IO uint32_t SEMC_Type::IPTXDAT

TX DATA register (for IP Command), offset: 0xA0

Definition at line 34161 of file MIMXRT1052.h.

IPTXFCR

__IO uint32_t FLEXSPI_Type::IPTXFCR

IP TX FIFO Control Register, offset: 0xBC

Definition at line 18112 of file MIMXRT1052.h.

IPTXFSTS

__I uint32_t FLEXSPI_Type::IPTXFSTS

IP TX FIFO Status Register, offset: 0xF4

Definition at line 18120 of file MIMXRT1052.h.

IR

__IO uint32_t GPT_Type::IR

GPT Interrupt Register, offset: 0xC

Definition at line 19581 of file MIMXRT1052.h.

ISR [1/2]

__I uint32_t GPC_Type::ISR[4]

IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4

Definition at line 19000 of file MIMXRT1052.h.

ISR [2/2]

__IO uint32_t GPIO_Type::ISR

GPIO interrupt status register, offset: 0x18

Definition at line 19132 of file MIMXRT1052.h.

ISR5

__I uint32_t GPC_Type::ISR5

IRQ status resister 5, offset: 0x38

Definition at line 19003 of file MIMXRT1052.h.

KDDR

__IO uint16_t KPP_Type::KDDR

Keypad Data Direction Register, offset: 0x4

Definition at line 23380 of file MIMXRT1052.h.

KEY

__IO uint32_t DCP_Type::KEY

DCP key index, offset: 0x60

Definition at line 10288 of file MIMXRT1052.h.

KEYDATA

__IO uint32_t DCP_Type::KEYDATA

DCP key data, offset: 0x70

Definition at line 10290 of file MIMXRT1052.h.

KPCR

__IO uint16_t KPP_Type::KPCR

Keypad Control Register, offset: 0x0

Definition at line 23378 of file MIMXRT1052.h.

KPDR

__IO uint16_t KPP_Type::KPDR

Keypad Data Register, offset: 0x6

Definition at line 23381 of file MIMXRT1052.h.

KPSR

__IO uint16_t KPP_Type::KPSR

Keypad Status Register, offset: 0x2

Definition at line 23379 of file MIMXRT1052.h.

LCOMP

__IO uint16_t ENC_Type::LCOMP

Lower Position Compare Register, offset: 0x26

Definition at line 15158 of file MIMXRT1052.h.

LDVAL [1/2]

__IO uint32_t PIT_Type::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

Definition at line 28516 of file MIMXRT1052.h.

LDVAL [2/2]

__IO { ... } ::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

Definition at line 28516 of file MIMXRT1052.h.

LINIT

__IO uint16_t ENC_Type::LINIT

Lower Initialization Register, offset: 0x18

Definition at line 15151 of file MIMXRT1052.h.

LMOD

__IO uint16_t ENC_Type::LMOD

Lower Modulus Register, offset: 0x22

Definition at line 15156 of file MIMXRT1052.h.

LOAD [1/2]

__IO uint16_t TMR_Type::LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

Definition at line 37383 of file MIMXRT1052.h.

LOAD [2/2]

__IO { ... } ::LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

Definition at line 37383 of file MIMXRT1052.h.

LOCK

__IO uint32_t OCOTP_Type::LOCK

Value of OTP Bank0 Word0 (Lock controls), offset: 0x400

Definition at line 27722 of file MIMXRT1052.h.

LOOPBACK [1/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK

USB Loopback Test Register, array offset: 0x1E0, array step: 0x60

Definition at line 41813 of file MIMXRT1052.h.

LOOPBACK [2/2]

__IO { ... } ::LOOPBACK

USB Loopback Test Register, array offset: 0x1E0, array step: 0x60

Definition at line 41813 of file MIMXRT1052.h.

LOOPBACK_CLR [1/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK_CLR

USB Loopback Test Register, array offset: 0x1E8, array step: 0x60

Definition at line 41815 of file MIMXRT1052.h.

LOOPBACK_CLR [2/2]

__IO { ... } ::LOOPBACK_CLR

USB Loopback Test Register, array offset: 0x1E8, array step: 0x60

Definition at line 41815 of file MIMXRT1052.h.

LOOPBACK_SET [1/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK_SET

USB Loopback Test Register, array offset: 0x1E4, array step: 0x60

Definition at line 41814 of file MIMXRT1052.h.

LOOPBACK_SET [2/2]

__IO { ... } ::LOOPBACK_SET

USB Loopback Test Register, array offset: 0x1E4, array step: 0x60

Definition at line 41814 of file MIMXRT1052.h.

LOOPBACK_TOG [1/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK_TOG

USB Loopback Test Register, array offset: 0x1EC, array step: 0x60

Definition at line 41816 of file MIMXRT1052.h.

LOOPBACK_TOG [2/2]

__IO { ... } ::LOOPBACK_TOG

USB Loopback Test Register, array offset: 0x1EC, array step: 0x60

Definition at line 41816 of file MIMXRT1052.h.

LOWPWR_CTRL

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL

XTAL OSC (LP) Control Register, offset: 0x270

Definition at line 45175 of file MIMXRT1052.h.

LOWPWR_CTRL_CLR

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_CLR

XTAL OSC (LP) Control Register, offset: 0x278

Definition at line 45177 of file MIMXRT1052.h.

LOWPWR_CTRL_SET

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_SET

XTAL OSC (LP) Control Register, offset: 0x274

Definition at line 45176 of file MIMXRT1052.h.

LOWPWR_CTRL_TOG

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_TOG

XTAL OSC (LP) Control Register, offset: 0x27C

Definition at line 45178 of file MIMXRT1052.h.

LPCR

__IO uint32_t SNVS_Type::LPCR

SNVS_LP Control Register, offset: 0x38

Definition at line 35334 of file MIMXRT1052.h.

LPGPR

__IO uint32_t SNVS_Type::LPGPR[8]

SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4

Definition at line 35351 of file MIMXRT1052.h.

LPGPR0_LEGACY_ALIAS

__IO uint32_t SNVS_Type::LPGPR0_LEGACY_ALIAS

SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68

Definition at line 35346 of file MIMXRT1052.h.

LPGPR_ALIAS

__IO uint32_t SNVS_Type::LPGPR_ALIAS[4]

SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4

Definition at line 35349 of file MIMXRT1052.h.

LPLR

__IO uint32_t SNVS_Type::LPLR

SNVS_LP Lock Register, offset: 0x34

Definition at line 35333 of file MIMXRT1052.h.

LPMKCR

__IO uint32_t SNVS_Type::LPMKCR

SNVS_LP Master Key Control Register, offset: 0x3C

Definition at line 35335 of file MIMXRT1052.h.

LPOS

__IO uint16_t ENC_Type::LPOS

Lower Position Counter Register, offset: 0x10

Definition at line 15147 of file MIMXRT1052.h.

LPOSH

__I uint16_t ENC_Type::LPOSH

Lower Position Hold Register, offset: 0x14

Definition at line 15149 of file MIMXRT1052.h.

LPPGDR

__IO uint32_t SNVS_Type::LPPGDR

SNVS_LP Power Glitch Detector Register, offset: 0x64

Definition at line 35345 of file MIMXRT1052.h.

LPSMCLR

__I uint32_t SNVS_Type::LPSMCLR

SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60

Definition at line 35344 of file MIMXRT1052.h.

LPSMCMR

__I uint32_t SNVS_Type::LPSMCMR

SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C

Definition at line 35343 of file MIMXRT1052.h.

LPSR

__IO uint32_t SNVS_Type::LPSR

SNVS_LP Status Register, offset: 0x4C

Definition at line 35339 of file MIMXRT1052.h.

LPSRTCLR

__IO uint32_t SNVS_Type::LPSRTCLR

SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54

Definition at line 35341 of file MIMXRT1052.h.

LPSRTCMR

__IO uint32_t SNVS_Type::LPSRTCMR

SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50

Definition at line 35340 of file MIMXRT1052.h.

LPSVCR

__IO uint32_t SNVS_Type::LPSVCR

SNVS_LP Security Violation Control Register, offset: 0x40

Definition at line 35336 of file MIMXRT1052.h.

LPTAR

__IO uint32_t SNVS_Type::LPTAR

SNVS_LP Time Alarm Register, offset: 0x58

Definition at line 35342 of file MIMXRT1052.h.

LPTDCR

__IO uint32_t SNVS_Type::LPTDCR

SNVS_LP Tamper Detectors Configuration Register, offset: 0x48

Definition at line 35338 of file MIMXRT1052.h.

LPZMKR

__IO uint32_t SNVS_Type::LPZMKR[8]

SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4

Definition at line 35347 of file MIMXRT1052.h.

LTMR64H

__I uint32_t PIT_Type::LTMR64H

PIT Upper Lifetime Timer Register, offset: 0xE0

Definition at line 28512 of file MIMXRT1052.h.

LTMR64L

__I uint32_t PIT_Type::LTMR64L

PIT Lower Lifetime Timer Register, offset: 0xE4

Definition at line 28513 of file MIMXRT1052.h.

LUT

__IO uint32_t FLEXSPI_Type::LUT[64]

LUT 0..LUT 63, array offset: 0x200, array step: 0x4

Definition at line 18124 of file MIMXRT1052.h.

LUT0_ADDR

__IO uint32_t LCDIF_Type::LUT0_ADDR

Lookup Table Control Register., offset: 0xB10

Definition at line 23580 of file MIMXRT1052.h.

LUT0_DATA

__IO uint32_t LCDIF_Type::LUT0_DATA

Lookup Table Data Register., offset: 0xB20

Definition at line 23582 of file MIMXRT1052.h.

LUT1_ADDR

__IO uint32_t LCDIF_Type::LUT1_ADDR

Lookup Table Control Register., offset: 0xB30

Definition at line 23584 of file MIMXRT1052.h.

LUT1_DATA

__IO uint32_t LCDIF_Type::LUT1_DATA

Lookup Table Data Register., offset: 0xB40

Definition at line 23586 of file MIMXRT1052.h.

LUT_CTRL

__IO uint32_t LCDIF_Type::LUT_CTRL

Lookup Table Data Register., offset: 0xB00

Definition at line 23578 of file MIMXRT1052.h.

LUTCR

__IO uint32_t FLEXSPI_Type::LUTCR

LUT Control Register, offset: 0x1C

Definition at line 18097 of file MIMXRT1052.h.

LUTKEY

__IO uint32_t FLEXSPI_Type::LUTKEY

LUT Key Register, offset: 0x18

Definition at line 18096 of file MIMXRT1052.h.

MAC0

__IO uint32_t OCOTP_Type::MAC0

Value of OTP Bank4 Word2 (MAC Address), offset: 0x620

Definition at line 27774 of file MIMXRT1052.h.

MAC1

__IO uint32_t OCOTP_Type::MAC1

Value of OTP Bank4 Word3 (MAC Address), offset: 0x630

Definition at line 27776 of file MIMXRT1052.h.

MASK

__IO uint16_t PWM_Type::MASK

Mask Register, offset: 0x182

Definition at line 30891 of file MIMXRT1052.h.

MATCH

__IO uint32_t LPUART_Type::MATCH

LPUART Match Address Register, offset: 0x20

Definition at line 26780 of file MIMXRT1052.h.

MB

struct { ... } CAN_Type::MB[64]

MCCR0

__IO uint32_t LPI2C_Type::MCCR0

Master Clock Configuration Register 0, offset: 0x48

Definition at line 25109 of file MIMXRT1052.h.

MCCR1

__IO uint32_t LPI2C_Type::MCCR1

Master Clock Configuration Register 1, offset: 0x50

Definition at line 25111 of file MIMXRT1052.h.

MCFGR0

__IO uint32_t LPI2C_Type::MCFGR0

Master Configuration Register 0, offset: 0x20

Definition at line 25102 of file MIMXRT1052.h.

MCFGR1

__IO uint32_t LPI2C_Type::MCFGR1

Master Configuration Register 1, offset: 0x24

Definition at line 25103 of file MIMXRT1052.h.

MCFGR2

__IO uint32_t LPI2C_Type::MCFGR2

Master Configuration Register 2, offset: 0x28

Definition at line 25104 of file MIMXRT1052.h.

MCFGR3

__IO uint32_t LPI2C_Type::MCFGR3

Master Configuration Register 3, offset: 0x2C

Definition at line 25105 of file MIMXRT1052.h.

MCR [1/4]

__IO uint32_t CAN_Type::MCR

Module Configuration Register, offset: 0x0

Definition at line 3313 of file MIMXRT1052.h.

MCR [2/4]

__IO uint32_t LPI2C_Type::MCR

Master Control Register, offset: 0x10

Definition at line 25098 of file MIMXRT1052.h.

MCR [3/4]

__IO uint32_t PIT_Type::MCR

PIT Module Control Register, offset: 0x0

Definition at line 28510 of file MIMXRT1052.h.

MCR [4/4]

__IO uint32_t SEMC_Type::MCR

Module Control Register, offset: 0x0

Definition at line 34130 of file MIMXRT1052.h.

MCR0

__IO uint32_t FLEXSPI_Type::MCR0

Module Control Register 0, offset: 0x0

Definition at line 18090 of file MIMXRT1052.h.

MCR1

__IO uint32_t FLEXSPI_Type::MCR1

Module Control Register 1, offset: 0x4

Definition at line 18091 of file MIMXRT1052.h.

MCR2

__IO uint32_t FLEXSPI_Type::MCR2

Module Control Register 2, offset: 0x8

Definition at line 18092 of file MIMXRT1052.h.

MCTL

__IO uint32_t TRNG_Type::MCTL

Miscellaneous Control Register, offset: 0x0

Definition at line 37875 of file MIMXRT1052.h.

MCTRL

__IO uint16_t PWM_Type::MCTRL

Master Control Register, offset: 0x188

Definition at line 30894 of file MIMXRT1052.h.

MCTRL2

__IO uint16_t PWM_Type::MCTRL2

Master Control 2 Register, offset: 0x18A

Definition at line 30895 of file MIMXRT1052.h.

MDER

__IO uint32_t LPI2C_Type::MDER

Master DMA Enable Register, offset: 0x1C

Definition at line 25101 of file MIMXRT1052.h.

MDMR

__IO uint32_t LPI2C_Type::MDMR

Master Data Match Register, offset: 0x40

Definition at line 25107 of file MIMXRT1052.h.

MEASEURE_VALUE

__I uint32_t TSC_Type::MEASEURE_VALUE

Measure Value, offset: 0x30

Definition at line 38553 of file MIMXRT1052.h.

MEGA_CTRL

__IO uint32_t PGC_Type::MEGA_CTRL

PGC Mega Control Register, offset: 0x220

Definition at line 28374 of file MIMXRT1052.h.

MEGA_PDNSCR

__IO uint32_t PGC_Type::MEGA_PDNSCR

PGC Mega Pull Down Sequence Control Register, offset: 0x228

Definition at line 28376 of file MIMXRT1052.h.

MEGA_PUPSCR

__IO uint32_t PGC_Type::MEGA_PUPSCR

PGC Mega Power Up Sequence Control Register, offset: 0x224

Definition at line 28375 of file MIMXRT1052.h.

MEGA_SR

__IO uint32_t PGC_Type::MEGA_SR

PGC Mega Power Gating Controller Status Register, offset: 0x22C

Definition at line 28377 of file MIMXRT1052.h.

MEM0

__IO uint32_t OCOTP_Type::MEM0

Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480

Definition at line 27738 of file MIMXRT1052.h.

MEM1

__IO uint32_t OCOTP_Type::MEM1

Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490

Definition at line 27740 of file MIMXRT1052.h.

MEM2

__IO uint32_t OCOTP_Type::MEM2

Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0

Definition at line 27742 of file MIMXRT1052.h.

MEM3

__IO uint32_t OCOTP_Type::MEM3

Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0

Definition at line 27744 of file MIMXRT1052.h.

MEM4

__IO uint32_t OCOTP_Type::MEM4

Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0

Definition at line 27746 of file MIMXRT1052.h.

MFCR

__IO uint32_t LPI2C_Type::MFCR

Master FIFO Control Register, offset: 0x58

Definition at line 25113 of file MIMXRT1052.h.

MFSR

__I uint32_t LPI2C_Type::MFSR

Master FIFO Status Register, offset: 0x5C

Definition at line 25114 of file MIMXRT1052.h.

MIBC

__IO uint32_t ENET_Type::MIBC

MIB Control Register, offset: 0x64

Definition at line 15617 of file MIMXRT1052.h.

MIER

__IO uint32_t LPI2C_Type::MIER

Master Interrupt Enable Register, offset: 0x18

Definition at line 25100 of file MIMXRT1052.h.

MISC [1/2]

__IO { ... } ::MISC

USB Misc Register, array offset: 0x1F0, array step: 0x60

Definition at line 41817 of file MIMXRT1052.h.

MISC [2/2]

__IO uint32_t USB_ANALOG_Type::MISC

USB Misc Register, array offset: 0x1F0, array step: 0x60

Definition at line 41817 of file MIMXRT1052.h.

MISC0 [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0

Miscellaneous Register 0, offset: 0x150

Definition at line 6124 of file MIMXRT1052.h.

MISC0 [2/3]

__IO uint32_t PMU_Type::MISC0

Miscellaneous Register 0, offset: 0x150

Definition at line 28685 of file MIMXRT1052.h.

MISC0 [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0

Miscellaneous Register 0, offset: 0x150

Definition at line 45170 of file MIMXRT1052.h.

MISC0_CLR [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0_CLR

Miscellaneous Register 0, offset: 0x158

Definition at line 6126 of file MIMXRT1052.h.

MISC0_CLR [2/3]

__IO uint32_t PMU_Type::MISC0_CLR

Miscellaneous Register 0, offset: 0x158

Definition at line 28687 of file MIMXRT1052.h.

MISC0_CLR [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0_CLR

Miscellaneous Register 0, offset: 0x158

Definition at line 45172 of file MIMXRT1052.h.

MISC0_SET [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0_SET

Miscellaneous Register 0, offset: 0x154

Definition at line 6125 of file MIMXRT1052.h.

MISC0_SET [2/3]

__IO uint32_t PMU_Type::MISC0_SET

Miscellaneous Register 0, offset: 0x154

Definition at line 28686 of file MIMXRT1052.h.

MISC0_SET [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0_SET

Miscellaneous Register 0, offset: 0x154

Definition at line 45171 of file MIMXRT1052.h.

MISC0_TOG [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0_TOG

Miscellaneous Register 0, offset: 0x15C

Definition at line 6127 of file MIMXRT1052.h.

MISC0_TOG [2/3]

__IO uint32_t PMU_Type::MISC0_TOG

Miscellaneous Register 0, offset: 0x15C

Definition at line 28688 of file MIMXRT1052.h.

MISC0_TOG [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0_TOG

Miscellaneous Register 0, offset: 0x15C

Definition at line 45173 of file MIMXRT1052.h.

MISC1 [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1

Miscellaneous Register 1, offset: 0x160

Definition at line 6128 of file MIMXRT1052.h.

MISC1 [2/2]

__IO uint32_t PMU_Type::MISC1

Miscellaneous Register 1, offset: 0x160

Definition at line 28689 of file MIMXRT1052.h.

MISC1_CLR [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1_CLR

Miscellaneous Register 1, offset: 0x168

Definition at line 6130 of file MIMXRT1052.h.

MISC1_CLR [2/2]

__IO uint32_t PMU_Type::MISC1_CLR

Miscellaneous Register 1, offset: 0x168

Definition at line 28691 of file MIMXRT1052.h.

MISC1_SET [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1_SET

Miscellaneous Register 1, offset: 0x164

Definition at line 6129 of file MIMXRT1052.h.

MISC1_SET [2/2]

__IO uint32_t PMU_Type::MISC1_SET

Miscellaneous Register 1, offset: 0x164

Definition at line 28690 of file MIMXRT1052.h.

MISC1_TOG [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1_TOG

Miscellaneous Register 1, offset: 0x16C

Definition at line 6131 of file MIMXRT1052.h.

MISC1_TOG [2/2]

__IO uint32_t PMU_Type::MISC1_TOG

Miscellaneous Register 1, offset: 0x16C

Definition at line 28692 of file MIMXRT1052.h.

MISC2 [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2

Miscellaneous Register 2, offset: 0x170

Definition at line 6132 of file MIMXRT1052.h.

MISC2 [2/2]

__IO uint32_t PMU_Type::MISC2

Miscellaneous Control Register, offset: 0x170

Definition at line 28693 of file MIMXRT1052.h.

MISC2_CLR [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2_CLR

Miscellaneous Register 2, offset: 0x178

Definition at line 6134 of file MIMXRT1052.h.

MISC2_CLR [2/2]

__IO uint32_t PMU_Type::MISC2_CLR

Miscellaneous Control Register, offset: 0x178

Definition at line 28695 of file MIMXRT1052.h.

MISC2_SET [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2_SET

Miscellaneous Register 2, offset: 0x174

Definition at line 6133 of file MIMXRT1052.h.

MISC2_SET [2/2]

__IO uint32_t PMU_Type::MISC2_SET

Miscellaneous Control Register, offset: 0x174

Definition at line 28694 of file MIMXRT1052.h.

MISC2_TOG [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2_TOG

Miscellaneous Register 2, offset: 0x17C

Definition at line 6135 of file MIMXRT1052.h.

MISC2_TOG [2/2]

__IO uint32_t PMU_Type::MISC2_TOG

Miscellaneous Control Register, offset: 0x17C

Definition at line 28696 of file MIMXRT1052.h.

MISC_CLR [1/2]

__IO { ... } ::MISC_CLR

USB Misc Register, array offset: 0x1F8, array step: 0x60

Definition at line 41819 of file MIMXRT1052.h.

MISC_CLR [2/2]

__IO uint32_t USB_ANALOG_Type::MISC_CLR

USB Misc Register, array offset: 0x1F8, array step: 0x60

Definition at line 41819 of file MIMXRT1052.h.

MISC_CONF0

__IO uint32_t OCOTP_Type::MISC_CONF0

Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0

Definition at line 27794 of file MIMXRT1052.h.

MISC_CONF1

__IO uint32_t OCOTP_Type::MISC_CONF1

Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0

Definition at line 27796 of file MIMXRT1052.h.

MISC_SET [1/2]

__IO { ... } ::MISC_SET

USB Misc Register, array offset: 0x1F4, array step: 0x60

Definition at line 41818 of file MIMXRT1052.h.

MISC_SET [2/2]

__IO uint32_t USB_ANALOG_Type::MISC_SET

USB Misc Register, array offset: 0x1F4, array step: 0x60

Definition at line 41818 of file MIMXRT1052.h.

MISC_TOG [1/2]

__IO { ... } ::MISC_TOG

USB Misc Register, array offset: 0x1FC, array step: 0x60

Definition at line 41820 of file MIMXRT1052.h.

MISC_TOG [2/2]

__IO uint32_t USB_ANALOG_Type::MISC_TOG

USB Misc Register, array offset: 0x1FC, array step: 0x60

Definition at line 41820 of file MIMXRT1052.h.

MIX_CTRL

__IO uint32_t USDHC_Type::MIX_CTRL

Mixer Control, offset: 0x48

Definition at line 42272 of file MIMXRT1052.h.

MMC_BOOT

__IO uint32_t USDHC_Type::MMC_BOOT

MMC Boot Register, offset: 0xC4

Definition at line 42283 of file MIMXRT1052.h.

MMFR

__IO uint32_t ENET_Type::MMFR

MII Management Frame Register, offset: 0x40

Definition at line 15614 of file MIMXRT1052.h.

MODIR

__IO uint32_t LPUART_Type::MODIR

LPUART Modem IrDA Register, offset: 0x24

Definition at line 26781 of file MIMXRT1052.h.

MPR

__IO uint32_t AIPSTZ_Type::MPR

Master Priviledge Registers, offset: 0x0

Definition at line 2078 of file MIMXRT1052.h.

MRBR

__IO uint32_t ENET_Type::MRBR

Maximum Receive Buffer Size Register, offset: 0x188

Definition at line 15639 of file MIMXRT1052.h.

MRDR

__I uint32_t LPI2C_Type::MRDR

Master Receive Data Register, offset: 0x70

Definition at line 25117 of file MIMXRT1052.h.

MSCR

__IO uint32_t ENET_Type::MSCR

MII Speed Control Register, offset: 0x44

Definition at line 15615 of file MIMXRT1052.h.

MSR

__IO uint32_t LPI2C_Type::MSR

Master Status Register, offset: 0x14

Definition at line 25099 of file MIMXRT1052.h.

MTDR

__O uint32_t LPI2C_Type::MTDR

Master Transmit Data Register, offset: 0x60

Definition at line 25115 of file MIMXRT1052.h.

MUXCR

__IO uint8_t CMP_Type::MUXCR

MUX Control Register, offset: 0x5

Definition at line 8547 of file MIMXRT1052.h.

NANDCR0

__IO uint32_t SEMC_Type::NANDCR0

NAND control register 0, offset: 0x50

Definition at line 34142 of file MIMXRT1052.h.

NANDCR1

__IO uint32_t SEMC_Type::NANDCR1

NAND control register 1, offset: 0x54

Definition at line 34143 of file MIMXRT1052.h.

NANDCR2

__IO uint32_t SEMC_Type::NANDCR2

NAND control register 2, offset: 0x58

Definition at line 34144 of file MIMXRT1052.h.

NANDCR3

__IO uint32_t SEMC_Type::NANDCR3

NAND control register 3, offset: 0x5C

Definition at line 34145 of file MIMXRT1052.h.

NBYTES_MLNO [1/2]

__IO uint32_t DMA_Type::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20

Definition at line 12009 of file MIMXRT1052.h.

NBYTES_MLNO [2/2]

__IO { ... } ::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20

Definition at line 12009 of file MIMXRT1052.h.

NBYTES_MLOFFNO [1/2]

__IO uint32_t DMA_Type::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

Definition at line 12010 of file MIMXRT1052.h.

NBYTES_MLOFFNO [2/2]

__IO { ... } ::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

Definition at line 12010 of file MIMXRT1052.h.

NBYTES_MLOFFYES [1/2]

__IO uint32_t DMA_Type::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20

Definition at line 12011 of file MIMXRT1052.h.

NBYTES_MLOFFYES [2/2]

__IO { ... } ::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20

Definition at line 12011 of file MIMXRT1052.h.

NEXT

__IO uint32_t PXP_Type::NEXT

Next Frame Pointer, offset: 0x400

Definition at line 32578 of file MIMXRT1052.h.

NEXT_BUF

__IO uint32_t LCDIF_Type::NEXT_BUF

LCD Interface Next Buffer Address Register, offset: 0x50

Definition at line 23535 of file MIMXRT1052.h.

NORCR0

__IO uint32_t SEMC_Type::NORCR0

NOR control register 0, offset: 0x60

Definition at line 34146 of file MIMXRT1052.h.

NORCR1

__IO uint32_t SEMC_Type::NORCR1

NOR control register 1, offset: 0x64

Definition at line 34147 of file MIMXRT1052.h.

NORCR2

__IO uint32_t SEMC_Type::NORCR2

NOR control register 2, offset: 0x68

Definition at line 34148 of file MIMXRT1052.h.

NORCR3

uint32_t SEMC_Type::NORCR3

NOR control register 3, offset: 0x6C

Definition at line 34149 of file MIMXRT1052.h.

OCR

__IO uint32_t GPT_Type::OCR[3]

GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4

Definition at line 19582 of file MIMXRT1052.h.

OCTRL [1/2]

__IO uint16_t PWM_Type::OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

Definition at line 30862 of file MIMXRT1052.h.

OCTRL [2/2]

__IO { ... } ::OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

Definition at line 30862 of file MIMXRT1052.h.

OFS

__IO uint32_t ADC_Type::OFS

Offset correction value register, offset: 0x54

Definition at line 1304 of file MIMXRT1052.h.

OPACR

__IO uint32_t AIPSTZ_Type::OPACR

Off-Platform Peripheral Access Control Registers, offset: 0x40

Definition at line 2080 of file MIMXRT1052.h.

OPACR1

__IO uint32_t AIPSTZ_Type::OPACR1

Off-Platform Peripheral Access Control Registers, offset: 0x44

Definition at line 2081 of file MIMXRT1052.h.

OPACR2

__IO uint32_t AIPSTZ_Type::OPACR2

Off-Platform Peripheral Access Control Registers, offset: 0x48

Definition at line 2082 of file MIMXRT1052.h.

OPACR3

__IO uint32_t AIPSTZ_Type::OPACR3

Off-Platform Peripheral Access Control Registers, offset: 0x4C

Definition at line 2083 of file MIMXRT1052.h.

OPACR4

__IO uint32_t AIPSTZ_Type::OPACR4

Off-Platform Peripheral Access Control Registers, offset: 0x50

Definition at line 2084 of file MIMXRT1052.h.

OPD

__IO uint32_t ENET_Type::OPD

Opcode/Pause Duration Register, offset: 0xEC

Definition at line 15625 of file MIMXRT1052.h.

OSC_CONFIG0

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0

XTAL OSC Configuration 0 Register, offset: 0x2A0

Definition at line 45180 of file MIMXRT1052.h.

OSC_CONFIG0_CLR

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_CLR

XTAL OSC Configuration 0 Register, offset: 0x2A8

Definition at line 45182 of file MIMXRT1052.h.

OSC_CONFIG0_SET

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_SET

XTAL OSC Configuration 0 Register, offset: 0x2A4

Definition at line 45181 of file MIMXRT1052.h.

OSC_CONFIG0_TOG

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_TOG

XTAL OSC Configuration 0 Register, offset: 0x2AC

Definition at line 45183 of file MIMXRT1052.h.

OSC_CONFIG1

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1

XTAL OSC Configuration 1 Register, offset: 0x2B0

Definition at line 45184 of file MIMXRT1052.h.

OSC_CONFIG1_CLR

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_CLR

XTAL OSC Configuration 1 Register, offset: 0x2B8

Definition at line 45186 of file MIMXRT1052.h.

OSC_CONFIG1_SET

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_SET

XTAL OSC Configuration 1 Register, offset: 0x2B4

Definition at line 45185 of file MIMXRT1052.h.

OSC_CONFIG1_TOG

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_TOG

XTAL OSC Configuration 1 Register, offset: 0x2BC

Definition at line 45187 of file MIMXRT1052.h.

OSC_CONFIG2

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2

XTAL OSC Configuration 2 Register, offset: 0x2C0

Definition at line 45188 of file MIMXRT1052.h.

OSC_CONFIG2_CLR

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_CLR

XTAL OSC Configuration 2 Register, offset: 0x2C8

Definition at line 45190 of file MIMXRT1052.h.

OSC_CONFIG2_SET

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_SET

XTAL OSC Configuration 2 Register, offset: 0x2C4

Definition at line 45189 of file MIMXRT1052.h.

OSC_CONFIG2_TOG

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_TOG

XTAL OSC Configuration 2 Register, offset: 0x2CC

Definition at line 45191 of file MIMXRT1052.h.

OTGSC

__IO uint32_t USB_Type::OTGSC

On-The-Go Status & control, offset: 0x1A4

Definition at line 39039 of file MIMXRT1052.h.

OUT_AS_LRC

__IO uint32_t PXP_Type::OUT_AS_LRC

Alpha Surface Lower Right Coordinate, offset: 0xA0

Definition at line 32536 of file MIMXRT1052.h.

OUT_AS_ULC

__IO uint32_t PXP_Type::OUT_AS_ULC

Alpha Surface Upper Left Coordinate, offset: 0x90

Definition at line 32534 of file MIMXRT1052.h.

OUT_BUF

__IO uint32_t PXP_Type::OUT_BUF

Output Frame Buffer Pointer, offset: 0x30

Definition at line 32522 of file MIMXRT1052.h.

OUT_BUF2

__IO uint32_t PXP_Type::OUT_BUF2

Output Frame Buffer Pointer #2, offset: 0x40

Definition at line 32524 of file MIMXRT1052.h.

OUT_CTRL

__IO uint32_t PXP_Type::OUT_CTRL

Output Buffer Control Register, offset: 0x20

Definition at line 32518 of file MIMXRT1052.h.

OUT_CTRL_CLR

__IO uint32_t PXP_Type::OUT_CTRL_CLR

Output Buffer Control Register, offset: 0x28

Definition at line 32520 of file MIMXRT1052.h.

OUT_CTRL_SET

__IO uint32_t PXP_Type::OUT_CTRL_SET

Output Buffer Control Register, offset: 0x24

Definition at line 32519 of file MIMXRT1052.h.

OUT_CTRL_TOG

__IO uint32_t PXP_Type::OUT_CTRL_TOG

Output Buffer Control Register, offset: 0x2C

Definition at line 32521 of file MIMXRT1052.h.

OUT_LRC

__IO uint32_t PXP_Type::OUT_LRC

Output Surface Lower Right Coordinate, offset: 0x60

Definition at line 32528 of file MIMXRT1052.h.

OUT_PITCH

__IO uint32_t PXP_Type::OUT_PITCH

Output Buffer Pitch, offset: 0x50

Definition at line 32526 of file MIMXRT1052.h.

OUT_PS_LRC

__IO uint32_t PXP_Type::OUT_PS_LRC

Processed Surface Lower Right Coordinate, offset: 0x80

Definition at line 32532 of file MIMXRT1052.h.

OUT_PS_ULC

__IO uint32_t PXP_Type::OUT_PS_ULC

Processed Surface Upper Left Coordinate, offset: 0x70

Definition at line 32530 of file MIMXRT1052.h.

OUTEN

__IO uint16_t PWM_Type::OUTEN

Output Enable Register, offset: 0x180

Definition at line 30890 of file MIMXRT1052.h.

PACKET0

__I uint32_t DCP_Type::PACKET0

DCP work packet 0 status register, offset: 0x80

Definition at line 10292 of file MIMXRT1052.h.

PACKET1

__I uint32_t DCP_Type::PACKET1

DCP work packet 1 status register, offset: 0x90

Definition at line 10294 of file MIMXRT1052.h.

PACKET2

__I uint32_t DCP_Type::PACKET2

DCP work packet 2 status register, offset: 0xA0

Definition at line 10296 of file MIMXRT1052.h.

PACKET3

__I uint32_t DCP_Type::PACKET3

DCP work packet 3 status register, offset: 0xB0

Definition at line 10298 of file MIMXRT1052.h.

PACKET4

__I uint32_t DCP_Type::PACKET4

DCP work packet 4 status register, offset: 0xC0

Definition at line 10300 of file MIMXRT1052.h.

PACKET5

__I uint32_t DCP_Type::PACKET5

DCP work packet 5 status register, offset: 0xD0

Definition at line 10302 of file MIMXRT1052.h.

PACKET6

__I uint32_t DCP_Type::PACKET6

DCP work packet 6 status register, offset: 0xE0

Definition at line 10304 of file MIMXRT1052.h.

PAGETABLE

__IO uint32_t DCP_Type::PAGETABLE

DCP page table register, offset: 0x420

Definition at line 10359 of file MIMXRT1052.h.

PALR

__IO uint32_t ENET_Type::PALR

Physical Address Lower Register, offset: 0xE4

Definition at line 15623 of file MIMXRT1052.h.

PARAM [1/5]

__I uint32_t FLEXIO_Type::PARAM

Parameter Register, offset: 0x4

Definition at line 17368 of file MIMXRT1052.h.

PARAM [2/5]

__I uint32_t I2S_Type::PARAM

Parameter Register, offset: 0x4

Definition at line 19869 of file MIMXRT1052.h.

PARAM [3/5]

__I uint32_t LPI2C_Type::PARAM

Parameter Register, offset: 0x4

Definition at line 25096 of file MIMXRT1052.h.

PARAM [4/5]

__I uint32_t LPSPI_Type::PARAM

Parameter Register, offset: 0x4

Definition at line 26146 of file MIMXRT1052.h.

PARAM [5/5]

__I uint32_t LPUART_Type::PARAM

Parameter Register, offset: 0x4

Definition at line 26773 of file MIMXRT1052.h.

PAUR

__IO uint32_t ENET_Type::PAUR

Physical Address Upper Register, offset: 0xE8

Definition at line 15624 of file MIMXRT1052.h.

PERIODICLISTBASE [1/2]

__IO { ... } ::PERIODICLISTBASE

Frame List Base Address, offset: 0x154

Definition at line 39024 of file MIMXRT1052.h.

PERIODICLISTBASE [2/2]

__IO uint32_t USB_Type::PERIODICLISTBASE

Frame List Base Address, offset: 0x154

Definition at line 39024 of file MIMXRT1052.h.

PFD_480

__IO uint32_t CCM_ANALOG_Type::PFD_480

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0

Definition at line 6115 of file MIMXRT1052.h.

PFD_480_CLR

__IO uint32_t CCM_ANALOG_Type::PFD_480_CLR

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8

Definition at line 6117 of file MIMXRT1052.h.

PFD_480_SET

__IO uint32_t CCM_ANALOG_Type::PFD_480_SET

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4

Definition at line 6116 of file MIMXRT1052.h.

PFD_480_TOG

__IO uint32_t CCM_ANALOG_Type::PFD_480_TOG

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC

Definition at line 6118 of file MIMXRT1052.h.

PFD_528

__IO uint32_t CCM_ANALOG_Type::PFD_528

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100

Definition at line 6119 of file MIMXRT1052.h.

PFD_528_CLR

__IO uint32_t CCM_ANALOG_Type::PFD_528_CLR

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108

Definition at line 6121 of file MIMXRT1052.h.

PFD_528_SET

__IO uint32_t CCM_ANALOG_Type::PFD_528_SET

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104

Definition at line 6120 of file MIMXRT1052.h.

PFD_528_TOG

__IO uint32_t CCM_ANALOG_Type::PFD_528_TOG

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C

Definition at line 6122 of file MIMXRT1052.h.

PIGEON

struct { ... } LCDIF_Type::PIGEON[12]

PIGEON_0 [1/2]

__IO { ... } ::PIGEON_0

Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40

Definition at line 23571 of file MIMXRT1052.h.

PIGEON_0 [2/2]

__IO uint32_t LCDIF_Type::PIGEON_0

Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40

Definition at line 23571 of file MIMXRT1052.h.

PIGEON_1 [1/2]

__IO uint32_t LCDIF_Type::PIGEON_1

Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40

Definition at line 23573 of file MIMXRT1052.h.

PIGEON_1 [2/2]

__IO { ... } ::PIGEON_1

Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40

Definition at line 23573 of file MIMXRT1052.h.

PIGEON_2 [1/2]

__IO uint32_t LCDIF_Type::PIGEON_2

Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40

Definition at line 23575 of file MIMXRT1052.h.

PIGEON_2 [2/2]

__IO { ... } ::PIGEON_2

Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40

Definition at line 23575 of file MIMXRT1052.h.

PIGEONCTRL0

__IO uint32_t LCDIF_Type::PIGEONCTRL0

LCDIF Pigeon Mode Control0 Register, offset: 0x380

Definition at line 23557 of file MIMXRT1052.h.

PIGEONCTRL0_CLR

__IO uint32_t LCDIF_Type::PIGEONCTRL0_CLR

LCDIF Pigeon Mode Control0 Register, offset: 0x388

Definition at line 23559 of file MIMXRT1052.h.

PIGEONCTRL0_SET

__IO uint32_t LCDIF_Type::PIGEONCTRL0_SET

LCDIF Pigeon Mode Control0 Register, offset: 0x384

Definition at line 23558 of file MIMXRT1052.h.

PIGEONCTRL0_TOG

__IO uint32_t LCDIF_Type::PIGEONCTRL0_TOG

LCDIF Pigeon Mode Control0 Register, offset: 0x38C

Definition at line 23560 of file MIMXRT1052.h.

PIGEONCTRL1

__IO uint32_t LCDIF_Type::PIGEONCTRL1

LCDIF Pigeon Mode Control1 Register, offset: 0x390

Definition at line 23561 of file MIMXRT1052.h.

PIGEONCTRL1_CLR

__IO uint32_t LCDIF_Type::PIGEONCTRL1_CLR

LCDIF Pigeon Mode Control1 Register, offset: 0x398

Definition at line 23563 of file MIMXRT1052.h.

PIGEONCTRL1_SET

__IO uint32_t LCDIF_Type::PIGEONCTRL1_SET

LCDIF Pigeon Mode Control1 Register, offset: 0x394

Definition at line 23562 of file MIMXRT1052.h.

PIGEONCTRL1_TOG

__IO uint32_t LCDIF_Type::PIGEONCTRL1_TOG

LCDIF Pigeon Mode Control1 Register, offset: 0x39C

Definition at line 23564 of file MIMXRT1052.h.

PIGEONCTRL2

__IO uint32_t LCDIF_Type::PIGEONCTRL2

LCDIF Pigeon Mode Control2 Register, offset: 0x3A0

Definition at line 23565 of file MIMXRT1052.h.

PIGEONCTRL2_CLR

__IO uint32_t LCDIF_Type::PIGEONCTRL2_CLR

LCDIF Pigeon Mode Control2 Register, offset: 0x3A8

Definition at line 23567 of file MIMXRT1052.h.

PIGEONCTRL2_SET

__IO uint32_t LCDIF_Type::PIGEONCTRL2_SET

LCDIF Pigeon Mode Control2 Register, offset: 0x3A4

Definition at line 23566 of file MIMXRT1052.h.

PIGEONCTRL2_TOG

__IO uint32_t LCDIF_Type::PIGEONCTRL2_TOG

LCDIF Pigeon Mode Control2 Register, offset: 0x3AC

Definition at line 23568 of file MIMXRT1052.h.

PIN

__I uint32_t FLEXIO_Type::PIN

Pin State Register, offset: 0xC

Definition at line 17370 of file MIMXRT1052.h.

PINCFG

__IO uint32_t LPUART_Type::PINCFG

LPUART Pin Configuration Register, offset: 0xC

Definition at line 26775 of file MIMXRT1052.h.

PKRCNT10

__I uint32_t TRNG_Type::PKRCNT10

Statistical Check Poker Count 1 and 0 Register, offset: 0x80

Definition at line 37922 of file MIMXRT1052.h.

PKRCNT32

__I uint32_t TRNG_Type::PKRCNT32

Statistical Check Poker Count 3 and 2 Register, offset: 0x84

Definition at line 37923 of file MIMXRT1052.h.

PKRCNT54

__I uint32_t TRNG_Type::PKRCNT54

Statistical Check Poker Count 5 and 4 Register, offset: 0x88

Definition at line 37924 of file MIMXRT1052.h.

PKRCNT76

__I uint32_t TRNG_Type::PKRCNT76

Statistical Check Poker Count 7 and 6 Register, offset: 0x8C

Definition at line 37925 of file MIMXRT1052.h.

PKRCNT98

__I uint32_t TRNG_Type::PKRCNT98

Statistical Check Poker Count 9 and 8 Register, offset: 0x90

Definition at line 37926 of file MIMXRT1052.h.

PKRCNTBA

__I uint32_t TRNG_Type::PKRCNTBA

Statistical Check Poker Count B and A Register, offset: 0x94

Definition at line 37927 of file MIMXRT1052.h.

PKRCNTDC

__I uint32_t TRNG_Type::PKRCNTDC

Statistical Check Poker Count D and C Register, offset: 0x98

Definition at line 37928 of file MIMXRT1052.h.

PKRCNTFE

__I uint32_t TRNG_Type::PKRCNTFE

Statistical Check Poker Count F and E Register, offset: 0x9C

Definition at line 37929 of file MIMXRT1052.h.

PKRMAX [1/2]

__IO uint32_t TRNG_Type::PKRMAX

Poker Maximum Limit Register, offset: 0xC

Definition at line 37879 of file MIMXRT1052.h.

PKRMAX [2/2]

__IO { ... } ::PKRMAX

Poker Maximum Limit Register, offset: 0xC

Definition at line 37879 of file MIMXRT1052.h.

PKRRNG

__IO uint32_t TRNG_Type::PKRRNG

Poker Range Register, offset: 0x8

Definition at line 37877 of file MIMXRT1052.h.

PKRSQ [1/2]

__I uint32_t TRNG_Type::PKRSQ

Poker Square Calculation Result Register, offset: 0xC

Definition at line 37880 of file MIMXRT1052.h.

PKRSQ [2/2]

__I { ... } ::PKRSQ

Poker Square Calculation Result Register, offset: 0xC

Definition at line 37880 of file MIMXRT1052.h.

PLL_ARM

__IO uint32_t CCM_ANALOG_Type::PLL_ARM

Analog ARM PLL control Register, offset: 0x0

Definition at line 6073 of file MIMXRT1052.h.

PLL_ARM_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_ARM_CLR

Analog ARM PLL control Register, offset: 0x8

Definition at line 6075 of file MIMXRT1052.h.

PLL_ARM_SET

__IO uint32_t CCM_ANALOG_Type::PLL_ARM_SET

Analog ARM PLL control Register, offset: 0x4

Definition at line 6074 of file MIMXRT1052.h.

PLL_ARM_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_ARM_TOG

Analog ARM PLL control Register, offset: 0xC

Definition at line 6076 of file MIMXRT1052.h.

PLL_AUDIO

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO

Analog Audio PLL control Register, offset: 0x70

Definition at line 6095 of file MIMXRT1052.h.

PLL_AUDIO_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_CLR

Analog Audio PLL control Register, offset: 0x78

Definition at line 6097 of file MIMXRT1052.h.

PLL_AUDIO_DENOM

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_DENOM

Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90

Definition at line 6101 of file MIMXRT1052.h.

PLL_AUDIO_NUM

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_NUM

Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80

Definition at line 6099 of file MIMXRT1052.h.

PLL_AUDIO_SET

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_SET

Analog Audio PLL control Register, offset: 0x74

Definition at line 6096 of file MIMXRT1052.h.

PLL_AUDIO_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_TOG

Analog Audio PLL control Register, offset: 0x7C

Definition at line 6098 of file MIMXRT1052.h.

PLL_ENET

__IO uint32_t CCM_ANALOG_Type::PLL_ENET

Analog ENET PLL Control Register, offset: 0xE0

Definition at line 6111 of file MIMXRT1052.h.

PLL_ENET_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_ENET_CLR

Analog ENET PLL Control Register, offset: 0xE8

Definition at line 6113 of file MIMXRT1052.h.

PLL_ENET_SET

__IO uint32_t CCM_ANALOG_Type::PLL_ENET_SET

Analog ENET PLL Control Register, offset: 0xE4

Definition at line 6112 of file MIMXRT1052.h.

PLL_ENET_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_ENET_TOG

Analog ENET PLL Control Register, offset: 0xEC

Definition at line 6114 of file MIMXRT1052.h.

PLL_SYS

__IO uint32_t CCM_ANALOG_Type::PLL_SYS

Analog System PLL Control Register, offset: 0x30

Definition at line 6085 of file MIMXRT1052.h.

PLL_SYS_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_CLR

Analog System PLL Control Register, offset: 0x38

Definition at line 6087 of file MIMXRT1052.h.

PLL_SYS_DENOM

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_DENOM

Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60

Definition at line 6093 of file MIMXRT1052.h.

PLL_SYS_NUM

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_NUM

Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50

Definition at line 6091 of file MIMXRT1052.h.

PLL_SYS_SET

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_SET

Analog System PLL Control Register, offset: 0x34

Definition at line 6086 of file MIMXRT1052.h.

PLL_SYS_SS

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_SS

528MHz System PLL Spread Spectrum Register, offset: 0x40

Definition at line 6089 of file MIMXRT1052.h.

PLL_SYS_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_TOG

Analog System PLL Control Register, offset: 0x3C

Definition at line 6088 of file MIMXRT1052.h.

PLL_USB1

__IO uint32_t CCM_ANALOG_Type::PLL_USB1

Analog USB1 480MHz PLL Control Register, offset: 0x10

Definition at line 6077 of file MIMXRT1052.h.

PLL_USB1_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_USB1_CLR

Analog USB1 480MHz PLL Control Register, offset: 0x18

Definition at line 6079 of file MIMXRT1052.h.

PLL_USB1_SET

__IO uint32_t CCM_ANALOG_Type::PLL_USB1_SET

Analog USB1 480MHz PLL Control Register, offset: 0x14

Definition at line 6078 of file MIMXRT1052.h.

PLL_USB1_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_USB1_TOG

Analog USB1 480MHz PLL Control Register, offset: 0x1C

Definition at line 6080 of file MIMXRT1052.h.

PLL_USB2

__IO uint32_t CCM_ANALOG_Type::PLL_USB2

Analog USB2 480MHz PLL Control Register, offset: 0x20

Definition at line 6081 of file MIMXRT1052.h.

PLL_USB2_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_USB2_CLR

Analog USB2 480MHz PLL Control Register, offset: 0x28

Definition at line 6083 of file MIMXRT1052.h.

PLL_USB2_SET

__IO uint32_t CCM_ANALOG_Type::PLL_USB2_SET

Analog USB2 480MHz PLL Control Register, offset: 0x24

Definition at line 6082 of file MIMXRT1052.h.

PLL_USB2_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_USB2_TOG

Analog USB2 480MHz PLL Control Register, offset: 0x2C

Definition at line 6084 of file MIMXRT1052.h.

PLL_VIDEO

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO

Analog Video PLL control Register, offset: 0xA0

Definition at line 6103 of file MIMXRT1052.h.

PLL_VIDEO_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_CLR

Analog Video PLL control Register, offset: 0xA8

Definition at line 6105 of file MIMXRT1052.h.

PLL_VIDEO_DENOM

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_DENOM

Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0

Definition at line 6109 of file MIMXRT1052.h.

PLL_VIDEO_NUM

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_NUM

Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0

Definition at line 6107 of file MIMXRT1052.h.

PLL_VIDEO_SET

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_SET

Analog Video PLL control Register, offset: 0xA4

Definition at line 6104 of file MIMXRT1052.h.

PLL_VIDEO_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_TOG

Analog Video PLL control Register, offset: 0xAC

Definition at line 6106 of file MIMXRT1052.h.

PORTER_DUFF_CTRL

__IO uint32_t PXP_Type::PORTER_DUFF_CTRL

PXP Alpha Engine A Control Register., offset: 0x440

Definition at line 32580 of file MIMXRT1052.h.

PORTSC1

__IO uint32_t USB_Type::PORTSC1

Port Status & Control, offset: 0x184

Definition at line 39037 of file MIMXRT1052.h.

POSD

__IO uint16_t ENC_Type::POSD

Position Difference Counter Register, offset: 0x6

Definition at line 15142 of file MIMXRT1052.h.

POSDH

__I uint16_t ENC_Type::POSDH

Position Difference Hold Register, offset: 0x8

Definition at line 15143 of file MIMXRT1052.h.

POWER

__IO uint32_t PXP_Type::POWER

PXP Power Control Register, offset: 0x320

Definition at line 32576 of file MIMXRT1052.h.

PR

__IO uint32_t GPT_Type::PR

GPT Prescaler Register, offset: 0x4

Definition at line 19579 of file MIMXRT1052.h.

PRE_CHARGE_TIME

__IO uint32_t TSC_Type::PRE_CHARGE_TIME

Pre-charge Time, offset: 0x10

Definition at line 38549 of file MIMXRT1052.h.

PRES_STATE

__I uint32_t USDHC_Type::PRES_STATE

Present State, offset: 0x24

Definition at line 42263 of file MIMXRT1052.h.

PROT_CTRL

__IO uint32_t USDHC_Type::PROT_CTRL

Protocol Control, offset: 0x28

Definition at line 42264 of file MIMXRT1052.h.

PS_BACKGROUND

__IO uint32_t PXP_Type::PS_BACKGROUND

PS Background Color, offset: 0x100

Definition at line 32550 of file MIMXRT1052.h.

PS_BUF

__IO uint32_t PXP_Type::PS_BUF

PS Input Buffer Address, offset: 0xC0

Definition at line 32542 of file MIMXRT1052.h.

PS_CLRKEYHIGH

__IO uint32_t PXP_Type::PS_CLRKEYHIGH

PS Color Key High, offset: 0x140

Definition at line 32558 of file MIMXRT1052.h.

PS_CLRKEYLOW

__IO uint32_t PXP_Type::PS_CLRKEYLOW

PS Color Key Low, offset: 0x130

Definition at line 32556 of file MIMXRT1052.h.

PS_CTRL

__IO uint32_t PXP_Type::PS_CTRL

Processed Surface (PS) Control Register, offset: 0xB0

Definition at line 32538 of file MIMXRT1052.h.

PS_CTRL_CLR

__IO uint32_t PXP_Type::PS_CTRL_CLR

Processed Surface (PS) Control Register, offset: 0xB8

Definition at line 32540 of file MIMXRT1052.h.

PS_CTRL_SET

__IO uint32_t PXP_Type::PS_CTRL_SET

Processed Surface (PS) Control Register, offset: 0xB4

Definition at line 32539 of file MIMXRT1052.h.

PS_CTRL_TOG

__IO uint32_t PXP_Type::PS_CTRL_TOG

Processed Surface (PS) Control Register, offset: 0xBC

Definition at line 32541 of file MIMXRT1052.h.

PS_OFFSET

__IO uint32_t PXP_Type::PS_OFFSET

PS Scale Offset Register, offset: 0x120

Definition at line 32554 of file MIMXRT1052.h.

PS_PITCH

__IO uint32_t PXP_Type::PS_PITCH

Processed Surface Pitch, offset: 0xF0

Definition at line 32548 of file MIMXRT1052.h.

PS_SCALE

__IO uint32_t PXP_Type::PS_SCALE

PS Scale Factor Register, offset: 0x110

Definition at line 32552 of file MIMXRT1052.h.

PS_UBUF

__IO uint32_t PXP_Type::PS_UBUF

PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0

Definition at line 32544 of file MIMXRT1052.h.

PS_VBUF

__IO uint32_t PXP_Type::PS_VBUF

PS V/Cr Input Buffer Address, offset: 0xE0

Definition at line 32546 of file MIMXRT1052.h.

PSR

__I uint32_t GPIO_Type::PSR

GPIO pad status register, offset: 0x8

Definition at line 19128 of file MIMXRT1052.h.

PWD

__IO uint32_t USBPHY_Type::PWD

USB PHY Power-Down Register, offset: 0x0

Definition at line 40684 of file MIMXRT1052.h.

PWD_CLR

__IO uint32_t USBPHY_Type::PWD_CLR

USB PHY Power-Down Register, offset: 0x8

Definition at line 40686 of file MIMXRT1052.h.

PWD_SET

__IO uint32_t USBPHY_Type::PWD_SET

USB PHY Power-Down Register, offset: 0x4

Definition at line 40685 of file MIMXRT1052.h.

PWD_TOG

__IO uint32_t USBPHY_Type::PWD_TOG

USB PHY Power-Down Register, offset: 0xC

Definition at line 40687 of file MIMXRT1052.h.

R

__I uint32_t ADC_Type::R[8]

Data result register for HW triggers, array offset: 0x24, array step: 0x4

Definition at line 1299 of file MIMXRT1052.h.

RACC

__IO uint32_t ENET_Type::RACC

Receive Accelerator Function Configuration, offset: 0x1C4

Definition at line 15652 of file MIMXRT1052.h.

RAEM

__IO uint32_t ENET_Type::RAEM

Receive FIFO Almost Empty Threshold, offset: 0x198

Definition at line 15643 of file MIMXRT1052.h.

RAFL

__IO uint32_t ENET_Type::RAFL

Receive FIFO Almost Full Threshold, offset: 0x19C

Definition at line 15644 of file MIMXRT1052.h.

RCR

__IO uint32_t ENET_Type::RCR

Receive Control Register, offset: 0x84

Definition at line 15619 of file MIMXRT1052.h.

RCR1

__IO uint32_t I2S_Type::RCR1

SAI Receive Configuration 1 Register, offset: 0x8C

Definition at line 19883 of file MIMXRT1052.h.

RCR2

__IO uint32_t I2S_Type::RCR2

SAI Receive Configuration 2 Register, offset: 0x90

Definition at line 19884 of file MIMXRT1052.h.

RCR3

__IO uint32_t I2S_Type::RCR3

SAI Receive Configuration 3 Register, offset: 0x94

Definition at line 19885 of file MIMXRT1052.h.

RCR4

__IO uint32_t I2S_Type::RCR4

SAI Receive Configuration 4 Register, offset: 0x98

Definition at line 19886 of file MIMXRT1052.h.

RCR5

__IO uint32_t I2S_Type::RCR5

SAI Receive Configuration 5 Register, offset: 0x9C

Definition at line 19887 of file MIMXRT1052.h.

RCSR

__IO uint32_t I2S_Type::RCSR

SAI Receive Control Register, offset: 0x88

Definition at line 19882 of file MIMXRT1052.h.

RDAR

__IO uint32_t ENET_Type::RDAR

Receive Descriptor Active Register, offset: 0x10

Definition at line 15609 of file MIMXRT1052.h.

RDR [1/2]

__I uint32_t I2S_Type::RDR[4]

SAI Receive Data Register, array offset: 0xA0, array step: 0x4

Definition at line 19888 of file MIMXRT1052.h.

RDR [2/2]

__I uint32_t LPSPI_Type::RDR

Receive Data Register, offset: 0x74

Definition at line 26166 of file MIMXRT1052.h.

RDSR

__IO uint32_t ENET_Type::RDSR

Receive Descriptor Ring Start Register, offset: 0x180

Definition at line 15637 of file MIMXRT1052.h.

READ_CTRL

__IO uint32_t OCOTP_Type::READ_CTRL

OTP Controller Write Data Register, offset: 0x30

Definition at line 27707 of file MIMXRT1052.h.

READ_FUSE_DATA

__IO uint32_t OCOTP_Type::READ_FUSE_DATA

OTP Controller Read Data Register, offset: 0x40

Definition at line 27709 of file MIMXRT1052.h.

REG0

__IO uint32_t DCDC_Type::REG0

DCDC Register 0, offset: 0x0

Definition at line 10085 of file MIMXRT1052.h.

REG1

__IO uint32_t DCDC_Type::REG1

DCDC Register 1, offset: 0x4

Definition at line 10086 of file MIMXRT1052.h.

REG2

__IO uint32_t DCDC_Type::REG2

DCDC Register 2, offset: 0x8

Definition at line 10087 of file MIMXRT1052.h.

REG3

__IO uint32_t DCDC_Type::REG3

DCDC Register 3, offset: 0xC

Definition at line 10088 of file MIMXRT1052.h.

REG_1P1

__IO uint32_t PMU_Type::REG_1P1

Regulator 1P1 Register, offset: 0x110

Definition at line 28669 of file MIMXRT1052.h.

REG_1P1_CLR

__IO uint32_t PMU_Type::REG_1P1_CLR

Regulator 1P1 Register, offset: 0x118

Definition at line 28671 of file MIMXRT1052.h.

REG_1P1_SET

__IO uint32_t PMU_Type::REG_1P1_SET

Regulator 1P1 Register, offset: 0x114

Definition at line 28670 of file MIMXRT1052.h.

REG_1P1_TOG

__IO uint32_t PMU_Type::REG_1P1_TOG

Regulator 1P1 Register, offset: 0x11C

Definition at line 28672 of file MIMXRT1052.h.

REG_2P5

__IO uint32_t PMU_Type::REG_2P5

Regulator 2P5 Register, offset: 0x130

Definition at line 28677 of file MIMXRT1052.h.

REG_2P5_CLR

__IO uint32_t PMU_Type::REG_2P5_CLR

Regulator 2P5 Register, offset: 0x138

Definition at line 28679 of file MIMXRT1052.h.

REG_2P5_SET

__IO uint32_t PMU_Type::REG_2P5_SET

Regulator 2P5 Register, offset: 0x134

Definition at line 28678 of file MIMXRT1052.h.

REG_2P5_TOG

__IO uint32_t PMU_Type::REG_2P5_TOG

Regulator 2P5 Register, offset: 0x13C

Definition at line 28680 of file MIMXRT1052.h.

REG_3P0

__IO uint32_t PMU_Type::REG_3P0

Regulator 3P0 Register, offset: 0x120

Definition at line 28673 of file MIMXRT1052.h.

REG_3P0_CLR

__IO uint32_t PMU_Type::REG_3P0_CLR

Regulator 3P0 Register, offset: 0x128

Definition at line 28675 of file MIMXRT1052.h.

REG_3P0_SET

__IO uint32_t PMU_Type::REG_3P0_SET

Regulator 3P0 Register, offset: 0x124

Definition at line 28674 of file MIMXRT1052.h.

REG_3P0_TOG

__IO uint32_t PMU_Type::REG_3P0_TOG

Regulator 3P0 Register, offset: 0x12C

Definition at line 28676 of file MIMXRT1052.h.

REG_CORE

__IO uint32_t PMU_Type::REG_CORE

Digital Regulator Core Register, offset: 0x140

Definition at line 28681 of file MIMXRT1052.h.

REG_CORE_CLR

__IO uint32_t PMU_Type::REG_CORE_CLR

Digital Regulator Core Register, offset: 0x148

Definition at line 28683 of file MIMXRT1052.h.

REG_CORE_SET

__IO uint32_t PMU_Type::REG_CORE_SET

Digital Regulator Core Register, offset: 0x144

Definition at line 28682 of file MIMXRT1052.h.

REG_CORE_TOG

__IO uint32_t PMU_Type::REG_CORE_TOG

Digital Regulator Core Register, offset: 0x14C

Definition at line 28684 of file MIMXRT1052.h.

REGION1_BOT

__IO uint32_t BEE_Type::REGION1_BOT

Region1 Bottom Address Register, offset: 0x44

Definition at line 3028 of file MIMXRT1052.h.

REGION1_TOP

__IO uint32_t BEE_Type::REGION1_TOP

Region1 Top Address Register, offset: 0x40

Definition at line 3027 of file MIMXRT1052.h.

RESERVED_0 [1/44]

uint8_t GPIO_Type::RESERVED_0[100]

Definition at line 19134 of file MIMXRT1052.h.

RESERVED_0 [2/44]

uint8_t USB_Type::RESERVED_0[104]

Definition at line 39000 of file MIMXRT1052.h.

RESERVED_0 [3/44]

uint8_t CCM_ANALOG_Type::RESERVED_0[12]

Definition at line 6090 of file MIMXRT1052.h.

RESERVED_0 [4/44]

uint8_t DCP_Type::RESERVED_0[12]

Definition at line 10283 of file MIMXRT1052.h.

RESERVED_0 [5/44]

uint8_t FLEXRAM_Type::RESERVED_0[12]

Definition at line 17943 of file MIMXRT1052.h.

RESERVED_0 [6/44]

uint8_t LCDIF_Type::RESERVED_0[12]

Definition at line 23532 of file MIMXRT1052.h.

RESERVED_0 [7/44]

uint8_t { ... } ::RESERVED_0[12]

Definition at line 23572 of file MIMXRT1052.h.

RESERVED_0 [8/44]

uint8_t OCOTP_Type::RESERVED_0[12]

Definition at line 27704 of file MIMXRT1052.h.

RESERVED_0 [9/44]

uint8_t PXP_Type::RESERVED_0[12]

Definition at line 32523 of file MIMXRT1052.h.

RESERVED_0 [10/44]

uint8_t TSC_Type::RESERVED_0[12]

Definition at line 38548 of file MIMXRT1052.h.

RESERVED_0 [11/44]

uint8_t USBPHY_Type::RESERVED_0[12]

Definition at line 40701 of file MIMXRT1052.h.

RESERVED_0 [12/44]

uint8_t { ... } ::RESERVED_0[12]

Definition at line 41810 of file MIMXRT1052.h.

RESERVED_0 [13/44]

uint8_t I2S_Type::RESERVED_0[16]

Definition at line 19877 of file MIMXRT1052.h.

RESERVED_0 [14/44]

uint8_t SRC_Type::RESERVED_0[16]

Definition at line 36905 of file MIMXRT1052.h.

RESERVED_0 [15/44]

uint8_t USBNC_Type::RESERVED_0[2048]

Definition at line 40548 of file MIMXRT1052.h.

RESERVED_0 [16/44]

uint8_t IOMUXC_Type::RESERVED_0[20]

Definition at line 20699 of file MIMXRT1052.h.

RESERVED_0 [17/44]

uint8_t ROMC_Type::RESERVED_0[212]

Definition at line 33802 of file MIMXRT1052.h.

RESERVED_0 [18/44]

uint8_t PIT_Type::RESERVED_0[220]

Definition at line 28511 of file MIMXRT1052.h.

RESERVED_0 [19/44]

uint8_t PMU_Type::RESERVED_0[272]

Definition at line 28668 of file MIMXRT1052.h.

RESERVED_0 [20/44]

uint8_t PWM_Type::RESERVED_0[2]

Definition at line 30849 of file MIMXRT1052.h.

RESERVED_0 [21/44]

uint8_t { ... } ::RESERVED_0[2]

Definition at line 30849 of file MIMXRT1052.h.

RESERVED_0 [22/44]

uint8_t XTALOSC24M_Type::RESERVED_0[336]

Definition at line 45169 of file MIMXRT1052.h.

RESERVED_0 [23/44]

uint8_t CSU_Type::RESERVED_0[384]

Definition at line 9471 of file MIMXRT1052.h.

RESERVED_0 [24/44]

uint8_t TEMPMON_Type::RESERVED_0[384]

Definition at line 37130 of file MIMXRT1052.h.

RESERVED_0 [25/44]

uint8_t USB_ANALOG_Type::RESERVED_0[12]

Definition at line 41799 of file MIMXRT1052.h.

RESERVED_0 [26/44]

uint8_t FLEXSPI_Type::RESERVED_0[48]

Definition at line 18099 of file MIMXRT1052.h.

RESERVED_0 [27/44]

uint8_t CAN_Type::RESERVED_0[4]

Definition at line 3316 of file MIMXRT1052.h.

RESERVED_0 [28/44]

uint8_t CCM_Type::RESERVED_0[4]

Definition at line 4156 of file MIMXRT1052.h.

RESERVED_0 [29/44]

uint8_t CSI_Type::RESERVED_0[4]

Definition at line 8799 of file MIMXRT1052.h.

RESERVED_0 [30/44]

uint8_t DMA_Type::RESERVED_0[4]

Definition at line 11950 of file MIMXRT1052.h.

RESERVED_0 [31/44]

uint8_t ENET_Type::RESERVED_0[4]

Definition at line 15605 of file MIMXRT1052.h.

RESERVED_0 [32/44]

uint8_t FLEXIO_Type::RESERVED_0[4]

Definition at line 17374 of file MIMXRT1052.h.

RESERVED_0 [33/44]

uint8_t GPC_Type::RESERVED_0[4]

Definition at line 18998 of file MIMXRT1052.h.

RESERVED_0 [34/44]

uint8_t SEMC_Type::RESERVED_0[4]

Definition at line 34135 of file MIMXRT1052.h.

RESERVED_0 [35/44]

uint8_t SNVS_Type::RESERVED_0[4]

Definition at line 35337 of file MIMXRT1052.h.

RESERVED_0 [36/44]

uint8_t TMR_Type::RESERVED_0[4]

Definition at line 37393 of file MIMXRT1052.h.

RESERVED_0 [37/44]

uint8_t { ... } ::RESERVED_0[4]

Definition at line 37393 of file MIMXRT1052.h.

RESERVED_0 [38/44]

uint8_t USDHC_Type::RESERVED_0[4]

Definition at line 42273 of file MIMXRT1052.h.

RESERVED_0 [39/44]

uint8_t PGC_Type::RESERVED_0[544]

Definition at line 28373 of file MIMXRT1052.h.

RESERVED_0 [40/44]

uint8_t AIPSTZ_Type::RESERVED_0[60]

Definition at line 2079 of file MIMXRT1052.h.

RESERVED_0 [41/44]

uint8_t TRNG_Type::RESERVED_0[64]

Definition at line 37934 of file MIMXRT1052.h.

RESERVED_0 [42/44]

uint8_t LPI2C_Type::RESERVED_0[8]

Definition at line 25097 of file MIMXRT1052.h.

RESERVED_0 [43/44]

uint8_t LPSPI_Type::RESERVED_0[8]

Definition at line 26147 of file MIMXRT1052.h.

RESERVED_0 [44/44]

uint8_t SPDIF_Type::RESERVED_0[8]

Definition at line 36435 of file MIMXRT1052.h.

RESERVED_1 [1/35]

uint8_t USB_Type::RESERVED_1[108]

Definition at line 39006 of file MIMXRT1052.h.

RESERVED_1 [2/35]

uint8_t PGC_Type::RESERVED_1[112]

Definition at line 28378 of file MIMXRT1052.h.

RESERVED_1 [3/35]

uint8_t CCM_ANALOG_Type::RESERVED_1[12]

Definition at line 6092 of file MIMXRT1052.h.

RESERVED_1 [4/35]

uint8_t DCP_Type::RESERVED_1[12]

Definition at line 10285 of file MIMXRT1052.h.

RESERVED_1 [5/35]

uint8_t GPC_Type::RESERVED_1[12]

Definition at line 19001 of file MIMXRT1052.h.

RESERVED_1 [6/35]

uint8_t LCDIF_Type::RESERVED_1[12]

Definition at line 23534 of file MIMXRT1052.h.

RESERVED_1 [7/35]

uint8_t { ... } ::RESERVED_1[12]

Definition at line 23574 of file MIMXRT1052.h.

RESERVED_1 [8/35]

uint8_t OCOTP_Type::RESERVED_1[12]

Definition at line 27706 of file MIMXRT1052.h.

RESERVED_1 [9/35]

uint8_t PXP_Type::RESERVED_1[12]

Definition at line 32525 of file MIMXRT1052.h.

RESERVED_1 [10/35]

uint8_t TSC_Type::RESERVED_1[12]

Definition at line 38550 of file MIMXRT1052.h.

RESERVED_1 [11/35]

uint8_t USBPHY_Type::RESERVED_1[12]

Definition at line 40707 of file MIMXRT1052.h.

RESERVED_1 [12/35]

uint8_t { ... } ::RESERVED_1[12]

Definition at line 41812 of file MIMXRT1052.h.

RESERVED_1 [13/35]

uint8_t USB_ANALOG_Type::RESERVED_1[12]

Definition at line 41812 of file MIMXRT1052.h.

RESERVED_1 [14/35]

uint8_t CSI_Type::RESERVED_1[16]

Definition at line 8806 of file MIMXRT1052.h.

RESERVED_1 [15/35]

uint8_t I2S_Type::RESERVED_1[16]

Definition at line 19879 of file MIMXRT1052.h.

RESERVED_1 [16/35]

uint8_t LPI2C_Type::RESERVED_1[16]

Definition at line 25106 of file MIMXRT1052.h.

RESERVED_1 [17/35]

uint8_t ROMC_Type::RESERVED_1[200]

Definition at line 33808 of file MIMXRT1052.h.

RESERVED_1 [18/35]

uint8_t CSU_Type::RESERVED_1[20]

Definition at line 9473 of file MIMXRT1052.h.

RESERVED_1 [19/35]

uint8_t USBNC_Type::RESERVED_1[20]

Definition at line 40550 of file MIMXRT1052.h.

RESERVED_1 [20/35]

uint8_t TEMPMON_Type::RESERVED_1[240]

Definition at line 37139 of file MIMXRT1052.h.

RESERVED_1 [21/35]

uint8_t PIT_Type::RESERVED_1[24]

Definition at line 28514 of file MIMXRT1052.h.

RESERVED_1 [22/35]

uint8_t XTALOSC24M_Type::RESERVED_1[272]

Definition at line 45174 of file MIMXRT1052.h.

RESERVED_1 [23/35]

uint8_t CCM_Type::RESERVED_1[4]

Definition at line 4168 of file MIMXRT1052.h.

RESERVED_1 [24/35]

uint8_t DMA_Type::RESERVED_1[4]

Definition at line 11952 of file MIMXRT1052.h.

RESERVED_1 [25/35]

uint8_t ENET_Type::RESERVED_1[4]

Definition at line 15608 of file MIMXRT1052.h.

RESERVED_1 [26/35]

uint8_t FLEXIO_Type::RESERVED_1[4]

Definition at line 17378 of file MIMXRT1052.h.

RESERVED_1 [27/35]

uint8_t FLEXSPI_Type::RESERVED_1[4]

Definition at line 18103 of file MIMXRT1052.h.

RESERVED_1 [28/35]

uint8_t SNVS_Type::RESERVED_1[4]

Definition at line 35348 of file MIMXRT1052.h.

RESERVED_1 [29/35]

uint8_t USDHC_Type::RESERVED_1[4]

Definition at line 42277 of file MIMXRT1052.h.

RESERVED_1 [30/35]

uint8_t CAN_Type::RESERVED_1[8]

Definition at line 3328 of file MIMXRT1052.h.

RESERVED_1 [31/35]

uint8_t LPSPI_Type::RESERVED_1[8]

Definition at line 26154 of file MIMXRT1052.h.

RESERVED_1 [32/35]

uint8_t PWM_Type::RESERVED_1[8]

Definition at line 30888 of file MIMXRT1052.h.

RESERVED_1 [33/35]

uint8_t { ... } ::RESERVED_1[8]

Definition at line 30888 of file MIMXRT1052.h.

RESERVED_1 [34/35]

uint8_t SEMC_Type::RESERVED_1[8]

Definition at line 34156 of file MIMXRT1052.h.

RESERVED_1 [35/35]

uint8_t SPDIF_Type::RESERVED_1[8]

Definition at line 36437 of file MIMXRT1052.h.

RESERVED_10 [1/7]

uint8_t FLEXIO_Type::RESERVED_10[112]

Definition at line 17396 of file MIMXRT1052.h.

RESERVED_10 [2/7]

uint8_t DCP_Type::RESERVED_10[12]

Definition at line 10303 of file MIMXRT1052.h.

RESERVED_10 [3/7]

uint8_t OCOTP_Type::RESERVED_10[12]

Definition at line 27727 of file MIMXRT1052.h.

RESERVED_10 [4/7]

uint8_t PXP_Type::RESERVED_10[12]

Definition at line 32547 of file MIMXRT1052.h.

RESERVED_10 [5/7]

uint8_t ENET_Type::RESERVED_10[28]

Definition at line 15634 of file MIMXRT1052.h.

RESERVED_10 [6/7]

uint8_t LCDIF_Type::RESERVED_10[380]

Definition at line 23556 of file MIMXRT1052.h.

RESERVED_10 [7/7]

uint8_t LPI2C_Type::RESERVED_10[8]

Definition at line 25131 of file MIMXRT1052.h.

RESERVED_11 [1/7]

uint8_t LCDIF_Type::RESERVED_11[1104]

Definition at line 23569 of file MIMXRT1052.h.

RESERVED_11 [2/7]

uint8_t FLEXIO_Type::RESERVED_11[112]

Definition at line 17398 of file MIMXRT1052.h.

RESERVED_11 [3/7]

uint8_t LPI2C_Type::RESERVED_11[12]

Definition at line 25133 of file MIMXRT1052.h.

RESERVED_11 [4/7]

uint8_t OCOTP_Type::RESERVED_11[12]

Definition at line 27729 of file MIMXRT1052.h.

RESERVED_11 [5/7]

uint8_t PXP_Type::RESERVED_11[12]

Definition at line 32549 of file MIMXRT1052.h.

RESERVED_11 [6/7]

uint8_t DCP_Type::RESERVED_11[28]

Definition at line 10305 of file MIMXRT1052.h.

RESERVED_11 [7/7]

uint8_t ENET_Type::RESERVED_11[56]

Definition at line 15636 of file MIMXRT1052.h.

RESERVED_12 [1/6]

uint8_t DCP_Type::RESERVED_12[12]

Definition at line 10307 of file MIMXRT1052.h.

RESERVED_12 [2/6]

uint8_t LCDIF_Type::RESERVED_12[12]

Definition at line 23579 of file MIMXRT1052.h.

RESERVED_12 [3/6]

uint8_t OCOTP_Type::RESERVED_12[12]

Definition at line 27731 of file MIMXRT1052.h.

RESERVED_12 [4/6]

uint8_t PXP_Type::RESERVED_12[12]

Definition at line 32551 of file MIMXRT1052.h.

RESERVED_12 [5/6]

uint8_t FLEXIO_Type::RESERVED_12[368]

Definition at line 17400 of file MIMXRT1052.h.

RESERVED_12 [6/6]

uint8_t ENET_Type::RESERVED_12[4]

Definition at line 15640 of file MIMXRT1052.h.

RESERVED_13 [1/6]

uint8_t FLEXIO_Type::RESERVED_13[112]

Definition at line 17402 of file MIMXRT1052.h.

RESERVED_13 [2/6]

uint8_t DCP_Type::RESERVED_13[12]

Definition at line 10309 of file MIMXRT1052.h.

RESERVED_13 [3/6]

uint8_t ENET_Type::RESERVED_13[12]

Definition at line 15650 of file MIMXRT1052.h.

RESERVED_13 [4/6]

uint8_t LCDIF_Type::RESERVED_13[12]

Definition at line 23581 of file MIMXRT1052.h.

RESERVED_13 [5/6]

uint8_t OCOTP_Type::RESERVED_13[12]

Definition at line 27733 of file MIMXRT1052.h.

RESERVED_13 [6/6]

uint8_t PXP_Type::RESERVED_13[12]

Definition at line 32553 of file MIMXRT1052.h.

RESERVED_14 [1/6]

uint8_t FLEXIO_Type::RESERVED_14[112]

Definition at line 17404 of file MIMXRT1052.h.

RESERVED_14 [2/6]

uint8_t DCP_Type::RESERVED_14[12]

Definition at line 10319 of file MIMXRT1052.h.

RESERVED_14 [3/6]

uint8_t LCDIF_Type::RESERVED_14[12]

Definition at line 23583 of file MIMXRT1052.h.

RESERVED_14 [4/6]

uint8_t OCOTP_Type::RESERVED_14[12]

Definition at line 27735 of file MIMXRT1052.h.

RESERVED_14 [5/6]

uint8_t PXP_Type::RESERVED_14[12]

Definition at line 32555 of file MIMXRT1052.h.

RESERVED_14 [6/6]

uint8_t ENET_Type::RESERVED_14[56]

Definition at line 15653 of file MIMXRT1052.h.

RESERVED_15 [1/5]

uint8_t DCP_Type::RESERVED_15[12]

Definition at line 10321 of file MIMXRT1052.h.

RESERVED_15 [2/5]

uint8_t ENET_Type::RESERVED_15[12]

Definition at line 15684 of file MIMXRT1052.h.

RESERVED_15 [3/5]

uint8_t LCDIF_Type::RESERVED_15[12]

Definition at line 23585 of file MIMXRT1052.h.

RESERVED_15 [4/5]

uint8_t OCOTP_Type::RESERVED_15[12]

Definition at line 27737 of file MIMXRT1052.h.

RESERVED_15 [5/5]

uint8_t PXP_Type::RESERVED_15[12]

Definition at line 32557 of file MIMXRT1052.h.

RESERVED_16 [1/4]

uint8_t DCP_Type::RESERVED_16[12]

Definition at line 10331 of file MIMXRT1052.h.

RESERVED_16 [2/4]

uint8_t OCOTP_Type::RESERVED_16[12]

Definition at line 27739 of file MIMXRT1052.h.

RESERVED_16 [3/4]

uint8_t PXP_Type::RESERVED_16[12]

Definition at line 32559 of file MIMXRT1052.h.

RESERVED_16 [4/4]

uint8_t ENET_Type::RESERVED_16[284]

Definition at line 15709 of file MIMXRT1052.h.

RESERVED_17 [1/4]

uint8_t DCP_Type::RESERVED_17[12]

Definition at line 10333 of file MIMXRT1052.h.

RESERVED_17 [2/4]

uint8_t OCOTP_Type::RESERVED_17[12]

Definition at line 27741 of file MIMXRT1052.h.

RESERVED_17 [3/4]

uint8_t PXP_Type::RESERVED_17[12]

Definition at line 32561 of file MIMXRT1052.h.

RESERVED_17 [4/4]

uint8_t ENET_Type::RESERVED_17[488]

Definition at line 15717 of file MIMXRT1052.h.

RESERVED_18 [1/3]

uint8_t DCP_Type::RESERVED_18[12]

Definition at line 10343 of file MIMXRT1052.h.

RESERVED_18 [2/3]

uint8_t OCOTP_Type::RESERVED_18[12]

Definition at line 27743 of file MIMXRT1052.h.

RESERVED_18 [3/3]

uint8_t PXP_Type::RESERVED_18[12]

Definition at line 32563 of file MIMXRT1052.h.

RESERVED_19 [1/3]

uint8_t DCP_Type::RESERVED_19[12]

Definition at line 10345 of file MIMXRT1052.h.

RESERVED_19 [2/3]

uint8_t OCOTP_Type::RESERVED_19[12]

Definition at line 27745 of file MIMXRT1052.h.

RESERVED_19 [3/3]

uint8_t PXP_Type::RESERVED_19[12]

Definition at line 32565 of file MIMXRT1052.h.

RESERVED_2 [1/22]

uint8_t CCM_ANALOG_Type::RESERVED_2[12]

Definition at line 6094 of file MIMXRT1052.h.

RESERVED_2 [2/22]

uint8_t DCP_Type::RESERVED_2[12]

Definition at line 10287 of file MIMXRT1052.h.

RESERVED_2 [3/22]

uint8_t ENET_Type::RESERVED_2[12]

Definition at line 15611 of file MIMXRT1052.h.

RESERVED_2 [4/22]

uint8_t FLEXIO_Type::RESERVED_2[12]

Definition at line 17380 of file MIMXRT1052.h.

RESERVED_2 [5/22]

uint8_t OCOTP_Type::RESERVED_2[12]

Definition at line 27708 of file MIMXRT1052.h.

RESERVED_2 [6/22]

uint8_t PXP_Type::RESERVED_2[12]

Definition at line 32527 of file MIMXRT1052.h.

RESERVED_2 [7/22]

uint8_t SEMC_Type::RESERVED_2[12]

Definition at line 34162 of file MIMXRT1052.h.

RESERVED_2 [8/22]

uint8_t TSC_Type::RESERVED_2[12]

Definition at line 38552 of file MIMXRT1052.h.

RESERVED_2 [9/22]

uint8_t USB_Type::RESERVED_2[1]

Definition at line 39008 of file MIMXRT1052.h.

RESERVED_2 [10/22]

uint8_t LCDIF_Type::RESERVED_2[28]

Definition at line 23536 of file MIMXRT1052.h.

RESERVED_2 [11/22]

uint8_t { ... } ::RESERVED_2[28]

Definition at line 23576 of file MIMXRT1052.h.

RESERVED_2 [12/22]

uint8_t CSU_Type::RESERVED_2[316]

Definition at line 9475 of file MIMXRT1052.h.

RESERVED_2 [13/22]

uint8_t XTALOSC24M_Type::RESERVED_2[32]

Definition at line 45179 of file MIMXRT1052.h.

RESERVED_2 [14/22]

uint8_t I2S_Type::RESERVED_2[36]

Definition at line 19881 of file MIMXRT1052.h.

RESERVED_2 [15/22]

uint8_t DMA_Type::RESERVED_2[4]

Definition at line 11962 of file MIMXRT1052.h.

RESERVED_2 [16/22]

uint8_t LPI2C_Type::RESERVED_2[4]

Definition at line 25108 of file MIMXRT1052.h.

RESERVED_2 [17/22]

uint8_t USDHC_Type::RESERVED_2[84]

Definition at line 42281 of file MIMXRT1052.h.

RESERVED_2 [18/22]

uint8_t CAN_Type::RESERVED_2[8]

Definition at line 3332 of file MIMXRT1052.h.

RESERVED_2 [19/22]

uint8_t CCM_Type::RESERVED_2[8]

Definition at line 4171 of file MIMXRT1052.h.

RESERVED_2 [20/22]

uint8_t FLEXSPI_Type::RESERVED_2[8]

Definition at line 18105 of file MIMXRT1052.h.

RESERVED_2 [21/22]

uint8_t LPSPI_Type::RESERVED_2[8]

Definition at line 26157 of file MIMXRT1052.h.

RESERVED_2 [22/22]

uint8_t SNVS_Type::RESERVED_2[96]

Definition at line 35350 of file MIMXRT1052.h.

RESERVED_20 [1/3]

uint8_t OCOTP_Type::RESERVED_20[12]

Definition at line 27747 of file MIMXRT1052.h.

RESERVED_20 [2/3]

uint8_t PXP_Type::RESERVED_20[12]

Definition at line 32567 of file MIMXRT1052.h.

RESERVED_20 [3/3]

uint8_t DCP_Type::RESERVED_20[512]

Definition at line 10354 of file MIMXRT1052.h.

RESERVED_21 [1/3]

uint8_t DCP_Type::RESERVED_21[12]

Definition at line 10356 of file MIMXRT1052.h.

RESERVED_21 [2/3]

uint8_t OCOTP_Type::RESERVED_21[12]

Definition at line 27749 of file MIMXRT1052.h.

RESERVED_21 [3/3]

uint8_t PXP_Type::RESERVED_21[12]

Definition at line 32569 of file MIMXRT1052.h.

RESERVED_22 [1/3]

uint8_t DCP_Type::RESERVED_22[12]

Definition at line 10358 of file MIMXRT1052.h.

RESERVED_22 [2/3]

uint8_t OCOTP_Type::RESERVED_22[12]

Definition at line 27751 of file MIMXRT1052.h.

RESERVED_22 [3/3]

uint8_t PXP_Type::RESERVED_22[12]

Definition at line 32571 of file MIMXRT1052.h.

RESERVED_23 [1/3]

uint8_t DCP_Type::RESERVED_23[12]

Definition at line 10360 of file MIMXRT1052.h.

RESERVED_23 [2/3]

uint8_t PXP_Type::RESERVED_23[12]

Definition at line 32573 of file MIMXRT1052.h.

RESERVED_23 [3/3]

uint8_t OCOTP_Type::RESERVED_23[140]

Definition at line 27753 of file MIMXRT1052.h.

RESERVED_24 [1/2]

uint8_t OCOTP_Type::RESERVED_24[12]

Definition at line 27755 of file MIMXRT1052.h.

RESERVED_24 [2/2]

uint8_t PXP_Type::RESERVED_24[348]

Definition at line 32575 of file MIMXRT1052.h.

RESERVED_25 [1/2]

uint8_t OCOTP_Type::RESERVED_25[12]

Definition at line 27757 of file MIMXRT1052.h.

RESERVED_25 [2/2]

uint8_t PXP_Type::RESERVED_25[220]

Definition at line 32577 of file MIMXRT1052.h.

RESERVED_26 [1/2]

uint8_t OCOTP_Type::RESERVED_26[12]

Definition at line 27759 of file MIMXRT1052.h.

RESERVED_26 [2/2]

uint8_t PXP_Type::RESERVED_26[60]

Definition at line 32579 of file MIMXRT1052.h.

RESERVED_27

uint8_t OCOTP_Type::RESERVED_27[12]

Definition at line 27761 of file MIMXRT1052.h.

RESERVED_28

uint8_t OCOTP_Type::RESERVED_28[12]

Definition at line 27763 of file MIMXRT1052.h.

RESERVED_29

uint8_t OCOTP_Type::RESERVED_29[12]

Definition at line 27765 of file MIMXRT1052.h.

RESERVED_3 [1/18]

uint8_t CCM_ANALOG_Type::RESERVED_3[12]

Definition at line 6100 of file MIMXRT1052.h.

RESERVED_3 [2/18]

uint8_t DCP_Type::RESERVED_3[12]

Definition at line 10289 of file MIMXRT1052.h.

RESERVED_3 [3/18]

uint8_t LCDIF_Type::RESERVED_3[12]

Definition at line 23542 of file MIMXRT1052.h.

RESERVED_3 [4/18]

uint8_t OCOTP_Type::RESERVED_3[12]

Definition at line 27710 of file MIMXRT1052.h.

RESERVED_3 [5/18]

uint8_t PXP_Type::RESERVED_3[12]

Definition at line 32529 of file MIMXRT1052.h.

RESERVED_3 [6/18]

uint8_t SEMC_Type::RESERVED_3[12]

Definition at line 34164 of file MIMXRT1052.h.

RESERVED_3 [7/18]

uint8_t TSC_Type::RESERVED_3[12]

Definition at line 38554 of file MIMXRT1052.h.

RESERVED_3 [8/18]

uint8_t I2S_Type::RESERVED_3[16]

Definition at line 19889 of file MIMXRT1052.h.

RESERVED_3 [9/18]

uint8_t LPSPI_Type::RESERVED_3[20]

Definition at line 26159 of file MIMXRT1052.h.

RESERVED_3 [10/18]

uint8_t USB_Type::RESERVED_3[20]

Definition at line 39012 of file MIMXRT1052.h.

RESERVED_3 [11/18]

uint8_t ENET_Type::RESERVED_3[24]

Definition at line 15613 of file MIMXRT1052.h.

RESERVED_3 [12/18]

uint8_t SNVS_Type::RESERVED_3[2776]

Definition at line 35352 of file MIMXRT1052.h.

RESERVED_3 [13/18]

uint8_t CAN_Type::RESERVED_3[32]

Definition at line 3335 of file MIMXRT1052.h.

RESERVED_3 [14/18]

uint8_t DMA_Type::RESERVED_3[4]

Definition at line 11964 of file MIMXRT1052.h.

RESERVED_3 [15/18]

uint8_t LPI2C_Type::RESERVED_3[4]

Definition at line 25110 of file MIMXRT1052.h.

RESERVED_3 [16/18]

uint8_t FLEXIO_Type::RESERVED_3[60]

Definition at line 17382 of file MIMXRT1052.h.

RESERVED_3 [17/18]

uint8_t CCM_Type::RESERVED_3[8]

Definition at line 4173 of file MIMXRT1052.h.

RESERVED_3 [18/18]

uint8_t FLEXSPI_Type::RESERVED_3[8]

Definition at line 18108 of file MIMXRT1052.h.

RESERVED_30

uint8_t OCOTP_Type::RESERVED_30[12]

Definition at line 27767 of file MIMXRT1052.h.

RESERVED_31

uint8_t OCOTP_Type::RESERVED_31[12]

Definition at line 27769 of file MIMXRT1052.h.

RESERVED_32

uint8_t OCOTP_Type::RESERVED_32[12]

Definition at line 27771 of file MIMXRT1052.h.

RESERVED_33

uint8_t OCOTP_Type::RESERVED_33[12]

Definition at line 27773 of file MIMXRT1052.h.

RESERVED_34

uint8_t OCOTP_Type::RESERVED_34[12]

Definition at line 27775 of file MIMXRT1052.h.

RESERVED_35

uint8_t OCOTP_Type::RESERVED_35[12]

Definition at line 27777 of file MIMXRT1052.h.

RESERVED_36

uint8_t OCOTP_Type::RESERVED_36[28]

Definition at line 27779 of file MIMXRT1052.h.

RESERVED_37

uint8_t OCOTP_Type::RESERVED_37[12]

Definition at line 27781 of file MIMXRT1052.h.

RESERVED_38

uint8_t OCOTP_Type::RESERVED_38[12]

Definition at line 27783 of file MIMXRT1052.h.

RESERVED_39

uint8_t OCOTP_Type::RESERVED_39[12]

Definition at line 27785 of file MIMXRT1052.h.

RESERVED_4 [1/16]

uint8_t CAN_Type::RESERVED_4[1024]

Definition at line 3342 of file MIMXRT1052.h.

RESERVED_4 [2/16]

uint8_t FLEXIO_Type::RESERVED_4[112]

Definition at line 17384 of file MIMXRT1052.h.

RESERVED_4 [3/16]

uint8_t CCM_ANALOG_Type::RESERVED_4[12]

Definition at line 6102 of file MIMXRT1052.h.

RESERVED_4 [4/16]

uint8_t DCP_Type::RESERVED_4[12]

Definition at line 10291 of file MIMXRT1052.h.

RESERVED_4 [5/16]

uint8_t LCDIF_Type::RESERVED_4[12]

Definition at line 23544 of file MIMXRT1052.h.

RESERVED_4 [6/16]

uint8_t OCOTP_Type::RESERVED_4[12]

Definition at line 27712 of file MIMXRT1052.h.

RESERVED_4 [7/16]

uint8_t PXP_Type::RESERVED_4[12]

Definition at line 32531 of file MIMXRT1052.h.

RESERVED_4 [8/16]

uint8_t TSC_Type::RESERVED_4[12]

Definition at line 38556 of file MIMXRT1052.h.

RESERVED_4 [9/16]

uint8_t I2S_Type::RESERVED_4[16]

Definition at line 19891 of file MIMXRT1052.h.

RESERVED_4 [10/16]

uint8_t ENET_Type::RESERVED_4[28]

Definition at line 15616 of file MIMXRT1052.h.

RESERVED_4 [11/16]

uint8_t USB_Type::RESERVED_4[2]

Definition at line 39014 of file MIMXRT1052.h.

RESERVED_4 [12/16]

uint8_t CCM_Type::RESERVED_4[4]

Definition at line 4186 of file MIMXRT1052.h.

RESERVED_4 [13/16]

uint8_t DMA_Type::RESERVED_4[4]

Definition at line 11966 of file MIMXRT1052.h.

RESERVED_4 [14/16]

uint8_t FLEXSPI_Type::RESERVED_4[4]

Definition at line 18110 of file MIMXRT1052.h.

RESERVED_4 [15/16]

uint8_t LPI2C_Type::RESERVED_4[4]

Definition at line 25112 of file MIMXRT1052.h.

RESERVED_4 [16/16]

uint8_t LPSPI_Type::RESERVED_4[8]

Definition at line 26164 of file MIMXRT1052.h.

RESERVED_40

uint8_t OCOTP_Type::RESERVED_40[12]

Definition at line 27787 of file MIMXRT1052.h.

RESERVED_41

uint8_t OCOTP_Type::RESERVED_41[12]

Definition at line 27789 of file MIMXRT1052.h.

RESERVED_42

uint8_t OCOTP_Type::RESERVED_42[12]

Definition at line 27791 of file MIMXRT1052.h.

RESERVED_43

uint8_t OCOTP_Type::RESERVED_43[12]

Definition at line 27793 of file MIMXRT1052.h.

RESERVED_44

uint8_t OCOTP_Type::RESERVED_44[12]

Definition at line 27795 of file MIMXRT1052.h.

RESERVED_45

uint8_t OCOTP_Type::RESERVED_45[12]

Definition at line 27797 of file MIMXRT1052.h.

RESERVED_5 [1/13]

uint8_t CCM_ANALOG_Type::RESERVED_5[12]

Definition at line 6108 of file MIMXRT1052.h.

RESERVED_5 [2/13]

uint8_t DCP_Type::RESERVED_5[12]

Definition at line 10293 of file MIMXRT1052.h.

RESERVED_5 [3/13]

uint8_t DMA_Type::RESERVED_5[12]

Definition at line 11968 of file MIMXRT1052.h.

RESERVED_5 [4/13]

uint8_t LCDIF_Type::RESERVED_5[12]

Definition at line 23546 of file MIMXRT1052.h.

RESERVED_5 [5/13]

uint8_t LPI2C_Type::RESERVED_5[12]

Definition at line 25116 of file MIMXRT1052.h.

RESERVED_5 [6/13]

uint8_t PXP_Type::RESERVED_5[12]

Definition at line 32533 of file MIMXRT1052.h.

RESERVED_5 [7/13]

uint8_t TSC_Type::RESERVED_5[12]

Definition at line 38558 of file MIMXRT1052.h.

RESERVED_5 [8/13]

uint8_t FLEXIO_Type::RESERVED_5[240]

Definition at line 17386 of file MIMXRT1052.h.

RESERVED_5 [9/13]

uint8_t FLEXSPI_Type::RESERVED_5[24]

Definition at line 18114 of file MIMXRT1052.h.

RESERVED_5 [10/13]

uint8_t USB_Type::RESERVED_5[24]

Definition at line 39016 of file MIMXRT1052.h.

RESERVED_5 [11/13]

uint8_t ENET_Type::RESERVED_5[28]

Definition at line 15618 of file MIMXRT1052.h.

RESERVED_5 [12/13]

uint8_t OCOTP_Type::RESERVED_5[32]

Definition at line 27717 of file MIMXRT1052.h.

RESERVED_5 [13/13]

uint8_t CAN_Type::RESERVED_5[96]

Definition at line 3344 of file MIMXRT1052.h.

RESERVED_6 [1/12]

uint8_t OCOTP_Type::RESERVED_6[108]

Definition at line 27719 of file MIMXRT1052.h.

RESERVED_6 [2/12]

uint8_t FLEXIO_Type::RESERVED_6[112]

Definition at line 17388 of file MIMXRT1052.h.

RESERVED_6 [3/12]

uint8_t DCP_Type::RESERVED_6[12]

Definition at line 10295 of file MIMXRT1052.h.

RESERVED_6 [4/12]

uint8_t PXP_Type::RESERVED_6[12]

Definition at line 32535 of file MIMXRT1052.h.

RESERVED_6 [5/12]

uint8_t TSC_Type::RESERVED_6[12]

Definition at line 38560 of file MIMXRT1052.h.

RESERVED_6 [6/12]

uint8_t LPI2C_Type::RESERVED_6[156]

Definition at line 25118 of file MIMXRT1052.h.

RESERVED_6 [7/12]

uint8_t DMA_Type::RESERVED_6[184]

Definition at line 11970 of file MIMXRT1052.h.

RESERVED_6 [8/12]

uint8_t LCDIF_Type::RESERVED_6[220]

Definition at line 23548 of file MIMXRT1052.h.

RESERVED_6 [9/12]

uint8_t CCM_ANALOG_Type::RESERVED_6[28]

Definition at line 6110 of file MIMXRT1052.h.

RESERVED_6 [10/12]

uint8_t USB_Type::RESERVED_6[4]

Definition at line 39021 of file MIMXRT1052.h.

RESERVED_6 [11/12]

uint8_t ENET_Type::RESERVED_6[60]

Definition at line 15620 of file MIMXRT1052.h.

RESERVED_6 [12/12]

uint8_t FLEXSPI_Type::RESERVED_6[8]

Definition at line 18121 of file MIMXRT1052.h.

RESERVED_7 [1/11]

uint8_t FLEXIO_Type::RESERVED_7[112]

Definition at line 17390 of file MIMXRT1052.h.

RESERVED_7 [2/11]

uint8_t DCP_Type::RESERVED_7[12]

Definition at line 10297 of file MIMXRT1052.h.

RESERVED_7 [3/11]

uint8_t LCDIF_Type::RESERVED_7[12]

Definition at line 23550 of file MIMXRT1052.h.

RESERVED_7 [4/11]

uint8_t PXP_Type::RESERVED_7[12]

Definition at line 32537 of file MIMXRT1052.h.

RESERVED_7 [5/11]

uint8_t TSC_Type::RESERVED_7[12]

Definition at line 38562 of file MIMXRT1052.h.

RESERVED_7 [6/11]

uint8_t ENET_Type::RESERVED_7[28]

Definition at line 15622 of file MIMXRT1052.h.

RESERVED_7 [7/11]

uint8_t DMA_Type::RESERVED_7[3808]

Definition at line 12003 of file MIMXRT1052.h.

RESERVED_7 [8/11]

uint8_t LPI2C_Type::RESERVED_7[4]

Definition at line 25123 of file MIMXRT1052.h.

RESERVED_7 [9/11]

uint8_t USB_Type::RESERVED_7[4]

Definition at line 39030 of file MIMXRT1052.h.

RESERVED_7 [10/11]

uint8_t CCM_ANALOG_Type::RESERVED_7[64]

Definition at line 6123 of file MIMXRT1052.h.

RESERVED_7 [11/11]

uint8_t OCOTP_Type::RESERVED_7[764]

Definition at line 27721 of file MIMXRT1052.h.

RESERVED_8 [1/8]

uint8_t FLEXIO_Type::RESERVED_8[112]

Definition at line 17392 of file MIMXRT1052.h.

RESERVED_8 [2/8]

uint8_t DCP_Type::RESERVED_8[12]

Definition at line 10299 of file MIMXRT1052.h.

RESERVED_8 [3/8]

uint8_t ENET_Type::RESERVED_8[12]

Definition at line 15627 of file MIMXRT1052.h.

RESERVED_8 [4/8]

uint8_t LCDIF_Type::RESERVED_8[12]

Definition at line 23552 of file MIMXRT1052.h.

RESERVED_8 [5/8]

uint8_t OCOTP_Type::RESERVED_8[12]

Definition at line 27723 of file MIMXRT1052.h.

RESERVED_8 [6/8]

uint8_t PXP_Type::RESERVED_8[12]

Definition at line 32543 of file MIMXRT1052.h.

RESERVED_8 [7/8]

uint8_t USB_Type::RESERVED_8[16]

Definition at line 39033 of file MIMXRT1052.h.

RESERVED_8 [8/8]

uint8_t LPI2C_Type::RESERVED_8[20]

Definition at line 25126 of file MIMXRT1052.h.

RESERVED_9 [1/8]

uint8_t FLEXIO_Type::RESERVED_9[112]

Definition at line 17394 of file MIMXRT1052.h.

RESERVED_9 [2/8]

uint8_t DCP_Type::RESERVED_9[12]

Definition at line 10301 of file MIMXRT1052.h.

RESERVED_9 [3/8]

uint8_t LPI2C_Type::RESERVED_9[12]

Definition at line 25128 of file MIMXRT1052.h.

RESERVED_9 [4/8]

uint8_t OCOTP_Type::RESERVED_9[12]

Definition at line 27725 of file MIMXRT1052.h.

RESERVED_9 [5/8]

uint8_t PXP_Type::RESERVED_9[12]

Definition at line 32545 of file MIMXRT1052.h.

RESERVED_9 [6/8]

uint8_t ENET_Type::RESERVED_9[20]

Definition at line 15629 of file MIMXRT1052.h.

RESERVED_9 [7/8]

uint8_t USB_Type::RESERVED_9[28]

Definition at line 39038 of file MIMXRT1052.h.

RESERVED_9 [8/8]

uint8_t LCDIF_Type::RESERVED_9[76]

Definition at line 23554 of file MIMXRT1052.h.

REV

__IO uint16_t ENC_Type::REV

Revolution Counter Register, offset: 0xA

Definition at line 15144 of file MIMXRT1052.h.

REVH

__I uint16_t ENC_Type::REVH

Revolution Hold Register, offset: 0xC

Definition at line 15145 of file MIMXRT1052.h.

RFDR

__I uint32_t FLEXSPI_Type::RFDR[32]

IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4

Definition at line 18122 of file MIMXRT1052.h.

RFR

__I uint32_t I2S_Type::RFR[4]

SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4

Definition at line 19890 of file MIMXRT1052.h.

RMON_R_BC_PKT

__I uint32_t ENET_Type::RMON_R_BC_PKT

Rx Broadcast Packets Statistic Register, offset: 0x288

Definition at line 15686 of file MIMXRT1052.h.

RMON_R_CRC_ALIGN

__I uint32_t ENET_Type::RMON_R_CRC_ALIGN

Rx Packets with CRC/Align Error Statistic Register, offset: 0x290

Definition at line 15688 of file MIMXRT1052.h.

RMON_R_FRAG

__I uint32_t ENET_Type::RMON_R_FRAG

Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C

Definition at line 15691 of file MIMXRT1052.h.

RMON_R_JAB

__I uint32_t ENET_Type::RMON_R_JAB

Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0

Definition at line 15692 of file MIMXRT1052.h.

RMON_R_MC_PKT

__I uint32_t ENET_Type::RMON_R_MC_PKT

Rx Multicast Packets Statistic Register, offset: 0x28C

Definition at line 15687 of file MIMXRT1052.h.

RMON_R_OCTETS

__I uint32_t ENET_Type::RMON_R_OCTETS

Rx Octets Statistic Register, offset: 0x2C4

Definition at line 15701 of file MIMXRT1052.h.

RMON_R_OVERSIZE

__I uint32_t ENET_Type::RMON_R_OVERSIZE

Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298

Definition at line 15690 of file MIMXRT1052.h.

RMON_R_P1024TO2047

__I uint32_t ENET_Type::RMON_R_P1024TO2047

Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC

Definition at line 15699 of file MIMXRT1052.h.

RMON_R_P128TO255

__I uint32_t ENET_Type::RMON_R_P128TO255

Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0

Definition at line 15696 of file MIMXRT1052.h.

RMON_R_P256TO511

__I uint32_t ENET_Type::RMON_R_P256TO511

Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4

Definition at line 15697 of file MIMXRT1052.h.

RMON_R_P512TO1023

__I uint32_t ENET_Type::RMON_R_P512TO1023

Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8

Definition at line 15698 of file MIMXRT1052.h.

RMON_R_P64

__I uint32_t ENET_Type::RMON_R_P64

Rx 64-Byte Packets Statistic Register, offset: 0x2A8

Definition at line 15694 of file MIMXRT1052.h.

RMON_R_P65TO127

__I uint32_t ENET_Type::RMON_R_P65TO127

Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC

Definition at line 15695 of file MIMXRT1052.h.

RMON_R_P_GTE2048

__I uint32_t ENET_Type::RMON_R_P_GTE2048

Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0

Definition at line 15700 of file MIMXRT1052.h.

RMON_R_PACKETS

__I uint32_t ENET_Type::RMON_R_PACKETS

Rx Packet Count Statistic Register, offset: 0x284

Definition at line 15685 of file MIMXRT1052.h.

RMON_R_RESVD_0

uint32_t ENET_Type::RMON_R_RESVD_0

Reserved Statistic Register, offset: 0x2A4

Definition at line 15693 of file MIMXRT1052.h.

RMON_R_UNDERSIZE

__I uint32_t ENET_Type::RMON_R_UNDERSIZE

Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294

Definition at line 15689 of file MIMXRT1052.h.

RMON_T_BC_PKT

__I uint32_t ENET_Type::RMON_T_BC_PKT

Tx Broadcast Packets Statistic Register, offset: 0x208

Definition at line 15656 of file MIMXRT1052.h.

RMON_T_COL

__I uint32_t ENET_Type::RMON_T_COL

Tx Collision Count Statistic Register, offset: 0x224

Definition at line 15663 of file MIMXRT1052.h.

RMON_T_CRC_ALIGN

__I uint32_t ENET_Type::RMON_T_CRC_ALIGN

Tx Packets with CRC/Align Error Statistic Register, offset: 0x210

Definition at line 15658 of file MIMXRT1052.h.

RMON_T_DROP

uint32_t ENET_Type::RMON_T_DROP

Reserved Statistic Register, offset: 0x200

Definition at line 15654 of file MIMXRT1052.h.

RMON_T_FRAG

__I uint32_t ENET_Type::RMON_T_FRAG

Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C

Definition at line 15661 of file MIMXRT1052.h.

RMON_T_JAB

__I uint32_t ENET_Type::RMON_T_JAB

Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220

Definition at line 15662 of file MIMXRT1052.h.

RMON_T_MC_PKT

__I uint32_t ENET_Type::RMON_T_MC_PKT

Tx Multicast Packets Statistic Register, offset: 0x20C

Definition at line 15657 of file MIMXRT1052.h.

RMON_T_OCTETS

__I uint32_t ENET_Type::RMON_T_OCTETS

Tx Octets Statistic Register, offset: 0x244

Definition at line 15671 of file MIMXRT1052.h.

RMON_T_OVERSIZE

__I uint32_t ENET_Type::RMON_T_OVERSIZE

Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218

Definition at line 15660 of file MIMXRT1052.h.

RMON_T_P1024TO2047

__I uint32_t ENET_Type::RMON_T_P1024TO2047

Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C

Definition at line 15669 of file MIMXRT1052.h.

RMON_T_P128TO255

__I uint32_t ENET_Type::RMON_T_P128TO255

Tx 128- to 255-byte Packets Statistic Register, offset: 0x230

Definition at line 15666 of file MIMXRT1052.h.

RMON_T_P256TO511

__I uint32_t ENET_Type::RMON_T_P256TO511

Tx 256- to 511-byte Packets Statistic Register, offset: 0x234

Definition at line 15667 of file MIMXRT1052.h.

RMON_T_P512TO1023

__I uint32_t ENET_Type::RMON_T_P512TO1023

Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238

Definition at line 15668 of file MIMXRT1052.h.

RMON_T_P64

__I uint32_t ENET_Type::RMON_T_P64

Tx 64-Byte Packets Statistic Register, offset: 0x228

Definition at line 15664 of file MIMXRT1052.h.

RMON_T_P65TO127

__I uint32_t ENET_Type::RMON_T_P65TO127

Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C

Definition at line 15665 of file MIMXRT1052.h.

RMON_T_P_GTE2048

__I uint32_t ENET_Type::RMON_T_P_GTE2048

Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240

Definition at line 15670 of file MIMXRT1052.h.

RMON_T_PACKETS

__I uint32_t ENET_Type::RMON_T_PACKETS

Tx Packet Count Statistic Register, offset: 0x204

Definition at line 15655 of file MIMXRT1052.h.

RMON_T_UNDERSIZE

__I uint32_t ENET_Type::RMON_T_UNDERSIZE

Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214

Definition at line 15659 of file MIMXRT1052.h.

RMR

__IO uint32_t I2S_Type::RMR

SAI Receive Mask Register, offset: 0xE0

Definition at line 19892 of file MIMXRT1052.h.

ROMPATCHA

__IO uint32_t ROMC_Type::ROMPATCHA[16]

ROMC Address Registers, array offset: 0x100, array step: 0x4

Definition at line 33807 of file MIMXRT1052.h.

ROMPATCHCNTL

__IO uint32_t ROMC_Type::ROMPATCHCNTL

ROMC Control Register, offset: 0xF4

Definition at line 33804 of file MIMXRT1052.h.

ROMPATCHD

__IO uint32_t ROMC_Type::ROMPATCHD[8]

ROMC Data Registers, array offset: 0xD4, array step: 0x4

Definition at line 33803 of file MIMXRT1052.h.

ROMPATCHENH

uint32_t ROMC_Type::ROMPATCHENH

ROMC Enable Register High, offset: 0xF8

Definition at line 33805 of file MIMXRT1052.h.

ROMPATCHENL

__IO uint32_t ROMC_Type::ROMPATCHENL

ROMC Enable Register Low, offset: 0xFC

Definition at line 33806 of file MIMXRT1052.h.

ROMPATCHSR

__IO uint32_t ROMC_Type::ROMPATCHSR

ROMC Status Register, offset: 0x208

Definition at line 33809 of file MIMXRT1052.h.

RSEM

__IO uint32_t ENET_Type::RSEM

Receive FIFO Section Empty Threshold, offset: 0x194

Definition at line 15642 of file MIMXRT1052.h.

RSFL

__IO uint32_t ENET_Type::RSFL

Receive FIFO Section Full Threshold, offset: 0x190

Definition at line 15641 of file MIMXRT1052.h.

RSR

__I uint32_t LPSPI_Type::RSR

Receive Status Register, offset: 0x70

Definition at line 26165 of file MIMXRT1052.h.

RX

__IO uint32_t USBPHY_Type::RX

USB PHY Receiver Control Register, offset: 0x20

Definition at line 40692 of file MIMXRT1052.h.

RX14MASK

__IO uint32_t CAN_Type::RX14MASK

Rx Buffer 14 Mask Register, offset: 0x14

Definition at line 3318 of file MIMXRT1052.h.

RX15MASK

__IO uint32_t CAN_Type::RX15MASK

Rx Buffer 15 Mask Register, offset: 0x18

Definition at line 3319 of file MIMXRT1052.h.

RX_CLR

__IO uint32_t USBPHY_Type::RX_CLR

USB PHY Receiver Control Register, offset: 0x28

Definition at line 40694 of file MIMXRT1052.h.

RX_SET

__IO uint32_t USBPHY_Type::RX_SET

USB PHY Receiver Control Register, offset: 0x24

Definition at line 40693 of file MIMXRT1052.h.

RX_TOG

__IO uint32_t USBPHY_Type::RX_TOG

USB PHY Receiver Control Register, offset: 0x2C

Definition at line 40695 of file MIMXRT1052.h.

RXFGMASK

__IO uint32_t CAN_Type::RXFGMASK

Rx FIFO Global Mask Register, offset: 0x48

Definition at line 3330 of file MIMXRT1052.h.

RXFIR

__I uint32_t CAN_Type::RXFIR

Rx FIFO Information Register, offset: 0x4C

Definition at line 3331 of file MIMXRT1052.h.

RXIC

__IO uint32_t ENET_Type::RXIC

Receive Interrupt Coalescing Register, offset: 0x100

Definition at line 15628 of file MIMXRT1052.h.

RXIMR

__IO uint32_t CAN_Type::RXIMR[64]

Rx Individual Mask Registers, array offset: 0x880, array step: 0x4

Definition at line 3343 of file MIMXRT1052.h.

RXMGMASK

__IO uint32_t CAN_Type::RXMGMASK

Rx Mailboxes Global Mask Register, offset: 0x10

Definition at line 3317 of file MIMXRT1052.h.

SA

__IO uint32_t CSU_Type::SA

Secure access register, offset: 0x218

Definition at line 9474 of file MIMXRT1052.h.

SADDR [1/2]

__IO { ... } ::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

Definition at line 12005 of file MIMXRT1052.h.

SADDR [2/2]

__IO uint32_t DMA_Type::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

Definition at line 12005 of file MIMXRT1052.h.

SAMR

__IO uint32_t LPI2C_Type::SAMR

Slave Address Match Register, offset: 0x140

Definition at line 25127 of file MIMXRT1052.h.

SASR

__I uint32_t LPI2C_Type::SASR

Slave Address Status Register, offset: 0x150

Definition at line 25129 of file MIMXRT1052.h.

SBLIM [1/2]

__IO uint32_t TRNG_Type::SBLIM

Sparse Bit Limit Register, offset: 0x14

Definition at line 37884 of file MIMXRT1052.h.

SBLIM [2/2]

__IO { ... } ::SBLIM

Sparse Bit Limit Register, offset: 0x14

Definition at line 37884 of file MIMXRT1052.h.

SBMR1

__I uint32_t SRC_Type::SBMR1

SRC Boot Mode Register 1, offset: 0x4

Definition at line 36903 of file MIMXRT1052.h.

SBMR2

__I uint32_t SRC_Type::SBMR2

SRC Boot Mode Register 2, offset: 0x1C

Definition at line 36906 of file MIMXRT1052.h.

SBUSCFG

__IO uint32_t USB_Type::SBUSCFG

System Bus Config, offset: 0x90

Definition at line 39005 of file MIMXRT1052.h.

SCFGR1

__IO uint32_t LPI2C_Type::SCFGR1

Slave Configuration Register 1, offset: 0x124

Definition at line 25124 of file MIMXRT1052.h.

SCFGR2

__IO uint32_t LPI2C_Type::SCFGR2

Slave Configuration Register 2, offset: 0x128

Definition at line 25125 of file MIMXRT1052.h.

SCMC [1/2]

__I { ... } ::SCMC

Statistical Check Monobit Count Register, offset: 0x20

Definition at line 37893 of file MIMXRT1052.h.

SCMC [2/2]

__I uint32_t TRNG_Type::SCMC

Statistical Check Monobit Count Register, offset: 0x20

Definition at line 37893 of file MIMXRT1052.h.

SCMISC

__IO uint32_t TRNG_Type::SCMISC

Statistical Check Miscellaneous Register, offset: 0x4

Definition at line 37876 of file MIMXRT1052.h.

SCML [1/2]

__IO { ... } ::SCML

Statistical Check Monobit Limit Register, offset: 0x20

Definition at line 37894 of file MIMXRT1052.h.

SCML [2/2]

__IO uint32_t TRNG_Type::SCML

Statistical Check Monobit Limit Register, offset: 0x20

Definition at line 37894 of file MIMXRT1052.h.

SCR [1/4]

__IO uint8_t CMP_Type::SCR

CMP Status and Control Register, offset: 0x3

Definition at line 8545 of file MIMXRT1052.h.

SCR [2/4]

__IO uint32_t LPI2C_Type::SCR

Slave Control Register, offset: 0x110

Definition at line 25119 of file MIMXRT1052.h.

SCR [3/4]

__IO uint32_t SPDIF_Type::SCR

SPDIF Configuration Register, offset: 0x0

Definition at line 36417 of file MIMXRT1052.h.

SCR [4/4]

__IO uint32_t SRC_Type::SCR

SRC Control Register, offset: 0x0

Definition at line 36902 of file MIMXRT1052.h.

SCR1C [1/2]

__I { ... } ::SCR1C

Statistical Check Run Length 1 Count Register, offset: 0x24

Definition at line 37897 of file MIMXRT1052.h.

SCR1C [2/2]

__I uint32_t TRNG_Type::SCR1C

Statistical Check Run Length 1 Count Register, offset: 0x24

Definition at line 37897 of file MIMXRT1052.h.

SCR1L [1/2]

__IO uint32_t TRNG_Type::SCR1L

Statistical Check Run Length 1 Limit Register, offset: 0x24

Definition at line 37898 of file MIMXRT1052.h.

SCR1L [2/2]

__IO { ... } ::SCR1L

Statistical Check Run Length 1 Limit Register, offset: 0x24

Definition at line 37898 of file MIMXRT1052.h.

SCR2C [1/2]

__I { ... } ::SCR2C

Statistical Check Run Length 2 Count Register, offset: 0x28

Definition at line 37901 of file MIMXRT1052.h.

SCR2C [2/2]

__I uint32_t TRNG_Type::SCR2C

Statistical Check Run Length 2 Count Register, offset: 0x28

Definition at line 37901 of file MIMXRT1052.h.

SCR2L [1/2]

__IO { ... } ::SCR2L

Statistical Check Run Length 2 Limit Register, offset: 0x28

Definition at line 37902 of file MIMXRT1052.h.

SCR2L [2/2]

__IO uint32_t TRNG_Type::SCR2L

Statistical Check Run Length 2 Limit Register, offset: 0x28

Definition at line 37902 of file MIMXRT1052.h.

SCR3C [1/2]

__I uint32_t TRNG_Type::SCR3C

Statistical Check Run Length 3 Count Register, offset: 0x2C

Definition at line 37905 of file MIMXRT1052.h.

SCR3C [2/2]

__I { ... } ::SCR3C

Statistical Check Run Length 3 Count Register, offset: 0x2C

Definition at line 37905 of file MIMXRT1052.h.

SCR3L [1/2]

__IO { ... } ::SCR3L

Statistical Check Run Length 3 Limit Register, offset: 0x2C

Definition at line 37906 of file MIMXRT1052.h.

SCR3L [2/2]

__IO uint32_t TRNG_Type::SCR3L

Statistical Check Run Length 3 Limit Register, offset: 0x2C

Definition at line 37906 of file MIMXRT1052.h.

SCR4C [1/2]

__I { ... } ::SCR4C

Statistical Check Run Length 4 Count Register, offset: 0x30

Definition at line 37909 of file MIMXRT1052.h.

SCR4C [2/2]

__I uint32_t TRNG_Type::SCR4C

Statistical Check Run Length 4 Count Register, offset: 0x30

Definition at line 37909 of file MIMXRT1052.h.

SCR4L [1/2]

__IO { ... } ::SCR4L

Statistical Check Run Length 4 Limit Register, offset: 0x30

Definition at line 37910 of file MIMXRT1052.h.

SCR4L [2/2]

__IO uint32_t TRNG_Type::SCR4L

Statistical Check Run Length 4 Limit Register, offset: 0x30

Definition at line 37910 of file MIMXRT1052.h.

SCR5C [1/2]

__I uint32_t TRNG_Type::SCR5C

Statistical Check Run Length 5 Count Register, offset: 0x34

Definition at line 37913 of file MIMXRT1052.h.

SCR5C [2/2]

__I { ... } ::SCR5C

Statistical Check Run Length 5 Count Register, offset: 0x34

Definition at line 37913 of file MIMXRT1052.h.

SCR5L [1/2]

__IO { ... } ::SCR5L

Statistical Check Run Length 5 Limit Register, offset: 0x34

Definition at line 37914 of file MIMXRT1052.h.

SCR5L [2/2]

__IO uint32_t TRNG_Type::SCR5L

Statistical Check Run Length 5 Limit Register, offset: 0x34

Definition at line 37914 of file MIMXRT1052.h.

SCR6PC [1/2]

__I uint32_t TRNG_Type::SCR6PC

Statistical Check Run Length 6+ Count Register, offset: 0x38

Definition at line 37917 of file MIMXRT1052.h.

SCR6PC [2/2]

__I { ... } ::SCR6PC

Statistical Check Run Length 6+ Count Register, offset: 0x38

Definition at line 37917 of file MIMXRT1052.h.

SCR6PL [1/2]

__IO uint32_t TRNG_Type::SCR6PL

Statistical Check Run Length 6+ Limit Register, offset: 0x38

Definition at line 37918 of file MIMXRT1052.h.

SCR6PL [2/2]

__IO { ... } ::SCR6PL

Statistical Check Run Length 6+ Limit Register, offset: 0x38

Definition at line 37918 of file MIMXRT1052.h.

SCS

__IO uint32_t OCOTP_Type::SCS

Software Controllable Signals Register, offset: 0x60

Definition at line 27713 of file MIMXRT1052.h.

SCS_CLR

__IO uint32_t OCOTP_Type::SCS_CLR

Software Controllable Signals Register, offset: 0x68

Definition at line 27715 of file MIMXRT1052.h.

SCS_SET

__IO uint32_t OCOTP_Type::SCS_SET

Software Controllable Signals Register, offset: 0x64

Definition at line 27714 of file MIMXRT1052.h.

SCS_TOG

__IO uint32_t OCOTP_Type::SCS_TOG

Software Controllable Signals Register, offset: 0x6C

Definition at line 27716 of file MIMXRT1052.h.

SCTRL [1/2]

__IO uint16_t TMR_Type::SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

Definition at line 37387 of file MIMXRT1052.h.

SCTRL [2/2]

__IO { ... } ::SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

Definition at line 37387 of file MIMXRT1052.h.

SDCTL

__IO uint32_t TRNG_Type::SDCTL

Seed Control Register, offset: 0x10

Definition at line 37882 of file MIMXRT1052.h.

SDER

__IO uint32_t LPI2C_Type::SDER

Slave DMA Enable Register, offset: 0x11C

Definition at line 25122 of file MIMXRT1052.h.

SDRAMCR0

__IO uint32_t SEMC_Type::SDRAMCR0

SDRAM control register 0, offset: 0x40

Definition at line 34138 of file MIMXRT1052.h.

SDRAMCR1

__IO uint32_t SEMC_Type::SDRAMCR1

SDRAM control register 1, offset: 0x44

Definition at line 34139 of file MIMXRT1052.h.

SDRAMCR2

__IO uint32_t SEMC_Type::SDRAMCR2

SDRAM control register 2, offset: 0x48

Definition at line 34140 of file MIMXRT1052.h.

SDRAMCR3

__IO uint32_t SEMC_Type::SDRAMCR3

SDRAM control register 3, offset: 0x4C

Definition at line 34141 of file MIMXRT1052.h.

SEC_CFG

__IO uint32_t TRNG_Type::SEC_CFG

Security Configuration Register, offset: 0xA0

Definition at line 37930 of file MIMXRT1052.h.

SEEI

__O uint8_t DMA_Type::SEEI

Set Enable Error Interrupt Register, offset: 0x19

Definition at line 11955 of file MIMXRT1052.h.

SEL0 [1/2]

__IO uint16_t XBARA_Type::SEL0

Crossbar A Select Register 0, offset: 0x0

Definition at line 44135 of file MIMXRT1052.h.

SEL0 [2/2]

__IO uint16_t XBARB_Type::SEL0

Crossbar B Select Register 0, offset: 0x0

Definition at line 45034 of file MIMXRT1052.h.

SEL1 [1/2]

__IO uint16_t XBARA_Type::SEL1

Crossbar A Select Register 1, offset: 0x2

Definition at line 44136 of file MIMXRT1052.h.

SEL1 [2/2]

__IO uint16_t XBARB_Type::SEL1

Crossbar B Select Register 1, offset: 0x2

Definition at line 45035 of file MIMXRT1052.h.

SEL10

__IO uint16_t XBARA_Type::SEL10

Crossbar A Select Register 10, offset: 0x14

Definition at line 44145 of file MIMXRT1052.h.

SEL11

__IO uint16_t XBARA_Type::SEL11

Crossbar A Select Register 11, offset: 0x16

Definition at line 44146 of file MIMXRT1052.h.

SEL12

__IO uint16_t XBARA_Type::SEL12

Crossbar A Select Register 12, offset: 0x18

Definition at line 44147 of file MIMXRT1052.h.

SEL13

__IO uint16_t XBARA_Type::SEL13

Crossbar A Select Register 13, offset: 0x1A

Definition at line 44148 of file MIMXRT1052.h.

SEL14

__IO uint16_t XBARA_Type::SEL14

Crossbar A Select Register 14, offset: 0x1C

Definition at line 44149 of file MIMXRT1052.h.

SEL15

__IO uint16_t XBARA_Type::SEL15

Crossbar A Select Register 15, offset: 0x1E

Definition at line 44150 of file MIMXRT1052.h.

SEL16

__IO uint16_t XBARA_Type::SEL16

Crossbar A Select Register 16, offset: 0x20

Definition at line 44151 of file MIMXRT1052.h.

SEL17

__IO uint16_t XBARA_Type::SEL17

Crossbar A Select Register 17, offset: 0x22

Definition at line 44152 of file MIMXRT1052.h.

SEL18

__IO uint16_t XBARA_Type::SEL18

Crossbar A Select Register 18, offset: 0x24

Definition at line 44153 of file MIMXRT1052.h.

SEL19

__IO uint16_t XBARA_Type::SEL19

Crossbar A Select Register 19, offset: 0x26

Definition at line 44154 of file MIMXRT1052.h.

SEL2 [1/2]

__IO uint16_t XBARA_Type::SEL2

Crossbar A Select Register 2, offset: 0x4

Definition at line 44137 of file MIMXRT1052.h.

SEL2 [2/2]

__IO uint16_t XBARB_Type::SEL2

Crossbar B Select Register 2, offset: 0x4

Definition at line 45036 of file MIMXRT1052.h.

SEL20

__IO uint16_t XBARA_Type::SEL20

Crossbar A Select Register 20, offset: 0x28

Definition at line 44155 of file MIMXRT1052.h.

SEL21

__IO uint16_t XBARA_Type::SEL21

Crossbar A Select Register 21, offset: 0x2A

Definition at line 44156 of file MIMXRT1052.h.

SEL22

__IO uint16_t XBARA_Type::SEL22

Crossbar A Select Register 22, offset: 0x2C

Definition at line 44157 of file MIMXRT1052.h.

SEL23

__IO uint16_t XBARA_Type::SEL23

Crossbar A Select Register 23, offset: 0x2E

Definition at line 44158 of file MIMXRT1052.h.

SEL24

__IO uint16_t XBARA_Type::SEL24

Crossbar A Select Register 24, offset: 0x30

Definition at line 44159 of file MIMXRT1052.h.

SEL25

__IO uint16_t XBARA_Type::SEL25

Crossbar A Select Register 25, offset: 0x32

Definition at line 44160 of file MIMXRT1052.h.

SEL26

__IO uint16_t XBARA_Type::SEL26

Crossbar A Select Register 26, offset: 0x34

Definition at line 44161 of file MIMXRT1052.h.

SEL27

__IO uint16_t XBARA_Type::SEL27

Crossbar A Select Register 27, offset: 0x36

Definition at line 44162 of file MIMXRT1052.h.

SEL28

__IO uint16_t XBARA_Type::SEL28

Crossbar A Select Register 28, offset: 0x38

Definition at line 44163 of file MIMXRT1052.h.

SEL29

__IO uint16_t XBARA_Type::SEL29

Crossbar A Select Register 29, offset: 0x3A

Definition at line 44164 of file MIMXRT1052.h.

SEL3 [1/2]

__IO uint16_t XBARA_Type::SEL3

Crossbar A Select Register 3, offset: 0x6

Definition at line 44138 of file MIMXRT1052.h.

SEL3 [2/2]

__IO uint16_t XBARB_Type::SEL3

Crossbar B Select Register 3, offset: 0x6

Definition at line 45037 of file MIMXRT1052.h.

SEL30

__IO uint16_t XBARA_Type::SEL30

Crossbar A Select Register 30, offset: 0x3C

Definition at line 44165 of file MIMXRT1052.h.

SEL31

__IO uint16_t XBARA_Type::SEL31

Crossbar A Select Register 31, offset: 0x3E

Definition at line 44166 of file MIMXRT1052.h.

SEL32

__IO uint16_t XBARA_Type::SEL32

Crossbar A Select Register 32, offset: 0x40

Definition at line 44167 of file MIMXRT1052.h.

SEL33

__IO uint16_t XBARA_Type::SEL33

Crossbar A Select Register 33, offset: 0x42

Definition at line 44168 of file MIMXRT1052.h.

SEL34

__IO uint16_t XBARA_Type::SEL34

Crossbar A Select Register 34, offset: 0x44

Definition at line 44169 of file MIMXRT1052.h.

SEL35

__IO uint16_t XBARA_Type::SEL35

Crossbar A Select Register 35, offset: 0x46

Definition at line 44170 of file MIMXRT1052.h.

SEL36

__IO uint16_t XBARA_Type::SEL36

Crossbar A Select Register 36, offset: 0x48

Definition at line 44171 of file MIMXRT1052.h.

SEL37

__IO uint16_t XBARA_Type::SEL37

Crossbar A Select Register 37, offset: 0x4A

Definition at line 44172 of file MIMXRT1052.h.

SEL38

__IO uint16_t XBARA_Type::SEL38

Crossbar A Select Register 38, offset: 0x4C

Definition at line 44173 of file MIMXRT1052.h.

SEL39

__IO uint16_t XBARA_Type::SEL39

Crossbar A Select Register 39, offset: 0x4E

Definition at line 44174 of file MIMXRT1052.h.

SEL4 [1/2]

__IO uint16_t XBARA_Type::SEL4

Crossbar A Select Register 4, offset: 0x8

Definition at line 44139 of file MIMXRT1052.h.

SEL4 [2/2]

__IO uint16_t XBARB_Type::SEL4

Crossbar B Select Register 4, offset: 0x8

Definition at line 45038 of file MIMXRT1052.h.

SEL40

__IO uint16_t XBARA_Type::SEL40

Crossbar A Select Register 40, offset: 0x50

Definition at line 44175 of file MIMXRT1052.h.

SEL41

__IO uint16_t XBARA_Type::SEL41

Crossbar A Select Register 41, offset: 0x52

Definition at line 44176 of file MIMXRT1052.h.

SEL42

__IO uint16_t XBARA_Type::SEL42

Crossbar A Select Register 42, offset: 0x54

Definition at line 44177 of file MIMXRT1052.h.

SEL43

__IO uint16_t XBARA_Type::SEL43

Crossbar A Select Register 43, offset: 0x56

Definition at line 44178 of file MIMXRT1052.h.

SEL44

__IO uint16_t XBARA_Type::SEL44

Crossbar A Select Register 44, offset: 0x58

Definition at line 44179 of file MIMXRT1052.h.

SEL45

__IO uint16_t XBARA_Type::SEL45

Crossbar A Select Register 45, offset: 0x5A

Definition at line 44180 of file MIMXRT1052.h.

SEL46

__IO uint16_t XBARA_Type::SEL46

Crossbar A Select Register 46, offset: 0x5C

Definition at line 44181 of file MIMXRT1052.h.

SEL47

__IO uint16_t XBARA_Type::SEL47

Crossbar A Select Register 47, offset: 0x5E

Definition at line 44182 of file MIMXRT1052.h.

SEL48

__IO uint16_t XBARA_Type::SEL48

Crossbar A Select Register 48, offset: 0x60

Definition at line 44183 of file MIMXRT1052.h.

SEL49

__IO uint16_t XBARA_Type::SEL49

Crossbar A Select Register 49, offset: 0x62

Definition at line 44184 of file MIMXRT1052.h.

SEL5 [1/2]

__IO uint16_t XBARA_Type::SEL5

Crossbar A Select Register 5, offset: 0xA

Definition at line 44140 of file MIMXRT1052.h.

SEL5 [2/2]

__IO uint16_t XBARB_Type::SEL5

Crossbar B Select Register 5, offset: 0xA

Definition at line 45039 of file MIMXRT1052.h.

SEL50

__IO uint16_t XBARA_Type::SEL50

Crossbar A Select Register 50, offset: 0x64

Definition at line 44185 of file MIMXRT1052.h.

SEL51

__IO uint16_t XBARA_Type::SEL51

Crossbar A Select Register 51, offset: 0x66

Definition at line 44186 of file MIMXRT1052.h.

SEL52

__IO uint16_t XBARA_Type::SEL52

Crossbar A Select Register 52, offset: 0x68

Definition at line 44187 of file MIMXRT1052.h.

SEL53

__IO uint16_t XBARA_Type::SEL53

Crossbar A Select Register 53, offset: 0x6A

Definition at line 44188 of file MIMXRT1052.h.

SEL54

__IO uint16_t XBARA_Type::SEL54

Crossbar A Select Register 54, offset: 0x6C

Definition at line 44189 of file MIMXRT1052.h.

SEL55

__IO uint16_t XBARA_Type::SEL55

Crossbar A Select Register 55, offset: 0x6E

Definition at line 44190 of file MIMXRT1052.h.

SEL56

__IO uint16_t XBARA_Type::SEL56

Crossbar A Select Register 56, offset: 0x70

Definition at line 44191 of file MIMXRT1052.h.

SEL57

__IO uint16_t XBARA_Type::SEL57

Crossbar A Select Register 57, offset: 0x72

Definition at line 44192 of file MIMXRT1052.h.

SEL58

__IO uint16_t XBARA_Type::SEL58

Crossbar A Select Register 58, offset: 0x74

Definition at line 44193 of file MIMXRT1052.h.

SEL59

__IO uint16_t XBARA_Type::SEL59

Crossbar A Select Register 59, offset: 0x76

Definition at line 44194 of file MIMXRT1052.h.

SEL6 [1/2]

__IO uint16_t XBARA_Type::SEL6

Crossbar A Select Register 6, offset: 0xC

Definition at line 44141 of file MIMXRT1052.h.

SEL6 [2/2]

__IO uint16_t XBARB_Type::SEL6

Crossbar B Select Register 6, offset: 0xC

Definition at line 45040 of file MIMXRT1052.h.

SEL60

__IO uint16_t XBARA_Type::SEL60

Crossbar A Select Register 60, offset: 0x78

Definition at line 44195 of file MIMXRT1052.h.

SEL61

__IO uint16_t XBARA_Type::SEL61

Crossbar A Select Register 61, offset: 0x7A

Definition at line 44196 of file MIMXRT1052.h.

SEL62

__IO uint16_t XBARA_Type::SEL62

Crossbar A Select Register 62, offset: 0x7C

Definition at line 44197 of file MIMXRT1052.h.

SEL63

__IO uint16_t XBARA_Type::SEL63

Crossbar A Select Register 63, offset: 0x7E

Definition at line 44198 of file MIMXRT1052.h.

SEL64

__IO uint16_t XBARA_Type::SEL64

Crossbar A Select Register 64, offset: 0x80

Definition at line 44199 of file MIMXRT1052.h.

SEL65

__IO uint16_t XBARA_Type::SEL65

Crossbar A Select Register 65, offset: 0x82

Definition at line 44200 of file MIMXRT1052.h.

SEL7 [1/2]

__IO uint16_t XBARA_Type::SEL7

Crossbar A Select Register 7, offset: 0xE

Definition at line 44142 of file MIMXRT1052.h.

SEL7 [2/2]

__IO uint16_t XBARB_Type::SEL7

Crossbar B Select Register 7, offset: 0xE

Definition at line 45041 of file MIMXRT1052.h.

SEL8

__IO uint16_t XBARA_Type::SEL8

Crossbar A Select Register 8, offset: 0x10

Definition at line 44143 of file MIMXRT1052.h.

SEL9

__IO uint16_t XBARA_Type::SEL9

Crossbar A Select Register 9, offset: 0x12

Definition at line 44144 of file MIMXRT1052.h.

SELECT_INPUT

__IO uint32_t IOMUXC_Type::SELECT_INPUT[154]

ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4

Definition at line 20702 of file MIMXRT1052.h.

SERQ

__O uint8_t DMA_Type::SERQ

Set Enable Request Register, offset: 0x1B

Definition at line 11957 of file MIMXRT1052.h.

SERV

__O uint8_t EWM_Type::SERV

Service Register, offset: 0x1

Definition at line 17248 of file MIMXRT1052.h.

SHIFTBUF

__IO uint32_t FLEXIO_Type::SHIFTBUF[4]

Shifter Buffer N Register, array offset: 0x200, array step: 0x4

Definition at line 17387 of file MIMXRT1052.h.

SHIFTBUFBBS

__IO uint32_t FLEXIO_Type::SHIFTBUFBBS[4]

Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4

Definition at line 17393 of file MIMXRT1052.h.

SHIFTBUFBIS

__IO uint32_t FLEXIO_Type::SHIFTBUFBIS[4]

Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4

Definition at line 17389 of file MIMXRT1052.h.

SHIFTBUFBYS

__IO uint32_t FLEXIO_Type::SHIFTBUFBYS[4]

Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4

Definition at line 17391 of file MIMXRT1052.h.

SHIFTBUFHWS

__IO uint32_t FLEXIO_Type::SHIFTBUFHWS[4]

Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4

Definition at line 17403 of file MIMXRT1052.h.

SHIFTBUFNBS

__IO uint32_t FLEXIO_Type::SHIFTBUFNBS[4]

Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4

Definition at line 17401 of file MIMXRT1052.h.

SHIFTBUFNIS

__IO uint32_t FLEXIO_Type::SHIFTBUFNIS[4]

Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4

Definition at line 17405 of file MIMXRT1052.h.

SHIFTCFG

__IO uint32_t FLEXIO_Type::SHIFTCFG[4]

Shifter Configuration N Register, array offset: 0x100, array step: 0x4

Definition at line 17385 of file MIMXRT1052.h.

SHIFTCTL

__IO uint32_t FLEXIO_Type::SHIFTCTL[4]

Shifter Control N Register, array offset: 0x80, array step: 0x4

Definition at line 17383 of file MIMXRT1052.h.

SHIFTEIEN

__IO uint32_t FLEXIO_Type::SHIFTEIEN

Shifter Error Interrupt Enable, offset: 0x24

Definition at line 17376 of file MIMXRT1052.h.

SHIFTERR

__IO uint32_t FLEXIO_Type::SHIFTERR

Shifter Error Register, offset: 0x14

Definition at line 17372 of file MIMXRT1052.h.

SHIFTSDEN

__IO uint32_t FLEXIO_Type::SHIFTSDEN

Shifter Status DMA Enable, offset: 0x30

Definition at line 17379 of file MIMXRT1052.h.

SHIFTSIEN

__IO uint32_t FLEXIO_Type::SHIFTSIEN

Shifter Status Interrupt Enable, offset: 0x20

Definition at line 17375 of file MIMXRT1052.h.

SHIFTSTAT

__IO uint32_t FLEXIO_Type::SHIFTSTAT

Shifter Status Register, offset: 0x10

Definition at line 17371 of file MIMXRT1052.h.

SHIFTSTATE

__IO uint32_t FLEXIO_Type::SHIFTSTATE

Shifter State Register, offset: 0x40

Definition at line 17381 of file MIMXRT1052.h.

SIC [1/2]

__O { ... } ::SIC

InterruptClear Register, offset: 0x10

Definition at line 36422 of file MIMXRT1052.h.

SIC [2/2]

__O uint32_t SPDIF_Type::SIC

InterruptClear Register, offset: 0x10

Definition at line 36422 of file MIMXRT1052.h.

SIE

__IO uint32_t SPDIF_Type::SIE

InterruptEn Register, offset: 0xC

Definition at line 36420 of file MIMXRT1052.h.

SIER

__IO uint32_t LPI2C_Type::SIER

Slave Interrupt Enable Register, offset: 0x118

Definition at line 25121 of file MIMXRT1052.h.

SIS [1/2]

__I uint32_t SPDIF_Type::SIS

InterruptStat Register, offset: 0x10

Definition at line 36423 of file MIMXRT1052.h.

SIS [2/2]

__I { ... } ::SIS

InterruptStat Register, offset: 0x10

Definition at line 36423 of file MIMXRT1052.h.

SJC_RESP0

__IO uint32_t OCOTP_Type::SJC_RESP0

Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600

Definition at line 27770 of file MIMXRT1052.h.

SJC_RESP1

__IO uint32_t OCOTP_Type::SJC_RESP1

Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610

Definition at line 27772 of file MIMXRT1052.h.

SLAST [1/2]

__IO uint32_t DMA_Type::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

Definition at line 12013 of file MIMXRT1052.h.

SLAST [2/2]

__IO { ... } ::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

Definition at line 12013 of file MIMXRT1052.h.

SM

struct { ... } PWM_Type::SM[4]

SOFF [1/2]

__IO { ... } ::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

Definition at line 12006 of file MIMXRT1052.h.

SOFF [2/2]

__IO uint16_t DMA_Type::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

Definition at line 12006 of file MIMXRT1052.h.

SR [1/2]

__IO uint32_t GPT_Type::SR

GPT Status Register, offset: 0x8

Definition at line 19580 of file MIMXRT1052.h.

SR [2/2]

__IO uint32_t LPSPI_Type::SR

Status Register, offset: 0x14

Definition at line 26149 of file MIMXRT1052.h.

SRAMCR0

__IO uint32_t SEMC_Type::SRAMCR0

SRAM control register 0, offset: 0x70

Definition at line 34150 of file MIMXRT1052.h.

SRAMCR1

__IO uint32_t SEMC_Type::SRAMCR1

SRAM control register 1, offset: 0x74

Definition at line 34151 of file MIMXRT1052.h.

SRAMCR2

__IO uint32_t SEMC_Type::SRAMCR2

SRAM control register 2, offset: 0x78

Definition at line 34152 of file MIMXRT1052.h.

SRAMCR3

uint32_t SEMC_Type::SRAMCR3

SRAM control register 3, offset: 0x7C

Definition at line 34153 of file MIMXRT1052.h.

SRCD

__IO uint32_t SPDIF_Type::SRCD

CDText Control Register, offset: 0x4

Definition at line 36418 of file MIMXRT1052.h.

SRCSH

__I uint32_t SPDIF_Type::SRCSH

SPDIFRxCChannel_h Register, offset: 0x1C

Definition at line 36427 of file MIMXRT1052.h.

SRCSL

__I uint32_t SPDIF_Type::SRCSL

SPDIFRxCChannel_l Register, offset: 0x20

Definition at line 36428 of file MIMXRT1052.h.

SRDR

__I uint32_t LPI2C_Type::SRDR

Slave Receive Data Register, offset: 0x170

Definition at line 25134 of file MIMXRT1052.h.

SRFM

__I uint32_t SPDIF_Type::SRFM

FreqMeas Register, offset: 0x44

Definition at line 36436 of file MIMXRT1052.h.

SRK0

__IO uint32_t OCOTP_Type::SRK0

Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580

Definition at line 27754 of file MIMXRT1052.h.

SRK1

__IO uint32_t OCOTP_Type::SRK1

Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590

Definition at line 27756 of file MIMXRT1052.h.

SRK2

__IO uint32_t OCOTP_Type::SRK2

Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0

Definition at line 27758 of file MIMXRT1052.h.

SRK3

__IO uint32_t OCOTP_Type::SRK3

Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0

Definition at line 27760 of file MIMXRT1052.h.

SRK4

__IO uint32_t OCOTP_Type::SRK4

Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0

Definition at line 27762 of file MIMXRT1052.h.

SRK5

__IO uint32_t OCOTP_Type::SRK5

Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0

Definition at line 27764 of file MIMXRT1052.h.

SRK6

__IO uint32_t OCOTP_Type::SRK6

Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0

Definition at line 27766 of file MIMXRT1052.h.

SRK7

__IO uint32_t OCOTP_Type::SRK7

Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0

Definition at line 27768 of file MIMXRT1052.h.

SRK_REVOKE

__IO uint32_t OCOTP_Type::SRK_REVOKE

Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0

Definition at line 27798 of file MIMXRT1052.h.

SRL

__I uint32_t SPDIF_Type::SRL

SPDIFRxLeft Register, offset: 0x14

Definition at line 36425 of file MIMXRT1052.h.

SRPC

__IO uint32_t SPDIF_Type::SRPC

PhaseConfig Register, offset: 0x8

Definition at line 36419 of file MIMXRT1052.h.

SRQ

__I uint32_t SPDIF_Type::SRQ

QchannelRx Register, offset: 0x28

Definition at line 36430 of file MIMXRT1052.h.

SRR

__I uint32_t SPDIF_Type::SRR

SPDIFRxRight Register, offset: 0x18

Definition at line 36426 of file MIMXRT1052.h.

SRSR

__IO uint32_t SRC_Type::SRSR

SRC Reset Status Register, offset: 0x8

Definition at line 36904 of file MIMXRT1052.h.

SRU

__I uint32_t SPDIF_Type::SRU

UchannelRx Register, offset: 0x24

Definition at line 36429 of file MIMXRT1052.h.

SSR

__IO uint32_t LPI2C_Type::SSR

Slave Status Register, offset: 0x114

Definition at line 25120 of file MIMXRT1052.h.

SSRT

__O uint8_t DMA_Type::SSRT

Set START Bit Register, offset: 0x1D

Definition at line 11959 of file MIMXRT1052.h.

STAR

__IO uint32_t LPI2C_Type::STAR

Slave Transmit ACK Register, offset: 0x154

Definition at line 25130 of file MIMXRT1052.h.

STAT [1/4]

__IO uint32_t DCP_Type::STAT

DCP status register, offset: 0x10

Definition at line 10274 of file MIMXRT1052.h.

STAT [2/4]

__I uint32_t LCDIF_Type::STAT

LCD Interface Status Register, offset: 0x1B0

Definition at line 23553 of file MIMXRT1052.h.

STAT [3/4]

__IO uint32_t LPUART_Type::STAT

LPUART Status Register, offset: 0x14

Definition at line 26777 of file MIMXRT1052.h.

STAT [4/4]

__IO uint32_t PXP_Type::STAT

Status Register, offset: 0x10

Definition at line 32514 of file MIMXRT1052.h.

STAT_CLR [1/2]

__IO uint32_t DCP_Type::STAT_CLR

DCP status register, offset: 0x18

Definition at line 10276 of file MIMXRT1052.h.

STAT_CLR [2/2]

__IO uint32_t PXP_Type::STAT_CLR

Status Register, offset: 0x18

Definition at line 32516 of file MIMXRT1052.h.

STAT_SET [1/2]

__IO uint32_t DCP_Type::STAT_SET

DCP status register, offset: 0x14

Definition at line 10275 of file MIMXRT1052.h.

STAT_SET [2/2]

__IO uint32_t PXP_Type::STAT_SET

Status Register, offset: 0x14

Definition at line 32515 of file MIMXRT1052.h.

STAT_TOG [1/2]

__IO uint32_t DCP_Type::STAT_TOG

DCP status register, offset: 0x1C

Definition at line 10277 of file MIMXRT1052.h.

STAT_TOG [2/2]

__IO uint32_t PXP_Type::STAT_TOG

Status Register, offset: 0x1C

Definition at line 32517 of file MIMXRT1052.h.

STATUS [1/3]

__IO uint32_t BEE_Type::STATUS

Status Register, offset: 0x1C

Definition at line 3018 of file MIMXRT1052.h.

STATUS [2/3]

__I uint32_t TRNG_Type::STATUS

Status Register, offset: 0x3C

Definition at line 37920 of file MIMXRT1052.h.

STATUS [3/3]

__IO uint32_t USBPHY_Type::STATUS

USB PHY Status Register, offset: 0x40

Definition at line 40700 of file MIMXRT1052.h.

STC

__IO uint32_t SPDIF_Type::STC

SPDIFTxClk Register, offset: 0x50

Definition at line 36438 of file MIMXRT1052.h.

STCSCH

__IO uint32_t SPDIF_Type::STCSCH

SPDIFTxCChannelCons_h Register, offset: 0x34

Definition at line 36433 of file MIMXRT1052.h.

STCSCL

__IO uint32_t SPDIF_Type::STCSCL

SPDIFTxCChannelCons_l Register, offset: 0x38

Definition at line 36434 of file MIMXRT1052.h.

STDR

__O uint32_t LPI2C_Type::STDR

Slave Transmit Data Register, offset: 0x160

Definition at line 25132 of file MIMXRT1052.h.

STL

__O uint32_t SPDIF_Type::STL

SPDIFTxLeft Register, offset: 0x2C

Definition at line 36431 of file MIMXRT1052.h.

STR

__O uint32_t SPDIF_Type::STR

SPDIFTxRight Register, offset: 0x30

Definition at line 36432 of file MIMXRT1052.h.

STS [1/2]

__IO uint16_t PWM_Type::STS

Status Register, array offset: 0x24, array step: 0x60

Definition at line 30863 of file MIMXRT1052.h.

STS [2/2]

__IO { ... } ::STS

Status Register, array offset: 0x24, array step: 0x60

Definition at line 30863 of file MIMXRT1052.h.

STS0 [1/2]

__I uint32_t FLEXSPI_Type::STS0

Status Register 0, offset: 0xE0

Definition at line 18115 of file MIMXRT1052.h.

STS0 [2/2]

__I uint32_t SEMC_Type::STS0

Status register 0, offset: 0xC0

Definition at line 34165 of file MIMXRT1052.h.

STS1 [1/2]

__I uint32_t FLEXSPI_Type::STS1

Status Register 1, offset: 0xE4

Definition at line 18116 of file MIMXRT1052.h.

STS1 [2/2]

uint32_t SEMC_Type::STS1

Status register 1, offset: 0xC4

Definition at line 34166 of file MIMXRT1052.h.

STS10

uint32_t SEMC_Type::STS10

Status register 10, offset: 0xE8

Definition at line 34175 of file MIMXRT1052.h.

STS11

uint32_t SEMC_Type::STS11

Status register 11, offset: 0xEC

Definition at line 34176 of file MIMXRT1052.h.

STS12

__I uint32_t SEMC_Type::STS12

Status register 12, offset: 0xF0

Definition at line 34177 of file MIMXRT1052.h.

STS13

uint32_t SEMC_Type::STS13

Status register 13, offset: 0xF4

Definition at line 34178 of file MIMXRT1052.h.

STS14

uint32_t SEMC_Type::STS14

Status register 14, offset: 0xF8

Definition at line 34179 of file MIMXRT1052.h.

STS15

uint32_t SEMC_Type::STS15

Status register 15, offset: 0xFC

Definition at line 34180 of file MIMXRT1052.h.

STS2 [1/2]

__I uint32_t FLEXSPI_Type::STS2

Status Register 2, offset: 0xE8

Definition at line 18117 of file MIMXRT1052.h.

STS2 [2/2]

__I uint32_t SEMC_Type::STS2

Status register 2, offset: 0xC8

Definition at line 34167 of file MIMXRT1052.h.

STS3

uint32_t SEMC_Type::STS3

Status register 3, offset: 0xCC

Definition at line 34168 of file MIMXRT1052.h.

STS4

uint32_t SEMC_Type::STS4

Status register 4, offset: 0xD0

Definition at line 34169 of file MIMXRT1052.h.

STS5

uint32_t SEMC_Type::STS5

Status register 5, offset: 0xD4

Definition at line 34170 of file MIMXRT1052.h.

STS6

uint32_t SEMC_Type::STS6

Status register 6, offset: 0xD8

Definition at line 34171 of file MIMXRT1052.h.

STS7

uint32_t SEMC_Type::STS7

Status register 7, offset: 0xDC

Definition at line 34172 of file MIMXRT1052.h.

STS8

uint32_t SEMC_Type::STS8

Status register 8, offset: 0xE0

Definition at line 34173 of file MIMXRT1052.h.

STS9

uint32_t SEMC_Type::STS9

Status register 9, offset: 0xE4

Definition at line 34174 of file MIMXRT1052.h.

SW_GP1

__IO uint32_t OCOTP_Type::SW_GP1

Value of OTP Bank5 Word0 (SW GP1), offset: 0x680

Definition at line 27784 of file MIMXRT1052.h.

SW_GP20

__IO uint32_t OCOTP_Type::SW_GP20

Value of OTP Bank5 Word1 (SW GP2), offset: 0x690

Definition at line 27786 of file MIMXRT1052.h.

SW_GP21

__IO uint32_t OCOTP_Type::SW_GP21

Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0

Definition at line 27788 of file MIMXRT1052.h.

SW_GP22

__IO uint32_t OCOTP_Type::SW_GP22

Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0

Definition at line 27790 of file MIMXRT1052.h.

SW_GP23

__IO uint32_t OCOTP_Type::SW_GP23

Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0

Definition at line 27792 of file MIMXRT1052.h.

SW_MUX_CTL_PAD

__IO uint32_t IOMUXC_Type::SW_MUX_CTL_PAD[124]

SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4

Definition at line 20700 of file MIMXRT1052.h.

SW_MUX_CTL_PAD_PMIC_ON_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ

SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4

Definition at line 22797 of file MIMXRT1052.h.

SW_MUX_CTL_PAD_PMIC_STBY_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ

SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8

Definition at line 22798 of file MIMXRT1052.h.

SW_MUX_CTL_PAD_WAKEUP

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP

SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0

Definition at line 22796 of file MIMXRT1052.h.

SW_PAD_CTL_PAD

__IO uint32_t IOMUXC_Type::SW_PAD_CTL_PAD[124]

SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4

Definition at line 20701 of file MIMXRT1052.h.

SW_PAD_CTL_PAD_ONOFF

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF

SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14

Definition at line 22801 of file MIMXRT1052.h.

SW_PAD_CTL_PAD_PMIC_ON_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ

SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C

Definition at line 22803 of file MIMXRT1052.h.

SW_PAD_CTL_PAD_PMIC_STBY_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ

SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20

Definition at line 22804 of file MIMXRT1052.h.

SW_PAD_CTL_PAD_POR_B

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B

SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10

Definition at line 22800 of file MIMXRT1052.h.

SW_PAD_CTL_PAD_TEST_MODE

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE

SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC

Definition at line 22799 of file MIMXRT1052.h.

SW_PAD_CTL_PAD_WAKEUP

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP

SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18

Definition at line 22802 of file MIMXRT1052.h.

SW_STICKY

__IO uint32_t OCOTP_Type::SW_STICKY

Sticky bit Register, offset: 0x50

Definition at line 27711 of file MIMXRT1052.h.

SWCOUT

__IO uint16_t PWM_Type::SWCOUT

Software Controlled Output Register, offset: 0x184

Definition at line 30892 of file MIMXRT1052.h.

SYS_CTRL

__IO uint32_t USDHC_Type::SYS_CTRL

System Control, offset: 0x2C

Definition at line 42265 of file MIMXRT1052.h.

TACC

__IO uint32_t ENET_Type::TACC

Transmit Accelerator Function Configuration, offset: 0x1C0

Definition at line 15651 of file MIMXRT1052.h.

TAEM

__IO uint32_t ENET_Type::TAEM

Transmit FIFO Almost Empty Threshold, offset: 0x1A4

Definition at line 15646 of file MIMXRT1052.h.

TAFL

__IO uint32_t ENET_Type::TAFL

Transmit FIFO Almost Full Threshold, offset: 0x1A8

Definition at line 15647 of file MIMXRT1052.h.

TCCR [1/2]

__IO { ... } ::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

Definition at line 15721 of file MIMXRT1052.h.

TCCR [2/2]

__IO uint32_t ENET_Type::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

Definition at line 15721 of file MIMXRT1052.h.

TCD

struct { ... } DMA_Type::TCD[32]

TCM_CTRL

__IO uint32_t FLEXRAM_Type::TCM_CTRL

TCM CRTL Register, offset: 0x0

Definition at line 17942 of file MIMXRT1052.h.

TCR [1/2]

__IO uint32_t ENET_Type::TCR

Transmit Control Register, offset: 0xC4

Definition at line 15621 of file MIMXRT1052.h.

TCR [2/2]

__IO uint32_t LPSPI_Type::TCR

Transmit Command Register, offset: 0x60

Definition at line 26162 of file MIMXRT1052.h.

TCR1

__IO uint32_t I2S_Type::TCR1

SAI Transmit Configuration 1 Register, offset: 0xC

Definition at line 19871 of file MIMXRT1052.h.

TCR2

__IO uint32_t I2S_Type::TCR2

SAI Transmit Configuration 2 Register, offset: 0x10

Definition at line 19872 of file MIMXRT1052.h.

TCR3

__IO uint32_t I2S_Type::TCR3

SAI Transmit Configuration 3 Register, offset: 0x14

Definition at line 19873 of file MIMXRT1052.h.

TCR4

__IO uint32_t I2S_Type::TCR4

SAI Transmit Configuration 4 Register, offset: 0x18

Definition at line 19874 of file MIMXRT1052.h.

TCR5

__IO uint32_t I2S_Type::TCR5

SAI Transmit Configuration 5 Register, offset: 0x1C

Definition at line 19875 of file MIMXRT1052.h.

TCSR [1/3]

__IO { ... } ::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

Definition at line 15720 of file MIMXRT1052.h.

TCSR [2/3]

__IO uint32_t ENET_Type::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

Definition at line 15720 of file MIMXRT1052.h.

TCSR [3/3]

__IO uint32_t I2S_Type::TCSR

SAI Transmit Control Register, offset: 0x8

Definition at line 19870 of file MIMXRT1052.h.

TCTRL [1/4]

__IO uint32_t PIT_Type::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

Definition at line 28518 of file MIMXRT1052.h.

TCTRL [2/4]

__IO { ... } ::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

Definition at line 28518 of file MIMXRT1052.h.

TCTRL [3/4]

__IO uint16_t PWM_Type::TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

Definition at line 30866 of file MIMXRT1052.h.

TCTRL [4/4]

__IO { ... } ::TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

Definition at line 30866 of file MIMXRT1052.h.

TDAR

__IO uint32_t ENET_Type::TDAR

Transmit Descriptor Active Register, offset: 0x14

Definition at line 15610 of file MIMXRT1052.h.

TDR [1/2]

__O uint32_t I2S_Type::TDR[4]

SAI Transmit Data Register, array offset: 0x20, array step: 0x4

Definition at line 19876 of file MIMXRT1052.h.

TDR [2/2]

__O uint32_t LPSPI_Type::TDR

Transmit Data Register, offset: 0x64

Definition at line 26163 of file MIMXRT1052.h.

TDSR

__IO uint32_t ENET_Type::TDSR

Transmit Buffer Descriptor Ring Start Register, offset: 0x184

Definition at line 15638 of file MIMXRT1052.h.

TEMPSENSE0

__IO uint32_t TEMPMON_Type::TEMPSENSE0

Tempsensor Control Register 0, offset: 0x180

Definition at line 37131 of file MIMXRT1052.h.

TEMPSENSE0_CLR

__IO uint32_t TEMPMON_Type::TEMPSENSE0_CLR

Tempsensor Control Register 0, offset: 0x188

Definition at line 37133 of file MIMXRT1052.h.

TEMPSENSE0_SET

__IO uint32_t TEMPMON_Type::TEMPSENSE0_SET

Tempsensor Control Register 0, offset: 0x184

Definition at line 37132 of file MIMXRT1052.h.

TEMPSENSE0_TOG

__IO uint32_t TEMPMON_Type::TEMPSENSE0_TOG

Tempsensor Control Register 0, offset: 0x18C

Definition at line 37134 of file MIMXRT1052.h.

TEMPSENSE1

__IO uint32_t TEMPMON_Type::TEMPSENSE1

Tempsensor Control Register 1, offset: 0x190

Definition at line 37135 of file MIMXRT1052.h.

TEMPSENSE1_CLR

__IO uint32_t TEMPMON_Type::TEMPSENSE1_CLR

Tempsensor Control Register 1, offset: 0x198

Definition at line 37137 of file MIMXRT1052.h.

TEMPSENSE1_SET

__IO uint32_t TEMPMON_Type::TEMPSENSE1_SET

Tempsensor Control Register 1, offset: 0x194

Definition at line 37136 of file MIMXRT1052.h.

TEMPSENSE1_TOG

__IO uint32_t TEMPMON_Type::TEMPSENSE1_TOG

Tempsensor Control Register 1, offset: 0x19C

Definition at line 37138 of file MIMXRT1052.h.

TEMPSENSE2

__IO uint32_t TEMPMON_Type::TEMPSENSE2

Tempsensor Control Register 2, offset: 0x290

Definition at line 37140 of file MIMXRT1052.h.

TEMPSENSE2_CLR

__IO uint32_t TEMPMON_Type::TEMPSENSE2_CLR

Tempsensor Control Register 2, offset: 0x298

Definition at line 37142 of file MIMXRT1052.h.

TEMPSENSE2_SET

__IO uint32_t TEMPMON_Type::TEMPSENSE2_SET

Tempsensor Control Register 2, offset: 0x294

Definition at line 37141 of file MIMXRT1052.h.

TEMPSENSE2_TOG

__IO uint32_t TEMPMON_Type::TEMPSENSE2_TOG

Tempsensor Control Register 2, offset: 0x29C

Definition at line 37143 of file MIMXRT1052.h.

TFDR

__O uint32_t FLEXSPI_Type::TFDR[32]

IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4

Definition at line 18123 of file MIMXRT1052.h.

TFLG [1/2]

__IO uint32_t PIT_Type::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

Definition at line 28519 of file MIMXRT1052.h.

TFLG [2/2]

__IO { ... } ::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

Definition at line 28519 of file MIMXRT1052.h.

TFR

__I uint32_t I2S_Type::TFR[4]

SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4

Definition at line 19878 of file MIMXRT1052.h.

TFWR

__IO uint32_t ENET_Type::TFWR

Transmit FIFO Watermark Register, offset: 0x144

Definition at line 15635 of file MIMXRT1052.h.

TGSR

__IO uint32_t ENET_Type::TGSR

Timer Global Status Register, offset: 0x604

Definition at line 15718 of file MIMXRT1052.h.

THRES

__IO uint32_t LCDIF_Type::THRES

LCDIF Threshold Register, offset: 0x200

Definition at line 23555 of file MIMXRT1052.h.

TIMCFG

__IO uint32_t FLEXIO_Type::TIMCFG[4]

Timer Configuration N Register, array offset: 0x480, array step: 0x4

Definition at line 17397 of file MIMXRT1052.h.

TIMCMP

__IO uint32_t FLEXIO_Type::TIMCMP[4]

Timer Compare N Register, array offset: 0x500, array step: 0x4

Definition at line 17399 of file MIMXRT1052.h.

TIMCTL

__IO uint32_t FLEXIO_Type::TIMCTL[4]

Timer Control N Register, array offset: 0x400, array step: 0x4

Definition at line 17395 of file MIMXRT1052.h.

TIMER

__IO uint32_t CAN_Type::TIMER

Free Running Timer Register, offset: 0x8

Definition at line 3315 of file MIMXRT1052.h.

TIMIEN

__IO uint32_t FLEXIO_Type::TIMIEN

Timer Interrupt Enable Register, offset: 0x28

Definition at line 17377 of file MIMXRT1052.h.

TIMING

__IO uint32_t OCOTP_Type::TIMING

OTP Controller Timing Register, offset: 0x10

Definition at line 27703 of file MIMXRT1052.h.

TIMING2

__IO uint32_t OCOTP_Type::TIMING2

OTP Controller Timing Register 2, offset: 0x100

Definition at line 27720 of file MIMXRT1052.h.

TIMSTAT

__IO uint32_t FLEXIO_Type::TIMSTAT

Timer Status Register, offset: 0x18

Definition at line 17373 of file MIMXRT1052.h.

TIPG

__IO uint32_t ENET_Type::TIPG

Transmit Inter-Packet Gap, offset: 0x1AC

Definition at line 15648 of file MIMXRT1052.h.

TMR

__IO uint32_t I2S_Type::TMR

SAI Transmit Mask Register, offset: 0x60

Definition at line 19880 of file MIMXRT1052.h.

TOTSAM [1/2]

__I { ... } ::TOTSAM

Total Samples Register, offset: 0x14

Definition at line 37885 of file MIMXRT1052.h.

TOTSAM [2/2]

__I uint32_t TRNG_Type::TOTSAM

Total Samples Register, offset: 0x14

Definition at line 37885 of file MIMXRT1052.h.

TOVAL

__IO uint32_t RTWDOG_Type::TOVAL

Watchdog Timeout Value Register, offset: 0x8

Definition at line 33930 of file MIMXRT1052.h.

TRANSFER_COUNT

__IO uint32_t LCDIF_Type::TRANSFER_COUNT

LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30

Definition at line 23531 of file MIMXRT1052.h.

TRIG

struct { ... } ADC_ETC_Type::TRIG[8]

TRIGn_CHAIN_1_0 [1/2]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_1_0

ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28

Definition at line 1625 of file MIMXRT1052.h.

TRIGn_CHAIN_1_0 [2/2]

__IO { ... } ::TRIGn_CHAIN_1_0

ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28

Definition at line 1625 of file MIMXRT1052.h.

TRIGn_CHAIN_3_2 [1/2]

__IO { ... } ::TRIGn_CHAIN_3_2

ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28

Definition at line 1626 of file MIMXRT1052.h.

TRIGn_CHAIN_3_2 [2/2]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_3_2

ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28

Definition at line 1626 of file MIMXRT1052.h.

TRIGn_CHAIN_5_4 [1/2]

__IO { ... } ::TRIGn_CHAIN_5_4

ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28

Definition at line 1627 of file MIMXRT1052.h.

TRIGn_CHAIN_5_4 [2/2]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_5_4

ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28

Definition at line 1627 of file MIMXRT1052.h.

TRIGn_CHAIN_7_6 [1/2]

__IO { ... } ::TRIGn_CHAIN_7_6

ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28

Definition at line 1628 of file MIMXRT1052.h.

TRIGn_CHAIN_7_6 [2/2]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_7_6

ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28

Definition at line 1628 of file MIMXRT1052.h.

TRIGn_COUNTER [1/2]

__IO { ... } ::TRIGn_COUNTER

ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28

Definition at line 1624 of file MIMXRT1052.h.

TRIGn_COUNTER [2/2]

__IO uint32_t ADC_ETC_Type::TRIGn_COUNTER

ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28

Definition at line 1624 of file MIMXRT1052.h.

TRIGn_CTRL [1/2]

__IO { ... } ::TRIGn_CTRL

ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28

Definition at line 1623 of file MIMXRT1052.h.

TRIGn_CTRL [2/2]

__IO uint32_t ADC_ETC_Type::TRIGn_CTRL

ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28

Definition at line 1623 of file MIMXRT1052.h.

TRIGn_RESULT_1_0 [1/2]

__I { ... } ::TRIGn_RESULT_1_0

ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28

Definition at line 1629 of file MIMXRT1052.h.

TRIGn_RESULT_1_0 [2/2]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_1_0

ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28

Definition at line 1629 of file MIMXRT1052.h.

TRIGn_RESULT_3_2 [1/2]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_3_2

ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28

Definition at line 1630 of file MIMXRT1052.h.

TRIGn_RESULT_3_2 [2/2]

__I { ... } ::TRIGn_RESULT_3_2

ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28

Definition at line 1630 of file MIMXRT1052.h.

TRIGn_RESULT_5_4 [1/2]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_5_4

ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28

Definition at line 1631 of file MIMXRT1052.h.

TRIGn_RESULT_5_4 [2/2]

__I { ... } ::TRIGn_RESULT_5_4

ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28

Definition at line 1631 of file MIMXRT1052.h.

TRIGn_RESULT_7_6 [1/2]

__I { ... } ::TRIGn_RESULT_7_6

ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28

Definition at line 1632 of file MIMXRT1052.h.

TRIGn_RESULT_7_6 [2/2]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_7_6

ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28

Definition at line 1632 of file MIMXRT1052.h.

TSEM

__IO uint32_t ENET_Type::TSEM

Transmit FIFO Section Empty Threshold, offset: 0x1A0

Definition at line 15645 of file MIMXRT1052.h.

TST

__IO uint16_t ENC_Type::TST

Test Register, offset: 0x1C

Definition at line 15153 of file MIMXRT1052.h.

TUNING_CTRL

__IO uint32_t USDHC_Type::TUNING_CTRL

Tuning Control Register, offset: 0xCC

Definition at line 42285 of file MIMXRT1052.h.

TX

__IO uint32_t USBPHY_Type::TX

USB PHY Transmitter Control Register, offset: 0x10

Definition at line 40688 of file MIMXRT1052.h.

TX_CLR

__IO uint32_t USBPHY_Type::TX_CLR

USB PHY Transmitter Control Register, offset: 0x18

Definition at line 40690 of file MIMXRT1052.h.

TX_SET

__IO uint32_t USBPHY_Type::TX_SET

USB PHY Transmitter Control Register, offset: 0x14

Definition at line 40689 of file MIMXRT1052.h.

TX_TOG

__IO uint32_t USBPHY_Type::TX_TOG

USB PHY Transmitter Control Register, offset: 0x1C

Definition at line 40691 of file MIMXRT1052.h.

TXFILLTUNING

__IO uint32_t USB_Type::TXFILLTUNING

TX FIFO Fill Tuning, offset: 0x164

Definition at line 39032 of file MIMXRT1052.h.

TXIC

__IO uint32_t ENET_Type::TXIC

Transmit Interrupt Coalescing Register, offset: 0xF0

Definition at line 15626 of file MIMXRT1052.h.

UCOMP

__IO uint16_t ENC_Type::UCOMP

Upper Position Compare Register, offset: 0x24

Definition at line 15157 of file MIMXRT1052.h.

UINIT

__IO uint16_t ENC_Type::UINIT

Upper Initialization Register, offset: 0x16

Definition at line 15150 of file MIMXRT1052.h.

UMOD

__IO uint16_t ENC_Type::UMOD

Upper Modulus Register, offset: 0x20

Definition at line 15155 of file MIMXRT1052.h.

UPOS

__IO uint16_t ENC_Type::UPOS

Upper Position Counter Register, offset: 0xE

Definition at line 15146 of file MIMXRT1052.h.

UPOSH

__I uint16_t ENC_Type::UPOSH

Upper Position Hold Register, offset: 0x12

Definition at line 15148 of file MIMXRT1052.h.

USB_OTGn_CTRL

__IO uint32_t USBNC_Type::USB_OTGn_CTRL

USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800

Definition at line 40549 of file MIMXRT1052.h.

USB_OTGn_PHY_CTRL_0

__IO uint32_t USBNC_Type::USB_OTGn_PHY_CTRL_0

OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818

Definition at line 40551 of file MIMXRT1052.h.

USBCMD

__IO uint32_t USB_Type::USBCMD

USB Command Register, offset: 0x140

Definition at line 39017 of file MIMXRT1052.h.

USBINTR

__IO uint32_t USB_Type::USBINTR

Interrupt Enable Register, offset: 0x148

Definition at line 39019 of file MIMXRT1052.h.

USBMODE

__IO uint32_t USB_Type::USBMODE

USB Device Mode, offset: 0x1A8

Definition at line 39040 of file MIMXRT1052.h.

USBSTS

__IO uint32_t USB_Type::USBSTS

USB Status Register, offset: 0x144

Definition at line 39018 of file MIMXRT1052.h.

VAL0 [1/2]

__IO uint16_t PWM_Type::VAL0

Value Register 0, array offset: 0xA, array step: 0x60

Definition at line 30850 of file MIMXRT1052.h.

VAL0 [2/2]

__IO { ... } ::VAL0

Value Register 0, array offset: 0xA, array step: 0x60

Definition at line 30850 of file MIMXRT1052.h.

VAL1 [1/2]

__IO { ... } ::VAL1

Value Register 1, array offset: 0xE, array step: 0x60

Definition at line 30852 of file MIMXRT1052.h.

VAL1 [2/2]

__IO uint16_t PWM_Type::VAL1

Value Register 1, array offset: 0xE, array step: 0x60

Definition at line 30852 of file MIMXRT1052.h.

VAL2 [1/2]

__IO { ... } ::VAL2

Value Register 2, array offset: 0x12, array step: 0x60

Definition at line 30854 of file MIMXRT1052.h.

VAL2 [2/2]

__IO uint16_t PWM_Type::VAL2

Value Register 2, array offset: 0x12, array step: 0x60

Definition at line 30854 of file MIMXRT1052.h.

VAL3 [1/2]

__IO uint16_t PWM_Type::VAL3

Value Register 3, array offset: 0x16, array step: 0x60

Definition at line 30856 of file MIMXRT1052.h.

VAL3 [2/2]

__IO { ... } ::VAL3

Value Register 3, array offset: 0x16, array step: 0x60

Definition at line 30856 of file MIMXRT1052.h.

VAL4 [1/2]

__IO uint16_t PWM_Type::VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

Definition at line 30858 of file MIMXRT1052.h.

VAL4 [2/2]

__IO { ... } ::VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

Definition at line 30858 of file MIMXRT1052.h.

VAL5 [1/2]

__IO uint16_t PWM_Type::VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

Definition at line 30860 of file MIMXRT1052.h.

VAL5 [2/2]

__IO { ... } ::VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

Definition at line 30860 of file MIMXRT1052.h.

VBUS_DETECT [1/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT

USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60

Definition at line 41801 of file MIMXRT1052.h.

VBUS_DETECT [2/2]

__IO { ... } ::VBUS_DETECT

USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60

Definition at line 41801 of file MIMXRT1052.h.

VBUS_DETECT_CLR [1/2]

__IO { ... } ::VBUS_DETECT_CLR

USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60

Definition at line 41803 of file MIMXRT1052.h.

VBUS_DETECT_CLR [2/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT_CLR

USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60

Definition at line 41803 of file MIMXRT1052.h.

VBUS_DETECT_SET [1/2]

__IO { ... } ::VBUS_DETECT_SET

USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60

Definition at line 41802 of file MIMXRT1052.h.

VBUS_DETECT_SET [2/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT_SET

USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60

Definition at line 41802 of file MIMXRT1052.h.

VBUS_DETECT_STAT [1/2]

__I { ... } ::VBUS_DETECT_STAT

USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60

Definition at line 41809 of file MIMXRT1052.h.

VBUS_DETECT_STAT [2/2]

__I uint32_t USB_ANALOG_Type::VBUS_DETECT_STAT

USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60

Definition at line 41809 of file MIMXRT1052.h.

VBUS_DETECT_TOG [1/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT_TOG

USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60

Definition at line 41804 of file MIMXRT1052.h.

VBUS_DETECT_TOG [2/2]

__IO { ... } ::VBUS_DETECT_TOG

USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60

Definition at line 41804 of file MIMXRT1052.h.

VDCTRL0

__IO uint32_t LCDIF_Type::VDCTRL0

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70

Definition at line 23537 of file MIMXRT1052.h.

VDCTRL0_CLR

__IO uint32_t LCDIF_Type::VDCTRL0_CLR

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78

Definition at line 23539 of file MIMXRT1052.h.

VDCTRL0_SET

__IO uint32_t LCDIF_Type::VDCTRL0_SET

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74

Definition at line 23538 of file MIMXRT1052.h.

VDCTRL0_TOG

__IO uint32_t LCDIF_Type::VDCTRL0_TOG

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C

Definition at line 23540 of file MIMXRT1052.h.

VDCTRL1

__IO uint32_t LCDIF_Type::VDCTRL1

LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80

Definition at line 23541 of file MIMXRT1052.h.

VDCTRL2

__IO uint32_t LCDIF_Type::VDCTRL2

LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90

Definition at line 23543 of file MIMXRT1052.h.

VDCTRL3

__IO uint32_t LCDIF_Type::VDCTRL3

LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0

Definition at line 23545 of file MIMXRT1052.h.

VDCTRL4

__IO uint32_t LCDIF_Type::VDCTRL4

LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0

Definition at line 23547 of file MIMXRT1052.h.

VEND_SPEC

__IO uint32_t USDHC_Type::VEND_SPEC

Vendor Specific Register, offset: 0xC0

Definition at line 42282 of file MIMXRT1052.h.

VEND_SPEC2

__IO uint32_t USDHC_Type::VEND_SPEC2

Vendor Specific 2 Register, offset: 0xC8

Definition at line 42284 of file MIMXRT1052.h.

VERID [1/5]

__I uint32_t FLEXIO_Type::VERID

Version ID Register, offset: 0x0

Definition at line 17367 of file MIMXRT1052.h.

VERID [2/5]

__I uint32_t I2S_Type::VERID

Version ID Register, offset: 0x0

Definition at line 19868 of file MIMXRT1052.h.

VERID [3/5]

__I uint32_t LPI2C_Type::VERID

Version ID Register, offset: 0x0

Definition at line 25095 of file MIMXRT1052.h.

VERID [4/5]

__I uint32_t LPSPI_Type::VERID

Version ID Register, offset: 0x0

Definition at line 26145 of file MIMXRT1052.h.

VERID [5/5]

__I uint32_t LPUART_Type::VERID

Version ID Register, offset: 0x0

Definition at line 26772 of file MIMXRT1052.h.

VERSION [1/3]

__I uint32_t DCP_Type::VERSION

DCP version register, offset: 0x430

Definition at line 10361 of file MIMXRT1052.h.

VERSION [2/3]

__I uint32_t OCOTP_Type::VERSION

OTP Controller Version Register, offset: 0x90

Definition at line 27718 of file MIMXRT1052.h.

VERSION [3/3]

__I uint32_t USBPHY_Type::VERSION

UTMI RTL Version, offset: 0x80

Definition at line 40712 of file MIMXRT1052.h.

VID1

__I uint32_t TRNG_Type::VID1

Version ID Register (MS), offset: 0xF0

Definition at line 37935 of file MIMXRT1052.h.

VID2

__I uint32_t TRNG_Type::VID2

Version ID Register (LS), offset: 0xF4

Definition at line 37936 of file MIMXRT1052.h.

WATER

__IO uint32_t LPUART_Type::WATER

LPUART Watermark Register, offset: 0x2C

Definition at line 26783 of file MIMXRT1052.h.

WCR

__IO uint16_t WDOG_Type::WCR

Watchdog Control Register, offset: 0x0

Definition at line 43937 of file MIMXRT1052.h.

WICR

__IO uint16_t WDOG_Type::WICR

Watchdog Interrupt Control Register, offset: 0x6

Definition at line 43940 of file MIMXRT1052.h.

WIN

__IO uint32_t RTWDOG_Type::WIN

Watchdog Window Register, offset: 0xC

Definition at line 33931 of file MIMXRT1052.h.

WMCR

__IO uint16_t WDOG_Type::WMCR

Watchdog Miscellaneous Control Register, offset: 0x8

Definition at line 43941 of file MIMXRT1052.h.

WORD0 [1/2]

__IO uint32_t CAN_Type::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10

Definition at line 3339 of file MIMXRT1052.h.

WORD0 [2/2]

__IO { ... } ::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10

Definition at line 3339 of file MIMXRT1052.h.

WORD1 [1/2]

__IO { ... } ::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10

Definition at line 3340 of file MIMXRT1052.h.

WORD1 [2/2]

__IO uint32_t CAN_Type::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10

Definition at line 3340 of file MIMXRT1052.h.

WRSR

__I uint16_t WDOG_Type::WRSR

Watchdog Reset Status Register, offset: 0x4

Definition at line 43939 of file MIMXRT1052.h.

WSR

__IO uint16_t WDOG_Type::WSR

Watchdog Service Register, offset: 0x2

Definition at line 43938 of file MIMXRT1052.h.

WTMK_LVL

__IO uint32_t USDHC_Type::WTMK_LVL

Watermark Level, offset: 0x44

Definition at line 42271 of file MIMXRT1052.h.

WTR

__IO uint16_t ENC_Type::WTR

Watchdog Timeout Register, offset: 0x4

Definition at line 15141 of file MIMXRT1052.h.