Macros
CSU Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » CSU Peripheral Access Layer
Collaboration diagram for CSU Register Masks:

Macros

#define CSU_CSL_COUNT   (32U)
 

CSL - Config security level register

#define CSU_CSL_SUR_S2_MASK   (0x1U)
 
#define CSU_CSL_SUR_S2_SHIFT   (0U)
 
#define CSU_CSL_SUR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
 
#define CSU_CSL_SSR_S2_MASK   (0x2U)
 
#define CSU_CSL_SSR_S2_SHIFT   (1U)
 
#define CSU_CSL_SSR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
 
#define CSU_CSL_NUR_S2_MASK   (0x4U)
 
#define CSU_CSL_NUR_S2_SHIFT   (2U)
 
#define CSU_CSL_NUR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
 
#define CSU_CSL_NSR_S2_MASK   (0x8U)
 
#define CSU_CSL_NSR_S2_SHIFT   (3U)
 
#define CSU_CSL_NSR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
 
#define CSU_CSL_SUW_S2_MASK   (0x10U)
 
#define CSU_CSL_SUW_S2_SHIFT   (4U)
 
#define CSU_CSL_SUW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
 
#define CSU_CSL_SSW_S2_MASK   (0x20U)
 
#define CSU_CSL_SSW_S2_SHIFT   (5U)
 
#define CSU_CSL_SSW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
 
#define CSU_CSL_NUW_S2_MASK   (0x40U)
 
#define CSU_CSL_NUW_S2_SHIFT   (6U)
 
#define CSU_CSL_NUW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
 
#define CSU_CSL_NSW_S2_MASK   (0x80U)
 
#define CSU_CSL_NSW_S2_SHIFT   (7U)
 
#define CSU_CSL_NSW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
 
#define CSU_CSL_LOCK_S2_MASK   (0x100U)
 
#define CSU_CSL_LOCK_S2_SHIFT   (8U)
 
#define CSU_CSL_LOCK_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
 
#define CSU_CSL_SUR_S1_MASK   (0x10000U)
 
#define CSU_CSL_SUR_S1_SHIFT   (16U)
 
#define CSU_CSL_SUR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
 
#define CSU_CSL_SSR_S1_MASK   (0x20000U)
 
#define CSU_CSL_SSR_S1_SHIFT   (17U)
 
#define CSU_CSL_SSR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
 
#define CSU_CSL_NUR_S1_MASK   (0x40000U)
 
#define CSU_CSL_NUR_S1_SHIFT   (18U)
 
#define CSU_CSL_NUR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
 
#define CSU_CSL_NSR_S1_MASK   (0x80000U)
 
#define CSU_CSL_NSR_S1_SHIFT   (19U)
 
#define CSU_CSL_NSR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
 
#define CSU_CSL_SUW_S1_MASK   (0x100000U)
 
#define CSU_CSL_SUW_S1_SHIFT   (20U)
 
#define CSU_CSL_SUW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
 
#define CSU_CSL_SSW_S1_MASK   (0x200000U)
 
#define CSU_CSL_SSW_S1_SHIFT   (21U)
 
#define CSU_CSL_SSW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
 
#define CSU_CSL_NUW_S1_MASK   (0x400000U)
 
#define CSU_CSL_NUW_S1_SHIFT   (22U)
 
#define CSU_CSL_NUW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
 
#define CSU_CSL_NSW_S1_MASK   (0x800000U)
 
#define CSU_CSL_NSW_S1_SHIFT   (23U)
 
#define CSU_CSL_NSW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
 
#define CSU_CSL_LOCK_S1_MASK   (0x1000000U)
 
#define CSU_CSL_LOCK_S1_SHIFT   (24U)
 
#define CSU_CSL_LOCK_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
 

HP0 - HP0 register

#define CSU_HP0_HP_DMA_MASK   (0x4U)
 
#define CSU_HP0_HP_DMA_SHIFT   (2U)
 
#define CSU_HP0_HP_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
 
#define CSU_HP0_L_DMA_MASK   (0x8U)
 
#define CSU_HP0_L_DMA_SHIFT   (3U)
 
#define CSU_HP0_L_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
 
#define CSU_HP0_HP_LCDIF_MASK   (0x10U)
 
#define CSU_HP0_HP_LCDIF_SHIFT   (4U)
 
#define CSU_HP0_HP_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
 
#define CSU_HP0_L_LCDIF_MASK   (0x20U)
 
#define CSU_HP0_L_LCDIF_SHIFT   (5U)
 
#define CSU_HP0_L_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
 
#define CSU_HP0_HP_CSI_MASK   (0x40U)
 
#define CSU_HP0_HP_CSI_SHIFT   (6U)
 
#define CSU_HP0_HP_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
 
#define CSU_HP0_L_CSI_MASK   (0x80U)
 
#define CSU_HP0_L_CSI_SHIFT   (7U)
 
#define CSU_HP0_L_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
 
#define CSU_HP0_HP_PXP_MASK   (0x100U)
 
#define CSU_HP0_HP_PXP_SHIFT   (8U)
 
#define CSU_HP0_HP_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
 
#define CSU_HP0_L_PXP_MASK   (0x200U)
 
#define CSU_HP0_L_PXP_SHIFT   (9U)
 
#define CSU_HP0_L_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
 
#define CSU_HP0_HP_DCP_MASK   (0x400U)
 
#define CSU_HP0_HP_DCP_SHIFT   (10U)
 
#define CSU_HP0_HP_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
 
#define CSU_HP0_L_DCP_MASK   (0x800U)
 
#define CSU_HP0_L_DCP_SHIFT   (11U)
 
#define CSU_HP0_L_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
 
#define CSU_HP0_HP_ENET_MASK   (0x4000U)
 
#define CSU_HP0_HP_ENET_SHIFT   (14U)
 
#define CSU_HP0_HP_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
 
#define CSU_HP0_L_ENET_MASK   (0x8000U)
 
#define CSU_HP0_L_ENET_SHIFT   (15U)
 
#define CSU_HP0_L_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
 
#define CSU_HP0_HP_USDHC1_MASK   (0x10000U)
 
#define CSU_HP0_HP_USDHC1_SHIFT   (16U)
 
#define CSU_HP0_HP_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
 
#define CSU_HP0_L_USDHC1_MASK   (0x20000U)
 
#define CSU_HP0_L_USDHC1_SHIFT   (17U)
 
#define CSU_HP0_L_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
 
#define CSU_HP0_HP_USDHC2_MASK   (0x40000U)
 
#define CSU_HP0_HP_USDHC2_SHIFT   (18U)
 
#define CSU_HP0_HP_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
 
#define CSU_HP0_L_USDHC2_MASK   (0x80000U)
 
#define CSU_HP0_L_USDHC2_SHIFT   (19U)
 
#define CSU_HP0_L_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
 
#define CSU_HP0_HP_TPSMP_MASK   (0x100000U)
 
#define CSU_HP0_HP_TPSMP_SHIFT   (20U)
 
#define CSU_HP0_HP_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
 
#define CSU_HP0_L_TPSMP_MASK   (0x200000U)
 
#define CSU_HP0_L_TPSMP_SHIFT   (21U)
 
#define CSU_HP0_L_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
 
#define CSU_HP0_HP_USB_MASK   (0x400000U)
 
#define CSU_HP0_HP_USB_SHIFT   (22U)
 
#define CSU_HP0_HP_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
 
#define CSU_HP0_L_USB_MASK   (0x800000U)
 
#define CSU_HP0_L_USB_SHIFT   (23U)
 
#define CSU_HP0_L_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
 

SA - Secure access register

#define CSU_SA_NSA_DMA_MASK   (0x4U)
 
#define CSU_SA_NSA_DMA_SHIFT   (2U)
 
#define CSU_SA_NSA_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
 
#define CSU_SA_L_DMA_MASK   (0x8U)
 
#define CSU_SA_L_DMA_SHIFT   (3U)
 
#define CSU_SA_L_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
 
#define CSU_SA_NSA_LCDIF_MASK   (0x10U)
 
#define CSU_SA_NSA_LCDIF_SHIFT   (4U)
 
#define CSU_SA_NSA_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
 
#define CSU_SA_L_LCDIF_MASK   (0x20U)
 
#define CSU_SA_L_LCDIF_SHIFT   (5U)
 
#define CSU_SA_L_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
 
#define CSU_SA_NSA_CSI_MASK   (0x40U)
 
#define CSU_SA_NSA_CSI_SHIFT   (6U)
 
#define CSU_SA_NSA_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
 
#define CSU_SA_L_CSI_MASK   (0x80U)
 
#define CSU_SA_L_CSI_SHIFT   (7U)
 
#define CSU_SA_L_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
 
#define CSU_SA_NSA_PXP_MASK   (0x100U)
 
#define CSU_SA_NSA_PXP_SHIFT   (8U)
 
#define CSU_SA_NSA_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
 
#define CSU_SA_L_PXP_MASK   (0x200U)
 
#define CSU_SA_L_PXP_SHIFT   (9U)
 
#define CSU_SA_L_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
 
#define CSU_SA_NSA_DCP_MASK   (0x400U)
 
#define CSU_SA_NSA_DCP_SHIFT   (10U)
 
#define CSU_SA_NSA_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
 
#define CSU_SA_L_DCP_MASK   (0x800U)
 
#define CSU_SA_L_DCP_SHIFT   (11U)
 
#define CSU_SA_L_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
 
#define CSU_SA_NSA_ENET_MASK   (0x4000U)
 
#define CSU_SA_NSA_ENET_SHIFT   (14U)
 
#define CSU_SA_NSA_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
 
#define CSU_SA_L_ENET_MASK   (0x8000U)
 
#define CSU_SA_L_ENET_SHIFT   (15U)
 
#define CSU_SA_L_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
 
#define CSU_SA_NSA_USDHC1_MASK   (0x10000U)
 
#define CSU_SA_NSA_USDHC1_SHIFT   (16U)
 
#define CSU_SA_NSA_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
 
#define CSU_SA_L_USDHC1_MASK   (0x20000U)
 
#define CSU_SA_L_USDHC1_SHIFT   (17U)
 
#define CSU_SA_L_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
 
#define CSU_SA_NSA_USDHC2_MASK   (0x40000U)
 
#define CSU_SA_NSA_USDHC2_SHIFT   (18U)
 
#define CSU_SA_NSA_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
 
#define CSU_SA_L_USDHC2_MASK   (0x80000U)
 
#define CSU_SA_L_USDHC2_SHIFT   (19U)
 
#define CSU_SA_L_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
 
#define CSU_SA_NSA_TPSMP_MASK   (0x100000U)
 
#define CSU_SA_NSA_TPSMP_SHIFT   (20U)
 
#define CSU_SA_NSA_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
 
#define CSU_SA_L_TPSMP_MASK   (0x200000U)
 
#define CSU_SA_L_TPSMP_SHIFT   (21U)
 
#define CSU_SA_L_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
 
#define CSU_SA_NSA_USB_MASK   (0x400000U)
 
#define CSU_SA_NSA_USB_SHIFT   (22U)
 
#define CSU_SA_NSA_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
 
#define CSU_SA_L_USB_MASK   (0x800000U)
 
#define CSU_SA_L_USB_SHIFT   (23U)
 
#define CSU_SA_L_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
 

HPCONTROL0 - HPCONTROL0 register

#define CSU_HPCONTROL0_HPC_DMA_MASK   (0x4U)
 
#define CSU_HPCONTROL0_HPC_DMA_SHIFT   (2U)
 
#define CSU_HPCONTROL0_HPC_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
 
#define CSU_HPCONTROL0_L_DMA_MASK   (0x8U)
 
#define CSU_HPCONTROL0_L_DMA_SHIFT   (3U)
 
#define CSU_HPCONTROL0_L_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
 
#define CSU_HPCONTROL0_HPC_LCDIF_MASK   (0x10U)
 
#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT   (4U)
 
#define CSU_HPCONTROL0_HPC_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
 
#define CSU_HPCONTROL0_L_LCDIF_MASK   (0x20U)
 
#define CSU_HPCONTROL0_L_LCDIF_SHIFT   (5U)
 
#define CSU_HPCONTROL0_L_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
 
#define CSU_HPCONTROL0_HPC_CSI_MASK   (0x40U)
 
#define CSU_HPCONTROL0_HPC_CSI_SHIFT   (6U)
 
#define CSU_HPCONTROL0_HPC_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
 
#define CSU_HPCONTROL0_L_CSI_MASK   (0x80U)
 
#define CSU_HPCONTROL0_L_CSI_SHIFT   (7U)
 
#define CSU_HPCONTROL0_L_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
 
#define CSU_HPCONTROL0_HPC_PXP_MASK   (0x100U)
 
#define CSU_HPCONTROL0_HPC_PXP_SHIFT   (8U)
 
#define CSU_HPCONTROL0_HPC_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
 
#define CSU_HPCONTROL0_L_PXP_MASK   (0x200U)
 
#define CSU_HPCONTROL0_L_PXP_SHIFT   (9U)
 
#define CSU_HPCONTROL0_L_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
 
#define CSU_HPCONTROL0_HPC_DCP_MASK   (0x400U)
 
#define CSU_HPCONTROL0_HPC_DCP_SHIFT   (10U)
 
#define CSU_HPCONTROL0_HPC_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
 
#define CSU_HPCONTROL0_L_DCP_MASK   (0x800U)
 
#define CSU_HPCONTROL0_L_DCP_SHIFT   (11U)
 
#define CSU_HPCONTROL0_L_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
 
#define CSU_HPCONTROL0_HPC_ENET_MASK   (0x4000U)
 
#define CSU_HPCONTROL0_HPC_ENET_SHIFT   (14U)
 
#define CSU_HPCONTROL0_HPC_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
 
#define CSU_HPCONTROL0_L_ENET_MASK   (0x8000U)
 
#define CSU_HPCONTROL0_L_ENET_SHIFT   (15U)
 
#define CSU_HPCONTROL0_L_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
 
#define CSU_HPCONTROL0_HPC_USDHC1_MASK   (0x10000U)
 
#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT   (16U)
 
#define CSU_HPCONTROL0_HPC_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
 
#define CSU_HPCONTROL0_L_USDHC1_MASK   (0x20000U)
 
#define CSU_HPCONTROL0_L_USDHC1_SHIFT   (17U)
 
#define CSU_HPCONTROL0_L_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
 
#define CSU_HPCONTROL0_HPC_USDHC2_MASK   (0x40000U)
 
#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT   (18U)
 
#define CSU_HPCONTROL0_HPC_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
 
#define CSU_HPCONTROL0_L_USDHC2_MASK   (0x80000U)
 
#define CSU_HPCONTROL0_L_USDHC2_SHIFT   (19U)
 
#define CSU_HPCONTROL0_L_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
 
#define CSU_HPCONTROL0_HPC_TPSMP_MASK   (0x100000U)
 
#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT   (20U)
 
#define CSU_HPCONTROL0_HPC_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
 
#define CSU_HPCONTROL0_L_TPSMP_MASK   (0x200000U)
 
#define CSU_HPCONTROL0_L_TPSMP_SHIFT   (21U)
 
#define CSU_HPCONTROL0_L_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
 
#define CSU_HPCONTROL0_HPC_USB_MASK   (0x400000U)
 
#define CSU_HPCONTROL0_HPC_USB_SHIFT   (22U)
 
#define CSU_HPCONTROL0_HPC_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
 
#define CSU_HPCONTROL0_L_USB_MASK   (0x800000U)
 
#define CSU_HPCONTROL0_L_USB_SHIFT   (23U)
 
#define CSU_HPCONTROL0_L_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
 

Detailed Description

Macro Definition Documentation

◆ CSU_CSL_COUNT

#define CSU_CSL_COUNT   (32U)

Definition at line 9619 of file MIMXRT1052.h.

◆ CSU_CSL_LOCK_S1

#define CSU_CSL_LOCK_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)

LOCK_S1 0b0..Not locked. The bits 16-23 can be written by the software. 0b1..The bits 16-23 are locked and can't be written by the software.

Definition at line 9615 of file MIMXRT1052.h.

◆ CSU_CSL_LOCK_S1_MASK

#define CSU_CSL_LOCK_S1_MASK   (0x1000000U)

Definition at line 9609 of file MIMXRT1052.h.

◆ CSU_CSL_LOCK_S1_SHIFT

#define CSU_CSL_LOCK_S1_SHIFT   (24U)

Definition at line 9610 of file MIMXRT1052.h.

◆ CSU_CSL_LOCK_S2

#define CSU_CSL_LOCK_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)

LOCK_S2 0b0..Not locked. Bits 7-0 can be written by the software. 0b1..Bits 7-0 are locked and cannot be written by the software

Definition at line 9552 of file MIMXRT1052.h.

◆ CSU_CSL_LOCK_S2_MASK

#define CSU_CSL_LOCK_S2_MASK   (0x100U)

Definition at line 9546 of file MIMXRT1052.h.

◆ CSU_CSL_LOCK_S2_SHIFT

#define CSU_CSL_LOCK_S2_SHIFT   (8U)

Definition at line 9547 of file MIMXRT1052.h.

◆ CSU_CSL_NSR_S1

#define CSU_CSL_NSR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)

NSR_S1 0b0..The non-secure supervisor read access is disabled for the first slave. 0b1..The non-secure supervisor read access is enabled for the first slave.

Definition at line 9580 of file MIMXRT1052.h.

◆ CSU_CSL_NSR_S1_MASK

#define CSU_CSL_NSR_S1_MASK   (0x80000U)

Definition at line 9574 of file MIMXRT1052.h.

◆ CSU_CSL_NSR_S1_SHIFT

#define CSU_CSL_NSR_S1_SHIFT   (19U)

Definition at line 9575 of file MIMXRT1052.h.

◆ CSU_CSL_NSR_S2

#define CSU_CSL_NSR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)

NSR_S2 0b0..The non-secure supervisor read access is disabled for the second slave. 0b1..The non-secure supervisor read access is enabled for the second slave.

Definition at line 9517 of file MIMXRT1052.h.

◆ CSU_CSL_NSR_S2_MASK

#define CSU_CSL_NSR_S2_MASK   (0x8U)

Definition at line 9511 of file MIMXRT1052.h.

◆ CSU_CSL_NSR_S2_SHIFT

#define CSU_CSL_NSR_S2_SHIFT   (3U)

Definition at line 9512 of file MIMXRT1052.h.

◆ CSU_CSL_NSW_S1

#define CSU_CSL_NSW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)

NSW_S1 0b0..The non-secure supervisor write access is disabled for the first slave. 0b1..The non-secure supervisor write access is enabled for the first slave

Definition at line 9608 of file MIMXRT1052.h.

◆ CSU_CSL_NSW_S1_MASK

#define CSU_CSL_NSW_S1_MASK   (0x800000U)

Definition at line 9602 of file MIMXRT1052.h.

◆ CSU_CSL_NSW_S1_SHIFT

#define CSU_CSL_NSW_S1_SHIFT   (23U)

Definition at line 9603 of file MIMXRT1052.h.

◆ CSU_CSL_NSW_S2

#define CSU_CSL_NSW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)

NSW_S2 0b0..The non-secure supervisor write access is disabled for the second slave. 0b1..The non-secure supervisor write access is enabled for the second slave.

Definition at line 9545 of file MIMXRT1052.h.

◆ CSU_CSL_NSW_S2_MASK

#define CSU_CSL_NSW_S2_MASK   (0x80U)

Definition at line 9539 of file MIMXRT1052.h.

◆ CSU_CSL_NSW_S2_SHIFT

#define CSU_CSL_NSW_S2_SHIFT   (7U)

Definition at line 9540 of file MIMXRT1052.h.

◆ CSU_CSL_NUR_S1

#define CSU_CSL_NUR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)

NUR_S1 0b0..The non-secure user read access is disabled for the first slave. 0b1..The non-secure user read access is enabled for the first slave.

Definition at line 9573 of file MIMXRT1052.h.

◆ CSU_CSL_NUR_S1_MASK

#define CSU_CSL_NUR_S1_MASK   (0x40000U)

Definition at line 9567 of file MIMXRT1052.h.

◆ CSU_CSL_NUR_S1_SHIFT

#define CSU_CSL_NUR_S1_SHIFT   (18U)

Definition at line 9568 of file MIMXRT1052.h.

◆ CSU_CSL_NUR_S2

#define CSU_CSL_NUR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)

NUR_S2 0b0..The non-secure user read access is disabled for the second slave. 0b1..The non-secure user read access is enabled for the second slave.

Definition at line 9510 of file MIMXRT1052.h.

◆ CSU_CSL_NUR_S2_MASK

#define CSU_CSL_NUR_S2_MASK   (0x4U)

Definition at line 9504 of file MIMXRT1052.h.

◆ CSU_CSL_NUR_S2_SHIFT

#define CSU_CSL_NUR_S2_SHIFT   (2U)

Definition at line 9505 of file MIMXRT1052.h.

◆ CSU_CSL_NUW_S1

#define CSU_CSL_NUW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)

NUW_S1 0b0..The non-secure user write access is disabled for the first slave. 0b1..The non-secure user write access is enabled for the first slave.

Definition at line 9601 of file MIMXRT1052.h.

◆ CSU_CSL_NUW_S1_MASK

#define CSU_CSL_NUW_S1_MASK   (0x400000U)

Definition at line 9595 of file MIMXRT1052.h.

◆ CSU_CSL_NUW_S1_SHIFT

#define CSU_CSL_NUW_S1_SHIFT   (22U)

Definition at line 9596 of file MIMXRT1052.h.

◆ CSU_CSL_NUW_S2

#define CSU_CSL_NUW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)

NUW_S2 0b0..The non-secure user write access is disabled for the second slave. 0b1..The non-secure user write access is enabled for the second slave.

Definition at line 9538 of file MIMXRT1052.h.

◆ CSU_CSL_NUW_S2_MASK

#define CSU_CSL_NUW_S2_MASK   (0x40U)

Definition at line 9532 of file MIMXRT1052.h.

◆ CSU_CSL_NUW_S2_SHIFT

#define CSU_CSL_NUW_S2_SHIFT   (6U)

Definition at line 9533 of file MIMXRT1052.h.

◆ CSU_CSL_SSR_S1

#define CSU_CSL_SSR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)

SSR_S1 0b0..The secure supervisor read access is disabled for the first slave. 0b1..The secure supervisor read access is enabled for the first slave.

Definition at line 9566 of file MIMXRT1052.h.

◆ CSU_CSL_SSR_S1_MASK

#define CSU_CSL_SSR_S1_MASK   (0x20000U)

Definition at line 9560 of file MIMXRT1052.h.

◆ CSU_CSL_SSR_S1_SHIFT

#define CSU_CSL_SSR_S1_SHIFT   (17U)

Definition at line 9561 of file MIMXRT1052.h.

◆ CSU_CSL_SSR_S2

#define CSU_CSL_SSR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)

SSR_S2 0b0..The secure supervisor read access is disabled for the second slave. 0b1..The secure supervisor read access is enabled for the second slave.

Definition at line 9503 of file MIMXRT1052.h.

◆ CSU_CSL_SSR_S2_MASK

#define CSU_CSL_SSR_S2_MASK   (0x2U)

Definition at line 9497 of file MIMXRT1052.h.

◆ CSU_CSL_SSR_S2_SHIFT

#define CSU_CSL_SSR_S2_SHIFT   (1U)

Definition at line 9498 of file MIMXRT1052.h.

◆ CSU_CSL_SSW_S1

#define CSU_CSL_SSW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)

SSW_S1 0b0..The secure supervisor write access is disabled for the first slave. 0b1..The secure supervisor write access is enabled for the first slave.

Definition at line 9594 of file MIMXRT1052.h.

◆ CSU_CSL_SSW_S1_MASK

#define CSU_CSL_SSW_S1_MASK   (0x200000U)

Definition at line 9588 of file MIMXRT1052.h.

◆ CSU_CSL_SSW_S1_SHIFT

#define CSU_CSL_SSW_S1_SHIFT   (21U)

Definition at line 9589 of file MIMXRT1052.h.

◆ CSU_CSL_SSW_S2

#define CSU_CSL_SSW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)

SSW_S2 0b0..The secure supervisor write access is disabled for the second slave. 0b1..The secure supervisor write access is enabled for the second slave.

Definition at line 9531 of file MIMXRT1052.h.

◆ CSU_CSL_SSW_S2_MASK

#define CSU_CSL_SSW_S2_MASK   (0x20U)

Definition at line 9525 of file MIMXRT1052.h.

◆ CSU_CSL_SSW_S2_SHIFT

#define CSU_CSL_SSW_S2_SHIFT   (5U)

Definition at line 9526 of file MIMXRT1052.h.

◆ CSU_CSL_SUR_S1

#define CSU_CSL_SUR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)

SUR_S1 0b0..The secure user read access is disabled for the first slave. 0b1..The secure user read access is enabled for the first slave.

Definition at line 9559 of file MIMXRT1052.h.

◆ CSU_CSL_SUR_S1_MASK

#define CSU_CSL_SUR_S1_MASK   (0x10000U)

Definition at line 9553 of file MIMXRT1052.h.

◆ CSU_CSL_SUR_S1_SHIFT

#define CSU_CSL_SUR_S1_SHIFT   (16U)

Definition at line 9554 of file MIMXRT1052.h.

◆ CSU_CSL_SUR_S2

#define CSU_CSL_SUR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)

SUR_S2 0b0..The secure user read access is disabled for the second slave. 0b1..The secure user read access is enabled for the second slave.

Definition at line 9496 of file MIMXRT1052.h.

◆ CSU_CSL_SUR_S2_MASK

#define CSU_CSL_SUR_S2_MASK   (0x1U)

Definition at line 9490 of file MIMXRT1052.h.

◆ CSU_CSL_SUR_S2_SHIFT

#define CSU_CSL_SUR_S2_SHIFT   (0U)

Definition at line 9491 of file MIMXRT1052.h.

◆ CSU_CSL_SUW_S1

#define CSU_CSL_SUW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)

SUW_S1 0b0..The secure user write access is disabled for the first slave. 0b1..The secure user write access is enabled for the first slave.

Definition at line 9587 of file MIMXRT1052.h.

◆ CSU_CSL_SUW_S1_MASK

#define CSU_CSL_SUW_S1_MASK   (0x100000U)

Definition at line 9581 of file MIMXRT1052.h.

◆ CSU_CSL_SUW_S1_SHIFT

#define CSU_CSL_SUW_S1_SHIFT   (20U)

Definition at line 9582 of file MIMXRT1052.h.

◆ CSU_CSL_SUW_S2

#define CSU_CSL_SUW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)

SUW_S2 0b0..The secure user write access is disabled for the second slave. 0b1..The secure user write access is enabled for the second slave.

Definition at line 9524 of file MIMXRT1052.h.

◆ CSU_CSL_SUW_S2_MASK

#define CSU_CSL_SUW_S2_MASK   (0x10U)

Definition at line 9518 of file MIMXRT1052.h.

◆ CSU_CSL_SUW_S2_SHIFT

#define CSU_CSL_SUW_S2_SHIFT   (4U)

Definition at line 9519 of file MIMXRT1052.h.

◆ CSU_HP0_HP_CSI

#define CSU_HP0_HP_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)

HP_CSI 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9657 of file MIMXRT1052.h.

◆ CSU_HP0_HP_CSI_MASK

#define CSU_HP0_HP_CSI_MASK   (0x40U)

Definition at line 9651 of file MIMXRT1052.h.

◆ CSU_HP0_HP_CSI_SHIFT

#define CSU_HP0_HP_CSI_SHIFT   (6U)

Definition at line 9652 of file MIMXRT1052.h.

◆ CSU_HP0_HP_DCP

#define CSU_HP0_HP_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)

HP_DCP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9685 of file MIMXRT1052.h.

◆ CSU_HP0_HP_DCP_MASK

#define CSU_HP0_HP_DCP_MASK   (0x400U)

Definition at line 9679 of file MIMXRT1052.h.

◆ CSU_HP0_HP_DCP_SHIFT

#define CSU_HP0_HP_DCP_SHIFT   (10U)

Definition at line 9680 of file MIMXRT1052.h.

◆ CSU_HP0_HP_DMA

#define CSU_HP0_HP_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)

HP_DMA 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9629 of file MIMXRT1052.h.

◆ CSU_HP0_HP_DMA_MASK

#define CSU_HP0_HP_DMA_MASK   (0x4U)

Definition at line 9623 of file MIMXRT1052.h.

◆ CSU_HP0_HP_DMA_SHIFT

#define CSU_HP0_HP_DMA_SHIFT   (2U)

Definition at line 9624 of file MIMXRT1052.h.

◆ CSU_HP0_HP_ENET

#define CSU_HP0_HP_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)

HP_ENET 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9699 of file MIMXRT1052.h.

◆ CSU_HP0_HP_ENET_MASK

#define CSU_HP0_HP_ENET_MASK   (0x4000U)

Definition at line 9693 of file MIMXRT1052.h.

◆ CSU_HP0_HP_ENET_SHIFT

#define CSU_HP0_HP_ENET_SHIFT   (14U)

Definition at line 9694 of file MIMXRT1052.h.

◆ CSU_HP0_HP_LCDIF

#define CSU_HP0_HP_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)

HP_LCDIF 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9643 of file MIMXRT1052.h.

◆ CSU_HP0_HP_LCDIF_MASK

#define CSU_HP0_HP_LCDIF_MASK   (0x10U)

Definition at line 9637 of file MIMXRT1052.h.

◆ CSU_HP0_HP_LCDIF_SHIFT

#define CSU_HP0_HP_LCDIF_SHIFT   (4U)

Definition at line 9638 of file MIMXRT1052.h.

◆ CSU_HP0_HP_PXP

#define CSU_HP0_HP_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)

HP_PXP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9671 of file MIMXRT1052.h.

◆ CSU_HP0_HP_PXP_MASK

#define CSU_HP0_HP_PXP_MASK   (0x100U)

Definition at line 9665 of file MIMXRT1052.h.

◆ CSU_HP0_HP_PXP_SHIFT

#define CSU_HP0_HP_PXP_SHIFT   (8U)

Definition at line 9666 of file MIMXRT1052.h.

◆ CSU_HP0_HP_TPSMP

#define CSU_HP0_HP_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)

HP_TPSMP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9741 of file MIMXRT1052.h.

◆ CSU_HP0_HP_TPSMP_MASK

#define CSU_HP0_HP_TPSMP_MASK   (0x100000U)

Definition at line 9735 of file MIMXRT1052.h.

◆ CSU_HP0_HP_TPSMP_SHIFT

#define CSU_HP0_HP_TPSMP_SHIFT   (20U)

Definition at line 9736 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USB

#define CSU_HP0_HP_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)

HP_USB 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9755 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USB_MASK

#define CSU_HP0_HP_USB_MASK   (0x400000U)

Definition at line 9749 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USB_SHIFT

#define CSU_HP0_HP_USB_SHIFT   (22U)

Definition at line 9750 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USDHC1

#define CSU_HP0_HP_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)

HP_USDHC1 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9713 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USDHC1_MASK

#define CSU_HP0_HP_USDHC1_MASK   (0x10000U)

Definition at line 9707 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USDHC1_SHIFT

#define CSU_HP0_HP_USDHC1_SHIFT   (16U)

Definition at line 9708 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USDHC2

#define CSU_HP0_HP_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)

HP_USDHC2 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 9727 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USDHC2_MASK

#define CSU_HP0_HP_USDHC2_MASK   (0x40000U)

Definition at line 9721 of file MIMXRT1052.h.

◆ CSU_HP0_HP_USDHC2_SHIFT

#define CSU_HP0_HP_USDHC2_SHIFT   (18U)

Definition at line 9722 of file MIMXRT1052.h.

◆ CSU_HP0_L_CSI

#define CSU_HP0_L_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9664 of file MIMXRT1052.h.

◆ CSU_HP0_L_CSI_MASK

#define CSU_HP0_L_CSI_MASK   (0x80U)

Definition at line 9658 of file MIMXRT1052.h.

◆ CSU_HP0_L_CSI_SHIFT

#define CSU_HP0_L_CSI_SHIFT   (7U)

Definition at line 9659 of file MIMXRT1052.h.

◆ CSU_HP0_L_DCP

#define CSU_HP0_L_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit cannot be written by the software.

Definition at line 9692 of file MIMXRT1052.h.

◆ CSU_HP0_L_DCP_MASK

#define CSU_HP0_L_DCP_MASK   (0x800U)

Definition at line 9686 of file MIMXRT1052.h.

◆ CSU_HP0_L_DCP_SHIFT

#define CSU_HP0_L_DCP_SHIFT   (11U)

Definition at line 9687 of file MIMXRT1052.h.

◆ CSU_HP0_L_DMA

#define CSU_HP0_L_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9636 of file MIMXRT1052.h.

◆ CSU_HP0_L_DMA_MASK

#define CSU_HP0_L_DMA_MASK   (0x8U)

Definition at line 9630 of file MIMXRT1052.h.

◆ CSU_HP0_L_DMA_SHIFT

#define CSU_HP0_L_DMA_SHIFT   (3U)

Definition at line 9631 of file MIMXRT1052.h.

◆ CSU_HP0_L_ENET

#define CSU_HP0_L_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9706 of file MIMXRT1052.h.

◆ CSU_HP0_L_ENET_MASK

#define CSU_HP0_L_ENET_MASK   (0x8000U)

Definition at line 9700 of file MIMXRT1052.h.

◆ CSU_HP0_L_ENET_SHIFT

#define CSU_HP0_L_ENET_SHIFT   (15U)

Definition at line 9701 of file MIMXRT1052.h.

◆ CSU_HP0_L_LCDIF

#define CSU_HP0_L_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9650 of file MIMXRT1052.h.

◆ CSU_HP0_L_LCDIF_MASK

#define CSU_HP0_L_LCDIF_MASK   (0x20U)

Definition at line 9644 of file MIMXRT1052.h.

◆ CSU_HP0_L_LCDIF_SHIFT

#define CSU_HP0_L_LCDIF_SHIFT   (5U)

Definition at line 9645 of file MIMXRT1052.h.

◆ CSU_HP0_L_PXP

#define CSU_HP0_L_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9678 of file MIMXRT1052.h.

◆ CSU_HP0_L_PXP_MASK

#define CSU_HP0_L_PXP_MASK   (0x200U)

Definition at line 9672 of file MIMXRT1052.h.

◆ CSU_HP0_L_PXP_SHIFT

#define CSU_HP0_L_PXP_SHIFT   (9U)

Definition at line 9673 of file MIMXRT1052.h.

◆ CSU_HP0_L_TPSMP

#define CSU_HP0_L_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9748 of file MIMXRT1052.h.

◆ CSU_HP0_L_TPSMP_MASK

#define CSU_HP0_L_TPSMP_MASK   (0x200000U)

Definition at line 9742 of file MIMXRT1052.h.

◆ CSU_HP0_L_TPSMP_SHIFT

#define CSU_HP0_L_TPSMP_SHIFT   (21U)

Definition at line 9743 of file MIMXRT1052.h.

◆ CSU_HP0_L_USB

#define CSU_HP0_L_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9762 of file MIMXRT1052.h.

◆ CSU_HP0_L_USB_MASK

#define CSU_HP0_L_USB_MASK   (0x800000U)

Definition at line 9756 of file MIMXRT1052.h.

◆ CSU_HP0_L_USB_SHIFT

#define CSU_HP0_L_USB_SHIFT   (23U)

Definition at line 9757 of file MIMXRT1052.h.

◆ CSU_HP0_L_USDHC1

#define CSU_HP0_L_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9720 of file MIMXRT1052.h.

◆ CSU_HP0_L_USDHC1_MASK

#define CSU_HP0_L_USDHC1_MASK   (0x20000U)

Definition at line 9714 of file MIMXRT1052.h.

◆ CSU_HP0_L_USDHC1_SHIFT

#define CSU_HP0_L_USDHC1_SHIFT   (17U)

Definition at line 9715 of file MIMXRT1052.h.

◆ CSU_HP0_L_USDHC2

#define CSU_HP0_L_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9734 of file MIMXRT1052.h.

◆ CSU_HP0_L_USDHC2_MASK

#define CSU_HP0_L_USDHC2_MASK   (0x80000U)

Definition at line 9728 of file MIMXRT1052.h.

◆ CSU_HP0_L_USDHC2_SHIFT

#define CSU_HP0_L_USDHC2_SHIFT   (19U)

Definition at line 9729 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_CSI

#define CSU_HPCONTROL0_HPC_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)

HPC_CSI 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 9945 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_CSI_MASK

#define CSU_HPCONTROL0_HPC_CSI_MASK   (0x40U)

Definition at line 9939 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_CSI_SHIFT

#define CSU_HPCONTROL0_HPC_CSI_SHIFT   (6U)

Definition at line 9940 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_DCP

#define CSU_HPCONTROL0_HPC_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)

HPC_DCP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 9973 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_DCP_MASK

#define CSU_HPCONTROL0_HPC_DCP_MASK   (0x400U)

Definition at line 9967 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_DCP_SHIFT

#define CSU_HPCONTROL0_HPC_DCP_SHIFT   (10U)

Definition at line 9968 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_DMA

#define CSU_HPCONTROL0_HPC_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)

HPC_DMA 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 9917 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_DMA_MASK

#define CSU_HPCONTROL0_HPC_DMA_MASK   (0x4U)

Definition at line 9911 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_DMA_SHIFT

#define CSU_HPCONTROL0_HPC_DMA_SHIFT   (2U)

Definition at line 9912 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_ENET

#define CSU_HPCONTROL0_HPC_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)

HPC_ENET 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 9987 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_ENET_MASK

#define CSU_HPCONTROL0_HPC_ENET_MASK   (0x4000U)

Definition at line 9981 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_ENET_SHIFT

#define CSU_HPCONTROL0_HPC_ENET_SHIFT   (14U)

Definition at line 9982 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_LCDIF

#define CSU_HPCONTROL0_HPC_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)

HPC_LCDIF 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 9931 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_LCDIF_MASK

#define CSU_HPCONTROL0_HPC_LCDIF_MASK   (0x10U)

Definition at line 9925 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_LCDIF_SHIFT

#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT   (4U)

Definition at line 9926 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_PXP

#define CSU_HPCONTROL0_HPC_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)

HPC_PXP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 9959 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_PXP_MASK

#define CSU_HPCONTROL0_HPC_PXP_MASK   (0x100U)

Definition at line 9953 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_PXP_SHIFT

#define CSU_HPCONTROL0_HPC_PXP_SHIFT   (8U)

Definition at line 9954 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_TPSMP

#define CSU_HPCONTROL0_HPC_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)

HPC_TPSMP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 10029 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_TPSMP_MASK

#define CSU_HPCONTROL0_HPC_TPSMP_MASK   (0x100000U)

Definition at line 10023 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_TPSMP_SHIFT

#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT   (20U)

Definition at line 10024 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USB

#define CSU_HPCONTROL0_HPC_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)

HPC_USB 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 10043 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USB_MASK

#define CSU_HPCONTROL0_HPC_USB_MASK   (0x400000U)

Definition at line 10037 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USB_SHIFT

#define CSU_HPCONTROL0_HPC_USB_SHIFT   (22U)

Definition at line 10038 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USDHC1

#define CSU_HPCONTROL0_HPC_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)

HPC_USDHC1 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 10001 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USDHC1_MASK

#define CSU_HPCONTROL0_HPC_USDHC1_MASK   (0x10000U)

Definition at line 9995 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USDHC1_SHIFT

#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT   (16U)

Definition at line 9996 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USDHC2

#define CSU_HPCONTROL0_HPC_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)

HPC_USDHC2 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 10015 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USDHC2_MASK

#define CSU_HPCONTROL0_HPC_USDHC2_MASK   (0x40000U)

Definition at line 10009 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_HPC_USDHC2_SHIFT

#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT   (18U)

Definition at line 10010 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_CSI

#define CSU_HPCONTROL0_L_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9952 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_CSI_MASK

#define CSU_HPCONTROL0_L_CSI_MASK   (0x80U)

Definition at line 9946 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_CSI_SHIFT

#define CSU_HPCONTROL0_L_CSI_SHIFT   (7U)

Definition at line 9947 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_DCP

#define CSU_HPCONTROL0_L_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9980 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_DCP_MASK

#define CSU_HPCONTROL0_L_DCP_MASK   (0x800U)

Definition at line 9974 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_DCP_SHIFT

#define CSU_HPCONTROL0_L_DCP_SHIFT   (11U)

Definition at line 9975 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_DMA

#define CSU_HPCONTROL0_L_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9924 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_DMA_MASK

#define CSU_HPCONTROL0_L_DMA_MASK   (0x8U)

Definition at line 9918 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_DMA_SHIFT

#define CSU_HPCONTROL0_L_DMA_SHIFT   (3U)

Definition at line 9919 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_ENET

#define CSU_HPCONTROL0_L_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9994 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_ENET_MASK

#define CSU_HPCONTROL0_L_ENET_MASK   (0x8000U)

Definition at line 9988 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_ENET_SHIFT

#define CSU_HPCONTROL0_L_ENET_SHIFT   (15U)

Definition at line 9989 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_LCDIF

#define CSU_HPCONTROL0_L_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9938 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_LCDIF_MASK

#define CSU_HPCONTROL0_L_LCDIF_MASK   (0x20U)

Definition at line 9932 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_LCDIF_SHIFT

#define CSU_HPCONTROL0_L_LCDIF_SHIFT   (5U)

Definition at line 9933 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_PXP

#define CSU_HPCONTROL0_L_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9966 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_PXP_MASK

#define CSU_HPCONTROL0_L_PXP_MASK   (0x200U)

Definition at line 9960 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_PXP_SHIFT

#define CSU_HPCONTROL0_L_PXP_SHIFT   (9U)

Definition at line 9961 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_TPSMP

#define CSU_HPCONTROL0_L_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10036 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_TPSMP_MASK

#define CSU_HPCONTROL0_L_TPSMP_MASK   (0x200000U)

Definition at line 10030 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_TPSMP_SHIFT

#define CSU_HPCONTROL0_L_TPSMP_SHIFT   (21U)

Definition at line 10031 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USB

#define CSU_HPCONTROL0_L_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10050 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USB_MASK

#define CSU_HPCONTROL0_L_USB_MASK   (0x800000U)

Definition at line 10044 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USB_SHIFT

#define CSU_HPCONTROL0_L_USB_SHIFT   (23U)

Definition at line 10045 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USDHC1

#define CSU_HPCONTROL0_L_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10008 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USDHC1_MASK

#define CSU_HPCONTROL0_L_USDHC1_MASK   (0x20000U)

Definition at line 10002 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USDHC1_SHIFT

#define CSU_HPCONTROL0_L_USDHC1_SHIFT   (17U)

Definition at line 10003 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USDHC2

#define CSU_HPCONTROL0_L_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10022 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USDHC2_MASK

#define CSU_HPCONTROL0_L_USDHC2_MASK   (0x80000U)

Definition at line 10016 of file MIMXRT1052.h.

◆ CSU_HPCONTROL0_L_USDHC2_SHIFT

#define CSU_HPCONTROL0_L_USDHC2_SHIFT   (19U)

Definition at line 10017 of file MIMXRT1052.h.

◆ CSU_SA_L_CSI

#define CSU_SA_L_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9808 of file MIMXRT1052.h.

◆ CSU_SA_L_CSI_MASK

#define CSU_SA_L_CSI_MASK   (0x80U)

Definition at line 9802 of file MIMXRT1052.h.

◆ CSU_SA_L_CSI_SHIFT

#define CSU_SA_L_CSI_SHIFT   (7U)

Definition at line 9803 of file MIMXRT1052.h.

◆ CSU_SA_L_DCP

#define CSU_SA_L_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9836 of file MIMXRT1052.h.

◆ CSU_SA_L_DCP_MASK

#define CSU_SA_L_DCP_MASK   (0x800U)

Definition at line 9830 of file MIMXRT1052.h.

◆ CSU_SA_L_DCP_SHIFT

#define CSU_SA_L_DCP_SHIFT   (11U)

Definition at line 9831 of file MIMXRT1052.h.

◆ CSU_SA_L_DMA

#define CSU_SA_L_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9780 of file MIMXRT1052.h.

◆ CSU_SA_L_DMA_MASK

#define CSU_SA_L_DMA_MASK   (0x8U)

Definition at line 9774 of file MIMXRT1052.h.

◆ CSU_SA_L_DMA_SHIFT

#define CSU_SA_L_DMA_SHIFT   (3U)

Definition at line 9775 of file MIMXRT1052.h.

◆ CSU_SA_L_ENET

#define CSU_SA_L_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9850 of file MIMXRT1052.h.

◆ CSU_SA_L_ENET_MASK

#define CSU_SA_L_ENET_MASK   (0x8000U)

Definition at line 9844 of file MIMXRT1052.h.

◆ CSU_SA_L_ENET_SHIFT

#define CSU_SA_L_ENET_SHIFT   (15U)

Definition at line 9845 of file MIMXRT1052.h.

◆ CSU_SA_L_LCDIF

#define CSU_SA_L_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9794 of file MIMXRT1052.h.

◆ CSU_SA_L_LCDIF_MASK

#define CSU_SA_L_LCDIF_MASK   (0x20U)

Definition at line 9788 of file MIMXRT1052.h.

◆ CSU_SA_L_LCDIF_SHIFT

#define CSU_SA_L_LCDIF_SHIFT   (5U)

Definition at line 9789 of file MIMXRT1052.h.

◆ CSU_SA_L_PXP

#define CSU_SA_L_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9822 of file MIMXRT1052.h.

◆ CSU_SA_L_PXP_MASK

#define CSU_SA_L_PXP_MASK   (0x200U)

Definition at line 9816 of file MIMXRT1052.h.

◆ CSU_SA_L_PXP_SHIFT

#define CSU_SA_L_PXP_SHIFT   (9U)

Definition at line 9817 of file MIMXRT1052.h.

◆ CSU_SA_L_TPSMP

#define CSU_SA_L_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9892 of file MIMXRT1052.h.

◆ CSU_SA_L_TPSMP_MASK

#define CSU_SA_L_TPSMP_MASK   (0x200000U)

Definition at line 9886 of file MIMXRT1052.h.

◆ CSU_SA_L_TPSMP_SHIFT

#define CSU_SA_L_TPSMP_SHIFT   (21U)

Definition at line 9887 of file MIMXRT1052.h.

◆ CSU_SA_L_USB

#define CSU_SA_L_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9906 of file MIMXRT1052.h.

◆ CSU_SA_L_USB_MASK

#define CSU_SA_L_USB_MASK   (0x800000U)

Definition at line 9900 of file MIMXRT1052.h.

◆ CSU_SA_L_USB_SHIFT

#define CSU_SA_L_USB_SHIFT   (23U)

Definition at line 9901 of file MIMXRT1052.h.

◆ CSU_SA_L_USDHC1

#define CSU_SA_L_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9864 of file MIMXRT1052.h.

◆ CSU_SA_L_USDHC1_MASK

#define CSU_SA_L_USDHC1_MASK   (0x20000U)

Definition at line 9858 of file MIMXRT1052.h.

◆ CSU_SA_L_USDHC1_SHIFT

#define CSU_SA_L_USDHC1_SHIFT   (17U)

Definition at line 9859 of file MIMXRT1052.h.

◆ CSU_SA_L_USDHC2

#define CSU_SA_L_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 9878 of file MIMXRT1052.h.

◆ CSU_SA_L_USDHC2_MASK

#define CSU_SA_L_USDHC2_MASK   (0x80000U)

Definition at line 9872 of file MIMXRT1052.h.

◆ CSU_SA_L_USDHC2_SHIFT

#define CSU_SA_L_USDHC2_SHIFT   (19U)

Definition at line 9873 of file MIMXRT1052.h.

◆ CSU_SA_NSA_CSI

#define CSU_SA_NSA_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)

NSA_CSI - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9801 of file MIMXRT1052.h.

◆ CSU_SA_NSA_CSI_MASK

#define CSU_SA_NSA_CSI_MASK   (0x40U)

Definition at line 9795 of file MIMXRT1052.h.

◆ CSU_SA_NSA_CSI_SHIFT

#define CSU_SA_NSA_CSI_SHIFT   (6U)

Definition at line 9796 of file MIMXRT1052.h.

◆ CSU_SA_NSA_DCP

#define CSU_SA_NSA_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)

NSA_DCP - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9829 of file MIMXRT1052.h.

◆ CSU_SA_NSA_DCP_MASK

#define CSU_SA_NSA_DCP_MASK   (0x400U)

Definition at line 9823 of file MIMXRT1052.h.

◆ CSU_SA_NSA_DCP_SHIFT

#define CSU_SA_NSA_DCP_SHIFT   (10U)

Definition at line 9824 of file MIMXRT1052.h.

◆ CSU_SA_NSA_DMA

#define CSU_SA_NSA_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)

NSA_DMA - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9773 of file MIMXRT1052.h.

◆ CSU_SA_NSA_DMA_MASK

#define CSU_SA_NSA_DMA_MASK   (0x4U)

Definition at line 9767 of file MIMXRT1052.h.

◆ CSU_SA_NSA_DMA_SHIFT

#define CSU_SA_NSA_DMA_SHIFT   (2U)

Definition at line 9768 of file MIMXRT1052.h.

◆ CSU_SA_NSA_ENET

#define CSU_SA_NSA_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)

NSA_ENET - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9843 of file MIMXRT1052.h.

◆ CSU_SA_NSA_ENET_MASK

#define CSU_SA_NSA_ENET_MASK   (0x4000U)

Definition at line 9837 of file MIMXRT1052.h.

◆ CSU_SA_NSA_ENET_SHIFT

#define CSU_SA_NSA_ENET_SHIFT   (14U)

Definition at line 9838 of file MIMXRT1052.h.

◆ CSU_SA_NSA_LCDIF

#define CSU_SA_NSA_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)

NSA_LCDIF - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9787 of file MIMXRT1052.h.

◆ CSU_SA_NSA_LCDIF_MASK

#define CSU_SA_NSA_LCDIF_MASK   (0x10U)

Definition at line 9781 of file MIMXRT1052.h.

◆ CSU_SA_NSA_LCDIF_SHIFT

#define CSU_SA_NSA_LCDIF_SHIFT   (4U)

Definition at line 9782 of file MIMXRT1052.h.

◆ CSU_SA_NSA_PXP

#define CSU_SA_NSA_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)

NSA_PXP - Non-Secure Access Policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9815 of file MIMXRT1052.h.

◆ CSU_SA_NSA_PXP_MASK

#define CSU_SA_NSA_PXP_MASK   (0x100U)

Definition at line 9809 of file MIMXRT1052.h.

◆ CSU_SA_NSA_PXP_SHIFT

#define CSU_SA_NSA_PXP_SHIFT   (8U)

Definition at line 9810 of file MIMXRT1052.h.

◆ CSU_SA_NSA_TPSMP

#define CSU_SA_NSA_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)

NSA_TPSMP - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9885 of file MIMXRT1052.h.

◆ CSU_SA_NSA_TPSMP_MASK

#define CSU_SA_NSA_TPSMP_MASK   (0x100000U)

Definition at line 9879 of file MIMXRT1052.h.

◆ CSU_SA_NSA_TPSMP_SHIFT

#define CSU_SA_NSA_TPSMP_SHIFT   (20U)

Definition at line 9880 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USB

#define CSU_SA_NSA_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)

NSA_USB - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9899 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USB_MASK

#define CSU_SA_NSA_USB_MASK   (0x400000U)

Definition at line 9893 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USB_SHIFT

#define CSU_SA_NSA_USB_SHIFT   (22U)

Definition at line 9894 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USDHC1

#define CSU_SA_NSA_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)

NSA_USDHC1 - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9857 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USDHC1_MASK

#define CSU_SA_NSA_USDHC1_MASK   (0x10000U)

Definition at line 9851 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USDHC1_SHIFT

#define CSU_SA_NSA_USDHC1_SHIFT   (16U)

Definition at line 9852 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USDHC2

#define CSU_SA_NSA_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)

NSA_USDHC2 - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 9871 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USDHC2_MASK

#define CSU_SA_NSA_USDHC2_MASK   (0x40000U)

Definition at line 9865 of file MIMXRT1052.h.

◆ CSU_SA_NSA_USDHC2_SHIFT

#define CSU_SA_NSA_USDHC2_SHIFT   (18U)

Definition at line 9866 of file MIMXRT1052.h.


picovoice_driver
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autogenerated on Fri Apr 1 2022 02:15:09