CR0 - CMP Control Register 0 | |
| #define | CMP_CR0_HYSTCTR_MASK (0x3U) |
| #define | CMP_CR0_HYSTCTR_SHIFT (0U) |
| #define | CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) |
| #define | CMP_CR0_FILTER_CNT_MASK (0x70U) |
| #define | CMP_CR0_FILTER_CNT_SHIFT (4U) |
| #define | CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) |
CR1 - CMP Control Register 1 | |
| #define | CMP_CR1_EN_MASK (0x1U) |
| #define | CMP_CR1_EN_SHIFT (0U) |
| #define | CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) |
| #define | CMP_CR1_OPE_MASK (0x2U) |
| #define | CMP_CR1_OPE_SHIFT (1U) |
| #define | CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) |
| #define | CMP_CR1_COS_MASK (0x4U) |
| #define | CMP_CR1_COS_SHIFT (2U) |
| #define | CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) |
| #define | CMP_CR1_INV_MASK (0x8U) |
| #define | CMP_CR1_INV_SHIFT (3U) |
| #define | CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) |
| #define | CMP_CR1_PMODE_MASK (0x10U) |
| #define | CMP_CR1_PMODE_SHIFT (4U) |
| #define | CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) |
| #define | CMP_CR1_WE_MASK (0x40U) |
| #define | CMP_CR1_WE_SHIFT (6U) |
| #define | CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) |
| #define | CMP_CR1_SE_MASK (0x80U) |
| #define | CMP_CR1_SE_SHIFT (7U) |
| #define | CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) |
FPR - CMP Filter Period Register | |
| #define | CMP_FPR_FILT_PER_MASK (0xFFU) |
| #define | CMP_FPR_FILT_PER_SHIFT (0U) |
| #define | CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) |
SCR - CMP Status and Control Register | |
| #define | CMP_SCR_COUT_MASK (0x1U) |
| #define | CMP_SCR_COUT_SHIFT (0U) |
| #define | CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) |
| #define | CMP_SCR_CFF_MASK (0x2U) |
| #define | CMP_SCR_CFF_SHIFT (1U) |
| #define | CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) |
| #define | CMP_SCR_CFR_MASK (0x4U) |
| #define | CMP_SCR_CFR_SHIFT (2U) |
| #define | CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) |
| #define | CMP_SCR_IEF_MASK (0x8U) |
| #define | CMP_SCR_IEF_SHIFT (3U) |
| #define | CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) |
| #define | CMP_SCR_IER_MASK (0x10U) |
| #define | CMP_SCR_IER_SHIFT (4U) |
| #define | CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) |
| #define | CMP_SCR_DMAEN_MASK (0x40U) |
| #define | CMP_SCR_DMAEN_SHIFT (6U) |
| #define | CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) |
DACCR - DAC Control Register | |
| #define | CMP_DACCR_VOSEL_MASK (0x3FU) |
| #define | CMP_DACCR_VOSEL_SHIFT (0U) |
| #define | CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) |
| #define | CMP_DACCR_VRSEL_MASK (0x40U) |
| #define | CMP_DACCR_VRSEL_SHIFT (6U) |
| #define | CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) |
| #define | CMP_DACCR_DACEN_MASK (0x80U) |
| #define | CMP_DACCR_DACEN_SHIFT (7U) |
| #define | CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) |
MUXCR - MUX Control Register | |
| #define | CMP_MUXCR_MSEL_MASK (0x7U) |
| #define | CMP_MUXCR_MSEL_SHIFT (0U) |
| #define | CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) |
| #define | CMP_MUXCR_PSEL_MASK (0x38U) |
| #define | CMP_MUXCR_PSEL_SHIFT (3U) |
| #define | CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) |
Detailed Description
Macro Definition Documentation
◆ CMP_CR0_FILTER_CNT
| #define CMP_CR0_FILTER_CNT | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) |
FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.
Definition at line 8582 of file MIMXRT1052.h.
◆ CMP_CR0_FILTER_CNT_MASK
| #define CMP_CR0_FILTER_CNT_MASK (0x70U) |
Definition at line 8570 of file MIMXRT1052.h.
◆ CMP_CR0_FILTER_CNT_SHIFT
| #define CMP_CR0_FILTER_CNT_SHIFT (4U) |
Definition at line 8571 of file MIMXRT1052.h.
◆ CMP_CR0_HYSTCTR
| #define CMP_CR0_HYSTCTR | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) |
HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3
Definition at line 8569 of file MIMXRT1052.h.
◆ CMP_CR0_HYSTCTR_MASK
| #define CMP_CR0_HYSTCTR_MASK (0x3U) |
Definition at line 8561 of file MIMXRT1052.h.
◆ CMP_CR0_HYSTCTR_SHIFT
| #define CMP_CR0_HYSTCTR_SHIFT (0U) |
Definition at line 8562 of file MIMXRT1052.h.
◆ CMP_CR1_COS
| #define CMP_CR1_COS | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) |
COS - Comparator Output Select 0b0..Set the filtered comparator output (CMPO) to equal COUT. 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
Definition at line 8609 of file MIMXRT1052.h.
◆ CMP_CR1_COS_MASK
| #define CMP_CR1_COS_MASK (0x4U) |
Definition at line 8603 of file MIMXRT1052.h.
◆ CMP_CR1_COS_SHIFT
| #define CMP_CR1_COS_SHIFT (2U) |
Definition at line 8604 of file MIMXRT1052.h.
◆ CMP_CR1_EN
| #define CMP_CR1_EN | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) |
EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.
Definition at line 8593 of file MIMXRT1052.h.
◆ CMP_CR1_EN_MASK
| #define CMP_CR1_EN_MASK (0x1U) |
Definition at line 8587 of file MIMXRT1052.h.
◆ CMP_CR1_EN_SHIFT
| #define CMP_CR1_EN_SHIFT (0U) |
Definition at line 8588 of file MIMXRT1052.h.
◆ CMP_CR1_INV
| #define CMP_CR1_INV | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) |
INV - Comparator INVERT 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.
Definition at line 8616 of file MIMXRT1052.h.
◆ CMP_CR1_INV_MASK
| #define CMP_CR1_INV_MASK (0x8U) |
Definition at line 8610 of file MIMXRT1052.h.
◆ CMP_CR1_INV_SHIFT
| #define CMP_CR1_INV_SHIFT (3U) |
Definition at line 8611 of file MIMXRT1052.h.
◆ CMP_CR1_OPE
| #define CMP_CR1_OPE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) |
OPE - Comparator Output Pin Enable 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
Definition at line 8602 of file MIMXRT1052.h.
◆ CMP_CR1_OPE_MASK
| #define CMP_CR1_OPE_MASK (0x2U) |
Definition at line 8594 of file MIMXRT1052.h.
◆ CMP_CR1_OPE_SHIFT
| #define CMP_CR1_OPE_SHIFT (1U) |
Definition at line 8595 of file MIMXRT1052.h.
◆ CMP_CR1_PMODE
| #define CMP_CR1_PMODE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) |
PMODE - Power Mode Select 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
Definition at line 8623 of file MIMXRT1052.h.
◆ CMP_CR1_PMODE_MASK
| #define CMP_CR1_PMODE_MASK (0x10U) |
Definition at line 8617 of file MIMXRT1052.h.
◆ CMP_CR1_PMODE_SHIFT
| #define CMP_CR1_PMODE_SHIFT (4U) |
Definition at line 8618 of file MIMXRT1052.h.
◆ CMP_CR1_SE
| #define CMP_CR1_SE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) |
SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.
Definition at line 8637 of file MIMXRT1052.h.
◆ CMP_CR1_SE_MASK
| #define CMP_CR1_SE_MASK (0x80U) |
Definition at line 8631 of file MIMXRT1052.h.
◆ CMP_CR1_SE_SHIFT
| #define CMP_CR1_SE_SHIFT (7U) |
Definition at line 8632 of file MIMXRT1052.h.
◆ CMP_CR1_WE
| #define CMP_CR1_WE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) |
WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.
Definition at line 8630 of file MIMXRT1052.h.
◆ CMP_CR1_WE_MASK
| #define CMP_CR1_WE_MASK (0x40U) |
Definition at line 8624 of file MIMXRT1052.h.
◆ CMP_CR1_WE_SHIFT
| #define CMP_CR1_WE_SHIFT (6U) |
Definition at line 8625 of file MIMXRT1052.h.
◆ CMP_DACCR_DACEN
| #define CMP_DACCR_DACEN | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) |
DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.
Definition at line 8713 of file MIMXRT1052.h.
◆ CMP_DACCR_DACEN_MASK
| #define CMP_DACCR_DACEN_MASK (0x80U) |
Definition at line 8707 of file MIMXRT1052.h.
◆ CMP_DACCR_DACEN_SHIFT
| #define CMP_DACCR_DACEN_SHIFT (7U) |
Definition at line 8708 of file MIMXRT1052.h.
◆ CMP_DACCR_VOSEL
| #define CMP_DACCR_VOSEL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) |
VOSEL - DAC Output Voltage Select
Definition at line 8699 of file MIMXRT1052.h.
◆ CMP_DACCR_VOSEL_MASK
| #define CMP_DACCR_VOSEL_MASK (0x3FU) |
Definition at line 8695 of file MIMXRT1052.h.
◆ CMP_DACCR_VOSEL_SHIFT
| #define CMP_DACCR_VOSEL_SHIFT (0U) |
Definition at line 8696 of file MIMXRT1052.h.
◆ CMP_DACCR_VRSEL
| #define CMP_DACCR_VRSEL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) |
VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference. 0b1..Vin2 is selected as resistor ladder network supply reference.
Definition at line 8706 of file MIMXRT1052.h.
◆ CMP_DACCR_VRSEL_MASK
| #define CMP_DACCR_VRSEL_MASK (0x40U) |
Definition at line 8700 of file MIMXRT1052.h.
◆ CMP_DACCR_VRSEL_SHIFT
| #define CMP_DACCR_VRSEL_SHIFT (6U) |
Definition at line 8701 of file MIMXRT1052.h.
◆ CMP_FPR_FILT_PER
| #define CMP_FPR_FILT_PER | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) |
FILT_PER - Filter Sample Period
Definition at line 8646 of file MIMXRT1052.h.
◆ CMP_FPR_FILT_PER_MASK
| #define CMP_FPR_FILT_PER_MASK (0xFFU) |
Definition at line 8642 of file MIMXRT1052.h.
◆ CMP_FPR_FILT_PER_SHIFT
| #define CMP_FPR_FILT_PER_SHIFT (0U) |
Definition at line 8643 of file MIMXRT1052.h.
◆ CMP_MUXCR_MSEL
| #define CMP_MUXCR_MSEL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) |
MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7
Definition at line 8730 of file MIMXRT1052.h.
◆ CMP_MUXCR_MSEL_MASK
| #define CMP_MUXCR_MSEL_MASK (0x7U) |
Definition at line 8718 of file MIMXRT1052.h.
◆ CMP_MUXCR_MSEL_SHIFT
| #define CMP_MUXCR_MSEL_SHIFT (0U) |
Definition at line 8719 of file MIMXRT1052.h.
◆ CMP_MUXCR_PSEL
| #define CMP_MUXCR_PSEL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) |
PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7
Definition at line 8743 of file MIMXRT1052.h.
◆ CMP_MUXCR_PSEL_MASK
| #define CMP_MUXCR_PSEL_MASK (0x38U) |
Definition at line 8731 of file MIMXRT1052.h.
◆ CMP_MUXCR_PSEL_SHIFT
| #define CMP_MUXCR_PSEL_SHIFT (3U) |
Definition at line 8732 of file MIMXRT1052.h.
◆ CMP_SCR_CFF
| #define CMP_SCR_CFF | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) |
CFF - Analog Comparator Flag Falling 0b0..Falling-edge on COUT has not been detected. 0b1..Falling-edge on COUT has occurred.
Definition at line 8662 of file MIMXRT1052.h.
◆ CMP_SCR_CFF_MASK
| #define CMP_SCR_CFF_MASK (0x2U) |
Definition at line 8656 of file MIMXRT1052.h.
◆ CMP_SCR_CFF_SHIFT
| #define CMP_SCR_CFF_SHIFT (1U) |
Definition at line 8657 of file MIMXRT1052.h.
◆ CMP_SCR_CFR
| #define CMP_SCR_CFR | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) |
CFR - Analog Comparator Flag Rising 0b0..Rising-edge on COUT has not been detected. 0b1..Rising-edge on COUT has occurred.
Definition at line 8669 of file MIMXRT1052.h.
◆ CMP_SCR_CFR_MASK
| #define CMP_SCR_CFR_MASK (0x4U) |
Definition at line 8663 of file MIMXRT1052.h.
◆ CMP_SCR_CFR_SHIFT
| #define CMP_SCR_CFR_SHIFT (2U) |
Definition at line 8664 of file MIMXRT1052.h.
◆ CMP_SCR_COUT
| #define CMP_SCR_COUT | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) |
COUT - Analog Comparator Output
Definition at line 8655 of file MIMXRT1052.h.
◆ CMP_SCR_COUT_MASK
| #define CMP_SCR_COUT_MASK (0x1U) |
Definition at line 8651 of file MIMXRT1052.h.
◆ CMP_SCR_COUT_SHIFT
| #define CMP_SCR_COUT_SHIFT (0U) |
Definition at line 8652 of file MIMXRT1052.h.
◆ CMP_SCR_DMAEN
| #define CMP_SCR_DMAEN | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) |
DMAEN - DMA Enable Control 0b0..DMA is disabled. 0b1..DMA is enabled.
Definition at line 8690 of file MIMXRT1052.h.
◆ CMP_SCR_DMAEN_MASK
| #define CMP_SCR_DMAEN_MASK (0x40U) |
Definition at line 8684 of file MIMXRT1052.h.
◆ CMP_SCR_DMAEN_SHIFT
| #define CMP_SCR_DMAEN_SHIFT (6U) |
Definition at line 8685 of file MIMXRT1052.h.
◆ CMP_SCR_IEF
| #define CMP_SCR_IEF | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) |
IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.
Definition at line 8676 of file MIMXRT1052.h.
◆ CMP_SCR_IEF_MASK
| #define CMP_SCR_IEF_MASK (0x8U) |
Definition at line 8670 of file MIMXRT1052.h.
◆ CMP_SCR_IEF_SHIFT
| #define CMP_SCR_IEF_SHIFT (3U) |
Definition at line 8671 of file MIMXRT1052.h.
◆ CMP_SCR_IER
| #define CMP_SCR_IER | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) |
IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.
Definition at line 8683 of file MIMXRT1052.h.
◆ CMP_SCR_IER_MASK
| #define CMP_SCR_IER_MASK (0x10U) |
Definition at line 8677 of file MIMXRT1052.h.
◆ CMP_SCR_IER_SHIFT
| #define CMP_SCR_IER_SHIFT (4U) |
Definition at line 8678 of file MIMXRT1052.h.