CCM Register Masks

Collaboration diagram for CCM Register Masks:

CCR - CCM Control Register
#define	CCM_CCR_OSCNT_MASK   (0xFFU)
#define	CCM_CCR_OSCNT_SHIFT   (0U)
#define	CCM_CCR_OSCNT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
#define	CCM_CCR_COSC_EN_MASK   (0x1000U)
#define	CCM_CCR_COSC_EN_SHIFT   (12U)
#define	CCM_CCR_COSC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
#define	CCM_CCR_REG_BYPASS_COUNT_MASK   (0x7E00000U)
#define	CCM_CCR_REG_BYPASS_COUNT_SHIFT   (21U)
#define	CCM_CCR_REG_BYPASS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
#define	CCM_CCR_RBC_EN_MASK   (0x8000000U)
#define	CCM_CCR_RBC_EN_SHIFT   (27U)
#define	CCM_CCR_RBC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)

CSR - CCM Status Register
#define	CCM_CSR_REF_EN_B_MASK   (0x1U)
#define	CCM_CSR_REF_EN_B_SHIFT   (0U)
#define	CCM_CSR_REF_EN_B(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
#define	CCM_CSR_CAMP2_READY_MASK   (0x8U)
#define	CCM_CSR_CAMP2_READY_SHIFT   (3U)
#define	CCM_CSR_CAMP2_READY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
#define	CCM_CSR_COSC_READY_MASK   (0x20U)
#define	CCM_CSR_COSC_READY_SHIFT   (5U)
#define	CCM_CSR_COSC_READY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)

CCSR - CCM Clock Switcher Register
#define	CCM_CCSR_PLL3_SW_CLK_SEL_MASK   (0x1U)
#define	CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT   (0U)
#define	CCM_CCSR_PLL3_SW_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)

CACRR - CCM Arm Clock Root Register
#define	CCM_CACRR_ARM_PODF_MASK   (0x7U)
#define	CCM_CACRR_ARM_PODF_SHIFT   (0U)
#define	CCM_CACRR_ARM_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)

CBCDR - CCM Bus Clock Divider Register
#define	CCM_CBCDR_SEMC_CLK_SEL_MASK   (0x40U)
#define	CCM_CBCDR_SEMC_CLK_SEL_SHIFT   (6U)
#define	CCM_CBCDR_SEMC_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
#define	CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK   (0x80U)
#define	CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT   (7U)
#define	CCM_CBCDR_SEMC_ALT_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
#define	CCM_CBCDR_IPG_PODF_MASK   (0x300U)
#define	CCM_CBCDR_IPG_PODF_SHIFT   (8U)
#define	CCM_CBCDR_IPG_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
#define	CCM_CBCDR_AHB_PODF_MASK   (0x1C00U)
#define	CCM_CBCDR_AHB_PODF_SHIFT   (10U)
#define	CCM_CBCDR_AHB_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
#define	CCM_CBCDR_SEMC_PODF_MASK   (0x70000U)
#define	CCM_CBCDR_SEMC_PODF_SHIFT   (16U)
#define	CCM_CBCDR_SEMC_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
#define	CCM_CBCDR_PERIPH_CLK_SEL_MASK   (0x2000000U)
#define	CCM_CBCDR_PERIPH_CLK_SEL_SHIFT   (25U)
#define	CCM_CBCDR_PERIPH_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
#define	CCM_CBCDR_PERIPH_CLK2_PODF_MASK   (0x38000000U)
#define	CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT   (27U)
#define	CCM_CBCDR_PERIPH_CLK2_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)

CBCMR - CCM Bus Clock Multiplexer Register
#define	CCM_CBCMR_LPSPI_CLK_SEL_MASK   (0x30U)
#define	CCM_CBCMR_LPSPI_CLK_SEL_SHIFT   (4U)
#define	CCM_CBCMR_LPSPI_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
#define	CCM_CBCMR_PERIPH_CLK2_SEL_MASK   (0x3000U)
#define	CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT   (12U)
#define	CCM_CBCMR_PERIPH_CLK2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
#define	CCM_CBCMR_TRACE_CLK_SEL_MASK   (0xC000U)
#define	CCM_CBCMR_TRACE_CLK_SEL_SHIFT   (14U)
#define	CCM_CBCMR_TRACE_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
#define	CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK   (0xC0000U)
#define	CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT   (18U)
#define	CCM_CBCMR_PRE_PERIPH_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
#define	CCM_CBCMR_LCDIF_PODF_MASK   (0x3800000U)
#define	CCM_CBCMR_LCDIF_PODF_SHIFT   (23U)
#define	CCM_CBCMR_LCDIF_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
#define	CCM_CBCMR_LPSPI_PODF_MASK   (0x1C000000U)
#define	CCM_CBCMR_LPSPI_PODF_SHIFT   (26U)
#define	CCM_CBCMR_LPSPI_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)

CSCMR1 - CCM Serial Clock Multiplexer Register 1
#define	CCM_CSCMR1_PERCLK_PODF_MASK   (0x3FU)
#define	CCM_CSCMR1_PERCLK_PODF_SHIFT   (0U)
#define	CCM_CSCMR1_PERCLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
#define	CCM_CSCMR1_PERCLK_CLK_SEL_MASK   (0x40U)
#define	CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT   (6U)
#define	CCM_CSCMR1_PERCLK_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
#define	CCM_CSCMR1_SAI1_CLK_SEL_MASK   (0xC00U)
#define	CCM_CSCMR1_SAI1_CLK_SEL_SHIFT   (10U)
#define	CCM_CSCMR1_SAI1_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
#define	CCM_CSCMR1_SAI2_CLK_SEL_MASK   (0x3000U)
#define	CCM_CSCMR1_SAI2_CLK_SEL_SHIFT   (12U)
#define	CCM_CSCMR1_SAI2_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
#define	CCM_CSCMR1_SAI3_CLK_SEL_MASK   (0xC000U)
#define	CCM_CSCMR1_SAI3_CLK_SEL_SHIFT   (14U)
#define	CCM_CSCMR1_SAI3_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
#define	CCM_CSCMR1_USDHC1_CLK_SEL_MASK   (0x10000U)
#define	CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT   (16U)
#define	CCM_CSCMR1_USDHC1_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
#define	CCM_CSCMR1_USDHC2_CLK_SEL_MASK   (0x20000U)
#define	CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT   (17U)
#define	CCM_CSCMR1_USDHC2_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
#define	CCM_CSCMR1_FLEXSPI_PODF_MASK   (0x3800000U)
#define	CCM_CSCMR1_FLEXSPI_PODF_SHIFT   (23U)
#define	CCM_CSCMR1_FLEXSPI_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
#define	CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK   (0x60000000U)
#define	CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT   (29U)
#define	CCM_CSCMR1_FLEXSPI_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)

CSCMR2 - CCM Serial Clock Multiplexer Register 2
#define	CCM_CSCMR2_CAN_CLK_PODF_MASK   (0xFCU)
#define	CCM_CSCMR2_CAN_CLK_PODF_SHIFT   (2U)
#define	CCM_CSCMR2_CAN_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
#define	CCM_CSCMR2_CAN_CLK_SEL_MASK   (0x300U)
#define	CCM_CSCMR2_CAN_CLK_SEL_SHIFT   (8U)
#define	CCM_CSCMR2_CAN_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
#define	CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK   (0x180000U)
#define	CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT   (19U)
#define	CCM_CSCMR2_FLEXIO2_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)

CSCDR1 - CCM Serial Clock Divider Register 1
#define	CCM_CSCDR1_UART_CLK_PODF_MASK   (0x3FU)
#define	CCM_CSCDR1_UART_CLK_PODF_SHIFT   (0U)
#define	CCM_CSCDR1_UART_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
#define	CCM_CSCDR1_UART_CLK_SEL_MASK   (0x40U)
#define	CCM_CSCDR1_UART_CLK_SEL_SHIFT   (6U)
#define	CCM_CSCDR1_UART_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
#define	CCM_CSCDR1_USDHC1_PODF_MASK   (0x3800U)
#define	CCM_CSCDR1_USDHC1_PODF_SHIFT   (11U)
#define	CCM_CSCDR1_USDHC1_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
#define	CCM_CSCDR1_USDHC2_PODF_MASK   (0x70000U)
#define	CCM_CSCDR1_USDHC2_PODF_SHIFT   (16U)
#define	CCM_CSCDR1_USDHC2_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
#define	CCM_CSCDR1_TRACE_PODF_MASK   (0x6000000U)
#define	CCM_CSCDR1_TRACE_PODF_SHIFT   (25U)
#define	CCM_CSCDR1_TRACE_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)

CS1CDR - CCM Clock Divider Register
#define	CCM_CS1CDR_SAI1_CLK_PODF_MASK   (0x3FU)
#define	CCM_CS1CDR_SAI1_CLK_PODF_SHIFT   (0U)
#define	CCM_CS1CDR_SAI1_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
#define	CCM_CS1CDR_SAI1_CLK_PRED_MASK   (0x1C0U)
#define	CCM_CS1CDR_SAI1_CLK_PRED_SHIFT   (6U)
#define	CCM_CS1CDR_SAI1_CLK_PRED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
#define	CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK   (0xE00U)
#define	CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT   (9U)
#define	CCM_CS1CDR_FLEXIO2_CLK_PRED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
#define	CCM_CS1CDR_SAI3_CLK_PODF_MASK   (0x3F0000U)
#define	CCM_CS1CDR_SAI3_CLK_PODF_SHIFT   (16U)
#define	CCM_CS1CDR_SAI3_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
#define	CCM_CS1CDR_SAI3_CLK_PRED_MASK   (0x1C00000U)
#define	CCM_CS1CDR_SAI3_CLK_PRED_SHIFT   (22U)
#define	CCM_CS1CDR_SAI3_CLK_PRED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
#define	CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK   (0xE000000U)
#define	CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT   (25U)
#define	CCM_CS1CDR_FLEXIO2_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)

CS2CDR - CCM Clock Divider Register
#define	CCM_CS2CDR_SAI2_CLK_PODF_MASK   (0x3FU)
#define	CCM_CS2CDR_SAI2_CLK_PODF_SHIFT   (0U)
#define	CCM_CS2CDR_SAI2_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
#define	CCM_CS2CDR_SAI2_CLK_PRED_MASK   (0x1C0U)
#define	CCM_CS2CDR_SAI2_CLK_PRED_SHIFT   (6U)
#define	CCM_CS2CDR_SAI2_CLK_PRED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)

CDCDR - CCM D1 Clock Divider Register
#define	CCM_CDCDR_FLEXIO1_CLK_SEL_MASK   (0x180U)
#define	CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT   (7U)
#define	CCM_CDCDR_FLEXIO1_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
#define	CCM_CDCDR_FLEXIO1_CLK_PODF_MASK   (0xE00U)
#define	CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT   (9U)
#define	CCM_CDCDR_FLEXIO1_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
#define	CCM_CDCDR_FLEXIO1_CLK_PRED_MASK   (0x7000U)
#define	CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT   (12U)
#define	CCM_CDCDR_FLEXIO1_CLK_PRED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
#define	CCM_CDCDR_SPDIF0_CLK_SEL_MASK   (0x300000U)
#define	CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT   (20U)
#define	CCM_CDCDR_SPDIF0_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
#define	CCM_CDCDR_SPDIF0_CLK_PODF_MASK   (0x1C00000U)
#define	CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT   (22U)
#define	CCM_CDCDR_SPDIF0_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
#define	CCM_CDCDR_SPDIF0_CLK_PRED_MASK   (0xE000000U)
#define	CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT   (25U)
#define	CCM_CDCDR_SPDIF0_CLK_PRED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)

CSCDR2 - CCM Serial Clock Divider Register 2
#define	CCM_CSCDR2_LCDIF_PRED_MASK   (0x7000U)
#define	CCM_CSCDR2_LCDIF_PRED_SHIFT   (12U)
#define	CCM_CSCDR2_LCDIF_PRED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
#define	CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK   (0x38000U)
#define	CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT   (15U)
#define	CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
#define	CCM_CSCDR2_LPI2C_CLK_SEL_MASK   (0x40000U)
#define	CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT   (18U)
#define	CCM_CSCDR2_LPI2C_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
#define	CCM_CSCDR2_LPI2C_CLK_PODF_MASK   (0x1F80000U)
#define	CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT   (19U)
#define	CCM_CSCDR2_LPI2C_CLK_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)

CSCDR3 - CCM Serial Clock Divider Register 3
#define	CCM_CSCDR3_CSI_CLK_SEL_MASK   (0x600U)
#define	CCM_CSCDR3_CSI_CLK_SEL_SHIFT   (9U)
#define	CCM_CSCDR3_CSI_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
#define	CCM_CSCDR3_CSI_PODF_MASK   (0x3800U)
#define	CCM_CSCDR3_CSI_PODF_SHIFT   (11U)
#define	CCM_CSCDR3_CSI_PODF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)

CDHIPR - CCM Divider Handshake In-Process Register
#define	CCM_CDHIPR_SEMC_PODF_BUSY_MASK   (0x1U)
#define	CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT   (0U)
#define	CCM_CDHIPR_SEMC_PODF_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
#define	CCM_CDHIPR_AHB_PODF_BUSY_MASK   (0x2U)
#define	CCM_CDHIPR_AHB_PODF_BUSY_SHIFT   (1U)
#define	CCM_CDHIPR_AHB_PODF_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
#define	CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK   (0x8U)
#define	CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT   (3U)
#define	CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
#define	CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK   (0x20U)
#define	CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT   (5U)
#define	CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
#define	CCM_CDHIPR_ARM_PODF_BUSY_MASK   (0x10000U)
#define	CCM_CDHIPR_ARM_PODF_BUSY_SHIFT   (16U)
#define	CCM_CDHIPR_ARM_PODF_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)

CLPCR - CCM Low Power Control Register
#define	CCM_CLPCR_LPM_MASK   (0x3U)
#define	CCM_CLPCR_LPM_SHIFT   (0U)
#define	CCM_CLPCR_LPM(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
#define	CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK   (0x20U)
#define	CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT   (5U)
#define	CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
#define	CCM_CLPCR_SBYOS_MASK   (0x40U)
#define	CCM_CLPCR_SBYOS_SHIFT   (6U)
#define	CCM_CLPCR_SBYOS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
#define	CCM_CLPCR_DIS_REF_OSC_MASK   (0x80U)
#define	CCM_CLPCR_DIS_REF_OSC_SHIFT   (7U)
#define	CCM_CLPCR_DIS_REF_OSC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
#define	CCM_CLPCR_VSTBY_MASK   (0x100U)
#define	CCM_CLPCR_VSTBY_SHIFT   (8U)
#define	CCM_CLPCR_VSTBY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
#define	CCM_CLPCR_STBY_COUNT_MASK   (0x600U)
#define	CCM_CLPCR_STBY_COUNT_SHIFT   (9U)
#define	CCM_CLPCR_STBY_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
#define	CCM_CLPCR_COSC_PWRDOWN_MASK   (0x800U)
#define	CCM_CLPCR_COSC_PWRDOWN_SHIFT   (11U)
#define	CCM_CLPCR_COSC_PWRDOWN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
#define	CCM_CLPCR_BYPASS_LPM_HS1_MASK   (0x80000U)
#define	CCM_CLPCR_BYPASS_LPM_HS1_SHIFT   (19U)
#define	CCM_CLPCR_BYPASS_LPM_HS1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
#define	CCM_CLPCR_BYPASS_LPM_HS0_MASK   (0x200000U)
#define	CCM_CLPCR_BYPASS_LPM_HS0_SHIFT   (21U)
#define	CCM_CLPCR_BYPASS_LPM_HS0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
#define	CCM_CLPCR_MASK_CORE0_WFI_MASK   (0x400000U)
#define	CCM_CLPCR_MASK_CORE0_WFI_SHIFT   (22U)
#define	CCM_CLPCR_MASK_CORE0_WFI(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
#define	CCM_CLPCR_MASK_SCU_IDLE_MASK   (0x4000000U)
#define	CCM_CLPCR_MASK_SCU_IDLE_SHIFT   (26U)
#define	CCM_CLPCR_MASK_SCU_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
#define	CCM_CLPCR_MASK_L2CC_IDLE_MASK   (0x8000000U)
#define	CCM_CLPCR_MASK_L2CC_IDLE_SHIFT   (27U)
#define	CCM_CLPCR_MASK_L2CC_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)

CISR - CCM Interrupt Status Register
#define	CCM_CISR_LRF_PLL_MASK   (0x1U)
#define	CCM_CISR_LRF_PLL_SHIFT   (0U)
#define	CCM_CISR_LRF_PLL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
#define	CCM_CISR_COSC_READY_MASK   (0x40U)
#define	CCM_CISR_COSC_READY_SHIFT   (6U)
#define	CCM_CISR_COSC_READY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
#define	CCM_CISR_SEMC_PODF_LOADED_MASK   (0x20000U)
#define	CCM_CISR_SEMC_PODF_LOADED_SHIFT   (17U)
#define	CCM_CISR_SEMC_PODF_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
#define	CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK   (0x80000U)
#define	CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT   (19U)
#define	CCM_CISR_PERIPH2_CLK_SEL_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
#define	CCM_CISR_AHB_PODF_LOADED_MASK   (0x100000U)
#define	CCM_CISR_AHB_PODF_LOADED_SHIFT   (20U)
#define	CCM_CISR_AHB_PODF_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
#define	CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK   (0x400000U)
#define	CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT   (22U)
#define	CCM_CISR_PERIPH_CLK_SEL_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
#define	CCM_CISR_ARM_PODF_LOADED_MASK   (0x4000000U)
#define	CCM_CISR_ARM_PODF_LOADED_SHIFT   (26U)
#define	CCM_CISR_ARM_PODF_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)

CIMR - CCM Interrupt Mask Register
#define	CCM_CIMR_MASK_LRF_PLL_MASK   (0x1U)
#define	CCM_CIMR_MASK_LRF_PLL_SHIFT   (0U)
#define	CCM_CIMR_MASK_LRF_PLL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
#define	CCM_CIMR_MASK_COSC_READY_MASK   (0x40U)
#define	CCM_CIMR_MASK_COSC_READY_SHIFT   (6U)
#define	CCM_CIMR_MASK_COSC_READY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
#define	CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK   (0x20000U)
#define	CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT   (17U)
#define	CCM_CIMR_MASK_SEMC_PODF_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
#define	CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK   (0x80000U)
#define	CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT   (19U)
#define	CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
#define	CCM_CIMR_MASK_AHB_PODF_LOADED_MASK   (0x100000U)
#define	CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT   (20U)
#define	CCM_CIMR_MASK_AHB_PODF_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
#define	CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK   (0x400000U)
#define	CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT   (22U)
#define	CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
#define	CCM_CIMR_ARM_PODF_LOADED_MASK   (0x4000000U)
#define	CCM_CIMR_ARM_PODF_LOADED_SHIFT   (26U)
#define	CCM_CIMR_ARM_PODF_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)

CCOSR - CCM Clock Output Source Register
#define	CCM_CCOSR_CLKO1_SEL_MASK   (0xFU)
#define	CCM_CCOSR_CLKO1_SEL_SHIFT   (0U)
#define	CCM_CCOSR_CLKO1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
#define	CCM_CCOSR_CLKO1_DIV_MASK   (0x70U)
#define	CCM_CCOSR_CLKO1_DIV_SHIFT   (4U)
#define	CCM_CCOSR_CLKO1_DIV(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
#define	CCM_CCOSR_CLKO1_EN_MASK   (0x80U)
#define	CCM_CCOSR_CLKO1_EN_SHIFT   (7U)
#define	CCM_CCOSR_CLKO1_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
#define	CCM_CCOSR_CLK_OUT_SEL_MASK   (0x100U)
#define	CCM_CCOSR_CLK_OUT_SEL_SHIFT   (8U)
#define	CCM_CCOSR_CLK_OUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
#define	CCM_CCOSR_CLKO2_SEL_MASK   (0x1F0000U)
#define	CCM_CCOSR_CLKO2_SEL_SHIFT   (16U)
#define	CCM_CCOSR_CLKO2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
#define	CCM_CCOSR_CLKO2_DIV_MASK   (0xE00000U)
#define	CCM_CCOSR_CLKO2_DIV_SHIFT   (21U)
#define	CCM_CCOSR_CLKO2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
#define	CCM_CCOSR_CLKO2_EN_MASK   (0x1000000U)
#define	CCM_CCOSR_CLKO2_EN_SHIFT   (24U)
#define	CCM_CCOSR_CLKO2_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)

CGPR - CCM General Purpose Register
#define	CCM_CGPR_PMIC_DELAY_SCALER_MASK   (0x1U)
#define	CCM_CGPR_PMIC_DELAY_SCALER_SHIFT   (0U)
#define	CCM_CGPR_PMIC_DELAY_SCALER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
#define	CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK   (0x10U)
#define	CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT   (4U)
#define	CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
#define	CCM_CGPR_SYS_MEM_DS_CTRL_MASK   (0xC000U)
#define	CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT   (14U)
#define	CCM_CGPR_SYS_MEM_DS_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
#define	CCM_CGPR_FPL_MASK   (0x10000U)
#define	CCM_CGPR_FPL_SHIFT   (16U)
#define	CCM_CGPR_FPL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
#define	CCM_CGPR_INT_MEM_CLK_LPM_MASK   (0x20000U)
#define	CCM_CGPR_INT_MEM_CLK_LPM_SHIFT   (17U)
#define	CCM_CGPR_INT_MEM_CLK_LPM(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)

CCGR0 - CCM Clock Gating Register 0
#define	CCM_CCGR0_CG0_MASK   (0x3U)
#define	CCM_CCGR0_CG0_SHIFT   (0U)
#define	CCM_CCGR0_CG0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
#define	CCM_CCGR0_CG1_MASK   (0xCU)
#define	CCM_CCGR0_CG1_SHIFT   (2U)
#define	CCM_CCGR0_CG1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
#define	CCM_CCGR0_CG2_MASK   (0x30U)
#define	CCM_CCGR0_CG2_SHIFT   (4U)
#define	CCM_CCGR0_CG2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
#define	CCM_CCGR0_CG3_MASK   (0xC0U)
#define	CCM_CCGR0_CG3_SHIFT   (6U)
#define	CCM_CCGR0_CG3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
#define	CCM_CCGR0_CG4_MASK   (0x300U)
#define	CCM_CCGR0_CG4_SHIFT   (8U)
#define	CCM_CCGR0_CG4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
#define	CCM_CCGR0_CG5_MASK   (0xC00U)
#define	CCM_CCGR0_CG5_SHIFT   (10U)
#define	CCM_CCGR0_CG5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
#define	CCM_CCGR0_CG6_MASK   (0x3000U)
#define	CCM_CCGR0_CG6_SHIFT   (12U)
#define	CCM_CCGR0_CG6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
#define	CCM_CCGR0_CG7_MASK   (0xC000U)
#define	CCM_CCGR0_CG7_SHIFT   (14U)
#define	CCM_CCGR0_CG7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
#define	CCM_CCGR0_CG8_MASK   (0x30000U)
#define	CCM_CCGR0_CG8_SHIFT   (16U)
#define	CCM_CCGR0_CG8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
#define	CCM_CCGR0_CG9_MASK   (0xC0000U)
#define	CCM_CCGR0_CG9_SHIFT   (18U)
#define	CCM_CCGR0_CG9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
#define	CCM_CCGR0_CG10_MASK   (0x300000U)
#define	CCM_CCGR0_CG10_SHIFT   (20U)
#define	CCM_CCGR0_CG10(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
#define	CCM_CCGR0_CG11_MASK   (0xC00000U)
#define	CCM_CCGR0_CG11_SHIFT   (22U)
#define	CCM_CCGR0_CG11(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
#define	CCM_CCGR0_CG12_MASK   (0x3000000U)
#define	CCM_CCGR0_CG12_SHIFT   (24U)
#define	CCM_CCGR0_CG12(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
#define	CCM_CCGR0_CG13_MASK   (0xC000000U)
#define	CCM_CCGR0_CG13_SHIFT   (26U)
#define	CCM_CCGR0_CG13(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
#define	CCM_CCGR0_CG14_MASK   (0x30000000U)
#define	CCM_CCGR0_CG14_SHIFT   (28U)
#define	CCM_CCGR0_CG14(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
#define	CCM_CCGR0_CG15_MASK   (0xC0000000U)
#define	CCM_CCGR0_CG15_SHIFT   (30U)
#define	CCM_CCGR0_CG15(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)

CCGR1 - CCM Clock Gating Register 1
#define	CCM_CCGR1_CG0_MASK   (0x3U)
#define	CCM_CCGR1_CG0_SHIFT   (0U)
#define	CCM_CCGR1_CG0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
#define	CCM_CCGR1_CG1_MASK   (0xCU)
#define	CCM_CCGR1_CG1_SHIFT   (2U)
#define	CCM_CCGR1_CG1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
#define	CCM_CCGR1_CG2_MASK   (0x30U)
#define	CCM_CCGR1_CG2_SHIFT   (4U)
#define	CCM_CCGR1_CG2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
#define	CCM_CCGR1_CG3_MASK   (0xC0U)
#define	CCM_CCGR1_CG3_SHIFT   (6U)
#define	CCM_CCGR1_CG3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
#define	CCM_CCGR1_CG4_MASK   (0x300U)
#define	CCM_CCGR1_CG4_SHIFT   (8U)
#define	CCM_CCGR1_CG4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
#define	CCM_CCGR1_CG5_MASK   (0xC00U)
#define	CCM_CCGR1_CG5_SHIFT   (10U)
#define	CCM_CCGR1_CG5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
#define	CCM_CCGR1_CG6_MASK   (0x3000U)
#define	CCM_CCGR1_CG6_SHIFT   (12U)
#define	CCM_CCGR1_CG6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
#define	CCM_CCGR1_CG7_MASK   (0xC000U)
#define	CCM_CCGR1_CG7_SHIFT   (14U)
#define	CCM_CCGR1_CG7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
#define	CCM_CCGR1_CG8_MASK   (0x30000U)
#define	CCM_CCGR1_CG8_SHIFT   (16U)
#define	CCM_CCGR1_CG8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
#define	CCM_CCGR1_CG9_MASK   (0xC0000U)
#define	CCM_CCGR1_CG9_SHIFT   (18U)
#define	CCM_CCGR1_CG9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
#define	CCM_CCGR1_CG10_MASK   (0x300000U)
#define	CCM_CCGR1_CG10_SHIFT   (20U)
#define	CCM_CCGR1_CG10(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
#define	CCM_CCGR1_CG11_MASK   (0xC00000U)
#define	CCM_CCGR1_CG11_SHIFT   (22U)
#define	CCM_CCGR1_CG11(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
#define	CCM_CCGR1_CG12_MASK   (0x3000000U)
#define	CCM_CCGR1_CG12_SHIFT   (24U)
#define	CCM_CCGR1_CG12(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
#define	CCM_CCGR1_CG13_MASK   (0xC000000U)
#define	CCM_CCGR1_CG13_SHIFT   (26U)
#define	CCM_CCGR1_CG13(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
#define	CCM_CCGR1_CG14_MASK   (0x30000000U)
#define	CCM_CCGR1_CG14_SHIFT   (28U)
#define	CCM_CCGR1_CG14(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
#define	CCM_CCGR1_CG15_MASK   (0xC0000000U)
#define	CCM_CCGR1_CG15_SHIFT   (30U)
#define	CCM_CCGR1_CG15(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)

CCGR2 - CCM Clock Gating Register 2
#define	CCM_CCGR2_CG0_MASK   (0x3U)
#define	CCM_CCGR2_CG0_SHIFT   (0U)
#define	CCM_CCGR2_CG0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
#define	CCM_CCGR2_CG1_MASK   (0xCU)
#define	CCM_CCGR2_CG1_SHIFT   (2U)
#define	CCM_CCGR2_CG1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
#define	CCM_CCGR2_CG2_MASK   (0x30U)
#define	CCM_CCGR2_CG2_SHIFT   (4U)
#define	CCM_CCGR2_CG2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
#define	CCM_CCGR2_CG3_MASK   (0xC0U)
#define	CCM_CCGR2_CG3_SHIFT   (6U)
#define	CCM_CCGR2_CG3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
#define	CCM_CCGR2_CG4_MASK   (0x300U)
#define	CCM_CCGR2_CG4_SHIFT   (8U)
#define	CCM_CCGR2_CG4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
#define	CCM_CCGR2_CG5_MASK   (0xC00U)
#define	CCM_CCGR2_CG5_SHIFT   (10U)
#define	CCM_CCGR2_CG5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
#define	CCM_CCGR2_CG6_MASK   (0x3000U)
#define	CCM_CCGR2_CG6_SHIFT   (12U)
#define	CCM_CCGR2_CG6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
#define	CCM_CCGR2_CG7_MASK   (0xC000U)
#define	CCM_CCGR2_CG7_SHIFT   (14U)
#define	CCM_CCGR2_CG7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
#define	CCM_CCGR2_CG8_MASK   (0x30000U)
#define	CCM_CCGR2_CG8_SHIFT   (16U)
#define	CCM_CCGR2_CG8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
#define	CCM_CCGR2_CG9_MASK   (0xC0000U)
#define	CCM_CCGR2_CG9_SHIFT   (18U)
#define	CCM_CCGR2_CG9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
#define	CCM_CCGR2_CG10_MASK   (0x300000U)
#define	CCM_CCGR2_CG10_SHIFT   (20U)
#define	CCM_CCGR2_CG10(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
#define	CCM_CCGR2_CG11_MASK   (0xC00000U)
#define	CCM_CCGR2_CG11_SHIFT   (22U)
#define	CCM_CCGR2_CG11(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
#define	CCM_CCGR2_CG12_MASK   (0x3000000U)
#define	CCM_CCGR2_CG12_SHIFT   (24U)
#define	CCM_CCGR2_CG12(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
#define	CCM_CCGR2_CG13_MASK   (0xC000000U)
#define	CCM_CCGR2_CG13_SHIFT   (26U)
#define	CCM_CCGR2_CG13(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
#define	CCM_CCGR2_CG14_MASK   (0x30000000U)
#define	CCM_CCGR2_CG14_SHIFT   (28U)
#define	CCM_CCGR2_CG14(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
#define	CCM_CCGR2_CG15_MASK   (0xC0000000U)
#define	CCM_CCGR2_CG15_SHIFT   (30U)
#define	CCM_CCGR2_CG15(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)

CCGR3 - CCM Clock Gating Register 3
#define	CCM_CCGR3_CG0_MASK   (0x3U)
#define	CCM_CCGR3_CG0_SHIFT   (0U)
#define	CCM_CCGR3_CG0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
#define	CCM_CCGR3_CG1_MASK   (0xCU)
#define	CCM_CCGR3_CG1_SHIFT   (2U)
#define	CCM_CCGR3_CG1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
#define	CCM_CCGR3_CG2_MASK   (0x30U)
#define	CCM_CCGR3_CG2_SHIFT   (4U)
#define	CCM_CCGR3_CG2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
#define	CCM_CCGR3_CG3_MASK   (0xC0U)
#define	CCM_CCGR3_CG3_SHIFT   (6U)
#define	CCM_CCGR3_CG3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
#define	CCM_CCGR3_CG4_MASK   (0x300U)
#define	CCM_CCGR3_CG4_SHIFT   (8U)
#define	CCM_CCGR3_CG4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
#define	CCM_CCGR3_CG5_MASK   (0xC00U)
#define	CCM_CCGR3_CG5_SHIFT   (10U)
#define	CCM_CCGR3_CG5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
#define	CCM_CCGR3_CG6_MASK   (0x3000U)
#define	CCM_CCGR3_CG6_SHIFT   (12U)
#define	CCM_CCGR3_CG6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
#define	CCM_CCGR3_CG7_MASK   (0xC000U)
#define	CCM_CCGR3_CG7_SHIFT   (14U)
#define	CCM_CCGR3_CG7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
#define	CCM_CCGR3_CG8_MASK   (0x30000U)
#define	CCM_CCGR3_CG8_SHIFT   (16U)
#define	CCM_CCGR3_CG8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
#define	CCM_CCGR3_CG9_MASK   (0xC0000U)
#define	CCM_CCGR3_CG9_SHIFT   (18U)
#define	CCM_CCGR3_CG9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
#define	CCM_CCGR3_CG10_MASK   (0x300000U)
#define	CCM_CCGR3_CG10_SHIFT   (20U)
#define	CCM_CCGR3_CG10(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
#define	CCM_CCGR3_CG11_MASK   (0xC00000U)
#define	CCM_CCGR3_CG11_SHIFT   (22U)
#define	CCM_CCGR3_CG11(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
#define	CCM_CCGR3_CG12_MASK   (0x3000000U)
#define	CCM_CCGR3_CG12_SHIFT   (24U)
#define	CCM_CCGR3_CG12(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
#define	CCM_CCGR3_CG13_MASK   (0xC000000U)
#define	CCM_CCGR3_CG13_SHIFT   (26U)
#define	CCM_CCGR3_CG13(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
#define	CCM_CCGR3_CG14_MASK   (0x30000000U)
#define	CCM_CCGR3_CG14_SHIFT   (28U)
#define	CCM_CCGR3_CG14(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
#define	CCM_CCGR3_CG15_MASK   (0xC0000000U)
#define	CCM_CCGR3_CG15_SHIFT   (30U)
#define	CCM_CCGR3_CG15(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)

CCGR4 - CCM Clock Gating Register 4
#define	CCM_CCGR4_CG0_MASK   (0x3U)
#define	CCM_CCGR4_CG0_SHIFT   (0U)
#define	CCM_CCGR4_CG0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
#define	CCM_CCGR4_CG1_MASK   (0xCU)
#define	CCM_CCGR4_CG1_SHIFT   (2U)
#define	CCM_CCGR4_CG1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
#define	CCM_CCGR4_CG2_MASK   (0x30U)
#define	CCM_CCGR4_CG2_SHIFT   (4U)
#define	CCM_CCGR4_CG2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
#define	CCM_CCGR4_CG3_MASK   (0xC0U)
#define	CCM_CCGR4_CG3_SHIFT   (6U)
#define	CCM_CCGR4_CG3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
#define	CCM_CCGR4_CG4_MASK   (0x300U)
#define	CCM_CCGR4_CG4_SHIFT   (8U)
#define	CCM_CCGR4_CG4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
#define	CCM_CCGR4_CG5_MASK   (0xC00U)
#define	CCM_CCGR4_CG5_SHIFT   (10U)
#define	CCM_CCGR4_CG5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
#define	CCM_CCGR4_CG6_MASK   (0x3000U)
#define	CCM_CCGR4_CG6_SHIFT   (12U)
#define	CCM_CCGR4_CG6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
#define	CCM_CCGR4_CG7_MASK   (0xC000U)
#define	CCM_CCGR4_CG7_SHIFT   (14U)
#define	CCM_CCGR4_CG7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
#define	CCM_CCGR4_CG8_MASK   (0x30000U)
#define	CCM_CCGR4_CG8_SHIFT   (16U)
#define	CCM_CCGR4_CG8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
#define	CCM_CCGR4_CG9_MASK   (0xC0000U)
#define	CCM_CCGR4_CG9_SHIFT   (18U)
#define	CCM_CCGR4_CG9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
#define	CCM_CCGR4_CG10_MASK   (0x300000U)
#define	CCM_CCGR4_CG10_SHIFT   (20U)
#define	CCM_CCGR4_CG10(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
#define	CCM_CCGR4_CG11_MASK   (0xC00000U)
#define	CCM_CCGR4_CG11_SHIFT   (22U)
#define	CCM_CCGR4_CG11(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
#define	CCM_CCGR4_CG12_MASK   (0x3000000U)
#define	CCM_CCGR4_CG12_SHIFT   (24U)
#define	CCM_CCGR4_CG12(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
#define	CCM_CCGR4_CG13_MASK   (0xC000000U)
#define	CCM_CCGR4_CG13_SHIFT   (26U)
#define	CCM_CCGR4_CG13(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
#define	CCM_CCGR4_CG14_MASK   (0x30000000U)
#define	CCM_CCGR4_CG14_SHIFT   (28U)
#define	CCM_CCGR4_CG14(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
#define	CCM_CCGR4_CG15_MASK   (0xC0000000U)
#define	CCM_CCGR4_CG15_SHIFT   (30U)
#define	CCM_CCGR4_CG15(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)

CCGR5 - CCM Clock Gating Register 5
#define	CCM_CCGR5_CG0_MASK   (0x3U)
#define	CCM_CCGR5_CG0_SHIFT   (0U)
#define	CCM_CCGR5_CG0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
#define	CCM_CCGR5_CG1_MASK   (0xCU)
#define	CCM_CCGR5_CG1_SHIFT   (2U)
#define	CCM_CCGR5_CG1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
#define	CCM_CCGR5_CG2_MASK   (0x30U)
#define	CCM_CCGR5_CG2_SHIFT   (4U)
#define	CCM_CCGR5_CG2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
#define	CCM_CCGR5_CG3_MASK   (0xC0U)
#define	CCM_CCGR5_CG3_SHIFT   (6U)
#define	CCM_CCGR5_CG3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
#define	CCM_CCGR5_CG4_MASK   (0x300U)
#define	CCM_CCGR5_CG4_SHIFT   (8U)
#define	CCM_CCGR5_CG4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
#define	CCM_CCGR5_CG5_MASK   (0xC00U)
#define	CCM_CCGR5_CG5_SHIFT   (10U)
#define	CCM_CCGR5_CG5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
#define	CCM_CCGR5_CG6_MASK   (0x3000U)
#define	CCM_CCGR5_CG6_SHIFT   (12U)
#define	CCM_CCGR5_CG6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
#define	CCM_CCGR5_CG7_MASK   (0xC000U)
#define	CCM_CCGR5_CG7_SHIFT   (14U)
#define	CCM_CCGR5_CG7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
#define	CCM_CCGR5_CG8_MASK   (0x30000U)
#define	CCM_CCGR5_CG8_SHIFT   (16U)
#define	CCM_CCGR5_CG8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
#define	CCM_CCGR5_CG9_MASK   (0xC0000U)
#define	CCM_CCGR5_CG9_SHIFT   (18U)
#define	CCM_CCGR5_CG9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
#define	CCM_CCGR5_CG10_MASK   (0x300000U)
#define	CCM_CCGR5_CG10_SHIFT   (20U)
#define	CCM_CCGR5_CG10(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
#define	CCM_CCGR5_CG11_MASK   (0xC00000U)
#define	CCM_CCGR5_CG11_SHIFT   (22U)
#define	CCM_CCGR5_CG11(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
#define	CCM_CCGR5_CG12_MASK   (0x3000000U)
#define	CCM_CCGR5_CG12_SHIFT   (24U)
#define	CCM_CCGR5_CG12(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
#define	CCM_CCGR5_CG13_MASK   (0xC000000U)
#define	CCM_CCGR5_CG13_SHIFT   (26U)
#define	CCM_CCGR5_CG13(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
#define	CCM_CCGR5_CG14_MASK   (0x30000000U)
#define	CCM_CCGR5_CG14_SHIFT   (28U)
#define	CCM_CCGR5_CG14(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
#define	CCM_CCGR5_CG15_MASK   (0xC0000000U)
#define	CCM_CCGR5_CG15_SHIFT   (30U)
#define	CCM_CCGR5_CG15(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)

CCGR6 - CCM Clock Gating Register 6
#define	CCM_CCGR6_CG0_MASK   (0x3U)
#define	CCM_CCGR6_CG0_SHIFT   (0U)
#define	CCM_CCGR6_CG0(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
#define	CCM_CCGR6_CG1_MASK   (0xCU)
#define	CCM_CCGR6_CG1_SHIFT   (2U)
#define	CCM_CCGR6_CG1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
#define	CCM_CCGR6_CG2_MASK   (0x30U)
#define	CCM_CCGR6_CG2_SHIFT   (4U)
#define	CCM_CCGR6_CG2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
#define	CCM_CCGR6_CG3_MASK   (0xC0U)
#define	CCM_CCGR6_CG3_SHIFT   (6U)
#define	CCM_CCGR6_CG3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
#define	CCM_CCGR6_CG4_MASK   (0x300U)
#define	CCM_CCGR6_CG4_SHIFT   (8U)
#define	CCM_CCGR6_CG4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
#define	CCM_CCGR6_CG5_MASK   (0xC00U)
#define	CCM_CCGR6_CG5_SHIFT   (10U)
#define	CCM_CCGR6_CG5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
#define	CCM_CCGR6_CG6_MASK   (0x3000U)
#define	CCM_CCGR6_CG6_SHIFT   (12U)
#define	CCM_CCGR6_CG6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
#define	CCM_CCGR6_CG7_MASK   (0xC000U)
#define	CCM_CCGR6_CG7_SHIFT   (14U)
#define	CCM_CCGR6_CG7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
#define	CCM_CCGR6_CG8_MASK   (0x30000U)
#define	CCM_CCGR6_CG8_SHIFT   (16U)
#define	CCM_CCGR6_CG8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
#define	CCM_CCGR6_CG9_MASK   (0xC0000U)
#define	CCM_CCGR6_CG9_SHIFT   (18U)
#define	CCM_CCGR6_CG9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
#define	CCM_CCGR6_CG10_MASK   (0x300000U)
#define	CCM_CCGR6_CG10_SHIFT   (20U)
#define	CCM_CCGR6_CG10(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
#define	CCM_CCGR6_CG11_MASK   (0xC00000U)
#define	CCM_CCGR6_CG11_SHIFT   (22U)
#define	CCM_CCGR6_CG11(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
#define	CCM_CCGR6_CG12_MASK   (0x3000000U)
#define	CCM_CCGR6_CG12_SHIFT   (24U)
#define	CCM_CCGR6_CG12(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
#define	CCM_CCGR6_CG13_MASK   (0xC000000U)
#define	CCM_CCGR6_CG13_SHIFT   (26U)
#define	CCM_CCGR6_CG13(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
#define	CCM_CCGR6_CG14_MASK   (0x30000000U)
#define	CCM_CCGR6_CG14_SHIFT   (28U)
#define	CCM_CCGR6_CG14(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
#define	CCM_CCGR6_CG15_MASK   (0xC0000000U)
#define	CCM_CCGR6_CG15_SHIFT   (30U)
#define	CCM_CCGR6_CG15(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)

CMEOR - CCM Module Enable Overide Register
#define	CCM_CMEOR_MOD_EN_OV_GPT_MASK   (0x20U)
#define	CCM_CMEOR_MOD_EN_OV_GPT_SHIFT   (5U)
#define	CCM_CMEOR_MOD_EN_OV_GPT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
#define	CCM_CMEOR_MOD_EN_OV_PIT_MASK   (0x40U)
#define	CCM_CMEOR_MOD_EN_OV_PIT_SHIFT   (6U)
#define	CCM_CMEOR_MOD_EN_OV_PIT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
#define	CCM_CMEOR_MOD_EN_USDHC_MASK   (0x80U)
#define	CCM_CMEOR_MOD_EN_USDHC_SHIFT   (7U)
#define	CCM_CMEOR_MOD_EN_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
#define	CCM_CMEOR_MOD_EN_OV_TRNG_MASK   (0x200U)
#define	CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT   (9U)
#define	CCM_CMEOR_MOD_EN_OV_TRNG(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
#define	CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK   (0x10000000U)
#define	CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT   (28U)
#define	CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
#define	CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK   (0x40000000U)
#define	CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT   (30U)
#define	CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)

Detailed Description

Macro Definition Documentation

CCM_CACRR_ARM_PODF

#define CCM_CACRR_ARM_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)

ARM_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4284 of file MIMXRT1052.h.

CCM_CACRR_ARM_PODF_MASK

#define CCM_CACRR_ARM_PODF_MASK   (0x7U)

Definition at line 4272 of file MIMXRT1052.h.

CCM_CACRR_ARM_PODF_SHIFT

#define CCM_CACRR_ARM_PODF_SHIFT   (0U)

Definition at line 4273 of file MIMXRT1052.h.

CCM_CBCDR_AHB_PODF

#define CCM_CBCDR_AHB_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)

AHB_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4324 of file MIMXRT1052.h.

CCM_CBCDR_AHB_PODF_MASK

#define CCM_CBCDR_AHB_PODF_MASK   (0x1C00U)

Definition at line 4312 of file MIMXRT1052.h.

CCM_CBCDR_AHB_PODF_SHIFT

#define CCM_CBCDR_AHB_PODF_SHIFT   (10U)

Definition at line 4313 of file MIMXRT1052.h.

CCM_CBCDR_IPG_PODF

#define CCM_CBCDR_IPG_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)

IPG_PODF 0b00..divide by 1 0b01..divide by 2 0b10..divide by 3 0b11..divide by 4

Definition at line 4311 of file MIMXRT1052.h.

CCM_CBCDR_IPG_PODF_MASK

#define CCM_CBCDR_IPG_PODF_MASK   (0x300U)

Definition at line 4303 of file MIMXRT1052.h.

CCM_CBCDR_IPG_PODF_SHIFT

#define CCM_CBCDR_IPG_PODF_SHIFT   (8U)

Definition at line 4304 of file MIMXRT1052.h.

CCM_CBCDR_PERIPH_CLK2_PODF

#define CCM_CBCDR_PERIPH_CLK2_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)

PERIPH_CLK2_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4357 of file MIMXRT1052.h.

CCM_CBCDR_PERIPH_CLK2_PODF_MASK

#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK   (0x38000000U)

Definition at line 4345 of file MIMXRT1052.h.

CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT

#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT   (27U)

Definition at line 4346 of file MIMXRT1052.h.

CCM_CBCDR_PERIPH_CLK_SEL

#define CCM_CBCDR_PERIPH_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)

PERIPH_CLK_SEL 0b0..derive clock from pre_periph_clk_sel 0b1..derive clock from periph_clk2_clk_divided

Definition at line 4344 of file MIMXRT1052.h.

CCM_CBCDR_PERIPH_CLK_SEL_MASK

#define CCM_CBCDR_PERIPH_CLK_SEL_MASK   (0x2000000U)

Definition at line 4338 of file MIMXRT1052.h.

CCM_CBCDR_PERIPH_CLK_SEL_SHIFT

#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT   (25U)

Definition at line 4339 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_ALT_CLK_SEL

#define CCM_CBCDR_SEMC_ALT_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)

SEMC_ALT_CLK_SEL 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock

Definition at line 4302 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK

#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK   (0x80U)

Definition at line 4296 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT

#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT   (7U)

Definition at line 4297 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_CLK_SEL

#define CCM_CBCDR_SEMC_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)

SEMC_CLK_SEL 0b0..Periph_clk output will be used as SEMC clock root 0b1..SEMC alternative clock will be used as SEMC clock root

Definition at line 4295 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_CLK_SEL_MASK

#define CCM_CBCDR_SEMC_CLK_SEL_MASK   (0x40U)

Definition at line 4289 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_CLK_SEL_SHIFT

#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT   (6U)

Definition at line 4290 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_PODF

#define CCM_CBCDR_SEMC_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)

SEMC_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4337 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_PODF_MASK

#define CCM_CBCDR_SEMC_PODF_MASK   (0x70000U)

Definition at line 4325 of file MIMXRT1052.h.

CCM_CBCDR_SEMC_PODF_SHIFT

#define CCM_CBCDR_SEMC_PODF_SHIFT   (16U)

Definition at line 4326 of file MIMXRT1052.h.

CCM_CBCMR_LCDIF_PODF

#define CCM_CBCMR_LCDIF_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)

LCDIF_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4410 of file MIMXRT1052.h.

CCM_CBCMR_LCDIF_PODF_MASK

#define CCM_CBCMR_LCDIF_PODF_MASK   (0x3800000U)

Definition at line 4398 of file MIMXRT1052.h.

CCM_CBCMR_LCDIF_PODF_SHIFT

#define CCM_CBCMR_LCDIF_PODF_SHIFT   (23U)

Definition at line 4399 of file MIMXRT1052.h.

CCM_CBCMR_LPSPI_CLK_SEL

#define CCM_CBCMR_LPSPI_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)

LPSPI_CLK_SEL 0b00..derive clock from PLL3 PFD1 clk 0b01..derive clock from PLL3 PFD0 0b10..derive clock from PLL2 0b11..derive clock from PLL2 PFD2

Definition at line 4370 of file MIMXRT1052.h.

CCM_CBCMR_LPSPI_CLK_SEL_MASK

#define CCM_CBCMR_LPSPI_CLK_SEL_MASK   (0x30U)

Definition at line 4362 of file MIMXRT1052.h.

CCM_CBCMR_LPSPI_CLK_SEL_SHIFT

#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT   (4U)

Definition at line 4363 of file MIMXRT1052.h.

CCM_CBCMR_LPSPI_PODF

#define CCM_CBCMR_LPSPI_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)

LPSPI_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4423 of file MIMXRT1052.h.

CCM_CBCMR_LPSPI_PODF_MASK

#define CCM_CBCMR_LPSPI_PODF_MASK   (0x1C000000U)

Definition at line 4411 of file MIMXRT1052.h.

CCM_CBCMR_LPSPI_PODF_SHIFT

#define CCM_CBCMR_LPSPI_PODF_SHIFT   (26U)

Definition at line 4412 of file MIMXRT1052.h.

CCM_CBCMR_PERIPH_CLK2_SEL

#define CCM_CBCMR_PERIPH_CLK2_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)

PERIPH_CLK2_SEL 0b00..derive clock from pll3_sw_clk 0b01..derive clock from osc_clk (pll1_ref_clk) 0b10..derive clock from pll2_bypass_clk 0b11..reserved

Definition at line 4379 of file MIMXRT1052.h.

CCM_CBCMR_PERIPH_CLK2_SEL_MASK

#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK   (0x3000U)

Definition at line 4371 of file MIMXRT1052.h.

CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT

#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT   (12U)

Definition at line 4372 of file MIMXRT1052.h.

CCM_CBCMR_PRE_PERIPH_CLK_SEL

#define CCM_CBCMR_PRE_PERIPH_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)

PRE_PERIPH_CLK_SEL 0b00..derive clock from PLL2 0b01..derive clock from PLL2 PFD2 0b10..derive clock from PLL2 PFD0 0b11..derive clock from divided PLL1

Definition at line 4397 of file MIMXRT1052.h.

CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK

#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK   (0xC0000U)

Definition at line 4389 of file MIMXRT1052.h.

CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT

#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT   (18U)

Definition at line 4390 of file MIMXRT1052.h.

CCM_CBCMR_TRACE_CLK_SEL

#define CCM_CBCMR_TRACE_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)

TRACE_CLK_SEL 0b00..derive clock from PLL2 0b01..derive clock from PLL2 PFD2 0b10..derive clock from PLL2 PFD0 0b11..derive clock from PLL2 PFD1

Definition at line 4388 of file MIMXRT1052.h.

CCM_CBCMR_TRACE_CLK_SEL_MASK

#define CCM_CBCMR_TRACE_CLK_SEL_MASK   (0xC000U)

Definition at line 4380 of file MIMXRT1052.h.

CCM_CBCMR_TRACE_CLK_SEL_SHIFT

#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT   (14U)

Definition at line 4381 of file MIMXRT1052.h.

CCM_CCGR0_CG0

#define CCM_CCGR0_CG0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)

Definition at line 5633 of file MIMXRT1052.h.

CCM_CCGR0_CG0_MASK

#define CCM_CCGR0_CG0_MASK   (0x3U)

Definition at line 5631 of file MIMXRT1052.h.

CCM_CCGR0_CG0_SHIFT

#define CCM_CCGR0_CG0_SHIFT   (0U)

Definition at line 5632 of file MIMXRT1052.h.

CCM_CCGR0_CG1

#define CCM_CCGR0_CG1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)

Definition at line 5636 of file MIMXRT1052.h.

CCM_CCGR0_CG10

#define CCM_CCGR0_CG10

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)

Definition at line 5663 of file MIMXRT1052.h.

CCM_CCGR0_CG10_MASK

#define CCM_CCGR0_CG10_MASK   (0x300000U)

Definition at line 5661 of file MIMXRT1052.h.

CCM_CCGR0_CG10_SHIFT

#define CCM_CCGR0_CG10_SHIFT   (20U)

Definition at line 5662 of file MIMXRT1052.h.

CCM_CCGR0_CG11

#define CCM_CCGR0_CG11

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)

Definition at line 5666 of file MIMXRT1052.h.

CCM_CCGR0_CG11_MASK

#define CCM_CCGR0_CG11_MASK   (0xC00000U)

Definition at line 5664 of file MIMXRT1052.h.

CCM_CCGR0_CG11_SHIFT

#define CCM_CCGR0_CG11_SHIFT   (22U)

Definition at line 5665 of file MIMXRT1052.h.

CCM_CCGR0_CG12

#define CCM_CCGR0_CG12

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)

Definition at line 5669 of file MIMXRT1052.h.

CCM_CCGR0_CG12_MASK

#define CCM_CCGR0_CG12_MASK   (0x3000000U)

Definition at line 5667 of file MIMXRT1052.h.

CCM_CCGR0_CG12_SHIFT

#define CCM_CCGR0_CG12_SHIFT   (24U)

Definition at line 5668 of file MIMXRT1052.h.

CCM_CCGR0_CG13

#define CCM_CCGR0_CG13

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)

Definition at line 5672 of file MIMXRT1052.h.

CCM_CCGR0_CG13_MASK

#define CCM_CCGR0_CG13_MASK   (0xC000000U)

Definition at line 5670 of file MIMXRT1052.h.

CCM_CCGR0_CG13_SHIFT

#define CCM_CCGR0_CG13_SHIFT   (26U)

Definition at line 5671 of file MIMXRT1052.h.

CCM_CCGR0_CG14

#define CCM_CCGR0_CG14

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)

Definition at line 5675 of file MIMXRT1052.h.

CCM_CCGR0_CG14_MASK

#define CCM_CCGR0_CG14_MASK   (0x30000000U)

Definition at line 5673 of file MIMXRT1052.h.

CCM_CCGR0_CG14_SHIFT

#define CCM_CCGR0_CG14_SHIFT   (28U)

Definition at line 5674 of file MIMXRT1052.h.

CCM_CCGR0_CG15

#define CCM_CCGR0_CG15

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)

Definition at line 5678 of file MIMXRT1052.h.

CCM_CCGR0_CG15_MASK

#define CCM_CCGR0_CG15_MASK   (0xC0000000U)

Definition at line 5676 of file MIMXRT1052.h.

CCM_CCGR0_CG15_SHIFT

#define CCM_CCGR0_CG15_SHIFT   (30U)

Definition at line 5677 of file MIMXRT1052.h.

CCM_CCGR0_CG1_MASK

#define CCM_CCGR0_CG1_MASK   (0xCU)

Definition at line 5634 of file MIMXRT1052.h.

CCM_CCGR0_CG1_SHIFT

#define CCM_CCGR0_CG1_SHIFT   (2U)

Definition at line 5635 of file MIMXRT1052.h.

CCM_CCGR0_CG2

#define CCM_CCGR0_CG2

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)

Definition at line 5639 of file MIMXRT1052.h.

CCM_CCGR0_CG2_MASK

#define CCM_CCGR0_CG2_MASK   (0x30U)

Definition at line 5637 of file MIMXRT1052.h.

CCM_CCGR0_CG2_SHIFT

#define CCM_CCGR0_CG2_SHIFT   (4U)

Definition at line 5638 of file MIMXRT1052.h.

CCM_CCGR0_CG3

#define CCM_CCGR0_CG3

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)

Definition at line 5642 of file MIMXRT1052.h.

CCM_CCGR0_CG3_MASK

#define CCM_CCGR0_CG3_MASK   (0xC0U)

Definition at line 5640 of file MIMXRT1052.h.

CCM_CCGR0_CG3_SHIFT

#define CCM_CCGR0_CG3_SHIFT   (6U)

Definition at line 5641 of file MIMXRT1052.h.

CCM_CCGR0_CG4

#define CCM_CCGR0_CG4

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)

Definition at line 5645 of file MIMXRT1052.h.

CCM_CCGR0_CG4_MASK

#define CCM_CCGR0_CG4_MASK   (0x300U)

Definition at line 5643 of file MIMXRT1052.h.

CCM_CCGR0_CG4_SHIFT

#define CCM_CCGR0_CG4_SHIFT   (8U)

Definition at line 5644 of file MIMXRT1052.h.

CCM_CCGR0_CG5

#define CCM_CCGR0_CG5

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)

Definition at line 5648 of file MIMXRT1052.h.

CCM_CCGR0_CG5_MASK

#define CCM_CCGR0_CG5_MASK   (0xC00U)

Definition at line 5646 of file MIMXRT1052.h.

CCM_CCGR0_CG5_SHIFT

#define CCM_CCGR0_CG5_SHIFT   (10U)

Definition at line 5647 of file MIMXRT1052.h.

CCM_CCGR0_CG6

#define CCM_CCGR0_CG6

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)

Definition at line 5651 of file MIMXRT1052.h.

CCM_CCGR0_CG6_MASK

#define CCM_CCGR0_CG6_MASK   (0x3000U)

Definition at line 5649 of file MIMXRT1052.h.

CCM_CCGR0_CG6_SHIFT

#define CCM_CCGR0_CG6_SHIFT   (12U)

Definition at line 5650 of file MIMXRT1052.h.

CCM_CCGR0_CG7

#define CCM_CCGR0_CG7

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)

Definition at line 5654 of file MIMXRT1052.h.

CCM_CCGR0_CG7_MASK

#define CCM_CCGR0_CG7_MASK   (0xC000U)

Definition at line 5652 of file MIMXRT1052.h.

CCM_CCGR0_CG7_SHIFT

#define CCM_CCGR0_CG7_SHIFT   (14U)

Definition at line 5653 of file MIMXRT1052.h.

CCM_CCGR0_CG8

#define CCM_CCGR0_CG8

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)

Definition at line 5657 of file MIMXRT1052.h.

CCM_CCGR0_CG8_MASK

#define CCM_CCGR0_CG8_MASK   (0x30000U)

Definition at line 5655 of file MIMXRT1052.h.

CCM_CCGR0_CG8_SHIFT

#define CCM_CCGR0_CG8_SHIFT   (16U)

Definition at line 5656 of file MIMXRT1052.h.

CCM_CCGR0_CG9

#define CCM_CCGR0_CG9

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)

Definition at line 5660 of file MIMXRT1052.h.

CCM_CCGR0_CG9_MASK

#define CCM_CCGR0_CG9_MASK   (0xC0000U)

Definition at line 5658 of file MIMXRT1052.h.

CCM_CCGR0_CG9_SHIFT

#define CCM_CCGR0_CG9_SHIFT   (18U)

Definition at line 5659 of file MIMXRT1052.h.

CCM_CCGR1_CG0

#define CCM_CCGR1_CG0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)

Definition at line 5685 of file MIMXRT1052.h.

CCM_CCGR1_CG0_MASK

#define CCM_CCGR1_CG0_MASK   (0x3U)

Definition at line 5683 of file MIMXRT1052.h.

CCM_CCGR1_CG0_SHIFT

#define CCM_CCGR1_CG0_SHIFT   (0U)

Definition at line 5684 of file MIMXRT1052.h.

CCM_CCGR1_CG1

#define CCM_CCGR1_CG1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)

Definition at line 5688 of file MIMXRT1052.h.

CCM_CCGR1_CG10

#define CCM_CCGR1_CG10

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)

Definition at line 5715 of file MIMXRT1052.h.

CCM_CCGR1_CG10_MASK

#define CCM_CCGR1_CG10_MASK   (0x300000U)

Definition at line 5713 of file MIMXRT1052.h.

CCM_CCGR1_CG10_SHIFT

#define CCM_CCGR1_CG10_SHIFT   (20U)

Definition at line 5714 of file MIMXRT1052.h.

CCM_CCGR1_CG11

#define CCM_CCGR1_CG11

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)

Definition at line 5718 of file MIMXRT1052.h.

CCM_CCGR1_CG11_MASK

#define CCM_CCGR1_CG11_MASK   (0xC00000U)

Definition at line 5716 of file MIMXRT1052.h.

CCM_CCGR1_CG11_SHIFT

#define CCM_CCGR1_CG11_SHIFT   (22U)

Definition at line 5717 of file MIMXRT1052.h.

CCM_CCGR1_CG12

#define CCM_CCGR1_CG12

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)

Definition at line 5721 of file MIMXRT1052.h.

CCM_CCGR1_CG12_MASK

#define CCM_CCGR1_CG12_MASK   (0x3000000U)

Definition at line 5719 of file MIMXRT1052.h.

CCM_CCGR1_CG12_SHIFT

#define CCM_CCGR1_CG12_SHIFT   (24U)

Definition at line 5720 of file MIMXRT1052.h.

CCM_CCGR1_CG13

#define CCM_CCGR1_CG13

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)

Definition at line 5724 of file MIMXRT1052.h.

CCM_CCGR1_CG13_MASK

#define CCM_CCGR1_CG13_MASK   (0xC000000U)

Definition at line 5722 of file MIMXRT1052.h.

CCM_CCGR1_CG13_SHIFT

#define CCM_CCGR1_CG13_SHIFT   (26U)

Definition at line 5723 of file MIMXRT1052.h.

CCM_CCGR1_CG14

#define CCM_CCGR1_CG14

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)

Definition at line 5727 of file MIMXRT1052.h.

CCM_CCGR1_CG14_MASK

#define CCM_CCGR1_CG14_MASK   (0x30000000U)

Definition at line 5725 of file MIMXRT1052.h.

CCM_CCGR1_CG14_SHIFT

#define CCM_CCGR1_CG14_SHIFT   (28U)

Definition at line 5726 of file MIMXRT1052.h.

CCM_CCGR1_CG15

#define CCM_CCGR1_CG15

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)

Definition at line 5730 of file MIMXRT1052.h.

CCM_CCGR1_CG15_MASK

#define CCM_CCGR1_CG15_MASK   (0xC0000000U)

Definition at line 5728 of file MIMXRT1052.h.

CCM_CCGR1_CG15_SHIFT

#define CCM_CCGR1_CG15_SHIFT   (30U)

Definition at line 5729 of file MIMXRT1052.h.

CCM_CCGR1_CG1_MASK

#define CCM_CCGR1_CG1_MASK   (0xCU)

Definition at line 5686 of file MIMXRT1052.h.

CCM_CCGR1_CG1_SHIFT

#define CCM_CCGR1_CG1_SHIFT   (2U)

Definition at line 5687 of file MIMXRT1052.h.

CCM_CCGR1_CG2

#define CCM_CCGR1_CG2

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)

Definition at line 5691 of file MIMXRT1052.h.

CCM_CCGR1_CG2_MASK

#define CCM_CCGR1_CG2_MASK   (0x30U)

Definition at line 5689 of file MIMXRT1052.h.

CCM_CCGR1_CG2_SHIFT

#define CCM_CCGR1_CG2_SHIFT   (4U)

Definition at line 5690 of file MIMXRT1052.h.

CCM_CCGR1_CG3

#define CCM_CCGR1_CG3

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)

Definition at line 5694 of file MIMXRT1052.h.

CCM_CCGR1_CG3_MASK

#define CCM_CCGR1_CG3_MASK   (0xC0U)

Definition at line 5692 of file MIMXRT1052.h.

CCM_CCGR1_CG3_SHIFT

#define CCM_CCGR1_CG3_SHIFT   (6U)

Definition at line 5693 of file MIMXRT1052.h.

CCM_CCGR1_CG4

#define CCM_CCGR1_CG4

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)

Definition at line 5697 of file MIMXRT1052.h.

CCM_CCGR1_CG4_MASK

#define CCM_CCGR1_CG4_MASK   (0x300U)

Definition at line 5695 of file MIMXRT1052.h.

CCM_CCGR1_CG4_SHIFT

#define CCM_CCGR1_CG4_SHIFT   (8U)

Definition at line 5696 of file MIMXRT1052.h.

CCM_CCGR1_CG5

#define CCM_CCGR1_CG5

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)

Definition at line 5700 of file MIMXRT1052.h.

CCM_CCGR1_CG5_MASK

#define CCM_CCGR1_CG5_MASK   (0xC00U)

Definition at line 5698 of file MIMXRT1052.h.

CCM_CCGR1_CG5_SHIFT

#define CCM_CCGR1_CG5_SHIFT   (10U)

Definition at line 5699 of file MIMXRT1052.h.

CCM_CCGR1_CG6

#define CCM_CCGR1_CG6

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)

Definition at line 5703 of file MIMXRT1052.h.

CCM_CCGR1_CG6_MASK

#define CCM_CCGR1_CG6_MASK   (0x3000U)

Definition at line 5701 of file MIMXRT1052.h.

CCM_CCGR1_CG6_SHIFT

#define CCM_CCGR1_CG6_SHIFT   (12U)

Definition at line 5702 of file MIMXRT1052.h.

CCM_CCGR1_CG7

#define CCM_CCGR1_CG7

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)

Definition at line 5706 of file MIMXRT1052.h.

CCM_CCGR1_CG7_MASK

#define CCM_CCGR1_CG7_MASK   (0xC000U)

Definition at line 5704 of file MIMXRT1052.h.

CCM_CCGR1_CG7_SHIFT

#define CCM_CCGR1_CG7_SHIFT   (14U)

Definition at line 5705 of file MIMXRT1052.h.

CCM_CCGR1_CG8

#define CCM_CCGR1_CG8

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)

Definition at line 5709 of file MIMXRT1052.h.

CCM_CCGR1_CG8_MASK

#define CCM_CCGR1_CG8_MASK   (0x30000U)

Definition at line 5707 of file MIMXRT1052.h.

CCM_CCGR1_CG8_SHIFT

#define CCM_CCGR1_CG8_SHIFT   (16U)

Definition at line 5708 of file MIMXRT1052.h.

CCM_CCGR1_CG9

#define CCM_CCGR1_CG9

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)

Definition at line 5712 of file MIMXRT1052.h.

CCM_CCGR1_CG9_MASK

#define CCM_CCGR1_CG9_MASK   (0xC0000U)

Definition at line 5710 of file MIMXRT1052.h.

CCM_CCGR1_CG9_SHIFT

#define CCM_CCGR1_CG9_SHIFT   (18U)

Definition at line 5711 of file MIMXRT1052.h.

CCM_CCGR2_CG0

#define CCM_CCGR2_CG0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)

Definition at line 5737 of file MIMXRT1052.h.

CCM_CCGR2_CG0_MASK

#define CCM_CCGR2_CG0_MASK   (0x3U)

Definition at line 5735 of file MIMXRT1052.h.

CCM_CCGR2_CG0_SHIFT

#define CCM_CCGR2_CG0_SHIFT   (0U)

Definition at line 5736 of file MIMXRT1052.h.

CCM_CCGR2_CG1

#define CCM_CCGR2_CG1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)

Definition at line 5740 of file MIMXRT1052.h.

CCM_CCGR2_CG10

#define CCM_CCGR2_CG10

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)

Definition at line 5767 of file MIMXRT1052.h.

CCM_CCGR2_CG10_MASK

#define CCM_CCGR2_CG10_MASK   (0x300000U)

Definition at line 5765 of file MIMXRT1052.h.

CCM_CCGR2_CG10_SHIFT

#define CCM_CCGR2_CG10_SHIFT   (20U)

Definition at line 5766 of file MIMXRT1052.h.

CCM_CCGR2_CG11

#define CCM_CCGR2_CG11

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)

Definition at line 5770 of file MIMXRT1052.h.

CCM_CCGR2_CG11_MASK

#define CCM_CCGR2_CG11_MASK   (0xC00000U)

Definition at line 5768 of file MIMXRT1052.h.

CCM_CCGR2_CG11_SHIFT

#define CCM_CCGR2_CG11_SHIFT   (22U)

Definition at line 5769 of file MIMXRT1052.h.

CCM_CCGR2_CG12

#define CCM_CCGR2_CG12

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)

Definition at line 5773 of file MIMXRT1052.h.

CCM_CCGR2_CG12_MASK

#define CCM_CCGR2_CG12_MASK   (0x3000000U)

Definition at line 5771 of file MIMXRT1052.h.

CCM_CCGR2_CG12_SHIFT

#define CCM_CCGR2_CG12_SHIFT   (24U)

Definition at line 5772 of file MIMXRT1052.h.

CCM_CCGR2_CG13

#define CCM_CCGR2_CG13

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)

Definition at line 5776 of file MIMXRT1052.h.

CCM_CCGR2_CG13_MASK

#define CCM_CCGR2_CG13_MASK   (0xC000000U)

Definition at line 5774 of file MIMXRT1052.h.

CCM_CCGR2_CG13_SHIFT

#define CCM_CCGR2_CG13_SHIFT   (26U)

Definition at line 5775 of file MIMXRT1052.h.

CCM_CCGR2_CG14

#define CCM_CCGR2_CG14

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)

Definition at line 5779 of file MIMXRT1052.h.

CCM_CCGR2_CG14_MASK

#define CCM_CCGR2_CG14_MASK   (0x30000000U)

Definition at line 5777 of file MIMXRT1052.h.

CCM_CCGR2_CG14_SHIFT

#define CCM_CCGR2_CG14_SHIFT   (28U)

Definition at line 5778 of file MIMXRT1052.h.

CCM_CCGR2_CG15

#define CCM_CCGR2_CG15

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)

Definition at line 5782 of file MIMXRT1052.h.

CCM_CCGR2_CG15_MASK

#define CCM_CCGR2_CG15_MASK   (0xC0000000U)

Definition at line 5780 of file MIMXRT1052.h.

CCM_CCGR2_CG15_SHIFT

#define CCM_CCGR2_CG15_SHIFT   (30U)

Definition at line 5781 of file MIMXRT1052.h.

CCM_CCGR2_CG1_MASK

#define CCM_CCGR2_CG1_MASK   (0xCU)

Definition at line 5738 of file MIMXRT1052.h.

CCM_CCGR2_CG1_SHIFT

#define CCM_CCGR2_CG1_SHIFT   (2U)

Definition at line 5739 of file MIMXRT1052.h.

CCM_CCGR2_CG2

#define CCM_CCGR2_CG2

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)

Definition at line 5743 of file MIMXRT1052.h.

CCM_CCGR2_CG2_MASK

#define CCM_CCGR2_CG2_MASK   (0x30U)

Definition at line 5741 of file MIMXRT1052.h.

CCM_CCGR2_CG2_SHIFT

#define CCM_CCGR2_CG2_SHIFT   (4U)

Definition at line 5742 of file MIMXRT1052.h.

CCM_CCGR2_CG3

#define CCM_CCGR2_CG3

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)

Definition at line 5746 of file MIMXRT1052.h.

CCM_CCGR2_CG3_MASK

#define CCM_CCGR2_CG3_MASK   (0xC0U)

Definition at line 5744 of file MIMXRT1052.h.

CCM_CCGR2_CG3_SHIFT

#define CCM_CCGR2_CG3_SHIFT   (6U)

Definition at line 5745 of file MIMXRT1052.h.

CCM_CCGR2_CG4

#define CCM_CCGR2_CG4

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)

Definition at line 5749 of file MIMXRT1052.h.

CCM_CCGR2_CG4_MASK

#define CCM_CCGR2_CG4_MASK   (0x300U)

Definition at line 5747 of file MIMXRT1052.h.

CCM_CCGR2_CG4_SHIFT

#define CCM_CCGR2_CG4_SHIFT   (8U)

Definition at line 5748 of file MIMXRT1052.h.

CCM_CCGR2_CG5

#define CCM_CCGR2_CG5

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)

Definition at line 5752 of file MIMXRT1052.h.

CCM_CCGR2_CG5_MASK

#define CCM_CCGR2_CG5_MASK   (0xC00U)

Definition at line 5750 of file MIMXRT1052.h.

CCM_CCGR2_CG5_SHIFT

#define CCM_CCGR2_CG5_SHIFT   (10U)

Definition at line 5751 of file MIMXRT1052.h.

CCM_CCGR2_CG6

#define CCM_CCGR2_CG6

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)

Definition at line 5755 of file MIMXRT1052.h.

CCM_CCGR2_CG6_MASK

#define CCM_CCGR2_CG6_MASK   (0x3000U)

Definition at line 5753 of file MIMXRT1052.h.

CCM_CCGR2_CG6_SHIFT

#define CCM_CCGR2_CG6_SHIFT   (12U)

Definition at line 5754 of file MIMXRT1052.h.

CCM_CCGR2_CG7

#define CCM_CCGR2_CG7

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)

Definition at line 5758 of file MIMXRT1052.h.

CCM_CCGR2_CG7_MASK

#define CCM_CCGR2_CG7_MASK   (0xC000U)

Definition at line 5756 of file MIMXRT1052.h.

CCM_CCGR2_CG7_SHIFT

#define CCM_CCGR2_CG7_SHIFT   (14U)

Definition at line 5757 of file MIMXRT1052.h.

CCM_CCGR2_CG8

#define CCM_CCGR2_CG8

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)

Definition at line 5761 of file MIMXRT1052.h.

CCM_CCGR2_CG8_MASK

#define CCM_CCGR2_CG8_MASK   (0x30000U)

Definition at line 5759 of file MIMXRT1052.h.

CCM_CCGR2_CG8_SHIFT

#define CCM_CCGR2_CG8_SHIFT   (16U)

Definition at line 5760 of file MIMXRT1052.h.

CCM_CCGR2_CG9

#define CCM_CCGR2_CG9

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)

Definition at line 5764 of file MIMXRT1052.h.

CCM_CCGR2_CG9_MASK

#define CCM_CCGR2_CG9_MASK   (0xC0000U)

Definition at line 5762 of file MIMXRT1052.h.

CCM_CCGR2_CG9_SHIFT

#define CCM_CCGR2_CG9_SHIFT   (18U)

Definition at line 5763 of file MIMXRT1052.h.

CCM_CCGR3_CG0

#define CCM_CCGR3_CG0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)

Definition at line 5789 of file MIMXRT1052.h.

CCM_CCGR3_CG0_MASK

#define CCM_CCGR3_CG0_MASK   (0x3U)

Definition at line 5787 of file MIMXRT1052.h.

CCM_CCGR3_CG0_SHIFT

#define CCM_CCGR3_CG0_SHIFT   (0U)

Definition at line 5788 of file MIMXRT1052.h.

CCM_CCGR3_CG1

#define CCM_CCGR3_CG1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)

Definition at line 5792 of file MIMXRT1052.h.

CCM_CCGR3_CG10

#define CCM_CCGR3_CG10

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)

Definition at line 5819 of file MIMXRT1052.h.

CCM_CCGR3_CG10_MASK

#define CCM_CCGR3_CG10_MASK   (0x300000U)

Definition at line 5817 of file MIMXRT1052.h.

CCM_CCGR3_CG10_SHIFT

#define CCM_CCGR3_CG10_SHIFT   (20U)

Definition at line 5818 of file MIMXRT1052.h.

CCM_CCGR3_CG11

#define CCM_CCGR3_CG11

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)

Definition at line 5822 of file MIMXRT1052.h.

CCM_CCGR3_CG11_MASK

#define CCM_CCGR3_CG11_MASK   (0xC00000U)

Definition at line 5820 of file MIMXRT1052.h.

CCM_CCGR3_CG11_SHIFT

#define CCM_CCGR3_CG11_SHIFT   (22U)

Definition at line 5821 of file MIMXRT1052.h.

CCM_CCGR3_CG12

#define CCM_CCGR3_CG12

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)

Definition at line 5825 of file MIMXRT1052.h.

CCM_CCGR3_CG12_MASK

#define CCM_CCGR3_CG12_MASK   (0x3000000U)

Definition at line 5823 of file MIMXRT1052.h.

CCM_CCGR3_CG12_SHIFT

#define CCM_CCGR3_CG12_SHIFT   (24U)

Definition at line 5824 of file MIMXRT1052.h.

CCM_CCGR3_CG13

#define CCM_CCGR3_CG13

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)

Definition at line 5828 of file MIMXRT1052.h.

CCM_CCGR3_CG13_MASK

#define CCM_CCGR3_CG13_MASK   (0xC000000U)

Definition at line 5826 of file MIMXRT1052.h.

CCM_CCGR3_CG13_SHIFT

#define CCM_CCGR3_CG13_SHIFT   (26U)

Definition at line 5827 of file MIMXRT1052.h.

CCM_CCGR3_CG14

#define CCM_CCGR3_CG14

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)

Definition at line 5831 of file MIMXRT1052.h.

CCM_CCGR3_CG14_MASK

#define CCM_CCGR3_CG14_MASK   (0x30000000U)

Definition at line 5829 of file MIMXRT1052.h.

CCM_CCGR3_CG14_SHIFT

#define CCM_CCGR3_CG14_SHIFT   (28U)

Definition at line 5830 of file MIMXRT1052.h.

CCM_CCGR3_CG15

#define CCM_CCGR3_CG15

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)

Definition at line 5834 of file MIMXRT1052.h.

CCM_CCGR3_CG15_MASK

#define CCM_CCGR3_CG15_MASK   (0xC0000000U)

Definition at line 5832 of file MIMXRT1052.h.

CCM_CCGR3_CG15_SHIFT

#define CCM_CCGR3_CG15_SHIFT   (30U)

Definition at line 5833 of file MIMXRT1052.h.

CCM_CCGR3_CG1_MASK

#define CCM_CCGR3_CG1_MASK   (0xCU)

Definition at line 5790 of file MIMXRT1052.h.

CCM_CCGR3_CG1_SHIFT

#define CCM_CCGR3_CG1_SHIFT   (2U)

Definition at line 5791 of file MIMXRT1052.h.

CCM_CCGR3_CG2

#define CCM_CCGR3_CG2

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)

Definition at line 5795 of file MIMXRT1052.h.

CCM_CCGR3_CG2_MASK

#define CCM_CCGR3_CG2_MASK   (0x30U)

Definition at line 5793 of file MIMXRT1052.h.

CCM_CCGR3_CG2_SHIFT

#define CCM_CCGR3_CG2_SHIFT   (4U)

Definition at line 5794 of file MIMXRT1052.h.

CCM_CCGR3_CG3

#define CCM_CCGR3_CG3

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)

Definition at line 5798 of file MIMXRT1052.h.

CCM_CCGR3_CG3_MASK

#define CCM_CCGR3_CG3_MASK   (0xC0U)

Definition at line 5796 of file MIMXRT1052.h.

CCM_CCGR3_CG3_SHIFT

#define CCM_CCGR3_CG3_SHIFT   (6U)

Definition at line 5797 of file MIMXRT1052.h.

CCM_CCGR3_CG4

#define CCM_CCGR3_CG4

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)

Definition at line 5801 of file MIMXRT1052.h.

CCM_CCGR3_CG4_MASK

#define CCM_CCGR3_CG4_MASK   (0x300U)

Definition at line 5799 of file MIMXRT1052.h.

CCM_CCGR3_CG4_SHIFT

#define CCM_CCGR3_CG4_SHIFT   (8U)

Definition at line 5800 of file MIMXRT1052.h.

CCM_CCGR3_CG5

#define CCM_CCGR3_CG5

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)

Definition at line 5804 of file MIMXRT1052.h.

CCM_CCGR3_CG5_MASK

#define CCM_CCGR3_CG5_MASK   (0xC00U)

Definition at line 5802 of file MIMXRT1052.h.

CCM_CCGR3_CG5_SHIFT

#define CCM_CCGR3_CG5_SHIFT   (10U)

Definition at line 5803 of file MIMXRT1052.h.

CCM_CCGR3_CG6

#define CCM_CCGR3_CG6

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)

Definition at line 5807 of file MIMXRT1052.h.

CCM_CCGR3_CG6_MASK

#define CCM_CCGR3_CG6_MASK   (0x3000U)

Definition at line 5805 of file MIMXRT1052.h.

CCM_CCGR3_CG6_SHIFT

#define CCM_CCGR3_CG6_SHIFT   (12U)

Definition at line 5806 of file MIMXRT1052.h.

CCM_CCGR3_CG7

#define CCM_CCGR3_CG7

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)

Definition at line 5810 of file MIMXRT1052.h.

CCM_CCGR3_CG7_MASK

#define CCM_CCGR3_CG7_MASK   (0xC000U)

Definition at line 5808 of file MIMXRT1052.h.

CCM_CCGR3_CG7_SHIFT

#define CCM_CCGR3_CG7_SHIFT   (14U)

Definition at line 5809 of file MIMXRT1052.h.

CCM_CCGR3_CG8

#define CCM_CCGR3_CG8

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)

Definition at line 5813 of file MIMXRT1052.h.

CCM_CCGR3_CG8_MASK

#define CCM_CCGR3_CG8_MASK   (0x30000U)

Definition at line 5811 of file MIMXRT1052.h.

CCM_CCGR3_CG8_SHIFT

#define CCM_CCGR3_CG8_SHIFT   (16U)

Definition at line 5812 of file MIMXRT1052.h.

CCM_CCGR3_CG9

#define CCM_CCGR3_CG9

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)

Definition at line 5816 of file MIMXRT1052.h.

CCM_CCGR3_CG9_MASK

#define CCM_CCGR3_CG9_MASK   (0xC0000U)

Definition at line 5814 of file MIMXRT1052.h.

CCM_CCGR3_CG9_SHIFT

#define CCM_CCGR3_CG9_SHIFT   (18U)

Definition at line 5815 of file MIMXRT1052.h.

CCM_CCGR4_CG0

#define CCM_CCGR4_CG0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)

Definition at line 5841 of file MIMXRT1052.h.

CCM_CCGR4_CG0_MASK

#define CCM_CCGR4_CG0_MASK   (0x3U)

Definition at line 5839 of file MIMXRT1052.h.

CCM_CCGR4_CG0_SHIFT

#define CCM_CCGR4_CG0_SHIFT   (0U)

Definition at line 5840 of file MIMXRT1052.h.

CCM_CCGR4_CG1

#define CCM_CCGR4_CG1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)

Definition at line 5844 of file MIMXRT1052.h.

CCM_CCGR4_CG10

#define CCM_CCGR4_CG10

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)

Definition at line 5871 of file MIMXRT1052.h.

CCM_CCGR4_CG10_MASK

#define CCM_CCGR4_CG10_MASK   (0x300000U)

Definition at line 5869 of file MIMXRT1052.h.

CCM_CCGR4_CG10_SHIFT

#define CCM_CCGR4_CG10_SHIFT   (20U)

Definition at line 5870 of file MIMXRT1052.h.

CCM_CCGR4_CG11

#define CCM_CCGR4_CG11

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)

Definition at line 5874 of file MIMXRT1052.h.

CCM_CCGR4_CG11_MASK

#define CCM_CCGR4_CG11_MASK   (0xC00000U)

Definition at line 5872 of file MIMXRT1052.h.

CCM_CCGR4_CG11_SHIFT

#define CCM_CCGR4_CG11_SHIFT   (22U)

Definition at line 5873 of file MIMXRT1052.h.

CCM_CCGR4_CG12

#define CCM_CCGR4_CG12

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)

Definition at line 5877 of file MIMXRT1052.h.

CCM_CCGR4_CG12_MASK

#define CCM_CCGR4_CG12_MASK   (0x3000000U)

Definition at line 5875 of file MIMXRT1052.h.

CCM_CCGR4_CG12_SHIFT

#define CCM_CCGR4_CG12_SHIFT   (24U)

Definition at line 5876 of file MIMXRT1052.h.

CCM_CCGR4_CG13

#define CCM_CCGR4_CG13

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)

Definition at line 5880 of file MIMXRT1052.h.

CCM_CCGR4_CG13_MASK

#define CCM_CCGR4_CG13_MASK   (0xC000000U)

Definition at line 5878 of file MIMXRT1052.h.

CCM_CCGR4_CG13_SHIFT

#define CCM_CCGR4_CG13_SHIFT   (26U)

Definition at line 5879 of file MIMXRT1052.h.

CCM_CCGR4_CG14

#define CCM_CCGR4_CG14

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)

Definition at line 5883 of file MIMXRT1052.h.

CCM_CCGR4_CG14_MASK

#define CCM_CCGR4_CG14_MASK   (0x30000000U)

Definition at line 5881 of file MIMXRT1052.h.

CCM_CCGR4_CG14_SHIFT

#define CCM_CCGR4_CG14_SHIFT   (28U)

Definition at line 5882 of file MIMXRT1052.h.

CCM_CCGR4_CG15

#define CCM_CCGR4_CG15

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)

Definition at line 5886 of file MIMXRT1052.h.

CCM_CCGR4_CG15_MASK

#define CCM_CCGR4_CG15_MASK   (0xC0000000U)

Definition at line 5884 of file MIMXRT1052.h.

CCM_CCGR4_CG15_SHIFT

#define CCM_CCGR4_CG15_SHIFT   (30U)

Definition at line 5885 of file MIMXRT1052.h.

CCM_CCGR4_CG1_MASK

#define CCM_CCGR4_CG1_MASK   (0xCU)

Definition at line 5842 of file MIMXRT1052.h.

CCM_CCGR4_CG1_SHIFT

#define CCM_CCGR4_CG1_SHIFT   (2U)

Definition at line 5843 of file MIMXRT1052.h.

CCM_CCGR4_CG2

#define CCM_CCGR4_CG2

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)

Definition at line 5847 of file MIMXRT1052.h.

CCM_CCGR4_CG2_MASK

#define CCM_CCGR4_CG2_MASK   (0x30U)

Definition at line 5845 of file MIMXRT1052.h.

CCM_CCGR4_CG2_SHIFT

#define CCM_CCGR4_CG2_SHIFT   (4U)

Definition at line 5846 of file MIMXRT1052.h.

CCM_CCGR4_CG3

#define CCM_CCGR4_CG3

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)

Definition at line 5850 of file MIMXRT1052.h.

CCM_CCGR4_CG3_MASK

#define CCM_CCGR4_CG3_MASK   (0xC0U)

Definition at line 5848 of file MIMXRT1052.h.

CCM_CCGR4_CG3_SHIFT

#define CCM_CCGR4_CG3_SHIFT   (6U)

Definition at line 5849 of file MIMXRT1052.h.

CCM_CCGR4_CG4

#define CCM_CCGR4_CG4

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)

Definition at line 5853 of file MIMXRT1052.h.

CCM_CCGR4_CG4_MASK

#define CCM_CCGR4_CG4_MASK   (0x300U)

Definition at line 5851 of file MIMXRT1052.h.

CCM_CCGR4_CG4_SHIFT

#define CCM_CCGR4_CG4_SHIFT   (8U)

Definition at line 5852 of file MIMXRT1052.h.

CCM_CCGR4_CG5

#define CCM_CCGR4_CG5

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)

Definition at line 5856 of file MIMXRT1052.h.

CCM_CCGR4_CG5_MASK

#define CCM_CCGR4_CG5_MASK   (0xC00U)

Definition at line 5854 of file MIMXRT1052.h.

CCM_CCGR4_CG5_SHIFT

#define CCM_CCGR4_CG5_SHIFT   (10U)

Definition at line 5855 of file MIMXRT1052.h.

CCM_CCGR4_CG6

#define CCM_CCGR4_CG6

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)

Definition at line 5859 of file MIMXRT1052.h.

CCM_CCGR4_CG6_MASK

#define CCM_CCGR4_CG6_MASK   (0x3000U)

Definition at line 5857 of file MIMXRT1052.h.

CCM_CCGR4_CG6_SHIFT

#define CCM_CCGR4_CG6_SHIFT   (12U)

Definition at line 5858 of file MIMXRT1052.h.

CCM_CCGR4_CG7

#define CCM_CCGR4_CG7

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)

Definition at line 5862 of file MIMXRT1052.h.

CCM_CCGR4_CG7_MASK

#define CCM_CCGR4_CG7_MASK   (0xC000U)

Definition at line 5860 of file MIMXRT1052.h.

CCM_CCGR4_CG7_SHIFT

#define CCM_CCGR4_CG7_SHIFT   (14U)

Definition at line 5861 of file MIMXRT1052.h.

CCM_CCGR4_CG8

#define CCM_CCGR4_CG8

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)

Definition at line 5865 of file MIMXRT1052.h.

CCM_CCGR4_CG8_MASK

#define CCM_CCGR4_CG8_MASK   (0x30000U)

Definition at line 5863 of file MIMXRT1052.h.

CCM_CCGR4_CG8_SHIFT

#define CCM_CCGR4_CG8_SHIFT   (16U)

Definition at line 5864 of file MIMXRT1052.h.

CCM_CCGR4_CG9

#define CCM_CCGR4_CG9

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)

Definition at line 5868 of file MIMXRT1052.h.

CCM_CCGR4_CG9_MASK

#define CCM_CCGR4_CG9_MASK   (0xC0000U)

Definition at line 5866 of file MIMXRT1052.h.

CCM_CCGR4_CG9_SHIFT

#define CCM_CCGR4_CG9_SHIFT   (18U)

Definition at line 5867 of file MIMXRT1052.h.

CCM_CCGR5_CG0

#define CCM_CCGR5_CG0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)

Definition at line 5893 of file MIMXRT1052.h.

CCM_CCGR5_CG0_MASK

#define CCM_CCGR5_CG0_MASK   (0x3U)

Definition at line 5891 of file MIMXRT1052.h.

CCM_CCGR5_CG0_SHIFT

#define CCM_CCGR5_CG0_SHIFT   (0U)

Definition at line 5892 of file MIMXRT1052.h.

CCM_CCGR5_CG1

#define CCM_CCGR5_CG1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)

Definition at line 5896 of file MIMXRT1052.h.

CCM_CCGR5_CG10

#define CCM_CCGR5_CG10

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)

Definition at line 5923 of file MIMXRT1052.h.

CCM_CCGR5_CG10_MASK

#define CCM_CCGR5_CG10_MASK   (0x300000U)

Definition at line 5921 of file MIMXRT1052.h.

CCM_CCGR5_CG10_SHIFT

#define CCM_CCGR5_CG10_SHIFT   (20U)

Definition at line 5922 of file MIMXRT1052.h.

CCM_CCGR5_CG11

#define CCM_CCGR5_CG11

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)

Definition at line 5926 of file MIMXRT1052.h.

CCM_CCGR5_CG11_MASK

#define CCM_CCGR5_CG11_MASK   (0xC00000U)

Definition at line 5924 of file MIMXRT1052.h.

CCM_CCGR5_CG11_SHIFT

#define CCM_CCGR5_CG11_SHIFT   (22U)

Definition at line 5925 of file MIMXRT1052.h.

CCM_CCGR5_CG12

#define CCM_CCGR5_CG12

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)

Definition at line 5929 of file MIMXRT1052.h.

CCM_CCGR5_CG12_MASK

#define CCM_CCGR5_CG12_MASK   (0x3000000U)

Definition at line 5927 of file MIMXRT1052.h.

CCM_CCGR5_CG12_SHIFT

#define CCM_CCGR5_CG12_SHIFT   (24U)

Definition at line 5928 of file MIMXRT1052.h.

CCM_CCGR5_CG13

#define CCM_CCGR5_CG13

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)

Definition at line 5932 of file MIMXRT1052.h.

CCM_CCGR5_CG13_MASK

#define CCM_CCGR5_CG13_MASK   (0xC000000U)

Definition at line 5930 of file MIMXRT1052.h.

CCM_CCGR5_CG13_SHIFT

#define CCM_CCGR5_CG13_SHIFT   (26U)

Definition at line 5931 of file MIMXRT1052.h.

CCM_CCGR5_CG14

#define CCM_CCGR5_CG14

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)

Definition at line 5935 of file MIMXRT1052.h.

CCM_CCGR5_CG14_MASK

#define CCM_CCGR5_CG14_MASK   (0x30000000U)

Definition at line 5933 of file MIMXRT1052.h.

CCM_CCGR5_CG14_SHIFT

#define CCM_CCGR5_CG14_SHIFT   (28U)

Definition at line 5934 of file MIMXRT1052.h.

CCM_CCGR5_CG15

#define CCM_CCGR5_CG15

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)

Definition at line 5938 of file MIMXRT1052.h.

CCM_CCGR5_CG15_MASK

#define CCM_CCGR5_CG15_MASK   (0xC0000000U)

Definition at line 5936 of file MIMXRT1052.h.

CCM_CCGR5_CG15_SHIFT

#define CCM_CCGR5_CG15_SHIFT   (30U)

Definition at line 5937 of file MIMXRT1052.h.

CCM_CCGR5_CG1_MASK

#define CCM_CCGR5_CG1_MASK   (0xCU)

Definition at line 5894 of file MIMXRT1052.h.

CCM_CCGR5_CG1_SHIFT

#define CCM_CCGR5_CG1_SHIFT   (2U)

Definition at line 5895 of file MIMXRT1052.h.

CCM_CCGR5_CG2

#define CCM_CCGR5_CG2

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)

Definition at line 5899 of file MIMXRT1052.h.

CCM_CCGR5_CG2_MASK

#define CCM_CCGR5_CG2_MASK   (0x30U)

Definition at line 5897 of file MIMXRT1052.h.

CCM_CCGR5_CG2_SHIFT

#define CCM_CCGR5_CG2_SHIFT   (4U)

Definition at line 5898 of file MIMXRT1052.h.

CCM_CCGR5_CG3

#define CCM_CCGR5_CG3

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)

Definition at line 5902 of file MIMXRT1052.h.

CCM_CCGR5_CG3_MASK

#define CCM_CCGR5_CG3_MASK   (0xC0U)

Definition at line 5900 of file MIMXRT1052.h.

CCM_CCGR5_CG3_SHIFT

#define CCM_CCGR5_CG3_SHIFT   (6U)

Definition at line 5901 of file MIMXRT1052.h.

CCM_CCGR5_CG4

#define CCM_CCGR5_CG4

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)

Definition at line 5905 of file MIMXRT1052.h.

CCM_CCGR5_CG4_MASK

#define CCM_CCGR5_CG4_MASK   (0x300U)

Definition at line 5903 of file MIMXRT1052.h.

CCM_CCGR5_CG4_SHIFT

#define CCM_CCGR5_CG4_SHIFT   (8U)

Definition at line 5904 of file MIMXRT1052.h.

CCM_CCGR5_CG5

#define CCM_CCGR5_CG5

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)

Definition at line 5908 of file MIMXRT1052.h.

CCM_CCGR5_CG5_MASK

#define CCM_CCGR5_CG5_MASK   (0xC00U)

Definition at line 5906 of file MIMXRT1052.h.

CCM_CCGR5_CG5_SHIFT

#define CCM_CCGR5_CG5_SHIFT   (10U)

Definition at line 5907 of file MIMXRT1052.h.

CCM_CCGR5_CG6

#define CCM_CCGR5_CG6

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)

Definition at line 5911 of file MIMXRT1052.h.

CCM_CCGR5_CG6_MASK

#define CCM_CCGR5_CG6_MASK   (0x3000U)

Definition at line 5909 of file MIMXRT1052.h.

CCM_CCGR5_CG6_SHIFT

#define CCM_CCGR5_CG6_SHIFT   (12U)

Definition at line 5910 of file MIMXRT1052.h.

CCM_CCGR5_CG7

#define CCM_CCGR5_CG7

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)

Definition at line 5914 of file MIMXRT1052.h.

CCM_CCGR5_CG7_MASK

#define CCM_CCGR5_CG7_MASK   (0xC000U)

Definition at line 5912 of file MIMXRT1052.h.

CCM_CCGR5_CG7_SHIFT

#define CCM_CCGR5_CG7_SHIFT   (14U)

Definition at line 5913 of file MIMXRT1052.h.

CCM_CCGR5_CG8

#define CCM_CCGR5_CG8

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)

Definition at line 5917 of file MIMXRT1052.h.

CCM_CCGR5_CG8_MASK

#define CCM_CCGR5_CG8_MASK   (0x30000U)

Definition at line 5915 of file MIMXRT1052.h.

CCM_CCGR5_CG8_SHIFT

#define CCM_CCGR5_CG8_SHIFT   (16U)

Definition at line 5916 of file MIMXRT1052.h.

CCM_CCGR5_CG9

#define CCM_CCGR5_CG9

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)

Definition at line 5920 of file MIMXRT1052.h.

CCM_CCGR5_CG9_MASK

#define CCM_CCGR5_CG9_MASK   (0xC0000U)

Definition at line 5918 of file MIMXRT1052.h.

CCM_CCGR5_CG9_SHIFT

#define CCM_CCGR5_CG9_SHIFT   (18U)

Definition at line 5919 of file MIMXRT1052.h.

CCM_CCGR6_CG0

#define CCM_CCGR6_CG0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)

Definition at line 5945 of file MIMXRT1052.h.

CCM_CCGR6_CG0_MASK

#define CCM_CCGR6_CG0_MASK   (0x3U)

Definition at line 5943 of file MIMXRT1052.h.

CCM_CCGR6_CG0_SHIFT

#define CCM_CCGR6_CG0_SHIFT   (0U)

Definition at line 5944 of file MIMXRT1052.h.

CCM_CCGR6_CG1

#define CCM_CCGR6_CG1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)

Definition at line 5948 of file MIMXRT1052.h.

CCM_CCGR6_CG10

#define CCM_CCGR6_CG10

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)

Definition at line 5975 of file MIMXRT1052.h.

CCM_CCGR6_CG10_MASK

#define CCM_CCGR6_CG10_MASK   (0x300000U)

Definition at line 5973 of file MIMXRT1052.h.

CCM_CCGR6_CG10_SHIFT

#define CCM_CCGR6_CG10_SHIFT   (20U)

Definition at line 5974 of file MIMXRT1052.h.

CCM_CCGR6_CG11

#define CCM_CCGR6_CG11

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)

Definition at line 5978 of file MIMXRT1052.h.

CCM_CCGR6_CG11_MASK

#define CCM_CCGR6_CG11_MASK   (0xC00000U)

Definition at line 5976 of file MIMXRT1052.h.

CCM_CCGR6_CG11_SHIFT

#define CCM_CCGR6_CG11_SHIFT   (22U)

Definition at line 5977 of file MIMXRT1052.h.

CCM_CCGR6_CG12

#define CCM_CCGR6_CG12

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)

Definition at line 5981 of file MIMXRT1052.h.

CCM_CCGR6_CG12_MASK

#define CCM_CCGR6_CG12_MASK   (0x3000000U)

Definition at line 5979 of file MIMXRT1052.h.

CCM_CCGR6_CG12_SHIFT

#define CCM_CCGR6_CG12_SHIFT   (24U)

Definition at line 5980 of file MIMXRT1052.h.

CCM_CCGR6_CG13

#define CCM_CCGR6_CG13

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)

Definition at line 5984 of file MIMXRT1052.h.

CCM_CCGR6_CG13_MASK

#define CCM_CCGR6_CG13_MASK   (0xC000000U)

Definition at line 5982 of file MIMXRT1052.h.

CCM_CCGR6_CG13_SHIFT

#define CCM_CCGR6_CG13_SHIFT   (26U)

Definition at line 5983 of file MIMXRT1052.h.

CCM_CCGR6_CG14

#define CCM_CCGR6_CG14

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)

Definition at line 5987 of file MIMXRT1052.h.

CCM_CCGR6_CG14_MASK

#define CCM_CCGR6_CG14_MASK   (0x30000000U)

Definition at line 5985 of file MIMXRT1052.h.

CCM_CCGR6_CG14_SHIFT

#define CCM_CCGR6_CG14_SHIFT   (28U)

Definition at line 5986 of file MIMXRT1052.h.

CCM_CCGR6_CG15

#define CCM_CCGR6_CG15

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)

Definition at line 5990 of file MIMXRT1052.h.

CCM_CCGR6_CG15_MASK

#define CCM_CCGR6_CG15_MASK   (0xC0000000U)

Definition at line 5988 of file MIMXRT1052.h.

CCM_CCGR6_CG15_SHIFT

#define CCM_CCGR6_CG15_SHIFT   (30U)

Definition at line 5989 of file MIMXRT1052.h.

CCM_CCGR6_CG1_MASK

#define CCM_CCGR6_CG1_MASK   (0xCU)

Definition at line 5946 of file MIMXRT1052.h.

CCM_CCGR6_CG1_SHIFT

#define CCM_CCGR6_CG1_SHIFT   (2U)

Definition at line 5947 of file MIMXRT1052.h.

CCM_CCGR6_CG2

#define CCM_CCGR6_CG2

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)

Definition at line 5951 of file MIMXRT1052.h.

CCM_CCGR6_CG2_MASK

#define CCM_CCGR6_CG2_MASK   (0x30U)

Definition at line 5949 of file MIMXRT1052.h.

CCM_CCGR6_CG2_SHIFT

#define CCM_CCGR6_CG2_SHIFT   (4U)

Definition at line 5950 of file MIMXRT1052.h.

CCM_CCGR6_CG3

#define CCM_CCGR6_CG3

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)

Definition at line 5954 of file MIMXRT1052.h.

CCM_CCGR6_CG3_MASK

#define CCM_CCGR6_CG3_MASK   (0xC0U)

Definition at line 5952 of file MIMXRT1052.h.

CCM_CCGR6_CG3_SHIFT

#define CCM_CCGR6_CG3_SHIFT   (6U)

Definition at line 5953 of file MIMXRT1052.h.

CCM_CCGR6_CG4

#define CCM_CCGR6_CG4

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)

Definition at line 5957 of file MIMXRT1052.h.

CCM_CCGR6_CG4_MASK

#define CCM_CCGR6_CG4_MASK   (0x300U)

Definition at line 5955 of file MIMXRT1052.h.

CCM_CCGR6_CG4_SHIFT

#define CCM_CCGR6_CG4_SHIFT   (8U)

Definition at line 5956 of file MIMXRT1052.h.

CCM_CCGR6_CG5

#define CCM_CCGR6_CG5

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)

Definition at line 5960 of file MIMXRT1052.h.

CCM_CCGR6_CG5_MASK

#define CCM_CCGR6_CG5_MASK   (0xC00U)

Definition at line 5958 of file MIMXRT1052.h.

CCM_CCGR6_CG5_SHIFT

#define CCM_CCGR6_CG5_SHIFT   (10U)

Definition at line 5959 of file MIMXRT1052.h.

CCM_CCGR6_CG6

#define CCM_CCGR6_CG6

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)

Definition at line 5963 of file MIMXRT1052.h.

CCM_CCGR6_CG6_MASK

#define CCM_CCGR6_CG6_MASK   (0x3000U)

Definition at line 5961 of file MIMXRT1052.h.

CCM_CCGR6_CG6_SHIFT

#define CCM_CCGR6_CG6_SHIFT   (12U)

Definition at line 5962 of file MIMXRT1052.h.

CCM_CCGR6_CG7

#define CCM_CCGR6_CG7

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)

Definition at line 5966 of file MIMXRT1052.h.

CCM_CCGR6_CG7_MASK

#define CCM_CCGR6_CG7_MASK   (0xC000U)

Definition at line 5964 of file MIMXRT1052.h.

CCM_CCGR6_CG7_SHIFT

#define CCM_CCGR6_CG7_SHIFT   (14U)

Definition at line 5965 of file MIMXRT1052.h.

CCM_CCGR6_CG8

#define CCM_CCGR6_CG8

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)

Definition at line 5969 of file MIMXRT1052.h.

CCM_CCGR6_CG8_MASK

#define CCM_CCGR6_CG8_MASK   (0x30000U)

Definition at line 5967 of file MIMXRT1052.h.

CCM_CCGR6_CG8_SHIFT

#define CCM_CCGR6_CG8_SHIFT   (16U)

Definition at line 5968 of file MIMXRT1052.h.

CCM_CCGR6_CG9

#define CCM_CCGR6_CG9

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)

Definition at line 5972 of file MIMXRT1052.h.

CCM_CCGR6_CG9_MASK

#define CCM_CCGR6_CG9_MASK   (0xC0000U)

Definition at line 5970 of file MIMXRT1052.h.

CCM_CCGR6_CG9_SHIFT

#define CCM_CCGR6_CG9_SHIFT   (18U)

Definition at line 5971 of file MIMXRT1052.h.

CCM_CCOSR_CLK_OUT_SEL

#define CCM_CCOSR_CLK_OUT_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)

CLK_OUT_SEL 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock

Definition at line 5546 of file MIMXRT1052.h.

CCM_CCOSR_CLK_OUT_SEL_MASK

#define CCM_CCOSR_CLK_OUT_SEL_MASK   (0x100U)

Definition at line 5540 of file MIMXRT1052.h.

CCM_CCOSR_CLK_OUT_SEL_SHIFT

#define CCM_CCOSR_CLK_OUT_SEL_SHIFT   (8U)

Definition at line 5541 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_DIV

#define CCM_CCOSR_CLKO1_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)

CLKO1_DIV 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5532 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_DIV_MASK

#define CCM_CCOSR_CLKO1_DIV_MASK   (0x70U)

Definition at line 5520 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_DIV_SHIFT

#define CCM_CCOSR_CLKO1_DIV_SHIFT   (4U)

Definition at line 5521 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_EN

#define CCM_CCOSR_CLKO1_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)

CLKO1_EN 0b0..CCM_CLKO1 disabled. 0b1..CCM_CLKO1 enabled.

Definition at line 5539 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_EN_MASK

#define CCM_CCOSR_CLKO1_EN_MASK   (0x80U)

Definition at line 5533 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_EN_SHIFT

#define CCM_CCOSR_CLKO1_EN_SHIFT   (7U)

Definition at line 5534 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_SEL

#define CCM_CCOSR_CLKO1_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)

CLKO1_SEL 0b0000..USB1 PLL clock (divided by 2) 0b0001..SYS PLL clock (divided by 2) 0b0011..VIDEO PLL clock (divided by 2) 0b0101..semc_clk_root 0b0110..Reserved 0b1010..lcdif_pix_clk_root 0b1011..ahb_clk_root 0b1100..ipg_clk_root 0b1101..perclk_root 0b1110..ckil_sync_clk_root 0b1111..pll4_main_clk

Definition at line 5519 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_SEL_MASK

#define CCM_CCOSR_CLKO1_SEL_MASK   (0xFU)

Definition at line 5504 of file MIMXRT1052.h.

CCM_CCOSR_CLKO1_SEL_SHIFT

#define CCM_CCOSR_CLKO1_SEL_SHIFT   (0U)

Definition at line 5505 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_DIV

#define CCM_CCOSR_CLKO2_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)

CLKO2_DIV 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5578 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_DIV_MASK

#define CCM_CCOSR_CLKO2_DIV_MASK   (0xE00000U)

Definition at line 5566 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_DIV_SHIFT

#define CCM_CCOSR_CLKO2_DIV_SHIFT   (21U)

Definition at line 5567 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_EN

#define CCM_CCOSR_CLKO2_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)

CLKO2_EN 0b0..CCM_CLKO2 disabled. 0b1..CCM_CLKO2 enabled.

Definition at line 5585 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_EN_MASK

#define CCM_CCOSR_CLKO2_EN_MASK   (0x1000000U)

Definition at line 5579 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_EN_SHIFT

#define CCM_CCOSR_CLKO2_EN_SHIFT   (24U)

Definition at line 5580 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_SEL

#define CCM_CCOSR_CLKO2_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)

CLKO2_SEL 0b00011..usdhc1_clk_root 0b00101..wrck_clk_root 0b00110..lpi2c_clk_root 0b01011..csi_clk_root 0b01110..osc_clk 0b10001..usdhc2_clk_root 0b10010..sai1_clk_root 0b10011..sai2_clk_root 0b10100..sai3_clk_root 0b10111..can_clk_root 0b11011..flexspi_clk_root 0b11100..uart_clk_root 0b11101..spdif0_clk_root 0b11111..Reserved

Definition at line 5565 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_SEL_MASK

#define CCM_CCOSR_CLKO2_SEL_MASK   (0x1F0000U)

Definition at line 5547 of file MIMXRT1052.h.

CCM_CCOSR_CLKO2_SEL_SHIFT

#define CCM_CCOSR_CLKO2_SEL_SHIFT   (16U)

Definition at line 5548 of file MIMXRT1052.h.

CCM_CCR_COSC_EN

#define CCM_CCR_COSC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)

COSC_EN 0b0..disable on chip oscillator 0b1..enable on chip oscillator

Definition at line 4216 of file MIMXRT1052.h.

CCM_CCR_COSC_EN_MASK

#define CCM_CCR_COSC_EN_MASK   (0x1000U)

Definition at line 4210 of file MIMXRT1052.h.

CCM_CCR_COSC_EN_SHIFT

#define CCM_CCR_COSC_EN_SHIFT   (12U)

Definition at line 4211 of file MIMXRT1052.h.

CCM_CCR_OSCNT

#define CCM_CCR_OSCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)

OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened.

Definition at line 4209 of file MIMXRT1052.h.

CCM_CCR_OSCNT_MASK

#define CCM_CCR_OSCNT_MASK   (0xFFU)

Definition at line 4201 of file MIMXRT1052.h.

CCM_CCR_OSCNT_SHIFT

#define CCM_CCR_OSCNT_SHIFT   (0U)

Definition at line 4202 of file MIMXRT1052.h.

CCM_CCR_RBC_EN

#define CCM_CCR_RBC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)

RBC_EN 0b1..REG_BYPASS_COUNTER enabled. 0b0..REG_BYPASS_COUNTER disabled

Definition at line 4231 of file MIMXRT1052.h.

CCM_CCR_RBC_EN_MASK

#define CCM_CCR_RBC_EN_MASK   (0x8000000U)

Definition at line 4225 of file MIMXRT1052.h.

CCM_CCR_RBC_EN_SHIFT

#define CCM_CCR_RBC_EN_SHIFT   (27U)

Definition at line 4226 of file MIMXRT1052.h.

CCM_CCR_REG_BYPASS_COUNT

#define CCM_CCR_REG_BYPASS_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)

REG_BYPASS_COUNT 0b000000..no delay 0b000001..1 CKIL clock period delay 0b111111..63 CKIL clock periods delay

Definition at line 4224 of file MIMXRT1052.h.

CCM_CCR_REG_BYPASS_COUNT_MASK

#define CCM_CCR_REG_BYPASS_COUNT_MASK   (0x7E00000U)

Definition at line 4217 of file MIMXRT1052.h.

CCM_CCR_REG_BYPASS_COUNT_SHIFT

#define CCM_CCR_REG_BYPASS_COUNT_SHIFT   (21U)

Definition at line 4218 of file MIMXRT1052.h.

CCM_CCSR_PLL3_SW_CLK_SEL

#define CCM_CCSR_PLL3_SW_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)

PLL3_SW_CLK_SEL 0b0..pll3_main_clk 0b1..pll3 bypass clock

Definition at line 4267 of file MIMXRT1052.h.

CCM_CCSR_PLL3_SW_CLK_SEL_MASK

#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK   (0x1U)

Definition at line 4261 of file MIMXRT1052.h.

CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT

#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT   (0U)

Definition at line 4262 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_PODF

#define CCM_CDCDR_FLEXIO1_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)

FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 5081 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_PODF_MASK

#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK   (0xE00U)

Definition at line 5069 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT

#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT   (9U)

Definition at line 5070 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_PRED

#define CCM_CDCDR_FLEXIO1_CLK_PRED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)

FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 5094 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_PRED_MASK

#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK   (0x7000U)

Definition at line 5082 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT

#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT   (12U)

Definition at line 5083 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_SEL

#define CCM_CDCDR_FLEXIO1_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)

FLEXIO1_CLK_SEL 0b00..derive clock from PLL4 0b01..derive clock from PLL3 PFD2 0b10..derive clock from PLL5 0b11..derive clock from pll3_sw_clk

Definition at line 5068 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_SEL_MASK

#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK   (0x180U)

Definition at line 5060 of file MIMXRT1052.h.

CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT

#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT   (7U)

Definition at line 5061 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_PODF

#define CCM_CDCDR_SPDIF0_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)

SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 5116 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_PODF_MASK

#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK   (0x1C00000U)

Definition at line 5104 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT

#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT   (22U)

Definition at line 5105 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_PRED

#define CCM_CDCDR_SPDIF0_CLK_PRED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)

SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 5129 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_PRED_MASK

#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK   (0xE000000U)

Definition at line 5117 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT

#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT   (25U)

Definition at line 5118 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_SEL

#define CCM_CDCDR_SPDIF0_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)

SPDIF0_CLK_SEL 0b00..derive clock from PLL4 0b01..derive clock from PLL3 PFD2 0b10..derive clock from PLL5 0b11..derive clock from pll3_sw_clk

Definition at line 5103 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_SEL_MASK

#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK   (0x300000U)

Definition at line 5095 of file MIMXRT1052.h.

CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT

#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT   (20U)

Definition at line 5096 of file MIMXRT1052.h.

CCM_CDHIPR_AHB_PODF_BUSY

#define CCM_CDHIPR_AHB_PODF_BUSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)

AHB_PODF_BUSY 0b0..divider is not busy and its value represents the actual division. 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied.

Definition at line 5281 of file MIMXRT1052.h.

CCM_CDHIPR_AHB_PODF_BUSY_MASK

#define CCM_CDHIPR_AHB_PODF_BUSY_MASK   (0x2U)

Definition at line 5274 of file MIMXRT1052.h.

CCM_CDHIPR_AHB_PODF_BUSY_SHIFT

#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT   (1U)

Definition at line 5275 of file MIMXRT1052.h.

CCM_CDHIPR_ARM_PODF_BUSY

#define CCM_CDHIPR_ARM_PODF_BUSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)

ARM_PODF_BUSY 0b0..divider is not busy and its value represents the actual division. 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied.

Definition at line 5305 of file MIMXRT1052.h.

CCM_CDHIPR_ARM_PODF_BUSY_MASK

#define CCM_CDHIPR_ARM_PODF_BUSY_MASK   (0x10000U)

Definition at line 5298 of file MIMXRT1052.h.

CCM_CDHIPR_ARM_PODF_BUSY_SHIFT

#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT   (16U)

Definition at line 5299 of file MIMXRT1052.h.

CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY

#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)

PERIPH2_CLK_SEL_BUSY 0b0..mux is not busy and its value represents the actual division. 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied.

Definition at line 5289 of file MIMXRT1052.h.

CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK

#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK   (0x8U)

Definition at line 5282 of file MIMXRT1052.h.

CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT

#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT   (3U)

Definition at line 5283 of file MIMXRT1052.h.

CCM_CDHIPR_PERIPH_CLK_SEL_BUSY

#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)

PERIPH_CLK_SEL_BUSY 0b0..mux is not busy and its value represents the actual division. 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied.

Definition at line 5297 of file MIMXRT1052.h.

CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK

#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK   (0x20U)

Definition at line 5290 of file MIMXRT1052.h.

CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT

#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT   (5U)

Definition at line 5291 of file MIMXRT1052.h.

CCM_CDHIPR_SEMC_PODF_BUSY

#define CCM_CDHIPR_SEMC_PODF_BUSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)

SEMC_PODF_BUSY 0b0..divider is not busy and its value represents the actual division. 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied.

Definition at line 5273 of file MIMXRT1052.h.

CCM_CDHIPR_SEMC_PODF_BUSY_MASK

#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK   (0x1U)

Definition at line 5266 of file MIMXRT1052.h.

CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT

#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT   (0U)

Definition at line 5267 of file MIMXRT1052.h.

CCM_CGPR_EFUSE_PROG_SUPPLY_GATE

#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)

EFUSE_PROG_SUPPLY_GATE 0b0..fuse programing supply voltage is gated off to the efuse module 0b1..allow fuse programing.

Definition at line 5603 of file MIMXRT1052.h.

CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK

#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK   (0x10U)

Definition at line 5597 of file MIMXRT1052.h.

CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT

#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT   (4U)

Definition at line 5598 of file MIMXRT1052.h.

CCM_CGPR_FPL

#define CCM_CGPR_FPL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)

FPL - Fast PLL enable. 0b0..Engage PLL enable default way. 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.

Definition at line 5618 of file MIMXRT1052.h.

CCM_CGPR_FPL_MASK

#define CCM_CGPR_FPL_MASK   (0x10000U)

Definition at line 5612 of file MIMXRT1052.h.

CCM_CGPR_FPL_SHIFT

#define CCM_CGPR_FPL_SHIFT   (16U)

Definition at line 5613 of file MIMXRT1052.h.

CCM_CGPR_INT_MEM_CLK_LPM

#define CCM_CGPR_INT_MEM_CLK_LPM

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)

INT_MEM_CLK_LPM 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)

Definition at line 5626 of file MIMXRT1052.h.

CCM_CGPR_INT_MEM_CLK_LPM_MASK

#define CCM_CGPR_INT_MEM_CLK_LPM_MASK   (0x20000U)

Definition at line 5619 of file MIMXRT1052.h.

CCM_CGPR_INT_MEM_CLK_LPM_SHIFT

#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT   (17U)

Definition at line 5620 of file MIMXRT1052.h.

CCM_CGPR_PMIC_DELAY_SCALER

#define CCM_CGPR_PMIC_DELAY_SCALER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)

PMIC_DELAY_SCALER 0b0..clock is not divided 0b1..clock is divided /8

Definition at line 5596 of file MIMXRT1052.h.

CCM_CGPR_PMIC_DELAY_SCALER_MASK

#define CCM_CGPR_PMIC_DELAY_SCALER_MASK   (0x1U)

Definition at line 5590 of file MIMXRT1052.h.

CCM_CGPR_PMIC_DELAY_SCALER_SHIFT

#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT   (0U)

Definition at line 5591 of file MIMXRT1052.h.

CCM_CGPR_SYS_MEM_DS_CTRL

#define CCM_CGPR_SYS_MEM_DS_CTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)

SYS_MEM_DS_CTRL 0b00..Disable memory DS mode always 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode

Definition at line 5611 of file MIMXRT1052.h.

CCM_CGPR_SYS_MEM_DS_CTRL_MASK

#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK   (0xC000U)

Definition at line 5604 of file MIMXRT1052.h.

CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT

#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT   (14U)

Definition at line 5605 of file MIMXRT1052.h.

CCM_CIMR_ARM_PODF_LOADED

#define CCM_CIMR_ARM_PODF_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)

ARM_PODF_LOADED 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created 0b1..mask interrupt due to frequency change of arm_podf

Definition at line 5499 of file MIMXRT1052.h.

CCM_CIMR_ARM_PODF_LOADED_MASK

#define CCM_CIMR_ARM_PODF_LOADED_MASK   (0x4000000U)

Definition at line 5493 of file MIMXRT1052.h.

CCM_CIMR_ARM_PODF_LOADED_SHIFT

#define CCM_CIMR_ARM_PODF_LOADED_SHIFT   (26U)

Definition at line 5494 of file MIMXRT1052.h.

CCM_CIMR_MASK_AHB_PODF_LOADED

#define CCM_CIMR_MASK_AHB_PODF_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)

MASK_AHB_PODF_LOADED 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created 0b1..mask interrupt due to frequency change of ahb_podf

Definition at line 5485 of file MIMXRT1052.h.

CCM_CIMR_MASK_AHB_PODF_LOADED_MASK

#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK   (0x100000U)

Definition at line 5479 of file MIMXRT1052.h.

CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT

#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT   (20U)

Definition at line 5480 of file MIMXRT1052.h.

CCM_CIMR_MASK_COSC_READY

#define CCM_CIMR_MASK_COSC_READY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)

MASK_COSC_READY 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created 0b1..mask interrupt due to on board oscillator ready

Definition at line 5464 of file MIMXRT1052.h.

CCM_CIMR_MASK_COSC_READY_MASK

#define CCM_CIMR_MASK_COSC_READY_MASK   (0x40U)

Definition at line 5458 of file MIMXRT1052.h.

CCM_CIMR_MASK_COSC_READY_SHIFT

#define CCM_CIMR_MASK_COSC_READY_SHIFT   (6U)

Definition at line 5459 of file MIMXRT1052.h.

CCM_CIMR_MASK_LRF_PLL

#define CCM_CIMR_MASK_LRF_PLL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)

MASK_LRF_PLL 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created 0b1..mask interrupt due to lrf of PLLs

Definition at line 5457 of file MIMXRT1052.h.

CCM_CIMR_MASK_LRF_PLL_MASK

#define CCM_CIMR_MASK_LRF_PLL_MASK   (0x1U)

Definition at line 5451 of file MIMXRT1052.h.

CCM_CIMR_MASK_LRF_PLL_SHIFT

#define CCM_CIMR_MASK_LRF_PLL_SHIFT   (0U)

Definition at line 5452 of file MIMXRT1052.h.

CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED

#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)

MASK_PERIPH2_CLK_SEL_LOADED 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created 0b1..mask interrupt due to update of periph2_clk_sel

Definition at line 5478 of file MIMXRT1052.h.

CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK

#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK   (0x80000U)

Definition at line 5472 of file MIMXRT1052.h.

CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT

#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT   (19U)

Definition at line 5473 of file MIMXRT1052.h.

CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED

#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)

MASK_PERIPH_CLK_SEL_LOADED 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created 0b1..mask interrupt due to update of periph_clk_sel

Definition at line 5492 of file MIMXRT1052.h.

CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK

#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK   (0x400000U)

Definition at line 5486 of file MIMXRT1052.h.

CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT

#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT   (22U)

Definition at line 5487 of file MIMXRT1052.h.

CCM_CIMR_MASK_SEMC_PODF_LOADED

#define CCM_CIMR_MASK_SEMC_PODF_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)

MASK_SEMC_PODF_LOADED 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created 0b1..mask interrupt due to frequency change of semc_podf

Definition at line 5471 of file MIMXRT1052.h.

CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK

#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK   (0x20000U)

Definition at line 5465 of file MIMXRT1052.h.

CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT

#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT   (17U)

Definition at line 5466 of file MIMXRT1052.h.

CCM_CISR_AHB_PODF_LOADED

#define CCM_CISR_AHB_PODF_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)

AHB_PODF_LOADED 0b0..interrupt is not generated due to frequency change of ahb_podf 0b1..interrupt generated due to frequency change of ahb_podf

Definition at line 5432 of file MIMXRT1052.h.

CCM_CISR_AHB_PODF_LOADED_MASK

#define CCM_CISR_AHB_PODF_LOADED_MASK   (0x100000U)

Definition at line 5426 of file MIMXRT1052.h.

CCM_CISR_AHB_PODF_LOADED_SHIFT

#define CCM_CISR_AHB_PODF_LOADED_SHIFT   (20U)

Definition at line 5427 of file MIMXRT1052.h.

CCM_CISR_ARM_PODF_LOADED

#define CCM_CISR_ARM_PODF_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)

ARM_PODF_LOADED 0b0..interrupt is not generated due to frequency change of arm_podf 0b1..interrupt generated due to frequency change of arm_podf

Definition at line 5446 of file MIMXRT1052.h.

CCM_CISR_ARM_PODF_LOADED_MASK

#define CCM_CISR_ARM_PODF_LOADED_MASK   (0x4000000U)

Definition at line 5440 of file MIMXRT1052.h.

CCM_CISR_ARM_PODF_LOADED_SHIFT

#define CCM_CISR_ARM_PODF_LOADED_SHIFT   (26U)

Definition at line 5441 of file MIMXRT1052.h.

CCM_CISR_COSC_READY

#define CCM_CISR_COSC_READY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)

COSC_READY 0b0..interrupt is not generated due to on board oscillator ready 0b1..interrupt generated due to on board oscillator ready

Definition at line 5411 of file MIMXRT1052.h.

CCM_CISR_COSC_READY_MASK

#define CCM_CISR_COSC_READY_MASK   (0x40U)

Definition at line 5405 of file MIMXRT1052.h.

CCM_CISR_COSC_READY_SHIFT

#define CCM_CISR_COSC_READY_SHIFT   (6U)

Definition at line 5406 of file MIMXRT1052.h.

CCM_CISR_LRF_PLL

#define CCM_CISR_LRF_PLL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)

LRF_PLL 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs

Definition at line 5404 of file MIMXRT1052.h.

CCM_CISR_LRF_PLL_MASK

#define CCM_CISR_LRF_PLL_MASK   (0x1U)

Definition at line 5398 of file MIMXRT1052.h.

CCM_CISR_LRF_PLL_SHIFT

#define CCM_CISR_LRF_PLL_SHIFT   (0U)

Definition at line 5399 of file MIMXRT1052.h.

CCM_CISR_PERIPH2_CLK_SEL_LOADED

#define CCM_CISR_PERIPH2_CLK_SEL_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)

PERIPH2_CLK_SEL_LOADED 0b0..interrupt is not generated due to frequency change of periph2_clk_sel 0b1..interrupt generated due to frequency change of periph2_clk_sel

Definition at line 5425 of file MIMXRT1052.h.

CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK

#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK   (0x80000U)

Definition at line 5419 of file MIMXRT1052.h.

CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT

#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT   (19U)

Definition at line 5420 of file MIMXRT1052.h.

CCM_CISR_PERIPH_CLK_SEL_LOADED

#define CCM_CISR_PERIPH_CLK_SEL_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)

PERIPH_CLK_SEL_LOADED 0b0..interrupt is not generated due to update of periph_clk_sel. 0b1..interrupt generated due to update of periph_clk_sel.

Definition at line 5439 of file MIMXRT1052.h.

CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK

#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK   (0x400000U)

Definition at line 5433 of file MIMXRT1052.h.

CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT

#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT   (22U)

Definition at line 5434 of file MIMXRT1052.h.

CCM_CISR_SEMC_PODF_LOADED

#define CCM_CISR_SEMC_PODF_LOADED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)

SEMC_PODF_LOADED 0b0..interrupt is not generated due to frequency change of semc_podf 0b1..interrupt generated due to frequency change of semc_podf

Definition at line 5418 of file MIMXRT1052.h.

CCM_CISR_SEMC_PODF_LOADED_MASK

#define CCM_CISR_SEMC_PODF_LOADED_MASK   (0x20000U)

Definition at line 5412 of file MIMXRT1052.h.

CCM_CISR_SEMC_PODF_LOADED_SHIFT

#define CCM_CISR_SEMC_PODF_LOADED_SHIFT   (17U)

Definition at line 5413 of file MIMXRT1052.h.

CCM_CLPCR_ARM_CLK_DIS_ON_LPM

#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)

ARM_CLK_DIS_ON_LPM 0b0..ARM clock enabled on wait mode. 0b1..ARM clock disabled on wait mode. .

Definition at line 5325 of file MIMXRT1052.h.

CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK

#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK   (0x20U)

Definition at line 5319 of file MIMXRT1052.h.

CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT

#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT   (5U)

Definition at line 5320 of file MIMXRT1052.h.

CCM_CLPCR_BYPASS_LPM_HS0

#define CCM_CLPCR_BYPASS_LPM_HS0

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)

Definition at line 5372 of file MIMXRT1052.h.

CCM_CLPCR_BYPASS_LPM_HS0_MASK

#define CCM_CLPCR_BYPASS_LPM_HS0_MASK   (0x200000U)

Definition at line 5370 of file MIMXRT1052.h.

CCM_CLPCR_BYPASS_LPM_HS0_SHIFT

#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT   (21U)

Definition at line 5371 of file MIMXRT1052.h.

CCM_CLPCR_BYPASS_LPM_HS1

#define CCM_CLPCR_BYPASS_LPM_HS1

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)

Definition at line 5369 of file MIMXRT1052.h.

CCM_CLPCR_BYPASS_LPM_HS1_MASK

#define CCM_CLPCR_BYPASS_LPM_HS1_MASK   (0x80000U)

Definition at line 5367 of file MIMXRT1052.h.

CCM_CLPCR_BYPASS_LPM_HS1_SHIFT

#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT   (19U)

Definition at line 5368 of file MIMXRT1052.h.

CCM_CLPCR_COSC_PWRDOWN

#define CCM_CLPCR_COSC_PWRDOWN

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)

COSC_PWRDOWN 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.

Definition at line 5366 of file MIMXRT1052.h.

CCM_CLPCR_COSC_PWRDOWN_MASK

#define CCM_CLPCR_COSC_PWRDOWN_MASK   (0x800U)

Definition at line 5360 of file MIMXRT1052.h.

CCM_CLPCR_COSC_PWRDOWN_SHIFT

#define CCM_CLPCR_COSC_PWRDOWN_SHIFT   (11U)

Definition at line 5361 of file MIMXRT1052.h.

CCM_CLPCR_DIS_REF_OSC

#define CCM_CLPCR_DIS_REF_OSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)

DIS_REF_OSC 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'

Definition at line 5343 of file MIMXRT1052.h.

CCM_CLPCR_DIS_REF_OSC_MASK

#define CCM_CLPCR_DIS_REF_OSC_MASK   (0x80U)

Definition at line 5337 of file MIMXRT1052.h.

CCM_CLPCR_DIS_REF_OSC_SHIFT

#define CCM_CLPCR_DIS_REF_OSC_SHIFT   (7U)

Definition at line 5338 of file MIMXRT1052.h.

CCM_CLPCR_LPM

#define CCM_CLPCR_LPM

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)

LPM 0b00..Remain in run mode 0b01..Transfer to wait mode 0b10..Transfer to stop mode 0b11..Reserved

Definition at line 5318 of file MIMXRT1052.h.

CCM_CLPCR_LPM_MASK

#define CCM_CLPCR_LPM_MASK   (0x3U)

Definition at line 5310 of file MIMXRT1052.h.

CCM_CLPCR_LPM_SHIFT

#define CCM_CLPCR_LPM_SHIFT   (0U)

Definition at line 5311 of file MIMXRT1052.h.

CCM_CLPCR_MASK_CORE0_WFI

#define CCM_CLPCR_MASK_CORE0_WFI

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)

MASK_CORE0_WFI 0b0..WFI of core0 is not masked 0b1..WFI of core0 is masked

Definition at line 5379 of file MIMXRT1052.h.

CCM_CLPCR_MASK_CORE0_WFI_MASK

#define CCM_CLPCR_MASK_CORE0_WFI_MASK   (0x400000U)

Definition at line 5373 of file MIMXRT1052.h.

CCM_CLPCR_MASK_CORE0_WFI_SHIFT

#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT   (22U)

Definition at line 5374 of file MIMXRT1052.h.

CCM_CLPCR_MASK_L2CC_IDLE

#define CCM_CLPCR_MASK_L2CC_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)

MASK_L2CC_IDLE 0b1..L2CC IDLE is masked 0b0..L2CC IDLE is not masked

Definition at line 5393 of file MIMXRT1052.h.

CCM_CLPCR_MASK_L2CC_IDLE_MASK

#define CCM_CLPCR_MASK_L2CC_IDLE_MASK   (0x8000000U)

Definition at line 5387 of file MIMXRT1052.h.

CCM_CLPCR_MASK_L2CC_IDLE_SHIFT

#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT   (27U)

Definition at line 5388 of file MIMXRT1052.h.

CCM_CLPCR_MASK_SCU_IDLE

#define CCM_CLPCR_MASK_SCU_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)

MASK_SCU_IDLE 0b1..SCU IDLE is masked 0b0..SCU IDLE is not masked

Definition at line 5386 of file MIMXRT1052.h.

CCM_CLPCR_MASK_SCU_IDLE_MASK

#define CCM_CLPCR_MASK_SCU_IDLE_MASK   (0x4000000U)

Definition at line 5380 of file MIMXRT1052.h.

CCM_CLPCR_MASK_SCU_IDLE_SHIFT

#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT   (26U)

Definition at line 5381 of file MIMXRT1052.h.

CCM_CLPCR_SBYOS

#define CCM_CLPCR_SBYOS

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)

SBYOS 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process.

Definition at line 5336 of file MIMXRT1052.h.

CCM_CLPCR_SBYOS_MASK

#define CCM_CLPCR_SBYOS_MASK   (0x40U)

Definition at line 5326 of file MIMXRT1052.h.

CCM_CLPCR_SBYOS_SHIFT

#define CCM_CLPCR_SBYOS_SHIFT   (6U)

Definition at line 5327 of file MIMXRT1052.h.

CCM_CLPCR_STBY_COUNT

#define CCM_CLPCR_STBY_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)

STBY_COUNT 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles

Definition at line 5359 of file MIMXRT1052.h.

CCM_CLPCR_STBY_COUNT_MASK

#define CCM_CLPCR_STBY_COUNT_MASK   (0x600U)

Definition at line 5351 of file MIMXRT1052.h.

CCM_CLPCR_STBY_COUNT_SHIFT

#define CCM_CLPCR_STBY_COUNT_SHIFT   (9U)

Definition at line 5352 of file MIMXRT1052.h.

CCM_CLPCR_VSTBY

#define CCM_CLPCR_VSTBY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)

VSTBY 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').

Definition at line 5350 of file MIMXRT1052.h.

CCM_CLPCR_VSTBY_MASK

#define CCM_CLPCR_VSTBY_MASK   (0x100U)

Definition at line 5344 of file MIMXRT1052.h.

CCM_CLPCR_VSTBY_SHIFT

#define CCM_CLPCR_VSTBY_SHIFT   (8U)

Definition at line 5345 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_CAN1_CPI

#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)

MOD_EN_OV_CAN1_CPI 0b0..don't overide module enable signal 0b1..overide module enable signal

Definition at line 6036 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK

#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK   (0x40000000U)

Definition at line 6030 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT

#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT   (30U)

Definition at line 6031 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_CAN2_CPI

#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)

MOD_EN_OV_CAN2_CPI 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 6029 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK

#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK   (0x10000000U)

Definition at line 6023 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT

#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT   (28U)

Definition at line 6024 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_GPT

#define CCM_CMEOR_MOD_EN_OV_GPT

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)

MOD_EN_OV_GPT 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 6001 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_GPT_MASK

#define CCM_CMEOR_MOD_EN_OV_GPT_MASK   (0x20U)

Definition at line 5995 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_GPT_SHIFT

#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT   (5U)

Definition at line 5996 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_PIT

#define CCM_CMEOR_MOD_EN_OV_PIT

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)

MOD_EN_OV_PIT 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 6008 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_PIT_MASK

#define CCM_CMEOR_MOD_EN_OV_PIT_MASK   (0x40U)

Definition at line 6002 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_PIT_SHIFT

#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT   (6U)

Definition at line 6003 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_TRNG

#define CCM_CMEOR_MOD_EN_OV_TRNG

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)

MOD_EN_OV_TRNG 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 6022 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_TRNG_MASK

#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK   (0x200U)

Definition at line 6016 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT

#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT   (9U)

Definition at line 6017 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_USDHC

#define CCM_CMEOR_MOD_EN_USDHC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)

MOD_EN_USDHC 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 6015 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_USDHC_MASK

#define CCM_CMEOR_MOD_EN_USDHC_MASK   (0x80U)

Definition at line 6009 of file MIMXRT1052.h.

CCM_CMEOR_MOD_EN_USDHC_SHIFT

#define CCM_CMEOR_MOD_EN_USDHC_SHIFT   (7U)

Definition at line 6010 of file MIMXRT1052.h.

CCM_CS1CDR_FLEXIO2_CLK_PODF

#define CCM_CS1CDR_FLEXIO2_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)

FLEXIO2_CLK_PODF - Divider for flexio2 clock. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 4968 of file MIMXRT1052.h.

CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK

#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK   (0xE000000U)

Definition at line 4956 of file MIMXRT1052.h.

CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT

#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT   (25U)

Definition at line 4957 of file MIMXRT1052.h.

CCM_CS1CDR_FLEXIO2_CLK_PRED

#define CCM_CS1CDR_FLEXIO2_CLK_PRED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)

FLEXIO2_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4872 of file MIMXRT1052.h.

CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK

#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK   (0xE00U)

Definition at line 4860 of file MIMXRT1052.h.

CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT

#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT   (9U)

Definition at line 4861 of file MIMXRT1052.h.

CCM_CS1CDR_SAI1_CLK_PODF

#define CCM_CS1CDR_SAI1_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)

SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 4846 of file MIMXRT1052.h.

CCM_CS1CDR_SAI1_CLK_PODF_MASK

#define CCM_CS1CDR_SAI1_CLK_PODF_MASK   (0x3FU)

Definition at line 4777 of file MIMXRT1052.h.

CCM_CS1CDR_SAI1_CLK_PODF_SHIFT

#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT   (0U)

Definition at line 4778 of file MIMXRT1052.h.

CCM_CS1CDR_SAI1_CLK_PRED

#define CCM_CS1CDR_SAI1_CLK_PRED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)

SAI1_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4859 of file MIMXRT1052.h.

CCM_CS1CDR_SAI1_CLK_PRED_MASK

#define CCM_CS1CDR_SAI1_CLK_PRED_MASK   (0x1C0U)

Definition at line 4847 of file MIMXRT1052.h.

CCM_CS1CDR_SAI1_CLK_PRED_SHIFT

#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT   (6U)

Definition at line 4848 of file MIMXRT1052.h.

CCM_CS1CDR_SAI3_CLK_PODF

#define CCM_CS1CDR_SAI3_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)

SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 4942 of file MIMXRT1052.h.

CCM_CS1CDR_SAI3_CLK_PODF_MASK

#define CCM_CS1CDR_SAI3_CLK_PODF_MASK   (0x3F0000U)

Definition at line 4873 of file MIMXRT1052.h.

CCM_CS1CDR_SAI3_CLK_PODF_SHIFT

#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT   (16U)

Definition at line 4874 of file MIMXRT1052.h.

CCM_CS1CDR_SAI3_CLK_PRED

#define CCM_CS1CDR_SAI3_CLK_PRED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)

SAI3_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4955 of file MIMXRT1052.h.

CCM_CS1CDR_SAI3_CLK_PRED_MASK

#define CCM_CS1CDR_SAI3_CLK_PRED_MASK   (0x1C00000U)

Definition at line 4943 of file MIMXRT1052.h.

CCM_CS1CDR_SAI3_CLK_PRED_SHIFT

#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT   (22U)

Definition at line 4944 of file MIMXRT1052.h.

CCM_CS2CDR_SAI2_CLK_PODF

#define CCM_CS2CDR_SAI2_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)

SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 5042 of file MIMXRT1052.h.

CCM_CS2CDR_SAI2_CLK_PODF_MASK

#define CCM_CS2CDR_SAI2_CLK_PODF_MASK   (0x3FU)

Definition at line 4973 of file MIMXRT1052.h.

CCM_CS2CDR_SAI2_CLK_PODF_SHIFT

#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT   (0U)

Definition at line 4974 of file MIMXRT1052.h.

CCM_CS2CDR_SAI2_CLK_PRED

#define CCM_CS2CDR_SAI2_CLK_PRED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)

SAI2_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5055 of file MIMXRT1052.h.

CCM_CS2CDR_SAI2_CLK_PRED_MASK

#define CCM_CS2CDR_SAI2_CLK_PRED_MASK   (0x1C0U)

Definition at line 5043 of file MIMXRT1052.h.

CCM_CS2CDR_SAI2_CLK_PRED_SHIFT

#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT   (6U)

Definition at line 5044 of file MIMXRT1052.h.

CCM_CSCDR1_TRACE_PODF

#define CCM_CSCDR1_TRACE_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)

TRACE_PODF 0b00..divide by 1 0b01..divide by 2 0b10..divide by 3 0b11..divide by 4

Definition at line 4772 of file MIMXRT1052.h.

CCM_CSCDR1_TRACE_PODF_MASK

#define CCM_CSCDR1_TRACE_PODF_MASK   (0x6000000U)

Definition at line 4764 of file MIMXRT1052.h.

CCM_CSCDR1_TRACE_PODF_SHIFT

#define CCM_CSCDR1_TRACE_PODF_SHIFT   (25U)

Definition at line 4765 of file MIMXRT1052.h.

CCM_CSCDR1_UART_CLK_PODF

#define CCM_CSCDR1_UART_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)

UART_CLK_PODF - Divider for uart clock podf. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 4730 of file MIMXRT1052.h.

CCM_CSCDR1_UART_CLK_PODF_MASK

#define CCM_CSCDR1_UART_CLK_PODF_MASK   (0x3FU)

Definition at line 4662 of file MIMXRT1052.h.

CCM_CSCDR1_UART_CLK_PODF_SHIFT

#define CCM_CSCDR1_UART_CLK_PODF_SHIFT   (0U)

Definition at line 4663 of file MIMXRT1052.h.

CCM_CSCDR1_UART_CLK_SEL

#define CCM_CSCDR1_UART_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)

UART_CLK_SEL 0b0..derive clock from pll3_80m 0b1..derive clock from osc_clk

Definition at line 4737 of file MIMXRT1052.h.

CCM_CSCDR1_UART_CLK_SEL_MASK

#define CCM_CSCDR1_UART_CLK_SEL_MASK   (0x40U)

Definition at line 4731 of file MIMXRT1052.h.

CCM_CSCDR1_UART_CLK_SEL_SHIFT

#define CCM_CSCDR1_UART_CLK_SEL_SHIFT   (6U)

Definition at line 4732 of file MIMXRT1052.h.

CCM_CSCDR1_USDHC1_PODF

#define CCM_CSCDR1_USDHC1_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)

USDHC1_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4750 of file MIMXRT1052.h.

CCM_CSCDR1_USDHC1_PODF_MASK

#define CCM_CSCDR1_USDHC1_PODF_MASK   (0x3800U)

Definition at line 4738 of file MIMXRT1052.h.

CCM_CSCDR1_USDHC1_PODF_SHIFT

#define CCM_CSCDR1_USDHC1_PODF_SHIFT   (11U)

Definition at line 4739 of file MIMXRT1052.h.

CCM_CSCDR1_USDHC2_PODF

#define CCM_CSCDR1_USDHC2_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)

USDHC2_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4763 of file MIMXRT1052.h.

CCM_CSCDR1_USDHC2_PODF_MASK

#define CCM_CSCDR1_USDHC2_PODF_MASK   (0x70000U)

Definition at line 4751 of file MIMXRT1052.h.

CCM_CSCDR1_USDHC2_PODF_SHIFT

#define CCM_CSCDR1_USDHC2_PODF_SHIFT   (16U)

Definition at line 4752 of file MIMXRT1052.h.

CCM_CSCDR2_LCDIF_PRE_CLK_SEL

#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)

LCDIF_PRE_CLK_SEL 0b000..derive clock from PLL2 0b001..derive clock from PLL3 PFD3 0b010..derive clock from PLL5 0b011..derive clock from PLL2 PFD0 0b100..derive clock from PLL2 PFD1 0b101..derive clock from PLL3 PFD1

Definition at line 5157 of file MIMXRT1052.h.

CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK

#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK   (0x38000U)

Definition at line 5147 of file MIMXRT1052.h.

CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT

#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT   (15U)

Definition at line 5148 of file MIMXRT1052.h.

CCM_CSCDR2_LCDIF_PRED

#define CCM_CSCDR2_LCDIF_PRED

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)

LCDIF_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5146 of file MIMXRT1052.h.

CCM_CSCDR2_LCDIF_PRED_MASK

#define CCM_CSCDR2_LCDIF_PRED_MASK   (0x7000U)

Definition at line 5134 of file MIMXRT1052.h.

CCM_CSCDR2_LCDIF_PRED_SHIFT

#define CCM_CSCDR2_LCDIF_PRED_SHIFT   (12U)

Definition at line 5135 of file MIMXRT1052.h.

CCM_CSCDR2_LPI2C_CLK_PODF

#define CCM_CSCDR2_LPI2C_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)

LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 5235 of file MIMXRT1052.h.

CCM_CSCDR2_LPI2C_CLK_PODF_MASK

#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK   (0x1F80000U)

Definition at line 5165 of file MIMXRT1052.h.

CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT

#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT   (19U)

Definition at line 5166 of file MIMXRT1052.h.

CCM_CSCDR2_LPI2C_CLK_SEL

#define CCM_CSCDR2_LPI2C_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)

LPI2C_CLK_SEL 0b0..derive clock from pll3_60m 0b1..derive clock from osc_clk

Definition at line 5164 of file MIMXRT1052.h.

CCM_CSCDR2_LPI2C_CLK_SEL_MASK

#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK   (0x40000U)

Definition at line 5158 of file MIMXRT1052.h.

CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT

#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT   (18U)

Definition at line 5159 of file MIMXRT1052.h.

CCM_CSCDR3_CSI_CLK_SEL

#define CCM_CSCDR3_CSI_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)

CSI_CLK_SEL 0b00..derive clock from osc_clk (24M) 0b01..derive clock from PLL2 PFD2 0b10..derive clock from pll3_120M 0b11..derive clock from PLL3 PFD1

Definition at line 5248 of file MIMXRT1052.h.

CCM_CSCDR3_CSI_CLK_SEL_MASK

#define CCM_CSCDR3_CSI_CLK_SEL_MASK   (0x600U)

Definition at line 5240 of file MIMXRT1052.h.

CCM_CSCDR3_CSI_CLK_SEL_SHIFT

#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT   (9U)

Definition at line 5241 of file MIMXRT1052.h.

CCM_CSCDR3_CSI_PODF

#define CCM_CSCDR3_CSI_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)

CSI_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5261 of file MIMXRT1052.h.

CCM_CSCDR3_CSI_PODF_MASK

#define CCM_CSCDR3_CSI_PODF_MASK   (0x3800U)

Definition at line 5249 of file MIMXRT1052.h.

CCM_CSCDR3_CSI_PODF_SHIFT

#define CCM_CSCDR3_CSI_PODF_SHIFT   (11U)

Definition at line 5250 of file MIMXRT1052.h.

CCM_CSCMR1_FLEXSPI_CLK_SEL

#define CCM_CSCMR1_FLEXSPI_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)

FLEXSPI_CLK_SEL 0b00..derive clock from semc_clk_root_pre 0b01..derive clock from pll3_sw_clk 0b10..derive clock from PLL2 PFD2 0b11..derive clock from PLL3 PFD0

Definition at line 4566 of file MIMXRT1052.h.

CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK

#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK   (0x60000000U)

Definition at line 4558 of file MIMXRT1052.h.

CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT

#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT   (29U)

Definition at line 4559 of file MIMXRT1052.h.

CCM_CSCMR1_FLEXSPI_PODF

#define CCM_CSCMR1_FLEXSPI_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)

FLEXSPI_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 4557 of file MIMXRT1052.h.

CCM_CSCMR1_FLEXSPI_PODF_MASK

#define CCM_CSCMR1_FLEXSPI_PODF_MASK   (0x3800000U)

Definition at line 4545 of file MIMXRT1052.h.

CCM_CSCMR1_FLEXSPI_PODF_SHIFT

#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT   (23U)

Definition at line 4546 of file MIMXRT1052.h.

CCM_CSCMR1_PERCLK_CLK_SEL

#define CCM_CSCMR1_PERCLK_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)

PERCLK_CLK_SEL 0b0..derive clock from ipg clk root 0b1..derive clock from osc_clk

Definition at line 4503 of file MIMXRT1052.h.

CCM_CSCMR1_PERCLK_CLK_SEL_MASK

#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK   (0x40U)

Definition at line 4497 of file MIMXRT1052.h.

CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT

#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT   (6U)

Definition at line 4498 of file MIMXRT1052.h.

CCM_CSCMR1_PERCLK_PODF

#define CCM_CSCMR1_PERCLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)

PERCLK_PODF - Divider for perclk podf. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 4496 of file MIMXRT1052.h.

CCM_CSCMR1_PERCLK_PODF_MASK

#define CCM_CSCMR1_PERCLK_PODF_MASK   (0x3FU)

Definition at line 4428 of file MIMXRT1052.h.

CCM_CSCMR1_PERCLK_PODF_SHIFT

#define CCM_CSCMR1_PERCLK_PODF_SHIFT   (0U)

Definition at line 4429 of file MIMXRT1052.h.

CCM_CSCMR1_SAI1_CLK_SEL

#define CCM_CSCMR1_SAI1_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)

SAI1_CLK_SEL 0b00..derive clock from PLL3 PFD2 0b01..derive clock from PLL5 0b10..derive clock from PLL4 0b11..Reserved

Definition at line 4512 of file MIMXRT1052.h.

CCM_CSCMR1_SAI1_CLK_SEL_MASK

#define CCM_CSCMR1_SAI1_CLK_SEL_MASK   (0xC00U)

Definition at line 4504 of file MIMXRT1052.h.

CCM_CSCMR1_SAI1_CLK_SEL_SHIFT

#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT   (10U)

Definition at line 4505 of file MIMXRT1052.h.

CCM_CSCMR1_SAI2_CLK_SEL

#define CCM_CSCMR1_SAI2_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)

SAI2_CLK_SEL 0b00..derive clock from PLL3 PFD2 0b01..derive clock from PLL5 0b10..derive clock from PLL4 0b11..Reserved

Definition at line 4521 of file MIMXRT1052.h.

CCM_CSCMR1_SAI2_CLK_SEL_MASK

#define CCM_CSCMR1_SAI2_CLK_SEL_MASK   (0x3000U)

Definition at line 4513 of file MIMXRT1052.h.

CCM_CSCMR1_SAI2_CLK_SEL_SHIFT

#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT   (12U)

Definition at line 4514 of file MIMXRT1052.h.

CCM_CSCMR1_SAI3_CLK_SEL

#define CCM_CSCMR1_SAI3_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)

SAI3_CLK_SEL 0b00..derive clock from PLL3 PFD2 0b01..derive clock from PLL5 0b10..derive clock from PLL4 0b11..Reserved

Definition at line 4530 of file MIMXRT1052.h.

CCM_CSCMR1_SAI3_CLK_SEL_MASK

#define CCM_CSCMR1_SAI3_CLK_SEL_MASK   (0xC000U)

Definition at line 4522 of file MIMXRT1052.h.

CCM_CSCMR1_SAI3_CLK_SEL_SHIFT

#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT   (14U)

Definition at line 4523 of file MIMXRT1052.h.

CCM_CSCMR1_USDHC1_CLK_SEL

#define CCM_CSCMR1_USDHC1_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)

USDHC1_CLK_SEL 0b0..derive clock from PLL2 PFD2 0b1..derive clock from PLL2 PFD0

Definition at line 4537 of file MIMXRT1052.h.

CCM_CSCMR1_USDHC1_CLK_SEL_MASK

#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK   (0x10000U)

Definition at line 4531 of file MIMXRT1052.h.

CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT

#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT   (16U)

Definition at line 4532 of file MIMXRT1052.h.

CCM_CSCMR1_USDHC2_CLK_SEL

#define CCM_CSCMR1_USDHC2_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)

USDHC2_CLK_SEL 0b0..derive clock from PLL2 PFD2 0b1..derive clock from PLL2 PFD0

Definition at line 4544 of file MIMXRT1052.h.

CCM_CSCMR1_USDHC2_CLK_SEL_MASK

#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK   (0x20000U)

Definition at line 4538 of file MIMXRT1052.h.

CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT

#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT   (17U)

Definition at line 4539 of file MIMXRT1052.h.

CCM_CSCMR2_CAN_CLK_PODF

#define CCM_CSCMR2_CAN_CLK_PODF

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)

CAN_CLK_PODF - Divider for CAN clock podf. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 4639 of file MIMXRT1052.h.

CCM_CSCMR2_CAN_CLK_PODF_MASK

#define CCM_CSCMR2_CAN_CLK_PODF_MASK   (0xFCU)

Definition at line 4571 of file MIMXRT1052.h.

CCM_CSCMR2_CAN_CLK_PODF_SHIFT

#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT   (2U)

Definition at line 4572 of file MIMXRT1052.h.

CCM_CSCMR2_CAN_CLK_SEL

#define CCM_CSCMR2_CAN_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)

CAN_CLK_SEL 0b00..derive clock from pll3_sw_clk divided clock (60M) 0b01..derive clock from osc_clk (24M) 0b10..derive clock from pll3_sw_clk divided clock (80M) 0b11..Disable FlexCAN clock

Definition at line 4648 of file MIMXRT1052.h.

CCM_CSCMR2_CAN_CLK_SEL_MASK

#define CCM_CSCMR2_CAN_CLK_SEL_MASK   (0x300U)

Definition at line 4640 of file MIMXRT1052.h.

CCM_CSCMR2_CAN_CLK_SEL_SHIFT

#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT   (8U)

Definition at line 4641 of file MIMXRT1052.h.

CCM_CSCMR2_FLEXIO2_CLK_SEL

#define CCM_CSCMR2_FLEXIO2_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)

FLEXIO2_CLK_SEL 0b00..derive clock from PLL4 divided clock 0b01..derive clock from PLL3 PFD2 clock 0b10..derive clock from PLL5 clock 0b11..derive clock from pll3_sw_clk

Definition at line 4657 of file MIMXRT1052.h.

CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK

#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK   (0x180000U)

Definition at line 4649 of file MIMXRT1052.h.

CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT

#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT   (19U)

Definition at line 4650 of file MIMXRT1052.h.

CCM_CSR_CAMP2_READY

#define CCM_CSR_CAMP2_READY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)

CAMP2_READY 0b0..CAMP2 is not ready. 0b1..CAMP2 is ready.

Definition at line 4249 of file MIMXRT1052.h.

CCM_CSR_CAMP2_READY_MASK

#define CCM_CSR_CAMP2_READY_MASK   (0x8U)

Definition at line 4243 of file MIMXRT1052.h.

CCM_CSR_CAMP2_READY_SHIFT

#define CCM_CSR_CAMP2_READY_SHIFT   (3U)

Definition at line 4244 of file MIMXRT1052.h.

CCM_CSR_COSC_READY

#define CCM_CSR_COSC_READY

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)

COSC_READY 0b0..on board oscillator is not ready. 0b1..on board oscillator is ready.

Definition at line 4256 of file MIMXRT1052.h.

CCM_CSR_COSC_READY_MASK

#define CCM_CSR_COSC_READY_MASK   (0x20U)

Definition at line 4250 of file MIMXRT1052.h.

CCM_CSR_COSC_READY_SHIFT

#define CCM_CSR_COSC_READY_SHIFT   (5U)

Definition at line 4251 of file MIMXRT1052.h.

CCM_CSR_REF_EN_B

#define CCM_CSR_REF_EN_B

(

x

)

(((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)

REF_EN_B 0b0..value of CCM_REF_EN_B is '0' 0b1..value of CCM_REF_EN_B is '1'

Definition at line 4242 of file MIMXRT1052.h.

CCM_CSR_REF_EN_B_MASK

#define CCM_CSR_REF_EN_B_MASK   (0x1U)

Definition at line 4236 of file MIMXRT1052.h.

CCM_CSR_REF_EN_B_SHIFT

#define CCM_CSR_REF_EN_B_SHIFT   (0U)

Definition at line 4237 of file MIMXRT1052.h.